JPH03101238A - Mos type semiconductor device and its manufacture - Google Patents

Mos type semiconductor device and its manufacture

Info

Publication number
JPH03101238A
JPH03101238A JP1239200A JP23920089A JPH03101238A JP H03101238 A JPH03101238 A JP H03101238A JP 1239200 A JP1239200 A JP 1239200A JP 23920089 A JP23920089 A JP 23920089A JP H03101238 A JPH03101238 A JP H03101238A
Authority
JP
Japan
Prior art keywords
gate electrode
film
oxide film
formed
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1239200A
Inventor
Masataka Takebuchi
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1239200A priority Critical patent/JPH03101238A/en
Publication of JPH03101238A publication Critical patent/JPH03101238A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To curtail the excessive heat history by oxidation process and also to solve the pollution problem of a polysilicon film by interposing a silicon nitride film between the gate electrode of a transistor and the silicon oxide film by CVD method at the sidewall.
CONSTITUTION: A gate electrode consisting of a gate insulating film 2 and a polysilicon film 3 is formed on a P-type silicon substrate 1. After that, an oxide film 4 is formed by thermal oxidation method, etc. Next, the ions of n-type impurities are implanted in low concentration, and N--type regions 5 in low concentration are formed within the substrate on both sides of it with the gate electrode as a mask. And it is thermally oxidized again to obtain an oxide film. Next, an extremely thin silicon nitride film 6 is accumulated on the whole face of the substrate by CVD method, or the like, and the silicon nitride film 6 is formed as to cover the whole face of the gate electrode. After that, a silicon oxide film 7 is accumulated by CVD method on the whole face of the substrate covered with the silicon nitride film 6. Next, by performing the anisotropic ion etching by RIE method, the silicon oxide film 6 is left only at the sidewall of the gate electrode.
COPYRIGHT: (C)1991,JPO&Japio
JP1239200A 1989-09-14 1989-09-14 Mos type semiconductor device and its manufacture Pending JPH03101238A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1239200A JPH03101238A (en) 1989-09-14 1989-09-14 Mos type semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1239200A JPH03101238A (en) 1989-09-14 1989-09-14 Mos type semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH03101238A true JPH03101238A (en) 1991-04-26

Family

ID=17041219

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1239200A Pending JPH03101238A (en) 1989-09-14 1989-09-14 Mos type semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH03101238A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0899792A2 (en) * 1997-08-26 1999-03-03 Texas Instruments Incorporated Transistor with structured sidewalls and method
US6632716B2 (en) * 1996-11-01 2003-10-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
JP2006066886A (en) * 2004-08-26 2006-03-09 Hynix Semiconductor Inc Method of manufacturing flash memory element
JP2007532001A (en) * 2004-03-31 2007-11-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated Method for forming sidewall spacer
US7387921B2 (en) 2004-11-24 2008-06-17 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JP2008227524A (en) * 2008-04-17 2008-09-25 Fujitsu Ltd Manufacturing method of semiconductor device and production method of dram
JP2008306061A (en) * 2007-06-08 2008-12-18 Rohm Co Ltd Manufacturing method of semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6632716B2 (en) * 1996-11-01 2003-10-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
EP0899792A2 (en) * 1997-08-26 1999-03-03 Texas Instruments Incorporated Transistor with structured sidewalls and method
EP0899792A3 (en) * 1997-08-26 1999-08-25 Texas Instruments Incorporated Transistor with structured sidewalls and method
JP2007532001A (en) * 2004-03-31 2007-11-08 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated Method for forming sidewall spacer
JP2006066886A (en) * 2004-08-26 2006-03-09 Hynix Semiconductor Inc Method of manufacturing flash memory element
US7387921B2 (en) 2004-11-24 2008-06-17 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JP2008306061A (en) * 2007-06-08 2008-12-18 Rohm Co Ltd Manufacturing method of semiconductor device
JP2008227524A (en) * 2008-04-17 2008-09-25 Fujitsu Ltd Manufacturing method of semiconductor device and production method of dram

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