JPS60245174A - Manufacture of insulated gate type semiconductor device - Google Patents

Manufacture of insulated gate type semiconductor device

Info

Publication number
JPS60245174A
JPS60245174A JP10025284A JP10025284A JPS60245174A JP S60245174 A JPS60245174 A JP S60245174A JP 10025284 A JP10025284 A JP 10025284A JP 10025284 A JP10025284 A JP 10025284A JP S60245174 A JPS60245174 A JP S60245174A
Authority
JP
Japan
Prior art keywords
gate electrode
semiconductor
insulating film
annealing
hydrogen
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10025284A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP10025284A priority Critical patent/JPS60245174A/en
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of JPS60245174A publication Critical patent/JPS60245174A/en
Priority to US06/912,498 priority patent/US4727044A/en
Priority to US07/153,477 priority patent/US4959700A/en
Priority to US07/707,178 priority patent/US5142344A/en
Priority to US07/987,179 priority patent/US5315132A/en
Priority to US08/054,842 priority patent/US5313077A/en
Priority to US08/171,769 priority patent/US6660574B1/en
Priority to US08/473,953 priority patent/US5543636A/en
Priority to US08/944,136 priority patent/US6680486B1/en
Priority to US08/947,731 priority patent/US6221701B1/en
Priority to US09/406,794 priority patent/US6635520B1/en
Priority to US09/406,791 priority patent/US6734499B1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain an IGFET having high withstand strength by passing a gate insulating film through hydrogen or halogen element-added nonsingle crystal with a gate electrode as a mask to implant an impurity, annealing it with light, and extending the crystallization to a channel region. CONSTITUTION:A laminate of nonsingle crystal semiconductor 2 which contains hydrogen of density higher than 1atom% by a CVD method and Si3N4 3 is formed on a quartz glass substrate 1, an N<+> type polysilicon gate electrode 4 is formed by a resist mask 6. P ions are implanted to form N type layers 7, 8. It is annealed with strong light 10 of mercury lamp, polycrystallized to the outside of the layers 7, 8, the bottom is approached to the substrate 1, set to channel side from the junction boundaries 17, 17' of the layers 7, 8, and the ends 15, 15' are disposed at the channel side from gate electrode ends 16, 16'. Light annealing is performed at 400 deg.C or lower. With this structure, the breakdown voltage of junction increases at the reverse bias time to obtain a high withstand IGFET.

Description

【発明の詳細な説明】 「産業上の利用分野」 本発明は半導体集積回路、液晶表示パネル等に用いられ
る絶縁ゲイト型電界効果半導体装置（以下ＩＧＦという
）の作製方法に関する。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a method for manufacturing an insulated gate field effect semiconductor device (hereinafter referred to as IGF) used for semiconductor integrated circuits, liquid crystal display panels, etc.

「従来の技術１ 単結晶珪素を用いたＩＧＦは広く半導体分野に用いられ
ている。その代表例は本発明人の発明になる特公昭５Ｏ
−１９８６ｒ半導体装置およびその作製方法」である。``Prior art 1 IGFs using single crystal silicon are widely used in the semiconductor field.
-1986r Semiconductor device and method for manufacturing the same.”

しかし水素が添加されていないチャネル形成領域に単結
晶半導体を用いるのではなく、水素またはハロゲン元素
が１原子％以上の濃度に添加された非単結晶半導体によ
り設けられたＩＧＦは本発明人の出願による特願昭５３
−１２４０２１　ｒ半導体装置およびその作製方法」（
昭和５３年１０月７日出１Ｎ）がその代表例である。However, instead of using a single crystal semiconductor in the channel forming region to which hydrogen is not added, an IGF formed by a non-single crystal semiconductor doped with hydrogen or a halogen element at a concentration of 1 atomic % or more is proposed by the present inventor. Special application by 1972
-124021 rSemiconductor device and its manufacturing method” (
1N) dated October 7, 1978 is a typical example.

かかる水素またはハロゲン元素が添加された半導体特に
珪素半導体がチャネル形成領域に用いられたＩＧＰは、
オフ電流が従来より公知の単結晶半導体を用いた場合に
比べて１０３〜１０５分の１も小さい。そのため液晶表
示パネル制御用ＩＧＦとして用いることが有効であると
されている。このＩＧＦは前記した引例のごとく、ゲイ
ト電極がチャネル形成領域の半導体に対しその上側に設
けられた横チャネル型ＩＧＦ　、また本発明人の出願に
なる特願昭５６−００１７６７　ｒ絶縁ゲイト型半導体
装置およびその作製方法」（昭和５６年１月９日）に示
された縦チャネル型ＩＧＦ　、およびゲイト電極がチャ
ネル形成領域を構成する半導体の下側に設けられたいわ
ゆる一般的に公知の薄膜ＩＧＦ　トランジスタ型が知ら
れている。しかしそのうち後２者に比べ前者の前記した
構造は従来より公知の単結晶珪素を用いたＩＧＦと構造
が同じであるため、すでに出来上がった技術を応用でき
るというきわめて優れた特長を有するものであった。An IGP in which a semiconductor doped with hydrogen or a halogen element, particularly a silicon semiconductor, is used in the channel formation region,
The off-state current is 103 to 105 times smaller than that when a conventionally known single crystal semiconductor is used. Therefore, it is said that it is effective to use it as an IGF for controlling a liquid crystal display panel. As mentioned above, this IGF is a lateral channel type IGF in which a gate electrode is provided above the semiconductor in the channel formation region, and is also referred to in Japanese Patent Application No. 56-001767 r insulated gate type semiconductor device filed by the present inventor. and the so-called generally known thin film IGF transistor in which the gate electrode is provided under the semiconductor constituting the channel forming region. type is known. However, compared to the latter two, the former has the same structure as the previously known IGF using single-crystal silicon, so it has an extremely superior feature of being able to apply already developed technology. .

しかし他方、かかるＩＧＦにおいては、ソース、ドレイ
ンの作製をＣＶＤ法（プラズマｃｖｎ法を含む）により
薄膜のディボジソションを行うのではなくイオン注入等
により添加し、かつその添加物を４００℃以下の水素ま
たはハロゲン元素が脱気しない温度範囲でのア二〜ルに
より活性のドナーまたはアクセプタとしなければならな
い。On the other hand, however, in such IGFs, the source and drain are not formed by thin film deposition using the CVD method (including plasma CVN method), but are added by ion implantation or the like, and the additives are added by hydrogen or The halogen element must be an active donor or acceptor with anyl in a temperature range in which it does not degas.

かかる観点に対し前記した本発明人の出願は必ずしも明
確でない。Regarding this point of view, the application of the present inventor mentioned above is not necessarily clear.

ｒ問題を解決するための手段」 本発明は上記の問題を解決するためのものであり、不純
物の添加のないまたはきわめて少ない非単結晶半導体（
以下水素またはハロゲン元素が添加された非単結晶半導
体を単に半導体または非単結晶半導体と略記する）上に
ゲイト絶縁物およびその上にゲイト電極を選択的に設け
た。さらにこのゲイト電極をマスクとしてイオン注入法
等によりソース、ドレイン用の不純物例えばＮチャネル
型ではリンまたは砒素、Ｐチャネル型ではホウ素を非単
結晶半導体内部にゲイト絶縁膜を貫通させて添加した。Means for Solving the Problem The present invention is intended to solve the above problem, and is directed to a non-single crystal semiconductor (with no or very little added impurities).
A gate insulator and a gate electrode were selectively provided on the non-single-crystal semiconductor to which hydrogen or a halogen element was added (hereinafter simply referred to as a semiconductor or non-single-crystal semiconductor). Further, using this gate electrode as a mask, an impurity for the source and drain, such as phosphorus or arsenic for an N-channel type, and boron for a P-channel type, was added by penetrating the gate insulating film into the non-single crystal semiconductor by ion implantation or the like.

この後、この不活性の不純物が添加された領域に対し、
４００°Ｃ以下の温度で強光照射をし、強光アニール（
以下単に光アニールという）を行い、水素またはハロゲ
ン元素が添加されたゲイト絶縁膜によりブロッキングさ
れて残存し、かつ結晶化度がチャネル形成領域よりも助
長された半導体、特に著しくは多結晶または単結晶構造
の半導体に変成せしめたことを特徴とするものである。After this, for the region added with this inactive impurity,
Strong light irradiation is performed at a temperature below 400°C, and strong light annealing (
Semiconductors that are blocked by a gate insulating film doped with hydrogen or a halogen element (hereinafter simply referred to as photo-annealing), and whose crystallinity is more favorable than that of the channel formation region, particularly polycrystalline or single crystalline. It is characterized by its structure being transformed into a semiconductor.

即ち本発明は従来より公知の水素またはハロゲン元素が
添加されていない単結晶半導体に対し、イオン注入後レ
ーザアニールを行うのではなく、水素またはハロゲン元
素が１原子％以上一般には５〜２０原子χの濃度に添加
されている非単結晶半導体に対しイオン注入をし、それ
に強光アニールを行い、かつ、好ましくはこの光を基板
表面を一端より他端に走査することにより結晶成長をプ
ロセス上含ませ結晶化度を助長とし不純物領域としたも
のである。That is, the present invention does not perform laser annealing after ion implantation on a conventionally known single crystal semiconductor to which no hydrogen or halogen element is added, but instead performs laser annealing after ion implantation. Crystal growth is included in the process by implanting ions into a non-single crystal semiconductor doped at a concentration of This is an impurity region that promotes crystallinity.

「作用ｊ その結果、本発明のＩＧＦの構造は、ゲイト電極が基板
上のチャネル形成領域を構成する非単結晶半導体の上方
に設けられ、かつこの半導体の光学的［！ｇ（珪素半導
体の場合１．７〜１．８ｅＶ）に対し１．６〜１．８ｅ
Ｖと殆ど同じ光学的Ｅｇを有しかつ活性な不純物領域を
得ることができた。かくのどと＜Ｅｇがチャネル形成領
域と同じまたは概略同じであるため、ＩＧＰのｒＯＮＪ
　、ｒＯＦＩＩ　Ｊに対しオン電流が立ち上がり時に流
れにくかったり、また他方、電流がたち下がり時にダラ
ダラ流れてしまったりすることがない、いわゆるオフ電
流が少なく、かつオン、オフを高速応答で行うことがで
きた。As a result, in the structure of the IGF of the present invention, the gate electrode is provided above the non-single crystal semiconductor constituting the channel formation region on the substrate, and the optical [! 1.7-1.8eV) vs. 1.6-1.8e
It was possible to obtain an active impurity region having almost the same optical Eg as V. Since the throat and <Eg are the same or approximately the same as the channel forming region, the rONJ of IGP
, rOFII J, the on-current does not flow easily when it rises, and on the other hand, the current does not flow lazily when it falls; the so-called off-current is small, and it can turn on and off with a high-speed response. Ta.

以下に実施例により本発明を説明する。The present invention will be explained below with reference to Examples.

ｒ実施例１」 基板（１）として第１図（＾）に示すごとく、厚さ１．
１ｍｍの石英ガラス基板１０ｃｍ　Ｘ　１０ｃｍを用い
た。この上面に、ジシラン（ＳｉＪｂ）の水銀励起法を
用いない光プラズマＣＶＤ　（２５３７人の波長を含む
低圧水銀灯、基板温度２１０℃）により水素が１原子％
以上の濃度に添加されたアモルファス構造を含む非単結
晶半導体（２）を０．２μの厚さに形成した。さらにこ
の上面に光ＣＶＤ法により窒化珪素膜（３）をゲイト絶
縁膜として同一反応炉内で半導体表面を大気に触れさせ
ることなく積層した。即ち５ｉＪ６とアンモニアまたは
ヒドラジンとの反応（２５３７人の波長を含む低圧水銀
灯、基板温度２５０℃）により５ｉＪ４を水銀増感法を
用いることなしに１０００人の厚さに作製した。rExample 1" As shown in FIG. 1 (^), the substrate (1) was made with a thickness of 1.
A 1 mm quartz glass substrate measuring 10 cm x 10 cm was used. Hydrogen was added to this upper surface by 1 at.
A non-single crystal semiconductor (2) containing an amorphous structure doped at the above concentration was formed to a thickness of 0.2 μm. Furthermore, a silicon nitride film (3) was deposited on this upper surface as a gate insulating film by photo-CVD method in the same reactor without exposing the semiconductor surface to the atmosphere. That is, 5iJ4 was produced to a thickness of 1000 nm without using a mercury sensitization method by reaction of 5iJ6 with ammonia or hydrazine (low pressure mercury lamp containing 2537 nm wavelength, substrate temperature 250° C.).

この後、ＩＧＦを形成する領域（５）を除く他部をプラ
ズマエツチング法により除去した。反応はＣＦ。Thereafter, the remaining portions except for the region (5) where the IGF was to be formed were removed by plasma etching. The reaction is CF.

＋０２（５χ）で１３．５６ＭＩＩｚ、室温で行った。+02(5χ) and 13.56 MIIz at room temperature.

このゲイト絶縁膜上にＮ゛の導電型の微結晶または多結
晶半導体を０．３　μの厚さに積層した。このＮ１の半
導体膜をレジスト（６）を用いてフォトエツチング法で
除去した後、このレジストとＮ＋半導体のゲイト電極部
（４）とをマスクとしてソース、ドレインとなる領域に
イオン注入法によりＩ　Ｘ　１０ｔ０ｃｆｆｌ−”の濃
度に第１図（Ｂ）に示すごとくリンを添加し、一対の不
純物領域（７）、（８）を形成した。On this gate insulating film, a microcrystalline or polycrystalline semiconductor of conductivity type N was laminated to a thickness of 0.3 μm. After removing this N1 semiconductor film by photoetching using a resist (6), using this resist and the gate electrode part (4) of the N+ semiconductor as a mask, IX is applied to the regions that will become the source and drain by ion implantation. Phosphorus was added to a concentration of 10t0cffl-'' as shown in FIG. 1(B) to form a pair of impurity regions (7) and (8).

さらにこの基板全体に対し、ゲイト電極のレジストを除
去した後、強光（１０）の光アニールを行った。即ち、
超高圧水銀灯（出力５問、波長２５０〜６００ｎｍ、光
径１５ｍｍφ、長さ１８０ｍｍ）に対し裏面側は放物面
の反射鏡を用い前方に石英のシリンドリカルレンズ（焦
点距離１５０ｃａ＋、集光部巾２　ｍ　ｍ　＋長さ１８
０＋＋＋ｍ）により線状に照射部を構成した。この照射
部に対し基板の照射面を５〜５０ｃｍ／分の速度で走査
（スキャン）し、基板１０ｃｍ　Ｘ　１０ｃｍの全面に
強光が照射されるようにした。Furthermore, after removing the resist of the gate electrode, the entire substrate was subjected to photo-annealing using strong light (10). That is,
Ultra-high pressure mercury lamp (output 5 questions, wavelength 250-600nm, light diameter 15mmφ, length 180mm) has a parabolic reflector on the back side and a quartz cylindrical lens (focal length 150ca+, condensing part width 2) in front. m m + length 18
0+++m), the irradiation part was configured in a linear manner. The irradiation surface of the substrate was scanned with respect to this irradiation section at a speed of 5 to 50 cm/min, so that the entire surface of the substrate (10 cm x 10 cm) was irradiated with intense light.

かくするとゲイト電極部はゲイト電極側にリンが多量に
添加されているため、この電極は十分光を吸収し多結晶
化した。また不純物領域（７）　、　（８）は一度溶融
し再結晶化することにより走査する方向即ちＸ方向に溶
融、再結晶がシフト（移動）させた。その結果単に全面
に均一に加熱または光照射するのみに比べ、成長機構が
加わるため結晶粒径を大きくすることができた。In this way, since a large amount of phosphorus is added to the gate electrode side of the gate electrode portion, this electrode sufficiently absorbs light and becomes polycrystalline. Further, the impurity regions (7) and (8) were once melted and recrystallized, thereby causing the melting and recrystallization to shift (move) in the scanning direction, that is, the X direction. As a result, compared to simply uniformly heating or irradiating the entire surface with light, it was possible to increase the crystal grain size because a growth mechanism was added.

この強光アニールにより多結晶化した領域は、不純物領
域の下側の全領域にまで及ぶ必要は必ずしもない。図面
での破線（１１）、　（１１’）に示したごとく、その
上部のみが少なくとも結晶化し不純物が活性になること
が重要である。さらに、その端部（１５）　（１５°）
はゲイト電極の端部（１６）　、　（１６”）に対しチ
ャネル側にわたって設けられ、Ｎ　（７）　、　（８）
−Ｉ　（２）接合界面（１７）、　（１７’）が結晶化
領域内部に設けられ、チャネル形成領域はｌ型半導体の
非単結晶半導体および結晶化半導体によりハイブリッド
構造に設けた。このＩ型半導体内の結晶化半導体の領域
の程度は光アニールの走査スピード、強度（照度）によ
って決めることができる。The region polycrystallized by this intense light annealing does not necessarily need to extend to the entire region below the impurity region. As shown by the broken lines (11) and (11') in the drawing, it is important that at least only the upper portion thereof is crystallized and the impurities are activated. Furthermore, its end (15) (15°)
are provided over the channel side with respect to the ends (16), (16") of the gate electrode, and N (7), (8)
-I (2) Junction interfaces (17) and (17') were provided inside the crystallized region, and the channel formation region was provided in a hybrid structure using a non-single crystal semiconductor of an l-type semiconductor and a crystallized semiconductor. The extent of the crystallized semiconductor region within this I-type semiconductor can be determined by the scanning speed and intensity (illuminance) of optical annealing.

図面においては、この第１図（Ｂ）の工程の後、ＰＴＱ
を全面に２μの厚さにコートし、さらに電極穴（１３）
　（１３’　）に形成した後、アルミニュームのオーム
コンタクトおよびそのリード（１４）　、　（１４”）
を形成している。この２層目の（１４）　、　（１４°
）の形成の際、ゲイト電極（４）と連結してもよい。In the drawing, after the process shown in Figure 1 (B), the PTQ
Coat the entire surface with a thickness of 2μ, and then add electrode holes (13).
(13'), then aluminum ohmic contacts and their leads (14), (14”)
is formed. This second layer (14), (14°
) may be connected to the gate electrode (4).

この光アニールの結果、シート抵抗が光照射前の４ＸＩ
Ｏ−”（Ωｃｍ）　−’よりＩ　ＸＩＯ”（Ωｃｍ）　
−’に比べ光照射アニールの後の電気伝導度特性の変化
により明らかにすることができた。As a result of this photoannealing, the sheet resistance is 4XI
O-"(Ωcm) -'I XIO"(Ωcm)
−' could be clarified by the change in electrical conductivity characteristics after light irradiation annealing.

チャネル形成領域の長さが３μおよび１０μの場合、チ
ャネル中が１ｍｍの条件下において、それぞれ第２図（
２１）、　（２２）に示されるごとく、Ｖｔｈ＝＋２Ｖ
、　ＶＤＤ−１０Ｖ　ニア　１　Ｘｌ０−５Ａ、　２　
Ｘｌ０−５Ａ　（７）電流を得ることができた。When the length of the channel forming region is 3 μ and 10 μ, the length in the channel is 1 mm, as shown in Fig. 2 (
21), (22), Vth=+2V
, VDD-10V Near 1 Xl0-5A, 2
Xl0-5A (7) current could be obtained.

（９） なオオフ電流は（ＶＧＧ＝ＯＶ）　１０−”　〜１０−
”　（八）であり、単結晶半導体の１０−６Ａに比べ１
０−４の１も小さかった。(9) The off-off current is (VGG=OV) 10-” ~10-
” (8), which is 1 compared to 10-6A for single crystal semiconductors.
0-4 1 was also small.

「効果」 本発明は下側から漸次被膜を彫威し加工するという製造
工程を採用したため、大面積大規模集積化を行うことが
可能になった。そのため大面積例えば３０ｃｍ　Ｘ　３
０ｃｍのパネル内に５００　Ｘ５００ケのＩＧＦの作製
すらも可能とすることができ、液晶表示素子の制御用Ｉ
ＧＦとして応用することができた。"Effects" Since the present invention employs a manufacturing process in which the coating is gradually carved and processed from the bottom, it has become possible to perform large-scale integration over a large area. Therefore, the area is large, e.g. 30cm x 3
It is possible to create even 500 x 500 IGFs in a 0cm panel, and it is possible to create IGFs for controlling liquid crystal display elements.
It was possible to apply it as a GF.

光アニールプロセスによる４００℃以下の低温処理であ
るため、多結晶化または単結晶化した半導体がその内部
の水素またはハロゲン元素を放出させることを防ぐこと
ができた。Since the photo-annealing process was performed at a low temperature of 400° C. or lower, it was possible to prevent the polycrystalline or single-crystalline semiconductor from releasing hydrogen or halogen elements therein.

また光アニールを基板全面に同時に行うのではなく一端
より他端に走査させた。この目的のため筒状の超高圧水
銀灯を放物ミラーおよび石英レンズにより集光し、線状
の光とし、この光に対し直交した方向に基板を走査する
ことにより面への光アニールを行うことができた。Furthermore, instead of performing optical annealing on the entire surface of the substrate at the same time, it was scanned from one end to the other. For this purpose, a cylindrical ultra-high pressure mercury lamp is focused using a parabolic mirror and a quartz lens to form linear light, and the surface is optically annealed by scanning the substrate in a direction perpendicular to this light. was completed.

（１０） この光アニールを紫外線で行うため、半導体の表面より
内部方向への結晶化を助長させた。このため十分に多結
晶化または単結晶化した表面近傍の不純物領域へチャネ
ル形成領域におけるゲイト絶縁膜のごく近傍に流れる電
流制御を支障なく行うことが可能となった。(10) Since this optical annealing was performed using ultraviolet rays, crystallization from the surface of the semiconductor toward the inside was promoted. Therefore, it has become possible to control the current flowing in the vicinity of the gate insulating film in the channel forming region to the sufficiently polycrystalline or single crystallized impurity region near the surface without any trouble.

基板として単結晶半導体をまったく用いていない。この
ため光照射アニール工程に際し、チャネル形成領域に添
加された水素またはハロゲン元素はまったく何等の影響
を受けず非単結晶半導体の状態を保持できる。そのため
オフ電流を単結晶半導体の１／１０”〜１／１０５にす
ることができる。No single crystal semiconductor is used as the substrate. Therefore, during the light irradiation annealing step, the hydrogen or halogen element added to the channel forming region is not affected at all and can maintain the state of a non-single crystal semiconductor. Therefore, the off-state current can be reduced to 1/10" to 1/105 of that of a single crystal semiconductor.

ゲイトを作った後ソース、ドレインを光アニールで作製
するため、ゲイト絶縁物界面に汚物が付着することがな
く特性が安定していた。Since the source and drain are fabricated by photo-annealing after forming the gate, there is no dirt attached to the gate insulator interface, and the characteristics are stable.

さらに従来より公知の方法に比べ、基板材料として石英
ガラスのみならず任意の基板であるソーダガラス、耐熱
性有機フィルムをも用いることができる。Furthermore, compared to conventionally known methods, not only quartz glass but also any arbitrary substrate such as soda glass or heat-resistant organic film can be used as the substrate material.

異種材料界面であるチャネル形成領域を構成す（１１） る半導体−ゲイト絶縁物−ゲイト電極の形成と同一反応
炉内でのプロセスにより、大気に触れさせることなく作
り得るため、界面準位の発生が少ないという特長を有す
る。The formation of the semiconductor-gate insulator-gate electrode that constitutes the channel formation region (11), which is the interface between dissimilar materials, can be performed in the same reactor, without exposing it to the atmosphere, thereby reducing the generation of interface states. It has the advantage of having a small amount of

なお本発明において、チャネル形成領域の非単結晶半導
体の酸素、炭素および窒素のいずれもが５　ＸＩＯ”ｃ
ｍ−”以下の不純物濃度であることが好ましい。即ちこ
れらが従来公知のＩＧＦにおいてはチャネル層に１〜３
　Ｘ　１０”ｃｍ−３の濃度に混合してしまった。アモ
ルファス珪素半導体を用いる場合においては、キャリア
特にホールのもつライフタイムが短くなり、特性が本発
明が有する特性のｌ／３以下の電流しか流れない。加え
てヒステリシス特性をＩＤＤ　Ｖ６６特性にドレイン電
界を２Ｘ１０６Ｖ／ｃｍ以上加える場合に観察されてし
まった。また他方酸素を５　Ｘｌ０１８ｃｍ−３以下と
すると、３Ｘ１０’Ｖ／Ｃｌ１１の電圧においてもヒス
テリシスの存在が観察されなかったIn the present invention, all of oxygen, carbon and nitrogen in the non-single crystal semiconductor in the channel forming region are 5XIO"c
It is preferable that the impurity concentration be less than
When using an amorphous silicon semiconductor, the lifetime of carriers, especially holes, is shortened, and the current characteristics are only 1/3 or less of the characteristics of the present invention. In addition, hysteresis characteristics were observed when applying a drain electric field of 2X106V/cm or more to the IDD V66 characteristics.On the other hand, when oxygen was set to 5X1018cm-3 or less, hysteresis was observed even at a voltage of 3X10'V/Cl11. the presence of was not observed

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の絶縁ゲイト型電界効果半導体（１２） 装置の製造工程の縦断面図を示す。 第２図はドレイン電流−ゲイト電圧の特性を示す。 特許出願人 （１３） 不１図 Figure 1 shows an insulated gate field effect semiconductor (12) of the present invention. FIG. 3 shows a longitudinal cross-sectional view of the manufacturing process of the device. FIG. 2 shows the drain current-gate voltage characteristics. patent applicant (13) No 1 drawing

Claims (1)

【特許請求の範囲】 １、基板上に水素またはハロゲン元素が添加された非単
結晶半導体を形成する工程と、該半導体上にゲイト絶縁
膜を形成する工程と、該絶縁膜上に選択的にゲイト電極
を形成する工程と、該ゲイト電極をマスクとして前記非
単結晶半導体にＰまたはＮ型用の不純物を添加する工程
と、該工程の後、強光照射をして前記不純物の添加され
た領域の結晶化を助長せしめた工程とを有することを特
徴とする絶縁ゲイト型電界効果半導体装置の作製方法。 ２、特許請求の範囲第１項において、ＰまたはＮ型用の
不純物はゲイト絶縁膜を透過して添加され、前記ゲイト
絶縁膜は強光照射において水素またはハロゲン元素の脱
気防止用被膜として構成されたことを特徴とする絶縁ゲ
イト型電界効果半導体装置の作製方法。[Claims] 1. A step of forming a non-single crystal semiconductor doped with hydrogen or a halogen element on a substrate, a step of forming a gate insulating film on the semiconductor, and a step of selectively forming a gate insulating film on the insulating film. a step of forming a gate electrode, a step of adding an impurity for P or N type to the non-single crystal semiconductor using the gate electrode as a mask, and after the step, applying strong light irradiation to add the impurity. 1. A method for manufacturing an insulated gate field effect semiconductor device, comprising the step of promoting crystallization of a region. 2. In claim 1, the impurity for P or N type is added through a gate insulating film, and the gate insulating film is configured as a film for preventing hydrogen or halogen elements from degassing when irradiated with strong light. A method for manufacturing an insulated gate field effect semiconductor device, characterized in that:
JP10025284A 1984-05-18 1984-05-18 Manufacture of insulated gate type semiconductor device Pending JPS60245174A (en)

Priority Applications (12)

Application Number Priority Date Filing Date Title
JP10025284A JPS60245174A (en) 1984-05-18 1984-05-18 Manufacture of insulated gate type semiconductor device
US06/912,498 US4727044A (en) 1984-05-18 1986-09-29 Method of making a thin film transistor with laser recrystallized source and drain
US07/153,477 US4959700A (en) 1984-05-18 1988-02-03 Insulated gate field effect transistor and its manufacturing method
US07/707,178 US5142344A (en) 1984-05-18 1991-05-24 Insulated gate field effect transistor and its manufacturing method
US07/987,179 US5315132A (en) 1984-05-18 1992-12-08 Insulated gate field effect transistor
US08/054,842 US5313077A (en) 1984-05-18 1993-04-30 Insulated gate field effect transistor and its manufacturing method
US08/171,769 US6660574B1 (en) 1984-05-18 1993-12-22 Method of forming a semiconductor device including recombination center neutralizer
US08/473,953 US5543636A (en) 1984-05-18 1995-06-07 Insulated gate field effect transistor
US08/944,136 US6680486B1 (en) 1984-05-18 1997-10-06 Insulated gate field effect transistor and its manufacturing method
US08/947,731 US6221701B1 (en) 1984-05-18 1997-10-16 Insulated gate field effect transistor and its manufacturing method
US09/406,794 US6635520B1 (en) 1984-05-18 1999-09-28 Operation method of semiconductor devices
US09/406,791 US6734499B1 (en) 1984-05-18 1999-09-28 Operation method of semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10025284A JPS60245174A (en) 1984-05-18 1984-05-18 Manufacture of insulated gate type semiconductor device

Related Child Applications (3)

Application Number Title Priority Date Filing Date
JP4333726A Division JP2648785B2 (en) 1992-11-20 1992-11-20 Method for manufacturing insulated gate field effect semiconductor device
JP6314315A Division JP2789171B2 (en) 1994-11-25 1994-11-25 Method for manufacturing insulated gate field effect semiconductor device
JP6314314A Division JP2789170B2 (en) 1994-11-25 1994-11-25 Method for manufacturing insulated gate field effect semiconductor device

Publications (1)

Publication Number Publication Date
JPS60245174A true JPS60245174A (en) 1985-12-04

Family

ID=14269029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10025284A Pending JPS60245174A (en) 1984-05-18 1984-05-18 Manufacture of insulated gate type semiconductor device

Country Status (1)

Country Link
JP (1) JPS60245174A (en)

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62214669A (en) * 1986-03-14 1987-09-21 Nec Corp Self-aligned amorphous silicon thin film transistor and manufacture thereof
JPH05283694A (en) * 1991-08-23 1993-10-29 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacture thereof
JPH0621096A (en) * 1991-05-11 1994-01-28 Semiconductor Energy Lab Co Ltd Manufacture of insulation gate type field effect transistor
JPH06296023A (en) * 1993-02-10 1994-10-21 Semiconductor Energy Lab Co Ltd Thin-film semiconductor device and manufacture thereof
JPH07111334A (en) * 1993-08-20 1995-04-25 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacture thereof
US5523240A (en) * 1990-05-29 1996-06-04 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor with a halogen doped blocking layer
US5849601A (en) * 1990-12-25 1998-12-15 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for manufacturing the same
US5859445A (en) * 1990-11-20 1999-01-12 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device including thin film transistors having spoiling impurities added thereto
US5946561A (en) * 1991-03-18 1999-08-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US5962870A (en) * 1991-08-26 1999-10-05 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices
US5962897A (en) * 1992-06-18 1999-10-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US6013928A (en) * 1991-08-23 2000-01-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having interlayer insulating film and method for forming the same
US6147375A (en) * 1992-02-05 2000-11-14 Semiconductor Energy Laboratory Co., Ltd. Active matrix display device
US6204099B1 (en) 1995-02-21 2001-03-20 Semiconductor Energy Laboratory Co., Ltd. Method for producing insulated gate thin film semiconductor device
US6323069B1 (en) 1992-03-25 2001-11-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor using light irradiation to form impurity regions
US6331717B1 (en) 1993-08-12 2001-12-18 Semiconductor Energy Laboratory Co. Ltd. Insulated gate semiconductor device and process for fabricating the same
US6448577B1 (en) 1990-10-15 2002-09-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with grain boundaries
US6479329B2 (en) 1994-09-16 2002-11-12 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device
US6482752B1 (en) * 1993-10-26 2002-11-19 Semiconductor Energy Laboratory Co., Ltd. Substrate processing apparatus and method and a manufacturing method of a thin film semiconductor device
US6500704B1 (en) 1995-07-03 2002-12-31 Sanyo Electric Co., Ltd Semiconductor device, display device and method of fabricating the same
US6500703B1 (en) 1993-08-12 2002-12-31 Semicondcutor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and process for fabricating the same
US6624477B1 (en) 1992-10-09 2003-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US6660575B1 (en) 1991-10-04 2003-12-09 Semiconductor Energy Laboratory Co., Ltd. Method for forming a semiconductor device
US6790714B2 (en) 1995-07-03 2004-09-14 Sanyo Electric Co., Ltd. Semiconductor device, display device and method of fabricating the same
US6797550B2 (en) 2001-12-21 2004-09-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method therefor
US6911358B2 (en) 2001-12-28 2005-06-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7554616B1 (en) 1992-04-28 2009-06-30 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582073A (en) * 1981-06-29 1983-01-07 Sony Corp Field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582073A (en) * 1981-06-29 1983-01-07 Sony Corp Field effect transistor

Cited By (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62214669A (en) * 1986-03-14 1987-09-21 Nec Corp Self-aligned amorphous silicon thin film transistor and manufacture thereof
US6607947B1 (en) 1990-05-29 2003-08-19 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device with fluorinated layer for blocking alkali ions
US7355202B2 (en) 1990-05-29 2008-04-08 Semiconductor Energy Co., Ltd. Thin-film transistor
US5523240A (en) * 1990-05-29 1996-06-04 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor with a halogen doped blocking layer
US6448577B1 (en) 1990-10-15 2002-09-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with grain boundaries
US6011277A (en) * 1990-11-20 2000-01-04 Semiconductor Energy Laboratory Co., Ltd. Gate insulated field effect transistors and method of manufacturing the same
US5859445A (en) * 1990-11-20 1999-01-12 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device including thin film transistors having spoiling impurities added thereto
US5849601A (en) * 1990-12-25 1998-12-15 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for manufacturing the same
US5946561A (en) * 1991-03-18 1999-08-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
JP2561572B2 (en) * 1991-05-11 1996-12-11 株式会社半導体エネルギー研究所 Method for manufacturing insulated gate field effect transistor
JPH0621096A (en) * 1991-05-11 1994-01-28 Semiconductor Energy Lab Co Ltd Manufacture of insulation gate type field effect transistor
JPH05283694A (en) * 1991-08-23 1993-10-29 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacture thereof
US6013928A (en) * 1991-08-23 2000-01-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having interlayer insulating film and method for forming the same
US6331723B1 (en) 1991-08-26 2001-12-18 Semiconductor Energy Laboratory Co., Ltd. Active matrix display device having at least two transistors having LDD region in one pixel
US7821011B2 (en) 1991-08-26 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices and method of manufacturing the same
US5962870A (en) * 1991-08-26 1999-10-05 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices
US6803600B2 (en) 1991-08-26 2004-10-12 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices and method of manufacturing the same
US6919239B2 (en) 1991-10-04 2005-07-19 Semiconductor Energy Laboratory Co., Ltd. Method for forming a semiconductor device
US6660575B1 (en) 1991-10-04 2003-12-09 Semiconductor Energy Laboratory Co., Ltd. Method for forming a semiconductor device
US6147375A (en) * 1992-02-05 2000-11-14 Semiconductor Energy Laboratory Co., Ltd. Active matrix display device
US6476447B1 (en) 1992-02-05 2002-11-05 Semiconductor Energy Laboratory Co., Ltd. Active matrix display device including a transistor
US6323069B1 (en) 1992-03-25 2001-11-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor using light irradiation to form impurity regions
US6887746B2 (en) 1992-03-25 2005-05-03 Semiconductor Energy Lab Insulated gate field effect transistor and method for forming the same
US6569724B2 (en) 1992-03-25 2003-05-27 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor and method for forming the same
US7554616B1 (en) 1992-04-28 2009-06-30 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US5962897A (en) * 1992-06-18 1999-10-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US6455875B2 (en) 1992-10-09 2002-09-24 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor having enhanced field mobility
US7602020B2 (en) 1992-10-09 2009-10-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US7723788B2 (en) 1992-10-09 2010-05-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US7109108B2 (en) 1992-10-09 2006-09-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device having metal silicide
US6624477B1 (en) 1992-10-09 2003-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US8017506B2 (en) 1992-10-09 2011-09-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US6790749B2 (en) 1992-10-09 2004-09-14 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
JPH06296023A (en) * 1993-02-10 1994-10-21 Semiconductor Energy Lab Co Ltd Thin-film semiconductor device and manufacture thereof
US6331717B1 (en) 1993-08-12 2001-12-18 Semiconductor Energy Laboratory Co. Ltd. Insulated gate semiconductor device and process for fabricating the same
US6500703B1 (en) 1993-08-12 2002-12-31 Semicondcutor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and process for fabricating the same
US7381598B2 (en) 1993-08-12 2008-06-03 Semiconductor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and process for fabricating the same
US6437366B1 (en) 1993-08-12 2002-08-20 Semiconductor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and process for fabricating the same
JPH07111334A (en) * 1993-08-20 1995-04-25 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacture thereof
US7691692B2 (en) 1993-10-26 2010-04-06 Semiconductor Energy Laboratory Co., Ltd. Substrate processing apparatus and a manufacturing method of a thin film semiconductor device
US8304350B2 (en) 1993-10-26 2012-11-06 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US7452794B2 (en) 1993-10-26 2008-11-18 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of a thin film semiconductor device
US7271082B2 (en) 1993-10-26 2007-09-18 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US6482752B1 (en) * 1993-10-26 2002-11-19 Semiconductor Energy Laboratory Co., Ltd. Substrate processing apparatus and method and a manufacturing method of a thin film semiconductor device
US7229861B2 (en) 1994-09-16 2007-06-12 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device
US6479329B2 (en) 1994-09-16 2002-11-12 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device
US6709905B2 (en) 1995-02-21 2004-03-23 Semiconductor Energy Laboratory Co., Ltd. Method for producing insulated gate thin film semiconductor device
US6204099B1 (en) 1995-02-21 2001-03-20 Semiconductor Energy Laboratory Co., Ltd. Method for producing insulated gate thin film semiconductor device
US7045403B2 (en) 1995-02-21 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Method for producing insulated gate thin film semiconductor device
US6921686B2 (en) 1995-02-21 2005-07-26 Semiconductor Energy Laboratory Co., Ltd. Method for producing insulated gate thin film semiconductor device
US6265745B1 (en) 1995-02-21 2001-07-24 Semiconductor Energy Laboratory Co., Ltd. Method for producing insulated gate thin film semiconductor device
US7615423B2 (en) 1995-02-21 2009-11-10 Semiconductor Energy Laboratory Co., Ltd. Method for producing insulated gate thin film semiconductor device
US7084052B2 (en) 1995-07-03 2006-08-01 Sanyo Electric Co., Ltd. Semiconductor device, display device and method of fabricating the same
US6790714B2 (en) 1995-07-03 2004-09-14 Sanyo Electric Co., Ltd. Semiconductor device, display device and method of fabricating the same
US6500704B1 (en) 1995-07-03 2002-12-31 Sanyo Electric Co., Ltd Semiconductor device, display device and method of fabricating the same
US6797550B2 (en) 2001-12-21 2004-09-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method therefor
US7319055B2 (en) 2001-12-21 2008-01-15 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a semiconductor device utilizing crystallization of semiconductor region with laser beam
US7635883B2 (en) 2001-12-28 2009-12-22 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7129121B2 (en) 2001-12-28 2006-10-31 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US6911358B2 (en) 2001-12-28 2005-06-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device

Similar Documents

Publication Publication Date Title
JPS60245174A (en) Manufacture of insulated gate type semiconductor device
JPS60245173A (en) Insulated gate type semiconductor device
JPS60245172A (en) Insulated gate type semiconductor device
US6806169B2 (en) Semiconductor device manufacturing method
JP3221251B2 (en) Amorphous silicon crystallization method and thin film transistor manufacturing method
JP2789168B2 (en) Method for manufacturing insulated gate field effect semiconductor device for liquid crystal display panel
JP3125982B2 (en) Insulated gate field effect semiconductor device
JP3127441B2 (en) Method for manufacturing insulated gate field effect semiconductor device
JP3125981B2 (en) Insulated gate field effect semiconductor device
JP2996887B2 (en) Insulated gate field effect semiconductor device
JP2996854B2 (en) Method for manufacturing insulated gate field effect semiconductor device
JP2648785B2 (en) Method for manufacturing insulated gate field effect semiconductor device
JP3125989B2 (en) Method for manufacturing insulated gate field effect semiconductor device
JP2648783B2 (en) Insulated gate field effect semiconductor device for liquid crystal display panel
JP2648788B2 (en) Insulated gate field effect semiconductor device
JPH10340855A (en) Crystallizing method of semiconductor thin film and manufacture of thin film transistor using the same
JP3125983B2 (en) Method for manufacturing insulated gate field effect semiconductor device
JP2789170B2 (en) Method for manufacturing insulated gate field effect semiconductor device
JP2001094119A (en) Insulated-gate field effect semiconductor device
JPH01200673A (en) Manufacture of semiconductor device
JP3383262B2 (en) Driving method of insulated gate field effect semiconductor device
JP2000315801A (en) Insulated gate field effect semiconductor device
JP2789171B2 (en) Method for manufacturing insulated gate field effect semiconductor device
JP2000077673A (en) Manufacture of liquid crystal panel
JP2996888B2 (en) Insulated gate field effect semiconductor device