JP3221251B2 - Amorphous silicon crystallization method and thin film transistor manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for crystallizing amorphous silicon used in a semiconductor device and a method for manufacturing a thin film transistor.

[0002]

2. Description of the Related Art Conventional methods for crystallizing an amorphous silicon layer include (a) a method of crystallizing an amorphous silicon layer by heating the same in a furnace; There is a method in which the amorphous silicon layer is melt-regrown and crystallized by irradiating a laser beam.

[0003]

However, since the method (a) described in the above prior art method uses solid phase growth, a high temperature of about 600 ° C. is required as the growth temperature. At this temperature, an inexpensive glass substrate cannot be used as the base on which the amorphous silicon layer is formed.
When this method is used, it is necessary to use expensive quartz glass, so that the cost is extremely high.
Therefore, there is a significant obstacle in terms of cost reduction in manufacturing a liquid crystal display device utilizing crystallization of an amorphous silicon layer.

The method (b) described in the above prior art is a so-called low-temperature process, so that a glass substrate can be used as a base on which an amorphous silicon layer is formed.
However, the crystal grain size of the polycrystalline silicon layer formed by crystallization is small. Therefore, when a crystallized silicon layer is used for a channel region of a transistor,
Carrier mobility is limited. In addition, very high temperatures are required to melt amorphous silicon. As a result, liquid silicon is temporarily present, so that the silicon layer to be crystallized is contaminated by the underlying material. Also, the interface between the lower layer and the silicon layer to be crystallized is damaged. As described above, when the channel region of the thin film transistor is formed using a silicon layer which is contaminated by impurities, the performance of the thin film transistor which depends on the purity and uniformity of silicon in the channel region is deteriorated.

An object of the present invention is to provide a laser solid-phase crystallization method of amorphous silicon and a method of manufacturing a thin film transistor, which enable crystallization of an amorphous silicon layer having excellent crystallinity in a low-temperature process. I do.

[0006]

SUMMARY OF THE INVENTION The present invention is a method for achieving the above object. That is, as a method of crystallizing amorphous silicon, in a first step, a first amorphous silicon layer containing impurities and a second amorphous silicon layer bonded to it and containing no impurities are formed on a substrate. Is formed, the first amorphous silicon layer is selectively irradiated with laser light to be modified into a crystalline silicon layer. Then, in the second step, by selectively heating the crystalline silicon layer, a crystal is grown on the second amorphous silicon layer from the interface between the crystalline silicon layer and the second amorphous silicon layer, and crystallized. I do. The selective heating is performed by laser beam irradiation.

As a method of manufacturing a thin film transistor (hereinafter referred to as a TFT), a bottom gate type TFT includes:
In a first step, a gate electrode and a gate dielectric layer covering the gate electrode are formed on a transparent substrate having at least an insulating surface, and a first amorphous silicon layer containing impurities is formed thereon. After that, the first amorphous silicon layer on the gate electrode is removed. Next, in a second step, a second amorphous silicon layer containing no impurities is formed on the gate dielectric layer so as to cover the first amorphous silicon layer. Subsequently, in a third step, the first amorphous silicon layer and the second amorphous silicon layer thereover are selectively crystallized by irradiating laser light from the transparent substrate side using the gate electrode as a mask. I do. At the same time, impurities in the first amorphous silicon layer are diffused into the second amorphous silicon layer to form source / drain regions. Thereafter, in a fourth step, the source / drain region is heated by irradiating laser light from the transparent substrate side, so that the interface between the source / drain region and the second amorphous silicon layer allows the inside of the second amorphous silicon layer to be heated. The crystal is grown toward and crystallized to form a channel region.

As another method of manufacturing a TFT, in a top gate type TFT, in a first step, an amorphous silicon layer containing no impurities and a gate dielectric layer are laminated on a substrate having at least an insulating surface. . Next, in a second step, after forming a gate electrode on a part of the gate dielectric layer, impurities are introduced into the amorphous silicon layer using the gate electrode as a mask. Subsequently, in a third step, the amorphous silicon layer is crystallized by irradiating a laser beam using the gate electrode as a mask to form source / drain regions made of polycrystalline silicon. Thereafter, in a fourth step, the source / drain regions are selectively heated by laser light irradiation using the gate electrode as a mask, so that the interface between the source / drain regions and the amorphous silicon layer enters the amorphous silicon layer. The crystal is grown and crystallized to form a channel region.

[0009]

According to the above-mentioned method for crystallizing amorphous silicon, the first amorphous silicon layer containing impurities is selectively irradiated with laser light to reform the crystalline silicon layer. Is crystallized. Then, the crystalline silicon layer is selectively heated to grow a crystal from the interface between the crystalline silicon layer and the second amorphous silicon layer containing no impurity on the second amorphous silicon layer and crystallize. Therefore, the crystal grown in the second amorphous silicon layer becomes large crystal grains. By performing this heating by laser beam irradiation, a so-called low-temperature process is achieved.

In the method of manufacturing the bottom gate type TFT, a laser beam is irradiated from the transparent substrate side using the gate electrode as a mask to form the first amorphous silicon layer and the second amorphous silicon layer thereabove. Since the source / drain regions are formed by selective crystallization, crystallization can be performed by a low-temperature process, and impurity diffusion for forming the source / drain regions can be performed. Then, the source / drain regions are heated by irradiating laser light from the transparent substrate side, and crystals are grown from the interface between the source / drain regions and the second amorphous silicon layer into the second amorphous silicon layer. As a result, the crystal grown in the second amorphous silicon layer becomes large crystal grains.

In the above method of manufacturing a top gate type TFT, the amorphous silicon layer doped with impurities is crystallized and the source / drain regions are formed by irradiating laser light with the gate electrode as a mask. Crystallized in a low temperature process. Then, laser light is irradiated using the gate electrode as a mask, the source / drain regions are heated, and the crystal is grown from the interface between the source / drain regions and the amorphous silicon layer into the amorphous silicon layer. Therefore, the crystal grown on the amorphous silicon layer becomes large crystal grains.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment relating to a method of crystallizing amorphous silicon according to the present invention will be described with reference to the crystallization process diagram of FIG.

As shown in FIG. 1A, in a first step, a first amorphous silicon layer 1 containing impurities is formed on a substrate 11.
2 and a second amorphous silicon layer 13 which is bonded to the first amorphous silicon layer 12 and contains no impurities. The first and second amorphous silicon layers 12 and 13 are formed, for example, as follows.

The first amorphous silicon layer 12 containing impurities is formed on the substrate 11 by a film forming technique using a low-temperature process such as sputtering or plasma CVD. The base 11 has a light shielding pattern 2 on a transparent substrate 21.
2 is formed, and a dielectric layer 23 is formed so as to cover the light shielding pattern 22. Therefore, the first amorphous silicon layer 12 is formed on the dielectric layer 23. Subsequently, the first amorphous silicon layer 12 on the light shielding pattern 22 is removed by, for example, lithography and etching. Then, for example, sputtering,
A second amorphous silicon layer 13 containing no impurities is formed on the base 11 in a state of covering the first amorphous silicon layer 12 by a film forming technique using a low-temperature process such as a plasma CVD method.

Then, as shown in FIG. 1 (2), the first amorphous silicon layer (12) is selectively irradiated with a laser beam L1. At this time, since the laser beam L1 is irradiated from the base 11 side, a part is blocked by the light shielding pattern 22. Therefore, the first amorphous silicon layer (12)
And an upper second amorphous silicon layer (13), and the first and second amorphous silicon layers (1
2, 13) undergo a melt-regrowth reaction and are transformed into a crystalline silicon layer 14. At this time, some of the impurities contained in the first amorphous silicon layer (12) are diffused into the second amorphous silicon layer (13) thereabove. The impurity contained in the first amorphous silicon layer (12) is the second amorphous silicon layer in the lateral direction because the first and second amorphous silicon layers 12 and 13 are thin. 13 hardly diffuses. Thus, the second amorphous silicon layer 13 containing no impurity and the crystalline silicon layer 14 containing the impurity bonded thereto are formed.

Next, a second step shown in FIG. 1C is performed. In this step, the crystalline silicon layer 14 is selectively heated. As the method, for example, the laser beam L2 is irradiated from the base 11 side. The laser beam L2 had an energy density that did not melt the crystalline silicon layer 14. Therefore, the laser light L2 is blocked by the light-shielding pattern 22, is irradiated to the crystalline silicon layer 14, and the crystalline silicon layer 14 is directly heated. Then, a crystal grows from the interface between the crystalline silicon layer 14 and the second amorphous silicon layer (13) toward the second amorphous silicon layer (13) (in the direction of arrow A). As described above, the laser-induced solid-phase crystallization (solid-phase growth) causes large crystal grains to grow from the small crystal grains at the interface. As a result, the second amorphous silicon layer (13) is crystallized and reformed into a polycrystalline silicon layer 15 having large crystal grains.

Next, the temperature distribution (1) and the crystallization state (2) in the second amorphous silicon layer 13 and the crystalline silicon layer 14 being irradiated with the laser beam L2 will be described with reference to FIG. I do. In the figure, the same components as those described in FIG. 1 are denoted by the same reference numerals. Here, the dielectric layer 23 is amorphous and has a thermal conductivity substantially equal to that of the second amorphous silicon layer 13.

As shown in FIG. 2, when the polycrystalline silicon layer 14 is heated by the irradiation of the laser beam L2, the heat flow in the vertical direction is regulated by the dielectric layer 23 formed on the surface of the transparent substrate 11. You. That is, heat is applied to the dielectric layer 2
3, the tendency to flow in the surface direction increases. Therefore, heat can easily flow at the interface between the polycrystalline silicon layer 14 and the second amorphous silicon layer 13. Further, since the second amorphous silicon layer 13 has a low thermal conductivity, the temperature gradient across the interface becomes large.

The temperature at the interface determines the speed at which crystallization proceeds toward the inside of the second amorphous silicon layer 13. Since the thermal conductivity of the second amorphous silicon layer 13 is lower than that of the polycrystalline silicon layer 14, the temperature rise of the second amorphous silicon layer 13 is slower. Therefore, nucleation of crystals having strong temperature dependence is suppressed. In the case of crystallization of the second amorphous silicon layer 13, large crystalline grains grow by activation energy of, for example, about 5 eV to form the crystalline silicon layer 15. Further, the magnitude of the thermal diffusion length of amorphous silicon relative to polycrystalline silicon (thermal diffusion length: 400 nm) is important, and its value is determined by the upper limit of the length of the second amorphous silicon layer 13 to be crystallized. decide. For example, assuming that thermal diffusion occurs from the crystalline silicon layers 14 on both sides, the upper limit is about 1 μm. If it is longer than that, the central portion of the second amorphous silicon layer 13 may not be sufficiently crystallized.

Next, in the case of a thin film transistor (hereinafter, referred to as TFT), the light-shielding pattern 22 described with reference to FIG. 1 is formed as a gate electrode. For this reason, since the gate electrode is formed of a metal such as molybdenum, the heat flow from the gate electrode must be considered. In particular, a metal gate electrode such as molybdenum has a large absorption coefficient over a wide wavelength range. Therefore, the heat flow absorbed by the gate electrode and emitted therefrom promotes crystallization of the second amorphous silicon layer 13 via the dielectric layer 23.
Also, it takes time for the heat released from the gate electrode to pass through the dielectric layer 23. Therefore, most of the heat reaches the second amorphous silicon layer 13 after the irradiation of one pulse of the laser beam L2 is completed, and thus the high-temperature region is widened. As a result, the crystallization of the second amorphous silicon layer 13 is further promoted.

Next, a method of manufacturing a bottom-gate TFT to which the method of crystallizing amorphous silicon described in FIG. 1 is applied will be described with reference to a manufacturing process diagram of FIG.

As shown in FIG. 3A, in the first step, a gate electrode 32 and a gate dielectric layer 33 covering the gate electrode 32 are formed on the surface of the transparent substrate 31 by a normal process. The transparent substrate 31 is formed by forming a light-transmitting buffer layer (not shown) on a glass substrate. Therefore, the transparent substrate 31 transmits a laser beam described later. Further, for example, sputtering, plasma CV
A first amorphous silicon layer 34 containing impurities is formed on the gate dielectric layer 33 by a low-temperature film forming technique such as a method D (for example, the film forming temperature is 500 ° C. or lower). Thereafter, the gate electrode 3 is formed by lithography and etching.
The first amorphous silicon layer 34 (portion indicated by a two-dot chain line) on the second substrate 2 is removed.

Next, a second step shown in FIG. 3B is performed. In this step, for example, sputtering, plasma C
The second amorphous silicon layer that covers the first amorphous silicon layer 34 and does not contain impurities is formed on the gate dielectric layer 33 by a low-temperature film forming technique such as a VD method (for example, the film forming temperature is 500 ° C. or less). The layer 35 is formed.

Subsequently, a third step shown in FIG. In this step, laser light L3 is irradiated from the transparent substrate 31 side using the gate electrode 32 as a mask. The laser beam L3 has, for example, an energy density of 200 mJ.
/ Cm ² -1 J / cm ² , pulse width 10 ns-500 μs
Is used. At this time, since the gate electrode 32 serves as a mask, the laser light L3 is irradiated to the first amorphous silicon layer (34) and the second amorphous silicon layer (35) thereover, so that the gate electrode 32 The portion of the second amorphous silicon layer 35 blocked by the laser beam L3 is not irradiated.

As a result, the first laser beam L3 irradiated
The portion of the amorphous silicon layer (34) and the upper portion of the second amorphous silicon layer (35) are selectively melted, and the crystal is regrown and crystallized. At the same time, impurities (not shown) in the first amorphous silicon layer (34) are removed from the second amorphous silicon layer (34).
The source / drain regions 36 and 37 are formed by diffusing into the amorphous silicon layer (35). On the other hand, the second amorphous silicon layer 35 not irradiated with the laser beam L3 is not crystallized.

Thereafter, a fourth step shown in FIG. 3D is performed. In this step, the source / drain regions 36 and 37 are heated by irradiating a laser beam L4 from the transparent substrate 31 side. As a result, solid phase crystallization (solid phase growth) starts from the crystal nuclei at the interface between the source / drain regions 36 and 37 and the second amorphous silicon layer (35). Then, the crystal grows in the second amorphous silicon layer (35) inward, and the second amorphous silicon layer (35) becomes a polycrystalline silicon layer. This polycrystalline silicon layer becomes the channel region 38. The source / drain regions 36 and 37 are activated by the irradiation of the laser beam L4. As described above, the bottom gate type TFT 30 is manufactured.

The energy density of the laser beam L4 is selected to be lower than the melting threshold energy of polycrystalline silicon (the melting point of crystalline silicon is 1410 ° C.). For example, the laser light L4 has a pulse width of 30 ns and a duty factor of 1
0 ^-6 excimer laser light. And the transparent substrate 31
Is formed from a glass substrate and a sufficiently thick transparent buffer layer formed on its surface, instantaneous heating is required so that the temperature of the glass substrate does not exceed its softening point. This is the same in the melt-regrowth process using the laser beam L3.

When laser light having a small duty factor and a short pulse width is used, the irradiated portion is in thermal equilibrium when each pulse rises. But,
Second amorphous silicon layer 35 and source / drain region 3
Since it takes time until the temperature of the interface with 6, 37 becomes high, the crystallization process becomes extremely slow. Therefore, in the case of annealing by irradiating a pulse laser beam, the duty time of the excimer laser beam and the instantaneous growth rate are:
Both must be determined in consideration of the actual growth rate.

In the method of manufacturing the bottom gate type TFT 30, the first amorphous silicon layer 34 is irradiated with the laser beam L3 from the transparent substrate 31 side using the gate electrode 32 as a mask.
And the second amorphous silicon layer 35 thereon are selectively crystallized to form the source / drain regions 36 and 37, so that crystallization can be performed by a low-temperature process and the source / drain regions 36 and 37 can be formed. Impurity diffusion for formation can be performed. Then, the source / drain regions 36 and 37 are heated by irradiating a laser beam L4 from the transparent substrate 31 side, and the source / drain regions 36 and 37 are heated.
Since the crystal is solid-phase grown and crystallized from the interface between the drain regions 36 and 37 and the second amorphous silicon layer 35 into the second amorphous silicon layer 35, the second amorphous silicon layer The crystal growing at 35 becomes large crystal grains.

In the method of manufacturing the TFT 30, as described with reference to FIG.
The crystallization of the amorphous silicon layer 35 is suitable when the length of the second amorphous silicon layer 35 to be crystallized is about 1 μm or less.

Next, a method of manufacturing a top gate type TFT to which the method of crystallizing amorphous silicon described in FIG. 1 is applied will be described with reference to a manufacturing process diagram of FIG.

As shown in FIG. 4A, in the first step, a low-temperature film forming technique such as sputtering or plasma CVD (for example, a film forming temperature of 500 ° C. or lower) is used.
An amorphous silicon layer 52 containing no impurities is formed on a base 51. The base 51 includes, for example, a glass substrate 53 and a buffer layer 54 made of, for example, silicon nitride formed on the upper surface thereof. Thereafter, a low-temperature film forming technique such as sputtering or plasma CVD (for example, when the film forming temperature is 50
(0 ° C. or lower) to form a gate dielectric layer 55 on the amorphous silicon layer 52.

Next, a second step shown in FIG. In this step, the gate dielectric layer 55 is formed by a normal process (film formation-lithography-etching).
A gate electrode 56 is formed on the upper part. After that, an impurity 57 is introduced into the amorphous silicon layer 52 using the gate electrode 56 as a mask by an impurity introduction technique such as an ion implantation method or a plasma doping method.

Subsequently, a third step shown in FIG. 4C is performed. In this step, laser light L5 is irradiated using the gate electrode 56 as a mask. As a result, the amorphous silicon layer (52) is melt-regrown and crystallized to become the source / drain regions 58 and 59 made of polycrystalline silicon. The irradiation of the laser light L5 activates the impurities introduced into the source / drain regions 58 and 59. At this time, since the laser beam L5 is blocked by the gate electrode 56, the amorphous silicon layer 52 below the gate electrode 56 is not crystallized.

Thereafter, a fourth step shown in FIG. In this step, the laser light L6 is irradiated using the gate electrode 56 as a mask. And the source / drain region 5
8 and 59, by selectively heating the amorphous silicon layer (5) from small crystal grains at the interface between the source / drain regions 58 and 59 and the amorphous silicon layer (52).
2) Solid phase growth of a crystal in the inside (laser induced solid phase crystallization). The amorphous silicon layer (52) is crystallized to form a polycrystalline silicon channel region 60 composed of large crystal grains.
To form As described above, the top gate type TFT 5
0 is formed.

In the method of manufacturing the top gate type TFT 50, the laser light L5 is irradiated using the gate electrode 56 as a mask.
2 and the source / drain regions 58 and 59 can be formed by a low-temperature process. Then, the source / drain regions 58 and 59 are heated by irradiating the laser beam L 6 with the gate electrode 56 as a mask, so that the amorphous silicon layer 52 is removed from the interface between the source / drain regions 58 and 59 and the amorphous silicon layer 52. Crystals are solid-phase grown into the layer 52. As a result, the amorphous silicon layer 52 is crystallized, and its crystals become large crystal grains.

In the above-described method of manufacturing the TFT 50, the crystallization of the amorphous silicon layer 52 by solid-phase growth is performed by the length of the amorphous silicon layer 52 to be crystallized, as described with reference to FIG. Is approximately 1 μm or less.

[0038]

As described above, according to the first and second aspects of the present invention, the crystalline silicon layer is formed by selectively irradiating the first amorphous silicon layer containing impurities with laser light. , It can be crystallized by a low-temperature process. Then, the crystalline silicon layer is selectively heated to grow a crystal from the interface between the crystalline silicon layer and the second amorphous silicon layer in the second amorphous silicon layer and to crystallize the same. Thus, polycrystalline silicon having large crystal grains can be formed.

According to the third aspect of the invention relating to the method of manufacturing a TFT, the source / drain region formed by laser crystallization is selectively irradiated with laser light from the transparent substrate side and heated, so that the source / drain region and the second region are formed. Since the crystal is grown and crystallized from the interface with the second amorphous silicon layer into the second amorphous silicon layer, it is possible to form the second amorphous silicon layer with large crystal grains. it can. Therefore, the polycrystalline silicon layer formed by this crystallization becomes a channel region where the mobility of carriers is large, so that a high-performance TFT can be manufactured. In addition, since it can be manufactured by a low-temperature process, an inexpensive glass substrate can be used. Therefore, the manufacturing cost can be reduced.

According to the invention relating to the method of manufacturing a TFT according to the fourth aspect, similarly to the above, the source / drain region is heated by selectively irradiating the laser beam, and the amorphous silicon Since the crystal is grown toward the layer, it can be modified into a polycrystalline silicon layer having large crystal grains. Therefore, this amorphous silicon layer becomes a channel region where the carrier mobility is large, so that the high-performance TF
T can be manufactured. In addition, since it can be manufactured by a low-temperature process, an inexpensive glass substrate can be used. Therefore, the manufacturing cost can be reduced. .

[Brief description of the drawings]

FIG. 1 is a crystallization process diagram of an embodiment according to the present invention.

FIG. 2 is a diagram showing a temperature distribution diagram of an interface and a crystallization state thereof.

FIG. 3 is a manufacturing process diagram of a bottom gate type TFT.

FIG. 4 is a manufacturing process diagram of a top gate type TFT.

[Explanation of symbols]

Reference Signs List 11 base 12 first amorphous silicon layer 13 second amorphous silicon layer 14 crystalline silicon layer 15 polycrystalline silicon layer 30 TFT 31 transparent base 32 gate electrode 33 gate dielectric layer 34 first amorphous silicon layer 35 Second amorphous silicon layer 36 Source / drain region 37 Source / drain region 38 Channel region 50 TFT 51 Base 52 Amorphous silicon layer 55 Gate dielectric layer 56 Gate electrode 58 Source / drain region 59 Source / drain region 60 Channel Area L1 Laser light L2 Laser light L3 Laser light L4 Laser light L5 Laser light L6 Laser light

────────────────────────────────────────────────── (5) References JP-A-6-85220 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/20 H01L 21/268 H01L 21 / 336 H01L 29/786

Claims (4)

(57) [Claims] After forming a first amorphous silicon layer containing an impurity and a second amorphous silicon layer which does not contain an impurity and is bonded to the first amorphous silicon layer on a substrate. ,
A first step of selectively irradiating the first amorphous silicon layer with a laser beam to modify the first amorphous silicon layer into a crystalline silicon layer; and selectively modifying the crystalline silicon layer. A step of growing a crystal from the interface between the crystalline silicon layer and the second amorphous silicon layer toward the second amorphous silicon layer and crystallizing the crystal. A method for crystallizing amorphous silicon, characterized in that: 2. The amorphous silicon crystallization method according to claim 1, wherein the selective heating in the second step is performed by laser light irradiation. 3. A method for manufacturing a thin film transistor to which the method for crystallizing amorphous silicon according to claim 1 or 2 is applied, wherein the gate electrode and the gate electrode are formed on a transparent substrate having at least a surface that is insulated. Forming a first amorphous silicon layer containing impurities on the gate dielectric layer, and removing the first amorphous silicon layer on the gate electrode. A second step of forming a second amorphous silicon layer containing no impurities on the gate dielectric layer so as to cover the first amorphous silicon layer; and By irradiating a laser beam from the transparent substrate side, the first amorphous silicon layer and the second amorphous silicon layer thereabove are selectively crystallized, and the first amorphous silicon layer is formed in the first amorphous silicon layer. Impurities in the second amorphous A third step of forming a source / drain region by diffusing into the porous silicon layer, and irradiating a laser beam from the transparent substrate side to heat the source / drain region, so that the source / drain region and the A fourth step of growing a crystal in the second amorphous silicon layer from an interface with the second amorphous silicon layer and crystallizing the second amorphous silicon layer to form a channel region. Manufacturing method of a thin film transistor. 4. A method for manufacturing a thin film transistor to which the method for crystallizing amorphous silicon according to claim 1 or 2 is applied, wherein at least a surface of the amorphous silicon does not contain impurities on an insulating substrate. Forming a layer, forming a gate dielectric layer on the amorphous silicon layer, forming a gate electrode on a part of the gate dielectric layer, and then using the gate electrode as a mask to form the gate electrode. A second step of introducing impurities into the crystalline silicon layer, and irradiating a laser beam with the gate electrode as a mask, thereby crystallizing the amorphous silicon layer to form a source / drain region made of polycrystalline silicon. A third step of forming, and irradiating a laser beam with the gate electrode as a mask to selectively heat the source / drain region, thereby forming the source / drain region and the non- From the interface between quality silicon layer was grown on the amorphous silicon layer, a method of manufacturing the thin film transistor characterized by comprising the amorphous silicon layer and a fourth step of forming a channel region is crystallized.