JP3125982B2 - Insulated gate field effect semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
The present invention relates to an insulated gate field effect semiconductor device. 2. Description of the Related Art In a field effect transistor disclosed in Japanese Patent Application Laid-Open No. 58-2073, a source region and a drain region are selectively annealed to form a polycrystalline region, and a channel forming region is made amorphous. Quality area. That is, the field effect transistor disclosed in the publication is
A part of the amorphous region is selectively made into a polycrystalline region by annealing. As described above, in a conventional insulated gate field effect semiconductor device, a channel forming region contains 1 to 3 × 10 ²⁰ cm ^{− of} oxygen, carbon, and nitrogen. ^It consisted of a non-single crystal containing about ^three . When all of oxygen, carbon, and nitrogen are contained at such a high concentration, the insulated gate field effect semiconductor device has poor "ON" and "OFF" characteristics when switching. For example, as described above, in an insulated gate field effect semiconductor device using a non-single-crystal semiconductor containing oxygen, carbon, and nitrogen at such a high concentration, good “ON” and “OFF” The frequency characteristic showing the characteristic was about 1 KHz. In the conventional insulated gate field effect semiconductor device, since the source region and the drain region are selectively annealed, an uncrystallized portion always remains in the non-single-crystal semiconductor layer. When an uncrystallized region remains in the insulated gate field effect semiconductor device as described above, a part of the current also flows in the amorphous portion when the device operates as an insulated gate field effect semiconductor device. Since the amorphous part has a higher resistance than the crystallized part,
The current is difficult to flow, and once it flows in, it is stored and flows out slowly. That is, the insulated gate field effect semiconductor device in the conventional example has a long lifetime in which current flows, and exhibits hysteresis characteristics. [0005] In order to solve the above problems, an object of the present invention is to provide an insulated gate field effect semiconductor device which has good switching characteristics and can be used at a high frequency. In order to achieve the above object, an insulated gate field effect semiconductor device according to the present invention comprises: a substrate (1) having silicon oxide as a main component and having an insulating surface; On the substrate (1), the concentrations of oxygen, carbon and nitrogen are 5
× In 10 ¹⁸ cm ^-3 or less, the non-single-crystal semiconductor layer made of polycrystalline silicon or microcrystalline silicon, and (2), the strong purple region excluding the channel formation region of the non-single crystal semiconductor layer (2)
A source region (7) and a drain region (8) that promoted crystallization by external light, a gate electrode (4) formed at a position matching the channel formation region, and the non-single-crystal semiconductor layer (2). A gate insulating film (formed between the gate electrode (4) and the source region (7) and the drain region (8), containing an impurity of the same type as that contained in the source region (7) and the drain region (8), and including a silicon nitride film; 3) is provided. According to the present invention, a gate is formed on a non-single-crystal semiconductor to which no or few impurities are added (hereinafter, a non-single-crystal semiconductor to which hydrogen or a halogen element is added is simply referred to as a semiconductor or a non-single-crystal semiconductor). An insulator and a gate electrode were selectively provided thereon. Further, using the gate electrode as a mask, impurities for the source region and the drain region, for example, phosphorus or arsenic for the N-channel type and boron for the P-channel type are added to the inside of the non-single-crystal semiconductor by an ion implantation method or the like. Thereafter, the region to which the inert impurities are added is irradiated with strong light at a temperature of 400 ° C. or less, and is subjected to strong light annealing (hereinafter, simply referred to as light annealing), so that hydrogen or a halogen element is added. In addition, the semiconductor is characterized by being transformed into a semiconductor whose crystallinity is promoted more than that of the channel formation region, particularly, a semiconductor having a remarkably polycrystalline or single crystal structure. That is,
The present invention does not perform laser annealing after ion implantation on a conventionally known single crystal semiconductor to which hydrogen or a halogen element is not added, but the hydrogen or halogen element is 1 atomic% or more—generally 5 atomic%. Or 20 atomic%
Is implanted into the non-single-crystal semiconductor added at a concentration of 0.1%, high-intensity annealing is performed on the non-single-crystal semiconductor, and preferably, the light is scanned from one end to the other end of the substrate surface to control crystal growth. In this case, the crystallinity is promoted to form an impurity region. In the insulated gate field effect semiconductor device of the present invention or the insulated gate field effect semiconductor device for a liquid crystal display panel, the depth of the morphological interface provided over the inside of the channel formation region is 0.3 μm to 3 μm. .
0 μm. The insulated gate field effect semiconductor device according to the present invention has an oxygen, carbon and nitrogen concentration of 5 × 10 ¹⁸ each.
cm ⁻³ or less, that is, a P-type or N-type impurity is added to a non-single-crystal semiconductor layer in which the above elements are reduced as much as possible. The source region and the drain region are formed by promoting crystallization only in the region to which the impurity is added. Further, a feature is that hydrogen and a P-type or N-type impurity are added to the channel formation region. Since the same impurity as in the source region and the drain region is added to the gate insulating film formed in close contact with the source region and the drain region, hydrogen in the non-single-crystal semiconductor layer is hardly degassed. The insulated gate field-effect semiconductor device having such a structure can be obtained by using a non-single-crystal semiconductor, for example, oxygen, carbon, or nitrogen of 1 to 3 × in the conventional example.
While the switching characteristics of the non-single-crystal semiconductor of 10 ²⁰ cm ^-3 were such that they could follow the frequency of 1 KHz, good switching characteristics were obtained even at a frequency of 1 MHz. [0010] Further, the insulated gate field effect semiconductor device is characterized in that oxygen, carbon and nitrogen in the non-single-crystal semiconductor layer are formed.
Since the source and drain regions, which have extremely low concentrations of 5 × 10 ¹⁸ cm ⁻³ or less, respectively , and promote crystallization by strong ultraviolet light in regions other than the channel formation region, are formed, The switching characteristics at higher frequencies were improved. In particular, since the source region and the drain region are not selectively annealed, all the non-single-crystal semiconductor layers other than the channel formation region can be easily formed by promoting crystallization. That is, in the insulated gate field effect semiconductor device according to the present invention, the concentrations of carbon and nitrogen are each 5 × 10 ¹⁸ cm ^−3.
In the following, regions other than a channel formation region in a non-single-crystal semiconductor layer formed of polycrystalline silicon or microcrystalline silicon are a source region and a drain region formed by promoting crystallization. No high-resistance area is left. In the insulated gate field effect semiconductor device of the present invention, the concentration of oxygen, carbon and nitrogen constituting the channel formation region on the substrate is 5 × 1 each.
0 ¹⁸ cm ⁻³ or less, and provided above a non-single-crystal semiconductor layer made of polycrystalline silicon or microcrystalline silicon. The optical energy gap (in the case of a silicon semiconductor) of the non-single-crystal semiconductor layer is from 1.7 eV to 1.
8 eV, while the optical energy gap of the source region and the drain region is 1.6 eV to 1.
It has almost the same optical energy gap as 8 eV. The source region and the drain region have the same energy gap as that of the non-single-crystal semiconductor layer, and an active impurity region can be obtained. Since the source region and the drain region have the same or substantially the same energy gap as the channel formation region, the ON current and the ON current of the insulated gate field-effect semiconductor device do not flow at the time of rising, or the other. When the current falls, the current does not flow. Therefore, the insulated gate field effect semiconductor device of the present invention has no hysteresis characteristics, has a small off-current, and can perform "ON" and "OFF" with a high-speed response. Further, since the crystallinity of the source region and the drain region is higher than that of the channel formation region, the sheet resistance is clearly reduced, and large-area large-scale integration can be performed on one substrate. In addition, since there is no amorphous portion in the source region and the drain region where current does not easily flow, current easily flows, and the switching does not flow in a switching manner. The gate insulating film is made of oxygen,
The concentration of carbon and nitrogen is at 5 × 10 ¹⁸ cm ^-3 or less, polycrystalline silicon or in contact with the non-single-crystal semiconductor layer formed of microcrystalline silicon, silicon film and the source region nitride and the drain region of the same type of impurities, Is formed, it is difficult for hydrogen in the non-single-crystal semiconductor to be degassed and moisture is hard to enter the non-single-crystal semiconductor. 1A to 1C are longitudinal sectional views of an insulated gate field effect semiconductor device according to an embodiment of the present invention. In FIG. 1, a substrate (1) is made of, for example, quartz glass and has a thickness of 1.1 m as shown in FIG.
m and the size was 10 cm × 10 cm. This board (1)
The upper surface of the substrate is plasma CVD of silane (SiH ₄ ) (high frequency 13.5
At 6 MHz and a substrate temperature of 210 ° C.), a non-single-crystal semiconductor (2) having an amorphous structure to which hydrogen was added at a concentration of 1 atomic% or more was formed to a thickness of, for example, 0.2 μm. Further, a gate insulating film (3) made of, for example, a silicon nitride film was formed on the upper surface of the non-single-crystal semiconductor (2) by a photo-CVD method. That is, the gate insulating film (3) is formed by a reaction between disilane (Si ₂ H ₆ ) and ammonia (NH ₃ ) or hydrazine (N ₂ H ₄ ) (a low-pressure mercury lamp including a wavelength of 2537 °, a substrate temperature of 250 ° C.). The Si ₃ N ₄ was fabricated to a thickness of 1000 mm without using the mercury sensitization method. Thereafter, the portion excluding the region (5) for forming the insulated gate field effect semiconductor device was removed by a plasma etching method. Plasma etching reaction is CF
₄ + O ₂ (5%) reactive gas was introduced, and 13.56 MHz frequency was applied to a parallel plate electrode (not shown).
Performed at room temperature. The gate insulating film (3) is formed over the entire surface of the substrate (1) as necessary. Then, on the gate insulating film (3), a microcrystalline or polycrystalline semiconductor of N ⁺ conductivity type was laminated to a thickness of 0.3 μm. this
Undesired portions of the N ⁺ semiconductor film are removed by a photo-etching method using the resist film (6) to form a gate electrode (4). Then, using the resist film (6), the gate electrode (4) of the N ⁺ semiconductor, and the gate portion composed of the gate insulating film (3) as a mask, the regions serving as the source and drain are formed as follows: 1 × 10 ²⁰ cm ^-3 concentration by ion implantation
As shown in (B), an impurity of one conductivity type, for example, phosphorus was added to form a pair of impurity regions (7) and (8). Further, after the resist film (6) of the gate electrode (4) is removed from the entire substrate (1), the substrate (1) is exposed to a strong ultraviolet light (10).
Processing was performed. That is, an ultra-high pressure mercury lamp (output 5K
W, wavelength 250-600 nm, light diameter 15 mm, length 180 m
m), the back side is a parabolic reflector, and a quartz cylindrical lens (focal length 150 cm, condensing part width
2 mm and a length of 180 mm), the irradiation part was linearly formed. The irradiating surface of the substrate (1) is scanned (scanned) at a speed of 5 to 50 cm / min in a direction perpendicular to the linear irradiating portion with respect to the irradiating portion, and a strong ultraviolet ray is applied to the entire surface of the substrate 10 cm × 10 cm. Light (10) was applied. Since the gate electrode (4) contains a large amount of phosphorus on the side of the gate electrode (4), it absorbs light sufficiently and is polycrystallized. The impurity regions (7) and (8) were once melted and recrystallized to shift (move) the melting and recrystallization in the scanning direction, that is, the X direction. As a result, the crystal grain size could be increased due to the addition of a growth mechanism, compared to simply heating or irradiating the entire surface uniformly.
A non-single-crystal semiconductor is selectively formed on an insulating substrate. Except for a channel formation region covered with a gate electrode (4) of the non-single-crystal semiconductor, the other non-single-crystal semiconductor has a source region or a drain region. Can promote the crystallization of all non-single-crystal semiconductors. The region polycrystallized by the intense ultraviolet light annealing does not need to reach the entire region under the impurity regions (7) and (8). In FIG. 1, as shown by lines (11) and (11 '), it is important that at least the upper layer is crystallized and the impurity regions (7) and (8) are activated. further,
Ends (15), (15 ') of its source and drain regions
Are provided so as to enter the channel region side with respect to the ends (16) and (16 ') of the gate electrode. Then, the N-type impurity regions (7) and (8), the I-type semiconductor region (2), and the junction interface (1
The channel forming region composed of (7) and (17 ') has a hybrid structure composed of a non-single-crystal semiconductor in the I-type semiconductor region (2) and a crystallized semiconductor entering from the impurity region. The degree of the crystallized semiconductor in the I-type semiconductor region (2) is determined by the scanning speed and intensity (illuminance) of the optical annealing. After the step of FIG. 1B, the polyimide resin is coated on the entire surface to a thickness of 2 μm. Then, after the electrode holes (13) and (13 ') are formed in the polyimide resin,
Aluminum ohmic contacts and their leads (1)
4) and (14 ') are formed. One of the contacts is formed on the upper surface of the source region, and the other is formed on the upper surface and side surfaces of the drain region. This contact is partially provided on the glass substrate, and the electrode holes (13), (1)
3 ′) can be formed large. Therefore, there is a feature that there is no unnecessary amorphous region outside the source region and the drain region. Further, the effective area of the insulated gate field effect semiconductor device for controlling the liquid crystal display element in the liquid crystal display can be reduced, and as a result, the aperture ratio can be improved. The leads (14) and (14 ') of the second layer may be connected to the gate electrode (4) when they are formed. As a result of this light annealing, the sheet resistance was changed from 4 × 10 ⁻³ (ohm cm) ⁻¹ before light irradiation to 1 × 10 ⁺² (ohm cm) ⁻¹ , and the electric resistance was ^lower than before light annealing. The conductivity characteristics have improved. FIG. 2 is a graph showing characteristics of drain current / drain voltage according to the embodiment of the present invention. When the length of the channel forming region was 10 μm, it was possible to make up to 60 V under the condition that the channel width was 1 mm. This is the condition when the gate voltage V _GG = 10V. This is a great advance in view of the fact that the conventional insulated gate field effect semiconductor device having an amorphous structure in the junction region varies widely from 30 V to 50 V. This embodiment employs a manufacturing process in which a film is gradually formed and processed from the lower side, so that large-area large-scale integration can be performed. Therefore, large area,
For example, 500 pieces x 50 in a 30cm x 30cm panel
Even zero insulated gate field effect semiconductor devices can be manufactured, and the device can be applied as an insulated gate field effect semiconductor device for controlling a liquid crystal display element. Since the low-temperature treatment is performed at a temperature of 400 ° C. or less by the photo-anneal process, it is possible to prevent the polycrystallized or single-crystallized semiconductor from releasing hydrogen or a halogen element therein. The optical annealing was not performed simultaneously on the entire surface of the substrate, but was scanned from one end to the other end. For this reason, the light emitted from the cylindrical ultra-high pressure mercury lamp was condensed linearly by a parabolic mirror and a quartz lens. Then, the light condensed in the form of a line could scan the substrate in a direction perpendicular to the linear direction, thereby optically annealing the surface of the non-single-crystal semiconductor. Since this light annealing is performed with ultraviolet light, crystallization from the surface of the non-single-crystal semiconductor to the inside is promoted. For this reason, in the impurity region near the surface that has been sufficiently polycrystallized or monocrystallized, it is possible to control the current flowing very close to the gate insulating film in the channel formation region without any trouble. Light irradiation annealing - Upon le step, hydrogen or a halogen element added to the channel formation region is not affected at all, since it is possible to hold the non-single-crystal semiconductor state, the off-current to 1/10 ^{3 to} the single crystal semiconductor Can be 1/10 ⁵ Since the source region and the drain region are formed by optical annealing after the gate electrode is formed, the characteristics are stabilized without contamination adhered to the gate insulator interface. Further, as compared with conventionally known methods, not only quartz glass but also soda glass and a heat-resistant organic film which are optional substrates can be used as the substrate material. Since the formation of the non-single-crystal semiconductor, the gate insulator, and the gate electrode that form the channel formation region, which is the interface between different materials, can be made without exposure to the atmosphere by a process in the same reactor,
It has the feature that the generation of interface levels is small. In this embodiment, it is important that all of oxygen, carbon and nitrogen of the non-single-crystal semiconductor in the channel formation region have an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ or less. That is, in the conventionally known insulated gate field effect semiconductor device, 1 to 3 ×
It is mixed to a concentration of 10 ²⁰ cm ^-3 . The P-channel insulated gate field-effect semiconductor device using a non-single-crystal semiconductor according to this conventional example allows only a current of 1/3 or less of the characteristics of the insulated gate field-effect semiconductor device according to the present embodiment to flow. The hysteresis characteristic of the insulated gate type field effect semiconductor device using a non-single-crystal semiconductor in the above conventional example is such that the drain electric field is 2 × 10 ⁶ V / c in the I _DD ─V _GG characteristic.
It was observed when adding more than m. Further, as in this embodiment, oxygen in the non-single-crystal semiconductor is reduced to 5 × 10 ¹⁸ cm ^−3.
Under the following conditions, no hysteresis was observed even at a voltage of 3 × 10 ⁶ V / cm. According to the present invention, oxygen, carbon and nitrogen are made of polycrystalline silicon or microcrystalline silicon on the surface of an insulating substrate at a very low concentration of 5 × 10 ¹⁸ cm ⁻³ or less, respectively. Since the non-single-crystal semiconductor layer was provided, there was no hysteresis in the gate voltage-drain current characteristics, and good switching characteristics at high frequencies were obtained. According to the present invention, oxygen, the concentration of carbon and nitrogen their
A non-single-crystal semiconductor layer composed of polycrystalline silicon or microcrystalline silicon and a gate electrode of 5 × 10 ¹⁸ cm ⁻³ or less,
Formed between the electrode and the source and drain regions
Contains the same type of impurities as the silicon nitride
A gate insulating film Motomaku is included, the non-single-crystal hydrogen in the semiconductor is not easily degassed, and moisture penetrates difficulty Kushitei
You.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are longitudinal sectional views of an insulated gate field effect semiconductor device according to one embodiment of the present invention. FIG. 2 is a graph showing characteristics of drain current─drain voltage according to an embodiment of the present invention. [Description of Signs] 1 ... Substrate 2 ... Non-single-crystal semiconductor layer 3 ... Gate insulating film 4 ... Gate electrode 5 ... Area 6 for forming an insulated gate type field effect semiconductor device ... Resist films 7, 8 Impurity region 10 Strong ultraviolet light 11, 11 'Lines 13, 13' Electrode holes 14, 14 'Leads 15, 15' Ends 16 and 16 'of source region and drain region Ends 17 and 17' of gate electrode junction interface

   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-59-75670 (JP, A)                 JP-A-58-197775 (JP, A)                 JP-A-55-50663 (JP, A)                 JP-A-59-35423 (JP, A)                 JP-A-56-108231 (JP, A)                 JP-A-58-2073 (JP, A)

Claims (1)

(57) [Claims] A substrate mainly composed of silicon oxide having an insulating surface; and oxygen, carbon and nitrogen concentrations of 5
A non-single-crystal semiconductor layer made of polycrystalline silicon or microcrystalline silicon at × 10 ¹⁸ cm ⁻³ or less, and crystallization of the non-single-crystal semiconductor layer excluding a channel formation region was promoted by strong ultraviolet light . A source region and a drain region, a gate electrode formed at a position aligned with the channel formation region, an impurity formed between the non-single-crystal semiconductor layer and the gate electrode, and contained in the source region and the drain region. And a gate insulating film containing the same kind of impurities and a silicon nitride film.