JPH09181327A - Insulated gate field-effect semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the switching characteristics of an insulated gate field- effect semiconductor device and to allow using the device at a high frequency. SOLUTION: A plurality of insular non-single crystal semiconductor layers 2, which respectively have at least a channel formation region, a source region and a drain region, are formed on an insulating substrate and with impurities doped to these layers 2, a crystallization of regions 7 and 8 doped with these impurities is furthered to form source and drain regions. The above source and drain regions are formed containing the impurities in the whole areas of the layers 2 excluding the above channel formation regions. The same impurities as those in the above source and drain regions are contained in a gate insulating film 3, which comes into contact closely to the above source and drain regions. Moreover, the above film 3 contains a silicon nitride.

Description

Detailed Description of the Invention

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
The present invention relates to an insulated gate field effect semiconductor device.

[0002]

2. Description of the Related Art In a field effect transistor described in Japanese Patent Application Laid-Open No. 58-2073, a source region and a drain region are selectively annealed to form a polycrystalline region and a channel forming region to an amorphous region. I have. That is, the field effect transistor disclosed in the publication is
A part of the amorphous region is selectively made into a polycrystalline region by annealing.

[0003]

As described above, the channel forming region in the conventional insulated gate field effect semiconductor device contains oxygen, carbon and nitrogen in an amount of 1 to 3 × 10 ²⁰ cm ^-3. It consisted of non-single crystals. When all of oxygen, carbon, and nitrogen are contained in such a high concentration, the insulated gate field effect semiconductor device has poor “ON” and “OFF” characteristics when switching. For example, as described above, in an insulated gate field effect semiconductor device using a non-single-crystal semiconductor containing oxygen, carbon, and nitrogen at such a high concentration, good “ON” and “OFF” The frequency characteristic showing the characteristic was about 1 KHz.

In the conventional insulated gate field effect semiconductor device, since the source region and the drain region are selectively annealed, an uncrystallized portion always remains in the non-single-crystal semiconductor layer. When an uncrystallized region remains in the insulated gate field effect semiconductor device as described above, a part of the current also flows in the amorphous portion when the device operates as an insulated gate field effect semiconductor device. Since the amorphous part has a higher resistance than the crystallized part,
The current is difficult to flow, and once it flows in, it is stored and flows out slowly. That is, the insulated gate field effect semiconductor device in the conventional example has a long lifetime in which a current flows and exhibits hysteresis characteristics.

In order to solve the above problems, it is an object of the present invention to provide an insulated gate field effect semiconductor device which has good switching characteristics and can be used at high frequencies.

[0006]

In order to achieve the above object, an insulated gate field effect semiconductor device according to the present invention comprises a substrate (1) having an insulating surface, and at least a channel formation region on the substrate (1). , Source region (7), drain region (8)
A plurality of island-shaped non-single-crystal semiconductor layers (2) having a gate electrode formed in a position aligned with the channel formation region
(4), the non-single crystal semiconductor layer (2) and the gate electrode
(4) and a gate insulating film (3) formed between the source region (7) and the drain region (8).
Is a non-single-crystal semiconductor layer excluding the channel formation region
The source region is formed by including impurities in the entire region (2).
The gate insulating film (3) in close contact with (7) and the drain region (8) contains the same type of impurities as those of the source region (7) and the drain region (8), and The insulating film (3) is characterized by containing silicon nitride. The insulated gate field effect semiconductor device of the present invention is characterized in that the substrate (1) having an insulating surface is a substrate containing silicon oxide as a main component. The non-single crystal semiconductor layer (2) in the insulated gate field effect semiconductor device of the present invention is oxygen,
It is characterized in that carbon or nitrogen is 5 × 10 ¹⁸ cm ⁻³ or less. The non-single-crystal semiconductor layer (2) in the insulated gate field effect semiconductor device of the present invention is characterized by being amorphous, polycrystalline or microcrystalline.

According to the present invention, a gate is formed on a non-single-crystal semiconductor having no or very few impurities (hereinafter, a non-single-crystal semiconductor to which hydrogen or a halogen element is added is simply referred to as a semiconductor or a non-single-crystal semiconductor). An insulating material and a gate electrode were selectively provided on the insulating material. Further, using the gate electrode as a mask, impurities for the source region and the drain region, for example, phosphorus or arsenic for the N-channel type and boron for the P-channel type are added to the inside of the non-single-crystal semiconductor by an ion implantation method or the like. Thereafter, the region to which the inert impurities are added is irradiated with strong light at a temperature of 400 ° C. or less, and is subjected to strong light annealing (hereinafter, simply referred to as light annealing), so that hydrogen or a halogen element is added. In addition, the semiconductor is characterized by being transformed into a semiconductor whose crystallinity is promoted more than that of the channel formation region, particularly, a semiconductor having a remarkably polycrystalline or single crystal structure. That is,
The present invention does not perform laser annealing after ion implantation on a single crystal semiconductor to which conventionally known hydrogen or halogen element is added, but the hydrogen or halogen element is 1 atomic% or more-generally 5 atomic%. To 20 atom%
Is implanted into the non-single-crystal semiconductor added at a concentration of 0.1%, high-intensity annealing is performed on the non-single-crystal semiconductor, and preferably, the light is scanned from one end to the other end of the substrate surface to control crystal growth. In this case, the crystallinity is promoted to form an impurity region.

In the insulated gate field effect semiconductor device or the insulated gate field effect semiconductor device for a liquid crystal display panel of the present invention, the depth of the morphological interface provided over the inside of the channel formation region is 0.3 μm to 3 μm. ．
0 μm.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The insulated gate field effect semiconductor device of the present invention contains oxygen, carbon or nitrogen at 5 × 10 ¹⁸ cm 2.
^-3 or less, that is, P-type or N-type impurities are added to the non-single crystal semiconductor layer in which the above elements are reduced as much as possible. The source region and the drain region are formed by promoting crystallization only in the region to which the impurity is added. Further, the channel formation region is characterized in that hydrogen or a halogen element and P-type or N-type impurities are added. Since the same impurity as that of the source region and the drain region is added to the gate insulating film formed in close contact with the source region and the drain region, hydrogen or a halogen element in the non-single-crystal semiconductor layer is degassed. It's hard to do. The insulated gate field effect semiconductor device having such a structure has a conventional non-single crystal semiconductor such as oxygen, carbon, or nitrogen of 1 to 3 × 10 ²⁰ cm ^−3.
The non-single crystal semiconductor, which has a switching characteristic of 1 MHz, can follow a frequency of 1 KHz, while the switching characteristic is 1 MHz.
Good switching characteristics were obtained even at the frequency of.

Further, in the insulated gate field effect semiconductor device, oxygen, carbon, or nitrogen in the non-single crystal semiconductor layer is extremely reduced to 5 × 10 ¹⁸ cm ^-3 or less, and all non-single crystal except the channel forming region is formed. Since the crystalline semiconductor layer is formed of the source region and the drain region that promote crystallization, the switching characteristics at higher frequencies are improved. In particular, since the source region and the drain region are not selectively annealed, crystallization can be promoted in all the non-single-crystal semiconductor layers other than the channel formation region. That is, in the insulated gate field-effect semiconductor device of the present invention, since all the regions other than the channel formation region in the non-single-crystal semiconductor layer are the source region and the drain region, a high-resistance region is formed in the amorphous portion. Not left. In the insulated gate field effect semiconductor device of the present invention, the gate electrode is provided above the non-single-crystal semiconductor layer forming the channel formation region on the substrate. The optical energy gap of the non-single-crystal semiconductor layer (in the case of a silicon semiconductor) is 1.7 eV to 1.
8 eV, whereas the optical energy gap between the source region and the drain region is 1.6 eV to 1.
It has almost the same optical energy gap as 8 eV. The source region and the drain region have the same energy gap as that of the non-single-crystal semiconductor layer, and an active impurity region can be obtained. Since the source region and the drain region have the same or substantially the same energy gap as that of the channel forming region, an on-current does not flow at the rising time with respect to “ON” and “OFF” of the insulated gate field effect semiconductor device, or the other. , The current doesn't flow at the falling edge. Therefore, the insulated gate field effect semiconductor device of the present invention has no hysteresis characteristics, has a small off-current, and can perform "ON" and "OFF" with a high-speed response. Further, since the crystallinity of the source region and the drain region is higher than that of the channel formation region, the sheet resistance is clearly reduced, and large-area large-scale integration can be performed on one substrate. In addition, since the source region and the drain region do not have an amorphous portion in which a current does not easily flow, a current easily flows, and the current does not dangle during switching. Since the gate insulating film has a silicon nitride film formed in contact with the non-single-crystal semiconductor layer, hydrogen or a halogen element in the non-single-crystal semiconductor is not easily degassed, and moisture enters the non-single-crystal semiconductor. hard.

[0011]

1A to 1C are longitudinal sectional views of an insulated gate field effect semiconductor device according to an embodiment of the present invention. In FIG. 1, a substrate (1) is made of, for example, quartz glass and has a thickness of 1.1 m as shown in FIG.
m and the size was 10 cm × 10 cm. This board (1)
The upper surface of the substrate is plasma CVD of silane (SiH ₄ ) (high frequency 13.5
At 6 MHz and a substrate temperature of 210 ° C., a non-single-crystal semiconductor (2) containing an amorphous structure to which hydrogen was added at a concentration of 1 atomic% or more was formed to a thickness of, for example, 0.2 μm. Further, a gate insulating film (3) made of, for example, a silicon nitride film was formed on the upper surface of the non-single-crystal semiconductor (2) by a photo-CVD method. That is, the gate insulating film (3) is formed by a reaction between disilane (Si ₂ H ₆ ) and ammonia (NH ₃ ) or hydrazine (N ₂ H ₄ ) (a low-pressure mercury lamp including a wavelength of 2537 °, a substrate temperature of 250 ° C.). The Si ₃ N ₄ was fabricated to a thickness of 1000 mm without using the mercury sensitization method.

Thereafter, the portion excluding the region (5) for forming the insulated gate field effect semiconductor device was removed by a plasma etching method. Plasma etching reaction is CF
_While introducing a reactive gas of ₄ + O ₂ (5%) and applying a frequency of 13.56 MHz to a parallel plate electrode (not shown),
Done at room temperature. The gate insulating film (3) is formed over the entire surface of the substrate (1) as necessary. Then, on the gate insulating film (3), a microcrystalline or polycrystalline semiconductor of N ⁺ conductivity type was laminated to a thickness of 0.3 μm. this
The N ⁺ semiconductor film becomes a gate electrode (4) by removing an undesired part by a photoetching method using the resist film (6).

Thereafter, with the gate portion composed of the resist film (6), the gate electrode (4) of N ⁺ semiconductor, and the gate insulating film (3) used as a mask, the regions to be the source and drain are The concentration of 1 × 10 ²⁰ cm ^{-3 was} obtained by the ion implantation method.
As shown in (B), an impurity of one conductivity type, for example, phosphorus was added to form a pair of impurity regions (7) and (8). Furthermore, the substrate (1) was exposed to light of the strong ultraviolet light (10) after the resist film (6) of the gate electrode (4) was removed.
Processing was performed. That is, ultra high pressure mercury lamp (output 5K
W, wavelength 250 to 600 nm, light diameter 15 mm, length 180 m
On the other hand, the back side uses a parabolic reflector and a quartz cylindrical lens in front (focal length 150 cm, converging part width
2 mm and length 180 mm), the irradiation part was formed linearly. The irradiation surface of the substrate (1) is scanned at a speed of 5 to 50 cm / min in the direction orthogonal to the linear irradiation portion with respect to this irradiation portion, and the entire surface of the substrate 10 cm × 10 cm is exposed to strong ultraviolet light. Light (10) was applied.

Since the gate electrode (4) has a large amount of phosphorus added to the side of the gate electrode (4), it has sufficiently absorbed light to be polycrystallized. Further, the impurity regions (7) and (8) were melted and recrystallized once, so that the melting and recrystallization were shifted (moved) in the scanning direction, that is, the X direction. As a result, the crystal grain size could be increased due to the addition of a growth mechanism, compared to simply heating or irradiating the entire surface uniformly.
A non-single-crystal semiconductor is selectively formed on an insulating substrate, and the non-single-crystal semiconductor of the other part is the source region or the drain region except the channel forming region covered with the gate electrode (4) of the non-single-crystal semiconductor. The crystallization of all the non-single crystal semiconductors can be promoted. The region polycrystallized by the strong ultraviolet light anneal does not have to extend to the entire region below the impurity regions (7) and (8).

As shown by lines (11) and (11 ') in FIG. 1, it is important that only the upper layer part thereof is crystallized and the impurity regions (7) and (8) are activated. further,
Edges (15), (15 ') of its source and drain regions
Are provided so as to enter the channel region side with respect to the ends (16) and (16 ′) of the gate electrode. Then, the N-type impurity regions (7) and (8), the I-type semiconductor region (2), and the junction interface (1
The channel forming region composed of 7) and (17 ′) has a hybrid structure composed of a non-single crystal semiconductor in the I-type semiconductor region (2) and a crystallized semiconductor that has entered from the impurity region. The degree of the crystallized semiconductor in the I-type semiconductor region (2) is determined by the scanning speed of the optical anneal and the intensity (illuminance).

After the step of FIG. 1B, the polyimide resin is coated on the entire surface to a thickness of 2 μm. Then, after the electrode holes (13) and (13 ') are formed in the polyimide resin,
Aluminum ohmic contacts and their leads (1)
4) and (14 ') are formed. One of the contacts is formed on the upper surface of the source region, and the other is formed on the upper surface and the side surface of the drain region. This contact is partially provided on the glass substrate, and the electrode holes (13), (1)
3 ′) can be formed large. For this reason, a feature is that there is no unnecessary amorphous region outside the source region and the drain region.

Further, it is possible to reduce an effective area as a control insulated gate field effect semiconductor device for a liquid crystal display element in a liquid crystal display, and as a result, it is possible to improve an aperture ratio. The leads (14) and (14 ') of the second layer may be connected to the gate electrode (4) when they are formed. The result of this optical annealing is that the sheet resistance changes from 4 × 10 ⁻³ (ohm cm) ⁻¹ before light irradiation to 1 × 10 ⁺² (ohm cm) ^−1, which is higher than that before light annealing. The conductivity characteristics are improved.

FIG. 2 is a graph showing characteristics of drain current-drain voltage according to the embodiment of the present invention. When the length of the channel forming region was 10 μm, it was possible to produce up to 60 V under the condition that the channel width was 1 mm. This is the condition when the gate voltage V _GG = 10V. This is a great advance in view of the fact that the conventional insulated gate field effect semiconductor device having an amorphous structure in the junction region varies widely from 30 V to 50 V.

This embodiment employs a manufacturing process in which a film is gradually formed and processed from the lower side, so that large-area large-scale integration can be performed. Therefore, a large area,
For example, 500 pieces x 50 in a 30 cm x 30 cm panel
It was possible to manufacture even zero insulated gate field effect semiconductor devices, and it could be applied as an insulated gate field effect semiconductor device for controlling liquid crystal display elements. Since the low-temperature treatment is performed at a temperature of 400 ° C. or less by the photo-anneal process, it is possible to prevent the polycrystallized or single-crystallized semiconductor from releasing hydrogen or a halogen element therein. The optical annealing was not performed simultaneously on the entire surface of the substrate, but was scanned from one end to the other end.

Therefore, the light emitted from the cylindrical ultrahigh pressure mercury lamp was linearly condensed by the parabolic mirror and the quartz lens. Then, the light condensed in the form of a line could scan the substrate in a direction perpendicular to the linear direction, thereby optically annealing the surface of the non-single-crystal semiconductor. Since this light annealing is performed with ultraviolet light, crystallization from the surface of the non-single-crystal semiconductor to the inside is promoted. For this reason, in the impurity region near the surface that has been sufficiently polycrystallized or monocrystallized, it is possible to control the current flowing very close to the gate insulating film in the channel formation region without any trouble. Light irradiation annealing - Upon le step, hydrogen or a halogen element added to the channel formation region is not affected at all, since it is possible to hold the non-single-crystal semiconductor state, the off-current to 1/10 ^{3 to} the single crystal semiconductor Can be 1/10 ⁵

Since the source region and the drain region are formed by optical annealing after forming the gate electrode, contaminants do not adhere to the interface of the gate insulator and the characteristics are stabilized. Further, as compared with conventionally known methods, not only quartz glass but also soda glass and a heat-resistant organic film which are optional substrates can be used as the substrate material. Since the formation of the non-single-crystal semiconductor, the gate insulator, and the gate electrode that form the channel formation region, which is the interface between different materials, can be made without exposure to the atmosphere by a process in the same reactor,
It has the feature that the generation of interface levels is small.

In this embodiment, it is important that the non-single crystal semiconductor in the channel forming region has an impurity concentration of 5 × 10 ¹⁸ cm ^-3 or less for all of oxygen, carbon and nitrogen. That is, in a conventionally known insulated gate field effect semiconductor device, 1 to 3 ×
It is mixed to a concentration of 10 ²⁰ cm ^-3 . The P-channel insulated gate field-effect semiconductor device using a non-single-crystal semiconductor according to this conventional example allows only a current of 1/3 or less of the characteristics of the insulated gate field-effect semiconductor device according to the present embodiment to flow. The hysteresis characteristic of the insulated gate type field effect semiconductor device using a non-single-crystal semiconductor in the above conventional example is such that the drain electric field is 2 × 10 ⁶ V / c in the I _DD ─V _GG characteristic.
It was observed when adding more than m. Further, as in this embodiment, oxygen in the non-single-crystal semiconductor is reduced to 5 × 10 ¹⁸ cm ^−3.
Under the following conditions, no hysteresis was observed even at a voltage of 3 × 10 ⁶ V / cm.

[0023]

According to the present invention, a non-single-crystal semiconductor layer containing oxygen, carbon, or nitrogen in an extremely small amount of 5 × 10 ¹⁸ cm ⁻³ or less is provided on the surface of an insulating substrate.
Since the non-single-crystal semiconductor layer promotes crystallization only in a region to which a P-type or N-type impurity is added, the gate voltage-
There was no hysteresis in the drain current characteristics, and good switching characteristics at high frequencies were obtained. According to the present invention, since the non-single-crystal semiconductor layer other than the channel formation region is all promoted to be crystallized, the switching characteristics of the insulated gate field effect semiconductor device are further improved even at high frequencies. According to the present invention, the crystallinity of the source region and the drain region is made higher than that of the channel forming region, so that the sheet resistance is lowered and a large area and large scale integration can be performed. According to the present invention, since the gate insulating film exists on the source region and the drain region,
Even if annealing treatment is performed through the gate insulating film, it is difficult for hydrogen or halogen elements to be degassed. According to the present invention, since hydrogen or a halogen element and a P-type or N-type impurity are added to the channel formation region, a channel formation region having high conductivity can be obtained. According to the present invention, in a gate insulating film in which a silicon nitride film is formed in contact with a non-single-crystal semiconductor layer, hydrogen or a halogen element in the non-single-crystal semiconductor is less likely to be degassed and moisture is less likely to enter.

[Brief description of the drawings]

FIGS. 1A to 1C are longitudinal sectional views of an insulated gate field effect semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a drain current-drain voltage characteristic according to an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Non-single-crystal semiconductor layer 3 ... Gate insulating film 4 ... Gate electrode 5 ... Area | region which forms an insulated gate field effect semiconductor device 6 ... Resist film 7, 8 ... Impurity region 10 ... Strong ultraviolet light 11, 11 '... Line 13, 13' ... Electrode hole 14, 14 '... Lead 15, 15' ... Source region and drain region Edges 16 and 16 '... Edges of gate electrode 17 and 17' ... Bonding interface

Claims (4)

[Claims] 1. A substrate having an insulating surface, a plurality of island-shaped non-single-crystal semiconductor layers having at least a channel formation region, a source region, and a drain region on the substrate, and formed at a position aligned with the channel formation region. And a gate insulating film formed between the non-single-crystal semiconductor layer and the gate electrode, the source region and the drain region are: The gate insulating film formed containing impurities in the entire region of the non-single-crystal semiconductor layer excluding the channel formation region and being in close contact with the source region and the drain region has the same type as the source region and the drain region. Insulated gate type field effect semiconductor device characterized in that it contains impurities and the gate insulating film contains silicon nitride. . 2. The insulated gate field effect semiconductor device according to claim 1, wherein the substrate having an insulating surface is a substrate containing silicon oxide as a main component. 3. The insulated gate type semiconductor device according to claim 1, wherein the non-single crystal semiconductor layer contains oxygen, carbon, or nitrogen at 5 × 10 ¹⁸ cm ⁻³ or less. Field effect semiconductor device. 4. The insulated gate field effect semiconductor device according to any one of claims 1 to 3, wherein the non-single crystal semiconductor layer is amorphous, polycrystal, or microcrystal.