JPS60245173A - Insulated gate type semiconductor device - Google Patents

Insulated gate type semiconductor device

Info

Publication number
JPS60245173A
JPS60245173A JP10025184A JP10025184A JPS60245173A JP S60245173 A JPS60245173 A JP S60245173A JP 10025184 A JP10025184 A JP 10025184A JP 10025184 A JP10025184 A JP 10025184A JP S60245173 A JPS60245173 A JP S60245173A
Authority
JP
Japan
Prior art keywords
semiconductor
channel
crystal semiconductor
region
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10025184A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP10025184A priority Critical patent/JPS60245173A/en
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Publication of JPS60245173A publication Critical patent/JPS60245173A/en
Priority to US06/912,498 priority patent/US4727044A/en
Priority to US07/153,477 priority patent/US4959700A/en
Priority to US07/707,178 priority patent/US5142344A/en
Priority to JP4333725A priority patent/JP2648784B2/en
Priority to US07/987,179 priority patent/US5315132A/en
Priority to US08/054,842 priority patent/US5313077A/en
Priority to US08/171,769 priority patent/US6660574B1/en
Priority to US08/473,953 priority patent/US5543636A/en
Priority to US08/944,136 priority patent/US6680486B1/en
Priority to US08/947,731 priority patent/US6221701B1/en
Priority to US09/406,794 priority patent/US6635520B1/en
Priority to US09/406,791 priority patent/US6734499B1/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78666—Amorphous silicon transistors with normal-type structure, e.g. with top gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain an IGEFT having high reverse withstand strength by using a nonsingle crystal semiconductor to which hydrogen or halogen element is added as a channel, extending a region aided to crystallize to the interior of the channel, and providing source and drain adjacent to the channel. CONSTITUTION:A laminate of nonsingle crystal semiconductor 2 which contains hydrogen of density higher than 1atom% and Si3N4 3 is formed on a quartz glass substrate 1, an N<+> type polysilicon gate electrode 4 is formed by a resist mask 6, P ions are implanted to form N type layers 7, 8. It is annealed with strong light 10 of mercury lamp, polycrystallized to the outside of the layers 7, 8, the bottom is approached to the substrate 1, advanced to channel side from the junction boundaries 17, 17' of the layers 7, 8, and the ends 15, 15' are disposed at the channel side from gate electrode ends 16, 16'. With this structure, the breakdown voltage of junction increases at the reverse bias time to obtain a high withstand IGFET.

Description

【発明の詳細な説明】 「産業上の利用分野」 本発明は半導体集積回路、液晶表示パネル等に用いられ
る絶縁ゲイト型電界効果半導体装置（以下ＩＧＦという
）に関する。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an insulated gate field effect semiconductor device (hereinafter referred to as IGF) used in semiconductor integrated circuits, liquid crystal display panels, etc.

「従来の技術ｊ 単結晶珪素を用いたＩＧＦは広く半導体分野に用いられ
ている。その代表例は本発明人の発明になる特公昭５Ｏ
−１９８６ｒ半導体装置およびその作製方法」である。``Prior art j IGFs using single-crystal silicon are widely used in the semiconductor field.
-1986r Semiconductor device and method for manufacturing the same.”

しかしチャネル形成領域を単結晶半導体を用いるのでは
なく、水素またはハロゲン元素が１原子％以上の濃度に
添加された非単結晶半導体により設けられたＩＧＦは本
発明人の出願による特願昭５３−１２４０２１　ｒ半導
体装置およびその作製方法」（昭和５３年１０月７日出
願）がその代表例である。However, an IGF in which the channel formation region is formed using a non-single-crystal semiconductor doped with hydrogen or a halogen element at a concentration of 1 atomic % or more, instead of using a single-crystal semiconductor, is proposed in the patent application filed by the present inventor in 1982- 124021r Semiconductor Device and Method for Manufacturing the Same'' (filed on October 7, 1978) is a typical example.

かかる水素またはハロゲン元素が添加された半導体特に
珪素半導体がチャネル形成領域に用いられたＩＧＦは、
オフ電流が従来より公知の単結晶半導体を用いた場合に
比べて１０３〜１０５分の１も小さい。そのため液晶表
示パネル制御用ＩＧＦとして用いることが有効であると
されている。このＴＧＦは前記した引例のごとく、ゲイ
ト電極がチャネル形成領域の半導体に対しその上側に設
けられた横チャネル型ＩＧＦ　、また本発明人の出願に
なる特願昭５６−００１７６７　ｒ絶縁ゲイト型半導体
装置およびその作製方法」（昭和５６年１月９日）に示
された縦チャネル型ＩＧＦ　、およびゲイト電極がチャ
ネル形成領域を構成する半導体の下側に設けられたいわ
ゆる一般的に公知の薄膜ＩＧＦ　）ランジスタ型が知ら
れている。そのうち後２者に比べ前者の前記した構造は
従来より公知の単結晶珪素を用いたＩＧＦと構造が同じ
であるため、すでに出来上がった技術を応用できるとい
うきわめて優れた特長を有するものであった。An IGF in which a semiconductor doped with hydrogen or a halogen element, particularly a silicon semiconductor, is used in the channel formation region,
The off-state current is 103 to 105 times smaller than that when a conventionally known single crystal semiconductor is used. Therefore, it is said that it is effective to use it as an IGF for controlling a liquid crystal display panel. As mentioned above, this TGF is a lateral channel type IGF in which the gate electrode is provided above the semiconductor in the channel formation region, and is also referred to in Japanese Patent Application No. 56-001767 r insulated gate type semiconductor device filed by the present inventor. and the so-called generally known thin film IGF in which the gate electrode is provided under the semiconductor constituting the channel forming region). A transistor type is known. Compared to the latter two, the former has the same structure as the previously known IGF using single-crystal silicon, and therefore has an extremely superior feature of being able to apply already developed technology.

しかし他方、かかるＩＧＦにおいては、ソース、ドレイ
ンの作製をＣＶＤ法（プラズマＣＶＤ法を含む）により
薄膜のディボジソションにより行うのではなくイオン注
入等により添加し、かつその添加物を４００℃以下の水
素またはハロゲン元素が脱気しない温度範囲でアニール
により活性のドナーまたはアクセプタとしなければなら
ない。On the other hand, however, in such IGFs, the source and drain are not fabricated by thin film deposition using the CVD method (including plasma CVD method), but are added by ion implantation or the like, and the additives are added by hydrogen or The halogen element must be made into an active donor or acceptor by annealing in a temperature range in which it does not degas.

加えて、ソース、ドレイン、特にドレインとチャネル形
成領域との間での逆耐圧の向上がめられている。In addition, it is desired to improve the reverse breakdown voltage between the source and the drain, especially between the drain and the channel forming region.

「問題を解決するための手段」 本発明は上記の問題を解決するためのものであり、不純
物の添加のないまたはきわめて少ない非単結晶半導体（
以下水素またはハロゲン元素が添加された非単結晶半導
体を単に半導体または非単結晶半導体と略記する）上に
ゲイト絶縁膜およびその上にゲイト電極を選択的に設り
た。さらにこのディト電極をマスクとしてイオン注入法
等によりソース、ドレイン用の不純物例えばＮチャネル
型ではリンまたは砒素、Ｐチャネル型ではホウ素を非単
結晶半導体内部に添加し不純物領域を構成させた。この
後この不活性の不純物が添加された領域に対し、４００
℃以下の温度で強光照射をし、強光アニール（以下単に
光アニールという）を行い、水素またはハロケン元素が
添加残存し、かっ結晶化度がチャネル形成領域よりも助
長された半導体、特に著しくは多結晶または単結晶構造
の半導体にこの不純物領域の半導体を変成せしめ、加え
てこの結晶化をチャネル形成領域にまで延在させること
によりＰＩまたはＮｌ接合部を結晶化度の高い領域とし
たものである。かくすることにより、チャネル形成領域
はオフ電流を少なくするための水素またはハロゲン元素
が添加された非単結晶半導体と接合部での耐圧の向上（
アバランシェブレイクダウン電圧の向上）用に多結晶ま
たは単結晶領域をＰＩまたはＮＩ接合界面近傍に設けた
ものである。"Means for Solving the Problem" The present invention is intended to solve the above problem, and is directed to a non-single crystal semiconductor (with no or very little added impurities).
A gate insulating film and a gate electrode were selectively provided on the gate insulating film (hereinafter a non-single crystal semiconductor doped with hydrogen or a halogen element will be simply referred to as a semiconductor or a non-single crystal semiconductor). Furthermore, impurities for the source and drain, such as phosphorus or arsenic for an N-channel type, and boron for a P-channel type, were added into the non-single crystal semiconductor by ion implantation using this DETO electrode as a mask to form an impurity region. Thereafter, 400
Semiconductors that are irradiated with strong light at a temperature below ℃ and subjected to strong light annealing (hereinafter simply referred to as photoannealing), have residual hydrogen or halogen elements added, and have a crystallinity that is more favorable than that of the channel forming region. In this method, the semiconductor in this impurity region is transformed into a polycrystalline or single crystal structure semiconductor, and in addition, this crystallization is extended to the channel formation region, thereby making the PI or Nl junction a region with a high degree of crystallinity. It is. In this way, the channel forming region is made of a non-single crystal semiconductor doped with hydrogen or a halogen element to reduce off-state current, and to improve breakdown voltage at the junction.
A polycrystalline or single crystalline region is provided near the PI or NI junction interface to improve avalanche breakdown voltage.

「作用」 その結果、本発明のＩＧＦの構造は、ソース、ドレイン
、特にドレインの接合耐圧を単結晶半導体と同様に高く
することができ、従来のアモルファス半導体を含む薄膜
トランジスタに比べ２０Ｖ近くも向上させることができ
た。加えてゲイト電極が基板上のチャネル形成領域を構
成する非単結晶半導体の上方に設けられ、かっこの半導
体の光学的［！ｇ（珪素半導体の場合１．７〜１．８ｅ
Ｖ）に対し１．６〜１．８ｅνと殆ど同し光学的Ｅｇを
有しかつ活性な不純物領域を得ることができた。がくの
ごと＜、Ｅｇがチャネル形成領域と同じまたはｍ略同じ
であるため、ＩＧＦ　（７）　ｒＯＮＪ　、ｒＯＦｌ’
　Ｊに対しオン電流が立ち上がり時に流れにくかったり
、また他方、電流がたち下がり時にダラダラ流れてしま
ったりすることがない、いわゆるオフ電流が少なく、が
っオン、オフを高速応答で行うことができた。"Operation" As a result, the structure of the IGF of the present invention can increase the junction breakdown voltage of the source and drain, especially the drain, as high as that of a single crystal semiconductor, and improves it by nearly 20 V compared to a conventional thin film transistor containing an amorphous semiconductor. I was able to do that. In addition, a gate electrode is provided above the non-single crystal semiconductor constituting the channel formation region on the substrate, and the optical [! g (1.7 to 1.8 e for silicon semiconductors
V), it was possible to obtain an active impurity region having almost the same optical Eg of 1.6 to 1.8eν. Since Eg is the same or almost the same as the channel forming region, IGF (7) rONJ , rOFl'
For J, the on-current does not flow easily when it rises, and on the other hand, the current does not flow lazily when it falls; the so-called off-current is low, and it can quickly turn on and off with a high-speed response. .

以下に実施例により本発明を説明する。The present invention will be explained below with reference to Examples.

「実施例１」 基板（１）として第１図（＾）に示すごとく、厚さ１　
、１ｍｍの石英ガラス基板１０ｃｍ　Ｘ　１０ｃｍを用
いた。この上面に、シラン（Ｓｉ１１４）のプラズマＣ
ＶＤ（高周波数１３．５６ＭＨｚ、基板温度２１０’Ｃ
）により水素が１原子％以上の濃度に添加されたアモル
ファス構造を含む非単結晶半導体（２）を０．２μの厚
さに形成した。"Example 1" As shown in FIG. 1 (^), the substrate (1) has a thickness of 1
, a 1 mm quartz glass substrate measuring 10 cm x 10 cm was used. On this top surface, silane (Si114) plasma C
VD (high frequency 13.56MHz, substrate temperature 210'C
), a non-single crystal semiconductor (2) containing an amorphous structure doped with hydrogen at a concentration of 1 atomic % or more was formed to a thickness of 0.2 μm.

さらにこの上面に光ＣＶＤ法により窒化珪素膜（３）を
ゲイト絶縁膜として積層した。即ち５ｉｚｌｌａ　とア
ンモニアまたはヒドラジンとの反応（２５３７人の波長
を含む低圧水銀灯、基板温度２５０°Ｃ）により、ｓｉ
、Ｎ４を水銀増感法を用いることなしに１０００人の厚
さに作製した。Furthermore, a silicon nitride film (3) was laminated as a gate insulating film on this upper surface by a photo-CVD method. That is, by reaction of 5izlla with ammonia or hydrazine (low-pressure mercury lamp containing 2537 wavelengths, substrate temperature 250°C), si
, N4 was fabricated to a thickness of 1000 mm without using mercury sensitization.

この後、ＴＧＦを形成する領域（５）を除く他部をプラ
ズマエツチング法により除去した。反応はＣＦ４十０２
（５χ）で１３．５６ＭＨｚ、室温で行った。このゲイ
ト絶縁膜上にＮ“の導電型の微結晶または多結晶半導体
を０．３　μの厚さに積層した。このＮ゛の半導体膜を
レジスト（６）を用いてフォトエツチング法で除去した
後、このレジストとＮ＋半導体のゲイト電極部（４）と
をマスクとしてソース、ドレインとなる領域にイオン注
入法によりＩ　Ｘ　１０”ｃｍ−３の濃度に第１図（Ｂ
）に示すごとくリンを添加し、一対の不純物領域（７）
、（８）を形成した。Thereafter, the remaining portions except for the region (5) where the TGF is to be formed were removed by plasma etching. The reaction is CF402
(5χ) at 13.56 MHz at room temperature. On this gate insulating film, a microcrystalline or polycrystalline semiconductor of N" conductivity type was laminated to a thickness of 0.3 μm. This N" semiconductor film was removed by photoetching using a resist (6). After that, using this resist and the gate electrode part (4) of the N+ semiconductor as a mask, the regions that will become the source and drain are ion-implanted to a concentration of I x 10"cm-3 as shown in FIG.
), doping phosphorus and forming a pair of impurity regions (7).
, (8) were formed.

さらにこの基板全体に対し、ゲイト電極のレジストを除
去した後、強光（１０）の光アニールを行った。即ち、
超高圧水銀灯（出力５ＫＷ、波長２５０〜６００ｎｎ＋
、光径１５ｍｍφ、長さ１８０ｍｍ）に対し裏面側は放
物面の反射鏡を用い前方に石英のシリンドリカルレンズ
（焦点距離１５０ｃｍ、集光部中２ｍｍ、長さ１８０ｍ
ｍ）により線状に照射部を構成した。この照射部に対し
基板の照射面を５〜５０ｃｍ／分の速度例えば１０ｃｍ
／分の速さで走査（スキャン）し、基板１０ｃｍ　Ｘ　
ｌ０ｃｍの全面に強光が照射されるようにした。Furthermore, after removing the resist of the gate electrode, the entire substrate was subjected to photo-annealing using strong light (10). That is,
Ultra-high pressure mercury lamp (output 5KW, wavelength 250-600nn+
, light diameter 15 mmφ, length 180 mm), a parabolic reflector is used on the back side, and a quartz cylindrical lens (focal length 150 cm, 2 mm in the condensing part, length 180 m) is used in the front.
The irradiation part was formed in a linear manner by m). The irradiation surface of the substrate is moved to this irradiation part at a speed of 5 to 50 cm/min, for example, 10 cm.
Scan at a speed of 10 cm x 10 cm.
The entire surface of 10 cm was irradiated with strong light.

かくするとゲイト電極部はゲイト電極側にリンが多量に
添加されているため、この電極は十分光を吸収し多結晶
化した。また不純物領域（７）　、　（８）は一度溶融
し再結晶化することにより走査する方向即ちＸ方向に溶
融、再結晶がシフト（移動）させた。その結果単に全面
に均一に加熱または光照射するのみに比べ、成長機構が
加わるため結晶粒径を大きくすることができた。In this way, since a large amount of phosphorus is added to the gate electrode side of the gate electrode portion, this electrode sufficiently absorbs light and becomes polycrystalline. Further, the impurity regions (7) and (8) were once melted and recrystallized, thereby causing the melting and recrystallization to shift (move) in the scanning direction, that is, the X direction. As a result, compared to simply uniformly heating or irradiating the entire surface with light, it was possible to increase the crystal grain size because a growth mechanism was added.

この強光アニールにより多結晶化した領域を、不純物領
域の外側の全領域にまで及ぼしめた。このため図面に示
されるごとく、その底面は基板（１）上にまで至り、破
線（１１）、（１１’）に示したごとく、不純物領域（
７）　、　（８）の接合界面（１７）、（１７°）より
もチャネル形成領域に０．３〜３μの深さにわたって設
けられ、モホロジ的な界面（１５）、（１５°）はゲイ
ト電極下に設けられている。即ちその端部（１５）（１
５’）はゲイト電極の端部（１６）　、　（１６’）よ
りもチャネル形成領域内側にわたって設けられている。This strong light annealing allowed the polycrystalline region to extend to the entire region outside the impurity region. Therefore, as shown in the drawing, its bottom surface reaches onto the substrate (1), and as shown by broken lines (11) and (11'), the impurity region (
7) and (8) are provided over a depth of 0.3 to 3 μ in the channel forming region than the junction interfaces (17) and (17°), and the morphological interfaces (15) and (15°) are the gate electrodes. It is located below. That is, the ends (15) (1
5') is provided extending further inside the channel forming region than the ends (16) and (16') of the gate electrode.

かくのどと＜　、Ｎ（７）　、　（８）−１（２）接合
界面（１７）　、　（１７’　）が結晶化領域内部に設
けられているため、逆バイアスに対し接合の破壊電圧が
大きくなり高耐圧ＩＧＦを作ることができた。このＩ型
半導体内の結晶化半導体の領域の程度は光アニールの走
査スピード、強度（照度）によって決めることができる
。Since the junction interface (17), (17') is provided inside the crystallized region, the breakdown voltage of the junction is large against reverse bias. As a result, we were able to create a high-voltage IGF. The extent of the crystallized semiconductor region within this I-type semiconductor can be determined by the scanning speed and intensity (illuminance) of optical annealing.

図面においては、この第１図（Ｂ）の工程の後、ＰＩＱ
を全面に２μの厚さにコートし、さらに電極穴（１３）
　（１３’）に形成した後、アルミニュームのオームコ
ンタクトおよびそのリード（１４）　、　（１４°）を
形成している。この２層目の（１４）　、　（１４°）
の形成の際、ゲイト電極（４）と連結してもよい。In the drawing, after the process shown in Figure 1 (B), the PIQ
Coat the entire surface with a thickness of 2μ, and then add electrode holes (13).
After forming (13'), aluminum ohmic contacts and their leads (14) and (14°) are formed. This second layer (14), (14°)
may be connected to the gate electrode (4) during formation.

この光アニールの結果、不純物領域のシート抵抗が光照
射前の４Ｘ１０−３（０ｃｍ）　−’より１×１０＋！
（０ｃｍ）　−’に比べ光照射アニールの後の電気伝導
度特性の変化により明らかにすることができた。As a result of this photoannealing, the sheet resistance of the impurity region is 1×10+! from 4×10−3 (0 cm) −′ before light irradiation!
(0 cm) −' This could be clarified by the change in electrical conductivity characteristics after light irradiation annealing compared to the case of (0 cm) −'.

さらにそのドレイン耐圧は第２図曲線（２１）に示され
るごとく、チャネル形成領域の長さが１０μの（９） 場合、チャネル１１が１ｍｍの条件下において、６０Ｖ
まで作ることができた。これはゲイト電圧ＶＧＧ−１０
Ｖとした時の条件である。Furthermore, as shown in curve (21) in Figure 2, when the length of the channel forming region is 10μ (9), the drain breakdown voltage is 60 V under the condition that the channel 11 is 1 mm.
I was able to make up to. This is the gate voltage VGG-10
These are the conditions when V is set.

これはこの接合領域がアモルファス構造の従来より公知
の薄膜トランジスタにおいては、３０へ・５０Ｖと大き
くばらつくことを考えると、大きな進歩であった。This was a major advance considering that in conventional thin film transistors in which this junction region has an amorphous structure, the voltage varies widely from 30V to 50V.

「効果」 本発明は下側から漸次被膜を形成し加工するという製造
工程を採用したため、大面積大規模集積化を行うことが
可能になった。そのため大面積例えば３０ｃｍ　Ｘ　３
０ｃｍのパネル内に５００　Ｘ５００ケのＩＧＦの作製
すらも可能とすることができ、液晶表示素子の制御用Ｉ
ＧＦとして応用することができた。"Effects" Since the present invention employs a manufacturing process in which a film is gradually formed and processed from the bottom, it has become possible to perform large-scale integration over a large area. Therefore, the area is large, e.g. 30cm x 3
It is possible to create even 500 x 500 IGFs in a 0cm panel, and it is possible to create IGFs for controlling liquid crystal display elements.
It was possible to apply it as a GF.

光アニールプロセスにより多結晶化または単結晶化した
半導体をチャネル形成領域にまで延在させた。このため
ドレイン耐圧を従来より２０Ｖ以上向上させることがで
きるようになった。The polycrystalline or single-crystalline semiconductor was extended to the channel formation region by a photo-annealing process. Therefore, it has become possible to improve the drain breakdown voltage by 20 V or more compared to the conventional device.

この光アニールを紫外線で行うため、半導体の表面より
内部方向への結晶化を助長させた。この（１０） ため十分に多結晶化または単結晶化した表面近傍の不純
物領域へチャネル形成領域におけるゲイト絶縁膜のごぐ
近傍に流れる電流制御を支障なく行うことが可能となっ
た。Since this optical annealing was performed using ultraviolet rays, crystallization from the surface of the semiconductor toward the inside was promoted. This (10) makes it possible to control the current flowing in the vicinity of the gate insulating film in the channel formation region to the impurity region near the surface which is sufficiently polycrystalline or monocrystalline.

基板として単結晶半導体をまったく用いていない。この
ため光照射アニール工程に際し、チャネル形成領域のソ
ース、ドレインより離れた内部はまったく何等の影響を
受けず非単結晶半導体の状態を保持できる。そのためオ
フ電流を単結晶半導体の１／１０３〜１／１０’にする
ことができた。No single crystal semiconductor is used as the substrate. Therefore, during the light irradiation annealing step, the inside of the channel forming region away from the source and drain is not affected at all and can maintain the state of a non-single crystal semiconductor. Therefore, the off-state current could be reduced to 1/103 to 1/10' of that of a single crystal semiconductor.

ゲイトを作った後ソース、ドレインを光アニールで作製
するため、ゲイト絶縁物界面に汚物が付着することがな
く特性が安定していた。Since the source and drain are fabricated by photo-annealing after forming the gate, there is no dirt attached to the gate insulator interface, and the characteristics are stable.

さらに従来より公知の方法に比べ、基板材料として石英
ガラスのみならず任意の基板であるソーダガラス、耐熱
性有機フィルムをも用いることができる。Furthermore, compared to conventionally known methods, not only quartz glass but also any arbitrary substrate such as soda glass or heat-resistant organic film can be used as the substrate material.

異種材料界面であるチャネル形成領域を構成する半導体
−ゲイト絶縁物−ゲイト電極の形成と同一反応炉内での
プロセスにより、大気に触れさせ（１１） ることなく作り得るため、界面単位の発生が少ないとい
う特長を有する。By performing the process in the same reactor as the formation of the semiconductor-gate insulator-gate electrode that constitutes the channel formation region, which is the interface between different materials, it can be formed without exposing it to the atmosphere (11), thereby reducing the generation of interface units. It has the advantage of being small in number.

なお本発明において、チャネル形成領域の非単結晶半導
体の酸素、炭素および窒素のいずれもが５　Ｘ１０１８
ｃｍ−”以下の不純物濃度であることが好ましい。即ち
これらが従来公知のＩＧＦにおいてはチャネル層に１〜
３　Ｘ　１０２０ｃｍ−３の濃度に混合してしまった。In the present invention, all of the oxygen, carbon and nitrogen of the non-single crystal semiconductor in the channel forming region are 5X1018
It is preferable that the impurity concentration is less than cm-". That is, in the conventionally known IGF, the impurity concentration is
The mixture was mixed to a concentration of 3 x 1020 cm-3.

アモルファス珪素半導体を用いる場合においては、キャ
リア特にホールのもつライフタイムが短くなり、特性が
本発明が有する特性の１／３以下の電流しか流れない。In the case of using an amorphous silicon semiconductor, the lifetime of carriers, especially holes, is shortened, and the current flowing therein has characteristics that are 1/3 or less of the characteristics possessed by the present invention.

加えてヒステリシス特性を１００　ＶＧＧ特性にドレイ
ン電界を２ｘ１０６Ｖ／ｃｍ以上加える場合に観察され
てしまった。また他方酸素を５　ＸＩＯ”ｃｍ−”以下
とすると、３Ｘ１０６Ｖ／ｃｍの電圧においてもヒステ
リシスの存在が観察されなかったIn addition, hysteresis characteristics were observed when a drain electric field of 2×10 6 V/cm or more was added to the 100 VGG characteristics. On the other hand, when oxygen was set to less than 5XIO"cm-", no hysteresis was observed even at a voltage of 3X106V/cm.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の絶縁ゲイト型電界効果半導体装置の製
造工程の縦断面図を示す。 第２図はドレイン電流−ドレイン電圧の特性を示す。 （１２） 茎１０ ト−Ｌｌシ１シンＥ（、し） 京ＰωFIG. 1 shows a longitudinal sectional view of the manufacturing process of an insulated gate field effect semiconductor device of the present invention. FIG. 2 shows the drain current-drain voltage characteristics. (12) Stem 10 To-Ll shi 1 Shin E (, shi) Kyo Pω

Claims (1)

【特許請求の範囲】 １、絶縁ゲイト型電界効果トランジスタのチャネル形成
領域は水素またはハロゲン元素が添加された非単結晶半
導体よりなり、該半導体に隣接するソースおよびドレイ
ンを構成する一対の不純物領域は前記非単結晶半導体よ
りも結晶化が助長されて設けられ、かつ該結晶化が助長
されて設けられた領域は前記ゲイト電極下のチャネル形
成領域の内部にわたって設けられたことを特徴とする絶
縁ゲイト型半導体装置。 ２、特許請求の範囲第１項において、水素またはハロゲ
ン元素が１原子％以上の濃度に添加されたチャネル形成
領域は非単結晶半導体と該半導体に比べて結晶化が助長
されて設けられた半導体とにより設けられたことを特徴
とする絶縁ゲイト型半導体装置。[Claims] 1. A channel forming region of an insulated gate field effect transistor is made of a non-single crystal semiconductor doped with hydrogen or a halogen element, and a pair of impurity regions constituting a source and a drain adjacent to the semiconductor are An insulated gate characterized in that crystallization is promoted more than in the non-single crystal semiconductor, and the region where the crystallization is promoted extends over the inside of the channel forming region under the gate electrode. type semiconductor device. 2. In claim 1, the channel forming region doped with hydrogen or a halogen element at a concentration of 1 atomic % or more is a non-single crystal semiconductor and a semiconductor provided with accelerated crystallization compared to the semiconductor. An insulated gate type semiconductor device characterized by being provided with.
JP10025184A 1984-05-18 1984-05-18 Insulated gate type semiconductor device Pending JPS60245173A (en)

Priority Applications (13)

Application Number Priority Date Filing Date Title
JP10025184A JPS60245173A (en) 1984-05-18 1984-05-18 Insulated gate type semiconductor device
US06/912,498 US4727044A (en) 1984-05-18 1986-09-29 Method of making a thin film transistor with laser recrystallized source and drain
US07/153,477 US4959700A (en) 1984-05-18 1988-02-03 Insulated gate field effect transistor and its manufacturing method
US07/707,178 US5142344A (en) 1984-05-18 1991-05-24 Insulated gate field effect transistor and its manufacturing method
JP4333725A JP2648784B2 (en) 1984-05-18 1992-11-20 Insulated gate field effect semiconductor device for liquid crystal display panel
US07/987,179 US5315132A (en) 1984-05-18 1992-12-08 Insulated gate field effect transistor
US08/054,842 US5313077A (en) 1984-05-18 1993-04-30 Insulated gate field effect transistor and its manufacturing method
US08/171,769 US6660574B1 (en) 1984-05-18 1993-12-22 Method of forming a semiconductor device including recombination center neutralizer
US08/473,953 US5543636A (en) 1984-05-18 1995-06-07 Insulated gate field effect transistor
US08/944,136 US6680486B1 (en) 1984-05-18 1997-10-06 Insulated gate field effect transistor and its manufacturing method
US08/947,731 US6221701B1 (en) 1984-05-18 1997-10-16 Insulated gate field effect transistor and its manufacturing method
US09/406,794 US6635520B1 (en) 1984-05-18 1999-09-28 Operation method of semiconductor devices
US09/406,791 US6734499B1 (en) 1984-05-18 1999-09-28 Operation method of semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10025184A JPS60245173A (en) 1984-05-18 1984-05-18 Insulated gate type semiconductor device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP4333725A Division JP2648784B2 (en) 1984-05-18 1992-11-20 Insulated gate field effect semiconductor device for liquid crystal display panel
JP6314313A Division JP2996888B2 (en) 1994-11-25 1994-11-25 Insulated gate field effect semiconductor device

Publications (1)

Publication Number Publication Date
JPS60245173A true JPS60245173A (en) 1985-12-04

Family

ID=14269004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10025184A Pending JPS60245173A (en) 1984-05-18 1984-05-18 Insulated gate type semiconductor device

Country Status (1)

Country Link
JP (1) JPS60245173A (en)

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US5294821A (en) * 1990-10-09 1994-03-15 Seiko Epson Corporation Thin-film SOI semiconductor device having heavily doped diffusion regions beneath the channels of transistors
JPH0799317A (en) * 1993-08-12 1995-04-11 Semiconductor Energy Lab Co Ltd Insulated thin-film gate type semiconductor device and manufacture thereof
US5849601A (en) * 1990-12-25 1998-12-15 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for manufacturing the same
US5859445A (en) * 1990-11-20 1999-01-12 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device including thin film transistors having spoiling impurities added thereto
US5917225A (en) * 1992-03-05 1999-06-29 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor having specific dielectric structures
US5962870A (en) * 1991-08-26 1999-10-05 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices
US6013928A (en) * 1991-08-23 2000-01-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having interlayer insulating film and method for forming the same
US6147375A (en) * 1992-02-05 2000-11-14 Semiconductor Energy Laboratory Co., Ltd. Active matrix display device
US6204099B1 (en) 1995-02-21 2001-03-20 Semiconductor Energy Laboratory Co., Ltd. Method for producing insulated gate thin film semiconductor device
US6271066B1 (en) 1991-03-18 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor material and method for forming the same and thin film transistor
US6323069B1 (en) 1992-03-25 2001-11-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor using light irradiation to form impurity regions
US6331717B1 (en) 1993-08-12 2001-12-18 Semiconductor Energy Laboratory Co. Ltd. Insulated gate semiconductor device and process for fabricating the same
US6337731B1 (en) 1992-04-28 2002-01-08 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US6369788B1 (en) 1990-11-26 2002-04-09 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same
US6479329B2 (en) 1994-09-16 2002-11-12 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device
US6562672B2 (en) 1991-03-18 2003-05-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor material and method for forming the same and thin film transistor
US6624450B1 (en) * 1992-03-27 2003-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US6797550B2 (en) 2001-12-21 2004-09-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method therefor
US6893906B2 (en) 1990-11-26 2005-05-17 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same
US6911358B2 (en) 2001-12-28 2005-06-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
CN106098542A (en) * 2016-06-20 2016-11-09 中国工程物理研究院电子工程研究所 A kind of method promoting silicon carbide power device reverse BV

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JPS582073A (en) * 1981-06-29 1983-01-07 Sony Corp Field effect transistor

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
JPS582073A (en) * 1981-06-29 1983-01-07 Sony Corp Field effect transistor

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US5294821A (en) * 1990-10-09 1994-03-15 Seiko Epson Corporation Thin-film SOI semiconductor device having heavily doped diffusion regions beneath the channels of transistors
US7462515B2 (en) 1990-11-13 2008-12-09 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same
US5859445A (en) * 1990-11-20 1999-01-12 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device including thin film transistors having spoiling impurities added thereto
US6011277A (en) * 1990-11-20 2000-01-04 Semiconductor Energy Laboratory Co., Ltd. Gate insulated field effect transistors and method of manufacturing the same
US6893906B2 (en) 1990-11-26 2005-05-17 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same
US6369788B1 (en) 1990-11-26 2002-04-09 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and driving method for the same
US5849601A (en) * 1990-12-25 1998-12-15 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for manufacturing the same
US6271066B1 (en) 1991-03-18 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor material and method for forming the same and thin film transistor
US6562672B2 (en) 1991-03-18 2003-05-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor material and method for forming the same and thin film transistor
US6013928A (en) * 1991-08-23 2000-01-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having interlayer insulating film and method for forming the same
US6331723B1 (en) 1991-08-26 2001-12-18 Semiconductor Energy Laboratory Co., Ltd. Active matrix display device having at least two transistors having LDD region in one pixel
US5962870A (en) * 1991-08-26 1999-10-05 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices
US6803600B2 (en) 1991-08-26 2004-10-12 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices and method of manufacturing the same
US7821011B2 (en) 1991-08-26 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices and method of manufacturing the same
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US6476447B1 (en) 1992-02-05 2002-11-05 Semiconductor Energy Laboratory Co., Ltd. Active matrix display device including a transistor
US5917225A (en) * 1992-03-05 1999-06-29 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor having specific dielectric structures
US6323069B1 (en) 1992-03-25 2001-11-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor using light irradiation to form impurity regions
US6887746B2 (en) 1992-03-25 2005-05-03 Semiconductor Energy Lab Insulated gate field effect transistor and method for forming the same
US6569724B2 (en) 1992-03-25 2003-05-27 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor and method for forming the same
US6624450B1 (en) * 1992-03-27 2003-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
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US6500703B1 (en) 1993-08-12 2002-12-31 Semicondcutor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and process for fabricating the same
US6437366B1 (en) 1993-08-12 2002-08-20 Semiconductor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and process for fabricating the same
US6331717B1 (en) 1993-08-12 2001-12-18 Semiconductor Energy Laboratory Co. Ltd. Insulated gate semiconductor device and process for fabricating the same
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US7381598B2 (en) 1993-08-12 2008-06-03 Semiconductor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and process for fabricating the same
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US7229861B2 (en) 1994-09-16 2007-06-12 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device
US6204099B1 (en) 1995-02-21 2001-03-20 Semiconductor Energy Laboratory Co., Ltd. Method for producing insulated gate thin film semiconductor device
US7045403B2 (en) 1995-02-21 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Method for producing insulated gate thin film semiconductor device
US6921686B2 (en) 1995-02-21 2005-07-26 Semiconductor Energy Laboratory Co., Ltd. Method for producing insulated gate thin film semiconductor device
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US6797550B2 (en) 2001-12-21 2004-09-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method therefor
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