JPH0396279A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0396279A
JPH0396279A JP23333089A JP23333089A JPH0396279A JP H0396279 A JPH0396279 A JP H0396279A JP 23333089 A JP23333089 A JP 23333089A JP 23333089 A JP23333089 A JP 23333089A JP H0396279 A JPH0396279 A JP H0396279A
Authority
JP
Japan
Prior art keywords
semiconductor device
thin film
decomposed
hydrogen gas
silicon thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23333089A
Other languages
Japanese (ja)
Inventor
Hideaki Oka
秀明 岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP23333089A priority Critical patent/JPH0396279A/en
Publication of JPH0396279A publication Critical patent/JPH0396279A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a simple method which completely eliminates a defect due to damage by a plasma and whose mass production operation is easy while an effect to enhance a TFT characteristic is being secured by a method wherein a semiconductor device in which at least one part of a channel region of a field-effect transistor is composed of a non-single-crystal semiconductor is put in an atmosphere in which hydrogen gas has been decomposed by an optical pumping method. CONSTITUTION:In a manufacturing method of a semiconductor device in which at least one part of a channel region of an insulated-gate field-effect transistor is composed of a non-single-crystal semiconductor, at least a process to put the semiconductor device in an atmosphere in which hydrogen gas has been decomposed by an optical pumping method is included. For example, a non-singlecrystal silicon thin film 1-2 is formed on an insulating amorphous material 1-1 ; a gate oxide film 1-4 is formed by a thermal oxidation method; after that, a gate electrode 1-5 is formed; a source region 1-6 and a drain region 1-7 are formed. Then, an interlayer insulating film 1-8 is deposited; a heat treatment is executed; after that, hydrogen gas is decomposed by an optical pumping method; a hydrogen radical 1-9 whose activity is high is formed; a hydrogenation treatment is executed; then, contact electrodes 1-10 in the source region and the drain region are formed.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、絶縁性透明基板等のような非品質絶縁基板あ
るいは絶縁膜上に形成される非単結晶半導体薄膜を用い
て作成される薄膜トランジスタ等の薄膜半導体装置の製
造方法に関する.[従来の技術] 非晶貿シリコン薄膜あるいは多結晶シリコン薄膜等の非
単結晶半導体薄膜には、ダングリングボンドが多数存在
する.たとえば、多結晶シリコン薄膜に関しては、結晶
粒界に存在するダングリングボンド等の欠陥が、キャリ
アに対するトラップ準位となりキャリアの伝導に対して
障壁として働<.   (J.  Y.  W.   
Se.to,  J.  AppI.  Phys. 
, 46, p5247 (1975) ).従って、
多結晶シリコン薄膜トランジスタの性能を向上させる為
には、前記欠陥を低減させる必要がある.   (J.
  Appl.  Phys.  ,  53  (2
),pll93 (1982)).  この目的の為に
水素による前記欠陥の終端化が行われており、その主な
方法として、水素プラズマ処理法、水素イオン注入法、
あるいはプラズマ窒化膜からの水素の拡散法等が知られ
ている. [本発明が解決しようとする課M] しかし、水素イオン注入法においては、イオン注入装置
と言う高価な装置を必要とする欠点を有しており、プラ
ズマ窒化膜からの水素の拡散法においては、必要としな
い窒化膜が成膜されるという欠点を有する.又、水素プ
ラズマ処理法ではプラズマ損傷によるダメージが発生し
、量産化を困難なものとしている. そこで、本発明はTPT特性向上の効果を確保しつつ、
前述のプラズマ損傷による不良を皆無にし、更に、量産
化の容易な簡便な方法を提供することを目的とする. [課題を解決するための手段] 本発明の半導体装置は、以下の特徴を有する.(1)絶
縁ゲイト型電界効果トランジスタのチャンネル領域の少
なくとも一部が非単結晶半導体よりなる半導体装置の製
造方法において、水素ガスを光励起法で分解した雰囲気
中に、該半導体装置を浸す工程を少なくとも有する. (2)絶縁ゲイト型電界効果トランジスタのチャンネル
領域の少なくとも一部が非単結晶半専体よりなる半導体
装置の製造方法において、アンモニア等の水素原子を含
むガスを光励起法で分解した雰囲気中に浸す工程を少な
くとも有する.(3)前記光励起法で所定のガスを分解
する工程において、水銀を増感材として用いる.[実施
例] 本発明の実施例lを、第1図の薄膜トランジスタの工程
図にしたがって説明する.同図(a)は、ガラス、石英
等の絶縁性非品質基板若しくはSi02等の絶縁性非晶
買材料層等の絶縁性非晶質材料1−1上に、非単結晶性
のシリコン薄膜を堆積させ、その後ホトリソグラフイ法
により非単結晶シリコン薄膜1−2を形成する工程であ
る.前記シリコン薄膜の形成方法としては次に述べるよ
うな方法がある. (1)減圧CVD法、MBE法(M
o1ecular  Beam  Epitaxy)、
等の方法で多結晶シリコン薄膜を堆積させる.(2)E
B (Electron  Beam)蒸着法、スパツ
タ法、プラズマCVD法、光励起CVD法、減圧CVD
法、MBE法、等の方法で、非晶質シリコン薄膜若しく
は微結晶シリコン薄膜を堆積させる.例えば、減圧CV
D法においては、デボ温度を約550℃以下にすれば非
晶質シリコン薄膜が堆積させられる. 同図(b)は、熱酸化法によりゲート酸化膜1−4を形
成する工程である.ドライ酸化法を用いれば酸素雰囲気
で約1150℃の熱処理によって、破壊耐圧の高い良質
のゲート酸化膜を得ることができる.ウェット酸化法を
用いれば900℃程度の低温でも酸化膜が形成されるが
、ドライ酸化法で形成された膜に比べれば破壊耐圧は低
く、膜質は劣る.この酸化工程により前記非単結晶シリ
コン薄膜1−2は、熱処理による結晶成長が進み、多結
晶シリコン薄膜1−3となる.前記非単結晶シリコン薄
膜1−2として多結晶シリコン薄膜を用いた場合には、
前記酸化工程後の多結晶シリコン薄膜1−3の結晶粒径
は2000A〜3000A程度の大きさとなる.前記非
単結晶シリコン薄膜1−2として非晶買シリコン薄膜若
しくは微結晶シリコン薄膜を用いた場合には、前記結晶
粒径は5000Aから数μmの大きさに結晶成長する.
同図(C)は、ゲート電極1−5を形成し、ソース・ド
レイン領域を形成する工程である.該ゲート電極材料に
は、一般的に多結晶シリコンが用いられている.該ゲー
ト電極1−5をマスクとして不純物元素をイオン注入し
て、ソース領域1−6及びドレイン領域1−7を形或す
る.前記不純物元素としては、リン、ヒ素あるいはボロ
ン等が用いられている. 同図(d)は、層間絶縁膜1−8を堆積させ、前記ソー
ス領域1−6及びドレイン領域1−7の不純物活性化と
、前記層間絶縁膜1−8の緻密化の目的で600℃〜1
.000℃程度の熱処理を行う工程である. 同図(e)は、光励起法で水素ガス、アンモニアガス等
の水素元素を含むガスを分解し、活性度の高い水素ラジ
カル1−9を形成して、水素化処理を行う工程である.
光励起法には、 (1)直接水素ガス等を励起し、分解
する方法、 (2)水銀等の増感材を用い、光照射によ
って、まず増感材を励起し、励起された増感材が水素ガ
ス等を分解する方法がある.以下に、増感材として水銀
を用いた水銀増感法の実施例を述べる.装置としては、
通常の光CVD装置等を用いることができる.まず、反
応室の中に基板をセットし、該反応室中に水素ガス等を
導入する.更に、増感材となる水銀を導入する. (内
圧は0.1〜2Torr程度とする.〉続いて、低圧水
銀ランプ、Xeランブ、重水素ランプ等の光源を用いて
、光を照射し、水銀を励起させる.励起された水銀は、
下記の反応式に従って、水素ガスを分解し、水素ラジカ
ルを生成する. Hg     十    hy    +    Hg
”Hg”   十    H2     →   2H
     +    Hgこうして、活性度の高い水素
ラジカルが基板中に導入され、多結晶シリコンの結晶粒
界部に存在する欠陥を終端化する.尚、水素ラジカルの
拡散速度を高め、処理時間を短縮する為に、基板温度は
200℃〜400℃程度が適当である.例一木ば、35
0℃〜400℃程度で処理した場合は、2 .0分〜3
0分程度の処理で十分な特性の向上がみられた. 同図(f)は、ソース領域及びドレイン領域のコンタク
ト電極1−10を形成する工程である.該コンタクト電
極材料としてtよアルミニュウムやクロムやニッケル等
の金属材料を用いる.尚、実施例では、水銀を増感剤と
して用いる場合を示したが(水銀増感法)、本発明はこ
れに限定されるものではない.例えば、紫外光によって
、水素ガスを直接分解する方法もあるが、水素ガスを直
接光励起法で分解するには100nm程度の紫外光を必
要とするため、2 5 0 nm程度の光を用いること
のできる水銀増感法の方が装置構戒上望ましい.また、
水素ガスの代わりに、アンモニア等の水素原子を含むガ
スを用いる方法もある.アンモニアを用いた場合を例に
とると、210nm以下の光を吸収し、190nm程度
に吸収率のピークを有するため、水素ガスを用いた場合
とは異なり、増感材を用いなくても、水銀ランプ、Xe
ランプ、重水素ランプ等の光源で容易に分解することが
できるという特徴がある. 本発明の実施例2を、第2図の薄膜トランジスタの工程
図にしたがって説明する.同図(a)は、ガラス、石英
等の絶縁性非品質基板若しくはSi02等の絶縁性非晶
質材料層等の絶縁性非晶質材料2−1上に、非単結晶性
のシリコン薄膜2−2を堆積させる工程である.堆積方
法については以前に述べたのでここでは省略する.2−
3は結晶粒界を示しており、a s − d e p 
O.  膜の結晶粒径は小さく欠陥が多い.尚、図(a
)では多結晶シリコン薄膜を堆積した場合を説明してい
るが、非晶買シリコン薄膜若しくは微結晶シリコン薄膜
を堆積してもよい. 同図(b)は、前記シリコン薄膜2−2を結晶成長させ
て、多結晶シリコン薄膜2−4を成長させる工程である
.前記シリコン薄膜2−2が非品質若しくは微結晶であ
れば、固相成長法が有効である.窒素ガス等の不活性ガ
ス雰囲気中に基板を設置し、500℃〜700℃の低温
で数時間〜数百時間の結晶化アニールをすると、固相成
長して、その結晶粒径が数千人から数μmの大きさに成
長する.また前記シリコン薄膜2−2が多結晶であれば
、該多結晶にシリコンイオンをイオン注入し該多結晶を
非晶質化し、その後上述のような固相成長法を行−えば
結晶成長する.結晶粒径が大きくなるので第2図(b)
に示すように結晶粒界2−3の間隔が大きくなる.この
他にも結晶成長させる方法としては、レーザアニール再
結晶化法、電子ビームアニール再結晶化法、あるいはカ
ーボンストリップヒータによる溶融再結晶化法などの方
法がある.前記固相戒長法は、約700℃以下の低温プ
ロセスにも応用できるきわめて有効な方法である. 同図(C)は、ゲート酸化膜2−5を形成する工程であ
る.プラズマCVD法では200”C程度で該ゲート酸
化膜が積層され、CVD法では4oO℃程度で積層され
る.又、スパッタ法では室温〜300℃程度の低温で形
成できる.そのほかプラズマ酸化法、高圧酸化法、レー
ザ酸化法などの方法によれば、低温でゲート酸化膜を形
成することができる.通常の熱酸化法を用いても良いこ
とはいうまでもない.該熱酸化法については、実施例1
の項で述べたのでここでは省略する.同図(d)は、ゲ
ート電極2−6を形成し、次に該ゲート電極2−6をマ
スクとして不純物元素をイオン注入して、ソース領域2
−7およびドレイン領域2−8を形成し、水素化処理を
行う工程である.前記不純物元素としては、リン、ヒ素
、ボロン等が用いられている.層間絶縁膜2−9を、L
PCVD法、AP CVD法、スパッタ法、ECRプラ
ズマCVD法、光CVD法などの方法で堆積させる.そ
の後、前記ソース領域とドレイン領域の活性化と、前記
層間絶縁膜の緻密化の目的で600℃〜1000℃程度
の熱処理を行う.次に、水素化処理を行う,2−10は
活性度の高い水素ラジカルを示している.水素化処理に
ついては実施例1の項で述べたのでここでは省略する.
同図(e)は、ソース領域及びドレイン領域とのコンタ
クト電極2−11を形成する工程である.尚、第1図及
び第zl!Iは製造工程の一例であり、水素化処理を行
う工程はゲート電極1−5、2−6形成前に行うことも
電極1−10、2−11形成後に行うこともできる. また、チャンネル領域に不純物をドーピングして、vt
h (L,きい値電圧)を制御することもできる.水素
化処理を行うと、Nチャンネルトランジスタがデブレッ
ション方向にvthがシフトし、Pチャンネルトランジ
スタがエンハンスメント方向にシフトするが、チャンネ
ル領域に1015〜10”/cm”程度の不純物をドー
ブすることで、Vthを制御することができる.例えば
、第1図において、ゲート電極を形成する前に、イオン
インプラ法等でB(ボロン)等の不純物を1011〜1
013/Cm2程度のドーズ量で打ち込む等の方法があ
る.特に、ドーズ量が前述の値程度であれば、Pチャン
ネルトランジスタ、Nチャンネルトランジスタ共オフ電
流が最小になるように、vthを制御することができる
.従って、CMOS型のTPT素子を形成する場合にお
いてもPch,Nchを選択的にチャンネルドーブせず
に、全面を同一の工程でチャンネルドーブすることもで
きる.前述のように、従来の水素プラズマ処理では、プ
ラズマ損傷による不良が多発し、実用化を困難なものと
していた.その原因は、プラズマ雰囲気中に浸されたこ
とにより、チャージアップが起こり、ゲート膜に電圧が
加わった状態になり、更に、基板温度が300℃程度と
比較的高いため、一種のBT (Bias−Tempe
rature)ストレスでTPTの不良が生じたと考え
られる.従って、不良を低減するには、チャージアップ
を防止する対策が特に有効であることが予測される.本
発明の光励起法で水素ガス等を分解する方法では、イオ
ン種によるチャージアップが殆ど起こらないため、ダメ
ージが著しく低減されることが判った. 以上述べたように、本発明を応用すれば、ON電流が大
きく、OFF電流が小さく、サブスレッシュホルド領域
の立ち上がりが急峻で、信頼性の優れた薄膜トランジス
タをプラズマ損傷等による不良も無く製造することがで
きる. 本発明の応用としては、例えば、アクティブマトリクス
基板に本発明を用いると、ドライバー内蔵高精細パネル
が実現する.また、シフトレジスタ回路と光電変換素子
を同一基板に集積したイメージセンサーに用いれば、高
速読み取りや、A3版等のような大型化や、あるいは、
カラー化等に対して大きな効果が期待できる.駆動電圧
の低減もできるので、低消費電力化にも役立ち、さらに
は信頼性の向上にも役立つ.更に、実施例2で説明した
ように、約700℃以下の低温プロセスに本発明を応用
することにより、大面積で高性能な半導体装置も実現可
能となる. 第3図に本発明の応用の一例として、シフトレジスタ回
路と光電変換素子を同一基板に集積したイメージセンサ
ーの断面図を示す.第3図において、3−1はガラス、
石英等の非晶買絶縁基板、3−2はゲート絶縁膜、3−
3はゲート電極、3−4はソース・ドレイン領域、3−
5は層間絶縁膜、3−6は光電変換素子の下部透明電極
、3−7は非晶質シリコン層、3−9は光電変換素子の
上部電極及び配線である.尚、第3図では簡単のため、
光電変換素子とその画1gswを成すTPTの断面図の
みを示してある,TPTの形成方法の詳細は第1図及び
第2図で述べたのでここでは省く.水素化処理を行った
後、層間絶縁膜3−5上に、充電変換素子の下部電極と
なる透明電極を形成する.該透明電極は、ITO,Sn
02等をスパッタ法等で形成しバターニングすることで
形成される.続いて、プラズマCVD法等で光電変換層
を成す非晶質シリコン層を形成し、パターン形成後、層
間絶縁膜3−5にコンタクト穴を開け、A1、Cr等の
金属材料で配線及び充電変換素子の上部電極を同一工程
で形成する.本発明の水素化処理を施すことで、前述の
通りTPT特性が向上し、シフトレジスタの走査速度が
向上した.従来のイメージセンサーがA4  200D
PIで5ms / l i n eであったものが、本
発明によりA4200DPIで1 m s / l i
 n eまで高速化することが出来た.この様に本発明
は、イメージセンサーの長尺化やカラーイメージセンサ
ーの実現等に対しても大きな効果がある. 尚、第1図〜第3図では、poly−SiTFT製造工
程に本発明を適用した場合を例としたが、本発明はこれ
に限定されるものではない.本発明は、チャンネル領域
の少なくとも一部が多結晶である絶縁ゲート型電界効果
トランジスタ全てに対して有効である.また、チャンネ
ル領域の少なくとも一部が微結晶であるトランジスタや
、スパッタ法や蒸着法等で形成した水素化が不十分な非
品質半導体がチャンネル領域の一部を成すトランジスタ
においても本発明は有効である. また、チャンネル領域が単結晶であっても、三次元IC
の様に再結晶化または固相成長させたシリコン層に素子
を形成する場合、結晶内に亜粒界等の欠陥を生じ易い.
その場合、本発明に基づく半導体装置の製造方法で、欠
陥の終端化を行うと特性の向上に効果がある. さらに、HBT (ヘテロバイボーラトランジスタ)等
のへテロ接合界面の欠陥密度の低減に対しても本発明は
有効である.特に、ヘテロ接合を形成する二つの半導体
層のうちの少なくとも一方が、非単結晶半導体よりなる
場合は、本発明による水素化処理により、膜中及び界面
の欠陥を同時に低減することが出来る. また、非単結晶半導体を素子材とした太陽電池・光セン
サやバイボーラトランジスタ、静電誘導トランジスタを
はじめとして本発明は幅広く半導体プロセス全般に応用
することができる.[発明の効果] 以上述べたように、本発明によればpoly−SiTF
T等のチャンネル領域の少なくとも一部が非単結晶半導
体よりなる絶縁ゲイト型電界効果トランジスタの高性能
化を、プラズマ損傷等による不良もなく実現できる.ま
た、本発明は絶縁ゲイト型電界効果トランジスタに限ら
ず、半導体プロセス全般に渡り広く応用することができ
、その効果はきわめて大きい.
Detailed Description of the Invention [Industrial Application Field] The present invention relates to a thin film transistor manufactured using a non-single crystal semiconductor thin film formed on a non-quality insulating substrate or insulating film such as an insulating transparent substrate. Related to methods for manufacturing thin film semiconductor devices such as. [Prior Art] Many dangling bonds exist in non-single crystal semiconductor thin films such as amorphous silicon thin films or polycrystalline silicon thin films. For example, in polycrystalline silicon thin films, defects such as dangling bonds that exist at grain boundaries become trap levels for carriers and act as barriers to carrier conduction. (J.Y.W.
Se. to, J. AppI. Phys.
, 46, p5247 (1975)). Therefore,
In order to improve the performance of polycrystalline silicon thin film transistors, it is necessary to reduce the defects mentioned above. (J.
Appl. Phys. , 53 (2
), pll93 (1982)). For this purpose, the defects are terminated with hydrogen, and the main methods include hydrogen plasma treatment, hydrogen ion implantation,
Alternatively, a method of hydrogen diffusion from a plasma nitride film is known. [Problem M to be solved by the present invention] However, the hydrogen ion implantation method has the drawback of requiring an expensive device called an ion implanter, and the hydrogen ion diffusion method from the plasma nitride film However, this method has the disadvantage that an unnecessary nitride film is deposited. Furthermore, the hydrogen plasma treatment method causes damage due to plasma damage, making mass production difficult. Therefore, the present invention secures the effect of improving TPT characteristics while
The purpose is to eliminate the defects caused by the plasma damage mentioned above, and to provide a simple method that can be easily mass-produced. [Means for Solving the Problems] The semiconductor device of the present invention has the following features. (1) A method for manufacturing a semiconductor device in which at least a portion of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, including at least the step of immersing the semiconductor device in an atmosphere in which hydrogen gas is decomposed by a photoexcitation method. have. (2) In a method for manufacturing a semiconductor device in which at least a part of the channel region of an insulated gate field effect transistor is semi-exclusively made of a non-single crystal, the method includes immersing the semiconductor device in an atmosphere in which a gas containing hydrogen atoms such as ammonia is decomposed by a photoexcitation method. It has at least a process. (3) Mercury is used as a sensitizing material in the step of decomposing a predetermined gas by the photoexcitation method. [Example] Example 1 of the present invention will be explained according to the process diagram of a thin film transistor shown in FIG. Figure (a) shows a non-monocrystalline silicon thin film on an insulating amorphous material 1-1 such as an insulating non-quality substrate such as glass or quartz or an insulating amorphous material layer such as Si02. In this step, a non-single crystal silicon thin film 1-2 is formed using a photolithography method. The following methods are available for forming the silicon thin film. (1) Low pressure CVD method, MBE method (M
o1ecular beam epitaxy),
A polycrystalline silicon thin film is deposited using the following method. (2)E
B (Electron Beam) evaporation method, sputtering method, plasma CVD method, photoexcitation CVD method, low pressure CVD
An amorphous silicon thin film or a microcrystalline silicon thin film is deposited by a method such as a method such as a method, an MBE method, or the like. For example, reduced pressure CV
In method D, an amorphous silicon thin film can be deposited by setting the debo temperature to about 550°C or less. FIG. 2B shows a step of forming a gate oxide film 1-4 by a thermal oxidation method. Using the dry oxidation method, a high-quality gate oxide film with high breakdown voltage can be obtained by heat treatment at approximately 1150°C in an oxygen atmosphere. If a wet oxidation method is used, an oxide film can be formed even at a low temperature of about 900°C, but the breakdown voltage is lower and the film quality is inferior to that of a film formed by a dry oxidation method. Through this oxidation step, the non-single crystal silicon thin film 1-2 progresses in crystal growth due to heat treatment, and becomes a polycrystalline silicon thin film 1-3. When a polycrystalline silicon thin film is used as the non-single crystal silicon thin film 1-2,
The crystal grain size of the polycrystalline silicon thin film 1-3 after the oxidation process is about 2000A to 3000A. When an amorphous silicon thin film or a microcrystalline silicon thin film is used as the non-single crystal silicon thin film 1-2, the crystal grain size grows from 5000A to several μm.
Figure (C) shows the step of forming the gate electrode 1-5 and forming the source/drain regions. Polycrystalline silicon is generally used as the gate electrode material. Using the gate electrode 1-5 as a mask, impurity elements are ion-implanted to form a source region 1-6 and a drain region 1-7. Phosphorus, arsenic, boron, etc. are used as the impurity element. In the same figure (d), an interlayer insulating film 1-8 is deposited at 600°C for the purpose of activating impurities in the source region 1-6 and drain region 1-7 and densifying the interlayer insulating film 1-8. ~1
.. This is a process that involves heat treatment at approximately 000°C. Figure (e) shows a step in which a gas containing hydrogen such as hydrogen gas or ammonia gas is decomposed by a photoexcitation method to form highly active hydrogen radicals 1-9, and hydrogenation treatment is performed.
The photoexcitation method includes (1) a method of directly exciting and decomposing hydrogen gas, etc., (2) a method of using a sensitizer such as mercury, first exciting the sensitizer by light irradiation, and decomposing the excited sensitizer. There is a method for decomposing hydrogen gas etc. An example of a mercury sensitization method using mercury as a sensitizing material is described below. As a device,
A normal optical CVD device or the like can be used. First, a substrate is set in a reaction chamber, and hydrogen gas or the like is introduced into the reaction chamber. Furthermore, mercury is introduced as a sensitizing material. (The internal pressure should be approximately 0.1 to 2 Torr.) Next, light is irradiated using a light source such as a low-pressure mercury lamp, a Xe lamp, or a deuterium lamp to excite the mercury. The excited mercury is
Hydrogen gas is decomposed to generate hydrogen radicals according to the reaction formula below. Hg hy + Hg
“Hg” 10 H2 → 2H
+Hg In this way, highly active hydrogen radicals are introduced into the substrate, terminating defects existing at the grain boundaries of polycrystalline silicon. Incidentally, in order to increase the diffusion rate of hydrogen radicals and shorten the processing time, it is appropriate for the substrate temperature to be about 200°C to 400°C. Example: 35
2. When processed at about 0°C to 400°C. 0 minutes to 3
Sufficient improvement in properties was observed after approximately 0 minutes of treatment. FIG. 5(f) shows a step of forming contact electrodes 1-10 in the source and drain regions. A metal material such as aluminum, chromium, or nickel is used as the contact electrode material. In addition, although the example shows the case where mercury is used as a sensitizer (mercury sensitization method), the present invention is not limited to this. For example, there is a method of directly decomposing hydrogen gas using ultraviolet light, but since decomposing hydrogen gas by direct photoexcitation requires ultraviolet light of about 100 nm, it is not recommended to use light of about 250 nm. The mercury sensitization method is preferable in terms of equipment configuration. Also,
There is also a method of using a gas containing hydrogen atoms, such as ammonia, instead of hydrogen gas. For example, when ammonia is used, it absorbs light of 210 nm or less and has an absorption peak at about 190 nm, so unlike when hydrogen gas is used, mercury can be Lamp, Xe
It has the characteristic that it can be easily decomposed using light sources such as lamps and deuterium lamps. Embodiment 2 of the present invention will be explained according to the process diagram of a thin film transistor shown in FIG. Figure (a) shows a non-monocrystalline silicon thin film 2 on an insulating amorphous material 2-1 such as an insulating non-quality substrate such as glass or quartz or an insulating amorphous material layer such as Si02. This is the process of depositing -2. The deposition method has been described previously, so it will be omitted here. 2-
3 indicates the grain boundary, a s - d e p
O. The crystal grain size of the film is small and there are many defects. In addition, figure (a
) describes the case where a polycrystalline silicon thin film is deposited, but an amorphous silicon thin film or a microcrystalline silicon thin film may also be deposited. FIG. 2B shows a step of crystal-growing the silicon thin film 2-2 to grow a polycrystalline silicon thin film 2-4. If the silicon thin film 2-2 is of poor quality or microcrystalline, solid phase growth is effective. When a substrate is placed in an inert gas atmosphere such as nitrogen gas and crystallized annealed at a low temperature of 500°C to 700°C for several hours to hundreds of hours, solid phase growth occurs and the crystal grain size increases to several thousand nanometers. It grows to a size of several micrometers. Further, if the silicon thin film 2-2 is polycrystalline, silicon ions are implanted into the polycrystal to make the polycrystalline amorphous, and then the solid phase growth method described above is performed to grow the crystal. As the crystal grain size increases, Figure 2(b)
As shown in , the interval between grain boundaries 2-3 becomes larger. Other crystal growth methods include laser annealing recrystallization, electron beam annealing recrystallization, and melt recrystallization using a carbon strip heater. The solid-phase method is an extremely effective method that can be applied to low-temperature processes below about 700°C. FIG. 2C shows a step of forming a gate oxide film 2-5. In the plasma CVD method, the gate oxide film is deposited at a temperature of about 200"C, and in the CVD method, it is deposited at a temperature of about 400"C.In addition, by the sputtering method, it can be formed at a low temperature of about room temperature to about 300"C.In addition, the plasma oxidation method, high pressure Gate oxide films can be formed at low temperatures using methods such as oxidation and laser oxidation.It goes without saying that ordinary thermal oxidation may also be used. Example 1
Since it was mentioned in the previous section, it will be omitted here. In the same figure (d), a gate electrode 2-6 is formed, and then an impurity element is ion-implanted using the gate electrode 2-6 as a mask to form a source region 2-6.
-7 and drain region 2-8 are formed, and hydrogenation treatment is performed. Phosphorus, arsenic, boron, etc. are used as the impurity elements. The interlayer insulating film 2-9 is
Deposition is performed by a method such as a PCVD method, an AP CVD method, a sputtering method, an ECR plasma CVD method, or a photoCVD method. Thereafter, heat treatment is performed at approximately 600° C. to 1000° C. for the purpose of activating the source region and drain region and densifying the interlayer insulating film. Next, hydrogenation treatment is performed. 2-10 shows highly active hydrogen radicals. Since the hydrogenation treatment was described in the section of Example 1, it will be omitted here.
FIG. 4(e) shows a step of forming contact electrodes 2-11 with the source and drain regions. In addition, Fig. 1 and No. zl! I is an example of a manufacturing process, and the hydrogenation process can be performed before forming the gate electrodes 1-5 and 2-6, or after forming the electrodes 1-10 and 2-11. Also, by doping impurities into the channel region, vt
It is also possible to control h (L, threshold voltage). When hydrogenation treatment is performed, the N-channel transistor shifts vth in the depletion direction, and the P-channel transistor shifts in the enhancement direction, but by doping the channel region with impurities of about 1015 to 10"/cm", Vth can be controlled. For example, in FIG. 1, before forming the gate electrode, an impurity such as B (boron) is added to the
There are methods such as implanting with a dose of about 0.013/Cm2. Particularly, if the dose amount is about the above value, vth can be controlled so that the off-state currents of both the P-channel transistor and the N-channel transistor are minimized. Therefore, even when forming a CMOS type TPT element, the entire surface can be channel doped in the same process without selectively channel doping Pch and Nch. As mentioned above, conventional hydrogen plasma processing frequently causes defects due to plasma damage, making it difficult to put it into practical use. The reason for this is that immersion in the plasma atmosphere causes charge-up and voltage is applied to the gate film, and furthermore, the substrate temperature is relatively high at around 300°C, which is a type of BT (Bias- Tempe
It is thought that TPT failure occurred due to stress. Therefore, measures to prevent charge-up are expected to be particularly effective in reducing defects. It has been found that in the method of decomposing hydrogen gas etc. using the photoexcitation method of the present invention, damage is significantly reduced because charge-up by ion species hardly occurs. As described above, by applying the present invention, it is possible to manufacture a highly reliable thin film transistor with a large ON current, a small OFF current, a steep rise in the subthreshold region, and no defects due to plasma damage or the like. Can be done. For example, when the present invention is applied to an active matrix substrate, a high-definition panel with a built-in driver can be realized. In addition, if it is used in an image sensor that integrates a shift register circuit and a photoelectric conversion element on the same substrate, it can be used for high-speed reading, large size such as A3 size, or
It can be expected to have a great effect on colorization, etc. Since the drive voltage can be reduced, it also helps reduce power consumption and improves reliability. Furthermore, as explained in Example 2, by applying the present invention to a low-temperature process of about 700° C. or less, a large-area, high-performance semiconductor device can be realized. As an example of the application of the present invention, FIG. 3 shows a cross-sectional view of an image sensor in which a shift register circuit and a photoelectric conversion element are integrated on the same substrate. In Figure 3, 3-1 is glass;
Amorphous insulating substrate such as quartz, 3-2 is gate insulating film, 3-
3 is a gate electrode, 3-4 is a source/drain region, 3-
5 is an interlayer insulating film, 3-6 is a lower transparent electrode of the photoelectric conversion element, 3-7 is an amorphous silicon layer, and 3-9 is an upper electrode and wiring of the photoelectric conversion element. In addition, in Figure 3, for simplicity,
Only a cross-sectional view of the photoelectric conversion element and the TPT that forms one gsw of the photoelectric conversion element is shown.The details of the method for forming the TPT have been described in FIGS. 1 and 2, so they are omitted here. After the hydrogenation treatment, a transparent electrode that will become the lower electrode of the charge conversion element is formed on the interlayer insulating film 3-5. The transparent electrode is made of ITO, Sn
It is formed by forming 02 etc. by sputtering method etc. and patterning it. Next, an amorphous silicon layer forming a photoelectric conversion layer is formed using a plasma CVD method or the like, and after patterning, contact holes are formed in the interlayer insulating film 3-5, and wiring and charge conversion are performed using a metal material such as A1 or Cr. The upper electrode of the device is formed in the same process. By applying the hydrogenation treatment of the present invention, the TPT characteristics were improved as described above, and the scanning speed of the shift register was improved. The conventional image sensor is A4 200D
What was 5ms/line with PI has been reduced to 1ms/line with A4200DPI by the present invention.
We were able to increase the speed to ne. In this way, the present invention has great effects on increasing the length of image sensors and realizing color image sensors. Although FIGS. 1 to 3 show an example in which the present invention is applied to a poly-SiTFT manufacturing process, the present invention is not limited to this. The present invention is effective for all insulated gate field effect transistors in which at least a portion of the channel region is polycrystalline. The present invention is also effective in transistors in which at least a portion of the channel region is made of microcrystals, or in transistors in which a portion of the channel region is made of a poor-quality semiconductor that is insufficiently hydrogenated and formed by sputtering or vapor deposition. be. Moreover, even if the channel region is single crystal, three-dimensional IC
When a device is formed in a silicon layer that has been recrystallized or grown in a solid phase, defects such as sub-grain boundaries are likely to occur within the crystal.
In this case, the characteristics can be effectively improved by terminating defects using the semiconductor device manufacturing method according to the present invention. Furthermore, the present invention is also effective in reducing the defect density at the heterojunction interface of HBTs (hetero-bibolar transistors) and the like. In particular, when at least one of the two semiconductor layers forming a heterojunction is made of a non-single crystal semiconductor, the hydrogenation treatment according to the present invention can simultaneously reduce defects in the film and at the interface. Furthermore, the present invention can be widely applied to semiconductor processes in general, including solar cells, optical sensors, bibolar transistors, and static induction transistors that use non-single crystal semiconductors as element materials. [Effects of the Invention] As described above, according to the present invention, poly-SiTF
It is possible to improve the performance of an insulated gate field effect transistor in which at least a portion of the channel region, such as T, is made of a non-single-crystal semiconductor without causing defects such as plasma damage. Further, the present invention can be widely applied not only to insulated gate field effect transistors but also to semiconductor processes in general, and its effects are extremely large.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)から(f)は、本発明における薄膜トラン
ジスタの工程図である. 第2図(a)から(e)は、本発明における薄膜トラン
ジスタの工程図である. 第3図は、本発明におけるイメージセンサーの断面図で
ある. 1−1.  2−1.  3−1; 絶縁性非晶質材料
1−2.  2−2     ; 非単結晶薄膜1−9
.2−10    ; 水素ラジカル2−3     
   ;結晶粒界 以上
FIGS. 1(a) to 1(f) are process diagrams of a thin film transistor according to the present invention. FIGS. 2(a) to 2(e) are process diagrams of the thin film transistor according to the present invention. FIG. 3 is a cross-sectional view of the image sensor according to the present invention. 1-1. 2-1. 3-1; Insulating amorphous material 1-2. 2-2; Non-single crystal thin film 1-9
.. 2-10; Hydrogen radical 2-3
; Above the grain boundary

Claims (3)

【特許請求の範囲】[Claims] (1)絶縁ゲイト型電界効果トランジスタのチャンネル
領域の少なくとも一部が非単結晶半導体よりなる半導体
装置の製造方法において、水素ガスを光励起法で分解し
た雰囲気中に、該半導体装置を浸す工程を少なくとも有
することを特徴とする半導体装置の製造方法。
(1) A method for manufacturing a semiconductor device in which at least a portion of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, including at least the step of immersing the semiconductor device in an atmosphere in which hydrogen gas is decomposed by a photoexcitation method. A method for manufacturing a semiconductor device, comprising:
(2)絶縁ゲイト型電界効果トランジスタのチャンネル
領域の少なくとも一部が非単結晶半導体よりなる半導体
装置の製造方法において、アンモニア等の水素原子を含
むガスを光励起法で分解した雰囲気中に浸す工程を少な
くとも有することを特徴とする半導体装置の製造方法。
(2) In a method for manufacturing a semiconductor device in which at least a portion of the channel region of an insulated gate field effect transistor is made of a non-single crystal semiconductor, the step of immersing the semiconductor device in an atmosphere in which a gas containing hydrogen atoms such as ammonia is decomposed by a photoexcitation method is performed. A method for manufacturing a semiconductor device, comprising at least the following.
(3)前記光励起法で所定のガスを分解する工程におい
て、水銀を増感材として用いたことを特徴とする請求項
1又は請求項2記載の半導体装置の製造方法。
(3) The method of manufacturing a semiconductor device according to claim 1 or 2, wherein mercury is used as a sensitizing material in the step of decomposing a predetermined gas by the optical excitation method.
JP23333089A 1989-09-08 1989-09-08 Manufacture of semiconductor device Pending JPH0396279A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23333089A JPH0396279A (en) 1989-09-08 1989-09-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23333089A JPH0396279A (en) 1989-09-08 1989-09-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0396279A true JPH0396279A (en) 1991-04-22

Family

ID=16953456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23333089A Pending JPH0396279A (en) 1989-09-08 1989-09-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0396279A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0621027A (en) * 1991-10-04 1994-01-28 Matsushita Electric Ind Co Ltd Method for removing damage of material
JPH08167596A (en) * 1994-12-09 1996-06-25 Sony Corp Plasma treatment device, plasma treatment method, and manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0621027A (en) * 1991-10-04 1994-01-28 Matsushita Electric Ind Co Ltd Method for removing damage of material
JPH08167596A (en) * 1994-12-09 1996-06-25 Sony Corp Plasma treatment device, plasma treatment method, and manufacture of semiconductor device

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