JPH08167596A - Plasma treatment device, plasma treatment method, and manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To provide a plasma treatment device which is capable of efficiently blocking out plasma to restrain it from causing damage to a work. CONSTITUTION: A plasma treatment device is equipped with a plasma generating chamber 10 which generates plasma and a plasma treatment chamber 20 where a work 50 to treat with plasma is arranged, wherein at least a plasma isolating mesh plate 40 is arranged between the plasma generating chamber 10 and the plasma treatment chamber 20, and openings 43 are provided in the mesh plate 40 and below twice as long in diameter as Debye length. Or, a voltage V0 which meets a formula, 0<V0 <=30 volts, may be applied to the mesh plate 40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma processing apparatus, a plasma processing method using the plasma processing apparatus, and a semiconductor device manufacturing method. More specifically,
The present invention relates to a plasma processing apparatus suitable for carrying out a remote plasma method for separating a plasma generation area and an object processing area, and more specifically, in a plasma CVD method, a plasma etching method, an ashing method, etc. The present invention relates to a plasma processing apparatus capable of satisfactorily processing a large-area processed object (for example, a wafer or various substrates) in a short time, a plasma processing method using the plasma processing apparatus, and a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art For example, in an active matrix type liquid crystal display device, its switching element is an insulated gate type transistor (MIS transistor).
It is composed of a TFT (Thin Film Transistor). And a large area MI
Studies for manufacturing an S-type semiconductor device by a low temperature process have been actively conducted. In this case, as the substrate,
A low melting point material such as borosilicate glass or plastic or a material having low heat resistance is used. Therefore, TF
It is necessary to manufacture T, more specifically, to form a gate insulating film at a low temperature of, for example, 600 ° C. or lower. However, at a process temperature of 600 ° C. or lower, the conventional gate insulating film forming method such as thermal oxidation cannot be used. Therefore, various gate insulating film forming techniques are currently being studied. Among them, as the method for forming the gate insulating film, the substrate temperature in forming the gate insulating film is 600.
A plasma CVD (Chemical Vapor Deposition) method capable of controlling the temperature below ° C has been proposed. The gate insulating film forming method using the plasma CVD method is promising in that it is easy to form a large-area and uniform insulating film.

[0003]

However, according to the previous knowledge, in the formation of the insulating film by the plasma CVD method, there is an advantage that the low temperature film formation can be performed, but the purpose of the invention is to damage the insulating film by the plasma. There is a problem that it is difficult to manufacture a MIS transistor having excellent characteristics. That is, for example, in the n-channel type MIS transistor, the operation is the depletion type. Also,
In the p-channel type MIS transistor, there occurs a phenomenon that the threshold voltage V _th increases, that is, the transistor does not turn on even when a predetermined negative voltage is applied to the gate electrode. As a result, it is difficult to integrate circuits using n-channel and p-channel transistors.

It is considered that such a phenomenon is caused by positive charges due to lattice defects in the gate insulating film generated by plasma irradiation during formation of the gate insulating film. That is, this positive charge is, for example, SiO ₂
It is considered that this is caused by dangling bonds (unbonded hands) of Si in the gate insulating film made of, that is, defects such as oxygen vacancies. If this positive charge exists near the interface between the gate insulating film and the semiconductor (eg, Si), the flat band voltage is shifted (moved) in the negative direction. As a result, it is considered that the above-mentioned depletion mode of the n-channel MIS transistor and increase of the threshold voltage V _th of the p-channel MIS transistor will occur. Further, when intense plasma is irradiated, the phenomenon that impurities are mixed into the gate insulating film may occur simultaneously with the plasma damage to the gate insulating film. This impurity
For example, in the case of a mobile and ionic impurity such as sodium, not only the shift of the flat band voltage is generated, but also the stability of the element characteristics of the MIS transistor is greatly impaired.

The flat band voltage shift is typically a few volts. Therefore, when the operating voltage of the MIS transistor is relatively high (for example, about ± 20V), 4V
Moderate flat band voltage shifts are acceptable. However, when considering low voltage driving, which has become more and more demanded these days, for example, 5V driving of a CMOS circuit,
Such a large flat band voltage shift cannot be tolerated.

Therefore, in order to solve these problems, it is necessary to reduce the occurrence of plasma damage at the insulating film / semiconductor interface as much as possible. Therefore, a plasma CVD apparatus having a structure in which a substrate (semiconductor substrate or the like) on which a gate insulating film is to be formed is not directly exposed to plasma has been actively developed. For example, the parallel plate type remote plasma device proposed by the present applicant is one example (see Japanese Patent Laid-Open No. 5-21393).

However, even when the parallel plate type remote plasma device disclosed in this publication is used,
The shielding of the charged particles in the plasma from the substrate is not perfect. For this reason, the device characteristics of the manufactured MIS transistor are recognized to have characteristic deterioration and characteristic variations. That is, a positive charge is generated in the gate insulating film, which causes a shift in the flat band voltage and impairs the device characteristics of the MIS transistor.

In the process of manufacturing a semiconductor device, various materials are plasma-etched, and plasma ashing (ashing) of the photoresist is performed to remove the photoresist used in the photolithography technique. In these cases as well, plasma damage occurs in the object to be processed or the substrate, resulting in deterioration of the quality or characteristics of the object to be processed or the substrate, or deterioration of the characteristics of the final semiconductor device.

Therefore, it is a first object of the present invention to provide a plasma processing apparatus capable of more efficiently shielding plasma and more effectively suppressing the occurrence of plasma damage. Further, a second object of the present invention is to provide a plasma processing method capable of more efficiently shielding plasma, more effectively suppressing generation of plasma damage to a substrate, and capable of performing high-quality plasma processing. To do. A third object of the present invention is to manufacture a semiconductor device capable of more efficiently shielding plasma, suppressing plasma damage to a substrate more effectively, and manufacturing a semiconductor device having excellent characteristics. To provide a method.

[0010]

A plasma processing apparatus according to a first aspect of the present invention for achieving the above first object is a plasma generating chamber for generating plasma, and an object to be processed by plasma processing. And a plasma processing chamber for arranging the plasma processing chamber, wherein at least one mesh plate for plasma separation is arranged between the plasma generating chamber and the plasma processing chamber, and the mesh plate is A plurality of openings are provided, and the diameter of the openings is less than twice the Debye length of the plasma.

The lower limit of the diameter of the opening depends on the technique for forming the opening in the mesh plate. When the opening is formed by punching, for example, the lower limit of the diameter of the opening is about 0.1 mm. On the other hand, when the opening is formed by etching, for example, the lower limit of the diameter of the opening is 0.01.
It is about mm.

In the plasma processing apparatus according to the first aspect of the present invention, two or more mesh plates for plasma separation are arranged between the plasma generation chamber and the plasma processing chamber, and each mesh plate has a mesh plate. The diameter of the opening provided may include a mode in which the Debye length of the plasma is equal to or less than twice the Debye length of the space in the space closer to the plasma generation chamber of the two spaces partitioned by the mesh plate.

Furthermore, when the electron density in the plasma generating chamber is n _e and the electron temperature is T _e , the diameter of the opening provided in the mesh plate adjacent to the plasma generating chamber is
(KT _e ε ₀ / n _e e ² ) ^1/2 may be twice or less (where k is Boltzmann's constant, ε ₀ is the dielectric constant of vacuum, and e is the electric charge of electron).

A plasma processing apparatus according to a second aspect of the present invention for achieving the above first object is a plasma processing chamber for generating plasma and a plasma processing chamber for arranging an object to be plasma-processed. And a plasma processing chamber, wherein at least one mesh plate for plasma separation is disposed between the generation chamber and the plasma processing chamber, and the mesh plate is provided with a plurality of openings. and, the mesh plate 0 volts <V ₀ ≦ 30 volts, preferably said the 10 volt ≦ V ₀ ≦ 30 volts, and more preferably capable of applying a 10 volt ≦ V ₀ ≦ 20 volts voltage V ₀ which To do. When the voltage V ₀ applied to the mesh plate deviates from the range of ₀ V <V ₀ ≦ 30 V, the charged particles in the plasma are generated by the potential difference between the plasma space potential near the mesh plate and the surface potential of the object to be treated. Between and is struck and hits the work piece. As a result, plasma damage occurs on the object to be processed.

In the plasma processing apparatus according to the second aspect of the present invention, the surface potential of the object to be processed in the plasma processing chamber and the plasma space near the mesh plate adjacent to the object to be processed. A mode in which the voltage V ₀ applied to the mesh plate adjacent to the object to be processed is controlled so that the potential is substantially the same can be included.

Further, two or more mesh plates for plasma separation are arranged between the plasma generation chamber and the plasma processing chamber, and the voltage V ₀ applied to each mesh plate is made substantially the same. Can be included.

The diameter of the opening, which is a feature of the plasma processing apparatus according to the first aspect of the present invention, with respect to the opening provided in the mesh plate in the plasma processing apparatus according to the second aspect of the present invention. The provisions of can also be applied.

Mounting a large number of mesh plates in a plasma processing apparatus tends to increase the effect of plasma shielding. When forming a thin film in a plasma processing device,
The film formation rate basically depends on the rate at which the electrically neutral precursor SiO ^* (reaction precursor) generated in the vapor phase is deposited on the surface of the object to be processed (substrate). Therefore, even if the charged particles are shielded by the mesh plate, the film forming speed does not change much as compared with the case where the mesh plate is not provided. However, if too many mesh plates are mounted, film deposition on the mesh plates becomes noticeable, which causes a decrease in the film formation rate on the surface of the object to be processed (base), so caution is required. In addition, the upper limit of the number of mesh plates may be limited by a decrease in conductance when exhausting the plasma processing apparatus. Therefore, although there is essentially no upper limit, a maximum of 10 sheets is sufficient for practical use.

The plane shape of the opening of the mesh plate is
The shape may be arbitrary, such as a circle, a polygon, or an ellipse. When the plane shape of the opening is circular, the diameter of the opening is the diameter of the circle, and when the plane shape of the opening is polygonal,
The diameter of the opening means the diameter of such a polygonal inscribed circle.
When the planar shape of the opening is elliptical, the diameter of the opening means the length of the major axis of the ellipse. Further, when the planar shape of the opening is an arbitrary shape, the longest distance between the straight line crossing the shape and the two intersections where the shape intersects is the diameter of the opening. The openings can be arranged in any pattern, such as on the vertices of a rectangle, a regular triangle, or a regular hexagon. The number of openings per unit area of mesh plate is
It may be constant over the entire area of the mesh plate, for example, the number may be increased in the central portion of the mesh plate and decreased in the peripheral portion, or in some cases, no opening may be provided in the peripheral portion. . The size of each opening may be constant or different. The cross-sectional shape of the opening in the axial direction can be any shape such as a rectangle or a trapezoid. The mesh plate can be produced, for example, by subjecting a stainless steel plate or the like to punching such as punching or etching, or by working an expanded metal. The planar shape of the entire mesh plate may be appropriately determined depending on the shape of the plasma processing apparatus, but a circular shape is most preferable.

In addition, in the plasma processing apparatus according to the first and second aspects of the present invention, it is preferable that a gas exhaust section is provided in the plasma generation chamber and the plasma processing chamber. In the case where two or more mesh plates for plasma separation are arranged between the plasma generation chamber and the plasma processing chamber, a mode in which a gas exhaust unit is provided between the mesh plates is a plasma processing apparatus. It is more preferable to exhaust in a short time. In the plasma processing apparatus of the present invention, it is preferable that the mesh plate mounting portion of the plasma processing apparatus is made of an electrically insulating material and the mesh plate mounting portion constitutes a part of the outer wall of the plasma processing apparatus.

As the plasma processing apparatus of the present invention, for example, a remote plasma CVD apparatus or a sputtering apparatus for the purpose of forming a film, a radical beam etching apparatus for the purpose of etching, or an ashing for the purpose of ashing a photoresist. A device can be mentioned.

The plasma processing method according to the first aspect of the present invention for achieving the above-mentioned second object uses the above-mentioned plasma processing apparatus of the present invention to deposit on a substrate arranged in a plasma processing chamber. It is characterized by forming a thin film.

Further, in the plasma processing method according to the second aspect of the present invention for achieving the above-mentioned second object, a substrate placed in a plasma processing chamber by using the above-mentioned plasma processing apparatus of the present invention. It is characterized in that the thin film formed above is etched.

Alternatively, the plasma processing method according to the third aspect of the present invention for achieving the above-mentioned second object,
It is characterized in that the above-described plasma processing apparatus of the present invention is used to ash the photoresist formed on the substrate arranged in the plasma processing chamber.

In the method of manufacturing a semiconductor device according to the first aspect of the present invention for achieving the above-mentioned third object, the semiconductor device is an insulated gate field effect transistor, and the plasma processing apparatus of the above-mentioned present invention. Is used to form an insulating film on the substrate arranged in the plasma processing chamber.

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, the insulating film is a SiO ₂ film, a SiN film,
It is preferably composed of a SiON film or a laminated structure of these films. Further, the base is preferably made of a single crystal semiconductor material, an amorphous semiconductor material or a polycrystalline semiconductor material. Alternatively, the substrate can be composed of a polycrystalline silicon layer that has been polycrystallized by heating with a laser.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention to achieve the third object, the semiconductor device is a solar cell, and the plasma processing apparatus of the present invention is used. The invention is characterized in that a protective insulating film is formed on a substrate arranged in the plasma processing chamber.

[0028]

In general, charged particles in plasma are surrounded by charged particles of opposite sign, and the electric field due to the central charge is shielded. This shielding distance is called the Debye length λ _D. When a metal piece, a substrate or the like (hereinafter referred to as a sample) is put in plasma, an ion sheath is generated around the sample. Ions are drawn to the sample side by the voltage applied to the ion sheath. Then, the electric field formed by the charge of the sample in the plasma is shielded, and the plasma maintains a substantially constant potential outside the ion sheath. Such a region is called a space charge region, and the potential of this region is called a plasma space potential.

By the way, the thickness of this sheath is the Debye length λ.
It will be about _D. Here, the Debye length λ _D can be expressed by the following formula, where n _e is the electron density and T _e is the electron temperature. λ _D = (kT _e ε ₀ / n _e e ² ) ^1/2 (1) ≈ 69 (T _e / n _e ) ^1/2 where k is the Boltzmann constant, ε ₀ is the dielectric constant of the vacuum, and e is the electron , And the unit is MKS system.

As is clear from the above equation, the Debye length λ _D
Varies depending on the plasma state. Although it depends on the plasma processing apparatus, in the case of Ar plasma with a relatively short Debye length λ _D due to a normal RF glow discharge, the electron temperature T _e and the electron density n are increased under the condition that the supplied RF power is 10 W.
_e is about 2 eV and 10 ⁹ cm ⁻³ , respectively. Therefore, the Debye length λ _D is about 0.33 mm.

In the plasma processing apparatus according to the first aspect of the present invention, the diameter of the opening provided in the mesh plate is set to not more than twice the Debye length of plasma. For example, under the above conditions, the diameter of the opening is set to 0.66 mm or less.

When the diameter of the opening exceeds twice the Debye length, the center of the opening becomes the space charge region. Then, this region becomes equal to the plasma parameters (electron density n _e and electron temperature T _e ) of the space charge region in the discharge region in the plasma generation chamber, for example. As a result, although the plasma density naturally lowers due to the presence of the mesh plate, the charged particles such as electrons and positive and negative ions leak into the plasma processing chamber where the object to be processed (base) is placed through the opening. The plasma density in the plasma processing chamber becomes high. Then, plasma discharge easily occurs in the plasma processing chamber. That is, the high-density plasma in the plasma generation chamber leaks into the plasma processing chamber through the opening of the mesh plate, which causes plasma damage to the object to be processed (base).

On the other hand, by setting the diameter of the opening provided in the mesh plate to be not more than twice the Debye length of the plasma, the space charge region cannot exist in the center of the opening of the mesh plate. That is, since the entire opening of the mesh plate serves as a sheath region and an electric field is applied to the opening, charged particles in the plasma are trapped by the mesh plate, and the plasma density in the plasma processing chamber is greatly reduced. To do. In other words, the charged particles in the plasma can be effectively shielded by the mesh plate, and the plasma damage to the object to be processed (base) can be greatly reduced.

Generally, the object to be processed is placed on the object placing part provided in the plasma processing chamber. Even if the target object placement part is kept at a certain constant potential, the surface of the target object is not always controlled to this constant potential due to plasma damage during plasma processing. For example, a thin film forming apparatus such as a plasma processing apparatus a plasma CVD apparatus, for example, when a SiO ₂ film, by the generation of plasma damage entails defects such as those having oxygen deficiency in the SiO ₂ film, which is It can generate a positive charge. The positive charge makes the surface potential of the object to be processed positive even if the object mounting portion is grounded.

In the plasma processing apparatus according to the second aspect of the present invention, the voltage V applied to the mesh plate
_{By controlling 0} to 0 <V ₀ ≦ 30 V, the plasma space potential in the vicinity of the mesh plate is brought as close as possible to the surface potential of the object to be processed. As a result, it is possible to effectively prevent charged particles in the plasma from being accelerated between them and colliding with the object to be processed due to the potential difference between the plasma space potential near the mesh plate and the surface potential of the object to be processed. You can Therefore, it is possible to effectively prevent plasma damage from occurring on the object to be processed.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described based on embodiments with reference to the drawings. In the plasma processing apparatus of the embodiment, the inside of the plasma processing apparatus is separated into the plasma generation chamber and the plasma processing chamber by the metal mesh plate. Then, using such a plasma processing apparatus, while suppressing the occurrence of plasma damage, a thin film is formed to form a semiconductor element (for example, a MIS transistor) on a semiconductor substrate that is a base, or a thin film is formed into a plasma. Etching or ashing (ashing) of the photoresist used in the semiconductor element manufacturing process is performed. Note that the semiconductor substrate includes, for example, a single crystal semiconductor layer, a polycrystalline semiconductor layer, and an amorphous semiconductor layer formed on an insulative or semi-insulating substrate, as well as a substrate having a bulk configuration in which the entire semiconductor is formed. A substrate having the above-mentioned configuration is also included.

The first to third embodiments are the first embodiment of the present invention.
Apparatus according to the aspect (specifically, a parallel plate remote plasma CVD apparatus for the purpose of forming a film)
Regarding Example 4, Example 4 and Example 5 relate to a plasma processing apparatus (specifically, a parallel plate remote plasma CVD apparatus for the purpose of film formation) according to the second aspect of the present invention. In addition, Examples 6 to 8 use the plasma processing apparatus according to the first aspect of the present invention, the plasma processing method according to the first aspect of the present invention, or the first and second aspects of the present invention.
Of the present invention relates to a method for manufacturing a semiconductor device. Furthermore,
Example 9 Example 9 relates to the plasma processing method according to the first aspect of the present invention, which uses the plasma processing apparatus according to the second aspect of the present invention.

(Example 1) Example 1 is a plasma processing apparatus according to the first aspect of the present invention. The plasma processing apparatus in Example 1 is a parallel plate type remote plasma CVD apparatus for the purpose of film formation. Its schematic structure is shown in FIG. The plasma processing apparatus of the first embodiment basically includes a plasma generation chamber 10 and a plasma processing chamber 20.

The plasma generating chamber 10 is composed of a disk-shaped metal outer wall member 11 and a cylindrical metal outer wall member 12. That is, the plasma processing apparatus is isolated from the outside air by the metal outer wall members 11, 12, and 21. A gas exhaust unit 17 with a valve 18 is provided in the plasma generation chamber 10, and the gas in the plasma generation chamber 10 is exhausted by an exhaust pump (not shown) to evacuate the inside of the plasma generation chamber 10. The gas for plasma generation is introduced into the plasma generation chamber 10 from the gas introduction part 15 with the valve 16 provided in the outer wall member 11. When forming a film of SiO ₂ , O ₂ gas and He gas are introduced into the plasma generation chamber 10 from the gas introduction unit 15. In order to generate plasma, RF power (13.56 MH) is applied to the upper electrode 14 through the power introduction terminal 13 attached to the outer wall member 11.
z) is supplied.

The plasma processing chamber 20 is composed of a cylindrical metal outer wall member 21. Plasma processing chamber 20
Includes a gas inlet 22 and a gas exhaust 2 with a valve 26.
5, a gas exhaust unit 27 with a valve 28 is provided. The gas introduced from the gas introduction unit 22 is uniformly diffused into the plasma processing chamber 20 through a large number of small holes provided in the ring-shaped gas diffuser 23. Then, the gas is exhausted from the gas exhaust unit 27 provided in the plasma processing chamber 20 by an exhaust pump (not shown). On the other hand, the gas for plasma generation introduced into the plasma generation chamber 10 flows downward in FIG. 1 and is exhausted from the gas exhaust unit 27 of the plasma processing chamber 20. At the bottom of the plasma processing chamber 20, there is provided a workpiece placing portion 24 that is provided with a heater (not shown) for heating and is electrically grounded. This object placement part 2
An object to be plasma-processed (eg, wafer) 5 on 4
Place 0.

Plasma generation chamber 10 and plasma processing chamber 20
And are connected by a cylindrical metal outer wall member 12.
A part of the outer wall member 12 is housed inside the plasma processing chamber 20 via the outer wall member 21 of the plasma processing chamber 20, and the end portion of the outer wall member 12 inside the plasma processing chamber 20 is located above the gas diffuser 23. To position.

A mesh plate 40 is arranged on the outer wall member 12. The mesh plate 40 is attached to the outer wall member 12 by a support member 44 via an insulating material (not shown). The structure and assembly method of the outer wall member 12 and the mesh plate attachment method can be appropriately changed.

The mesh plate 40 spatially separates the plasma generation chamber 10 and the plasma processing chamber 20. The mesh plate 40 is made of a metal plate, and its plane shape is
In the case of the plasma processing apparatus of the first embodiment shown in FIG. 1, it has a disk shape. The circular mesh plate has a plurality of circular openings 43. Plasma is generated in the plasma generation chamber 10 between the upper electrode 14 and the mesh plate 40.

The mesh plate in Example 1 includes
A large number of openings 43 having a diameter of 0.5 mm (planar shape is circular) are arranged on the vertices of an equilateral triangle having a side of 1.0 mm.
The mesh plate 40 is grounded. The Debye length λ _D represented by the equation (1) of the plasma generated in the plasma generation chamber 10 is about 0.33 mm. Therefore, the diameter of the opening 43 is not more than twice the Debye length λ _D of the plasma generated in the plasma generation chamber 10.

In the first embodiment, the gas introduced into the plasma generation chamber 10 passes through the openings 43 provided in the mesh plate 40 and flows into the plasma processing chamber 20. By setting the diameter of the opening 43 to not more than twice the Debye length λ _D , charged particles in the plasma can be effectively shielded, and electrically neutral excitation is performed on the object to be processed 50. Atomic species or molecular species are mainly irradiated. As a result, plasma damage to the object to be processed 50 (base) can be significantly reduced.

As an example, in the remote plasma method using argon gas, the electron density immediately below the mesh plate 40 of the plasma processing apparatus of Example 1 and 13.56 MHz supplied to the upper electrode 14 via the power introduction terminal 13.
FIG. 2 shows the relationship with the RF power (hereinafter referred to as the supplied RFF power). The flow rate of the argon gas was 30 sccm and the pressure was 40 Pa (300 mtorr). Plasma diagnostic methods are described, for example, in Appiled Physics Letters 65 (2), 1994, p.
162 Sano, et al., Based on a method applying the Langmuir probe analysis.

In FIG. 2, a curve (a) shows the electron density when the circular opening having a diameter of 2.0 mm provided in the mesh plate is arranged at the apex of an equilateral triangle having a side of 4.0 mm. . Curve (b) shows the electron density when the circular opening with a diameter of 1.0 mm provided in the mesh plate is arranged at the apex of an equilateral triangle with a side of 2.0 mm. Furthermore, the curve (c) is the case of Example 1, that is, the diameter of the mesh plate provided on the mesh plate is 0.5 m.
The electron density when the circular opening of m is arranged at the apex of an equilateral triangle with a side of 1.0 mm is shown. In addition, in the openings having diameters of 2.0 mm and 1.0 mm, the diameter of the openings exceeds twice the Debye length. The aperture ratio of each mesh plate is equal to 22.7%.

As is apparent from FIG. 2, the electron densities are greatly different even though the mesh plates have the same aperture ratio. Comparing the curves (b) and (c), it can be seen that the electron densities are different by two digits or more. Example 1
As described above, the reason why the electron density of the curve (c) is low is that the diameter of the opening provided in the mesh plate is not more than twice the Debye length, and the charged particles in the plasma are effectively absorbed by the mesh plate. Because it is shielded.

(Embodiment 2) Embodiment 2 is a modification of Embodiment 1. Example 2 is different from Example 1 in the number of mesh plates. In Example 1, one mesh plate was used. On the other hand, in Example 2, three mesh plates were used. An outline of the plasma processing apparatus of the second embodiment is schematically shown in FIG.

In the second embodiment, the outer wall member 12 is provided with the mesh plates 40, 41 and 42. still,
A mesh plate 42 is arranged at the end of the outer wall member 12. Each mesh plate 40, 41, 42 is attached to the outer wall member 12 by a support member 44 via an insulating material (not shown). Each mesh plate 40,
41 and 42 are grounded. The structure and assembly method of the outer wall member 12 and the mesh plate attachment method can be appropriately changed. In this way, the outer wall member 12 and the mesh plates 40 and 41 form the plasma separation chamber 30, and the outer wall member 12 and the mesh plates 41 and 42 form the plasma separation chamber 31. In the second embodiment, the outer wall member 12 and the mesh plates 40, 4
A gap 45 is formed between the first and second parts 42 and 42. That is,
The inner diameter of the outer wall member 12 is the mesh plates 40, 41,
Larger than the outer diameter of 42.

The outer wall member 12 is provided with a gas exhaust portion 34 with a valve 35. That is, the mesh plate 40
A gas exhaust unit 34 is provided in the plasma separation chamber 30 between the mesh plate 41 and the mesh plate 41. A gas exhaust unit may be provided between the mesh plate 41 and the mesh plate 42. Alternatively, a gas exhaust unit may be provided in each plasma separation chamber. The plasma separation chamber is evacuated by an exhaust pump (not shown) and evacuated.

The mesh plates 40, 41 and 42 spatially separate the plasma generation chamber 10 and the plasma processing chamber 20. The mesh plates 40, 41, 42 are, for example, metal plates of the same size, and the planar shape thereof is a disk shape in the case of the plasma processing apparatus of the second embodiment shown in FIG. A plurality of circular openings 43 are formed in the disc-shaped mesh plates 40, 41, 42. In the mesh plates 40, 41, and 42 of the second embodiment, similar to the first embodiment, a large number of openings 43 having a diameter of 0.5 mm (planar shape is circular) are provided on the vertices of an equilateral triangle having a side of 1.0 mm. Has been.

That is, when the electron density in the plasma generating chamber 10 is n _e and the electron temperature is T _e , the plasma generating chamber 1
The diameter r of the opening 43 provided in the mesh plate 40 adjacent to 0 satisfies r ≦ 2 (kT _e ε ₀ / n _e e ² ) ^1/2 .

The diameters of the openings 43 in the mesh plates 40, 41, 42 do not have to be the same. For example, the diameter of the opening 43 provided in the mesh plate 41 may be larger than the diameter of the opening 43 provided in the mesh plate 40. The reason is that, of the two spaces partitioned by the mesh plate, the electron density of plasma in the space far from the plasma generation chamber 10 is higher than the electron density of plasma in the space near the plasma generation chamber 10, for example. This is because the value becomes smaller on the order of 10 ⁻² , and as a result, the value of the Debye length λ _D becomes larger. For the same reason, the diameter of the opening 43 provided in the mesh plate 42 may be made larger than the diameter of the opening 43 provided in the mesh plate 41. However, in at least one mesh plate of the plurality of mesh plates, the size of the diameter of the opening provided in the mesh plate is set to be the plasma generation chamber 10 in the two spaces partitioned by the mesh plate. It is necessary to set the Debye length of the plasma in the space near to 2 times or less.

In the second embodiment, the plasma generation chamber 10
The gas introduced into the mesh plate 40, 41, 4
2 and the narrow gap 45 provided between the outer wall member 12 and each mesh plate 40, 41, 42 to flow into the plasma processing chamber 20.
With such a structure, it is difficult for the gas introduced from the gas diffuser 23 into the plasma processing chamber 20 to reversely diffuse upward in FIG. 3 and reach the plasma generation chamber 10.

(Embodiment 3) Embodiment 3 is also a modification of Embodiment 1. The third embodiment differs from the first embodiment in the number of mesh plates and the structure of the mesh plates. In Example 3, two mesh plates were used. The outline of the plasma processing apparatus of the third embodiment is schematically shown in FIG.

Two mesh plates 40A and 41A are arranged in the plasma processing apparatus of the third embodiment. The mesh plate 40A has the same structure as the mesh plate 40 described in the first embodiment. On the other hand, the mesh plate 41A also has a function as a gas diffuser. That is, the mesh plate 41A has a hollow disc structure, and the upper plate 41B and the lower plate 41C are provided with the openings 43. Further, the gas introduction part 22 is connected to the hollow part 41D of the mesh plate 41A, and the gas introduced into the hollow part 41D of the mesh plate 41A is supplied from the opening 43 provided in the lower plate 41C to the plasma processing chamber 20.
It is evenly dispersed inside. Moreover, the plasma generation chamber 1
The gas introduced to 0 is mesh plates 40A, 41
It passes through the opening 43 provided in A and flows into the plasma processing chamber 20. Mesh plates 40A and 41A
Is grounded. Mesh plate 40A, 41A
Has an opening 43 with a diameter of 0.5 mm (planar shape is circular)
Are provided on the vertices of an equilateral triangle having a side of 1.0 mm. The diameter of the opening 43 is not more than twice the Debye length λ _D of the plasma generated in the plasma generation chamber 10.

Example 4 Example 4 relates to the plasma processing apparatus according to the second aspect of the present invention. The plasma processing apparatus in Example 4 is a parallel plate type plasma CVD apparatus. Its schematic structure is shown in FIG. . The plasma processing apparatus of the fourth embodiment is different from that of the first embodiment in that a variable DC power supply 46 is provided to apply a voltage (V ₀ ) to the mesh plate 40. Other configurations are the same as those of the plasma processing apparatus described in the first embodiment, and detailed description will be omitted. The voltage V ₀ applied to the mesh plate 40 is controlled within the range of 0 volt <V ₀ ≦ 30 volt. The diameter of the opening 43 provided in the mesh plate 40 may exceed twice the Debye length λ _D of the plasma generated in the plasma generation chamber 10, but is preferably twice the Debye length or less.

As an example, in the remote plasma method using argon gas, the plasma space potential (plasma potential) immediately below the mesh plate 40 of the plasma processing apparatus of Example 4 and the voltage (V ₀ ) applied to the mesh plate 40. The relationship is shown in FIG.
RF supplied to the upper electrode 14 via the power introduction terminal 13
Electric power (13.56 MHz) 10 W, argon gas flow rate 30 sccm, argon gas pressure 40 Pa (300
My Little). It can be seen from FIG. 6A that the plasma space potential (plasma potential) changes substantially linearly with respect to the change in the voltage (V ₀ ) applied to the mesh plate. The supplied RF power is 5 W to 20
A similar tendency was observed although the value was changed to W.

FIG. 6B shows the relationship between the electron density immediately below the mesh plate 40 and the RF power (13.56 MHz) supplied to the upper electrode 14 via the power introduction terminal 13.
Shown in The argon gas flow rate was 30 sccm, and the argon gas pressure was 67 Pa (500 mtorr). From FIG. 6B, it can be seen that the electron density increases in proportion to the supplied RF power. Although the voltage applied to the mesh plate was changed from -20 V to +20 V, the same tendency was observed.

(Embodiment 5) Embodiment 5 is a modification of the plasma processing apparatus described in Embodiment 4. Unlike the plasma processing apparatus of the fourth embodiment, the plasma processing apparatus of the fifth embodiment shown in FIG. 7 is provided with two mesh plates 40A and 41A. The structure of the mesh plate 40A is the same as that of the mesh plate 40 described in the fourth embodiment. On the other hand, the mesh plate 41A has the same structure as the mesh plate 41A described in the third embodiment. The mesh plate 40A and 41A has a variable DC power source 4
Direct current is supplied from 6A and 47A.

Example 6 Example 6 relates to a plasma processing method for forming a thin film on a substrate arranged in a plasma processing chamber. In Example 6, the thin film was a gate insulating film made of a SiO ₂ film. The base body is made of a single crystal semiconductor material, specifically, a silicon semiconductor substrate.

In Example 6, the plasma processing apparatus according to the first aspect of the present invention was used. That is, in the sixth embodiment, the parallel plate type plasma C having the structure described in the third embodiment in which the mesh plates 40A and 41A are arranged between the plasma generation chamber 10 and the plasma processing chamber 20.
A plasma processing apparatus consisting of a VD apparatus was used. The diameter of the opening 43 provided in the mesh plates 40A and 41A is not more than twice the Debye length λ _D of the plasma generated in the plasma generation chamber 10. Incidentally, the mesh plate 40A,
41A is grounded.

As a result, it is possible to effectively prevent the charged particles of electrons or positive and negative ions in the plasma generated in the plasma generation chamber 10 from leaking to the plasma processing chamber 20 via the mesh plates 40A and 41A. As a result, the silicon semiconductor substrate, which is the base placed on the object placing portion 24, is mainly irradiated with neutral radicals, that is, electrically neutral excited atomic species or excited molecular species. Therefore, an insulating film (for example, SiO ₂ ) formed on the surface of the base (for example, a silicon semiconductor substrate) or on the surface thereof
It is possible to effectively prevent the gate insulating film made of (3) from being damaged by charged particles. The plasma processing apparatus is not limited to the plasma processing apparatus described in the third embodiment.

As shown in FIGS. 2 and 6B, the electron density in the plasma increases as the supplied RF power increases, so that plasma damage to the substrate made of the silicon semiconductor substrate is prevented. In order to suppress it, it is desirable to make the supplied RF power as low as possible within the range where the discharge can be maintained. The same applies to the following examples.

Using such a plasma processing apparatus, a gate insulating film is formed on a silicon semiconductor substrate which is a base. In Example 6, specifically, a p-type silicon single crystal substrate doped with 10 ¹⁵ atoms / cm ^{3 of} boron B was used as the base. Then, on the one main surface, with the substrate temperature set to 270 ° C., the plasma processing apparatus including the parallel plate type plasma CVD apparatus shown in FIG.
A gate insulating film made of SiO ₂ and having a thickness of 100 nm was formed. Therefore, oxygen O ₂ gas and He gas were supplied to the plasma generation chamber 10 from the gas introduction unit 15, while monosilane SiH ₄ gas and He gas were supplied to the plasma treatment chamber 20 from the gas introduction unit 22.

Next, a gate electrode made of a vapor deposited film of aluminum was formed on the gate insulating film to manufacture a MIS capacitor (MIS diode). And the electric capacity-voltage (CV) characteristic was measured. The measurement result is shown in FIG.

Further, in order to confirm the reduction of plasma damage from the viewpoint of the characteristics of the semiconductor device, as Comparative Example 1, a large number of circular openings having a diameter of 1.0 mm are provided at the vertices of an equilateral triangle having a side of 2.0 mm. Using the arranged mesh plates, a MIS capacitor (MIS diode) was manufactured under the same method and conditions as in Example 6. And the electric capacity-voltage (CV) characteristic was measured. The measurement result of Comparative Example 1 is shown in FIG. The diameter of the opening is 1.0m
In the case of m, the diameter of the opening exceeds twice the Debye length λ _D of the plasma generated in the plasma generation chamber 10.

As is clear from FIG. 8, in the case of Example 6 (the diameter of the opening is 0.5 mm), the flat band voltage is-.
0.89V, Comparative Example 1 (opening diameter 1.0m
In the case of m), the flat band voltage was -2.16V. That is, the flat band voltage shift is smaller in the case of Example 6 than in the case of Comparative Example 1. This means that the positive charge in the gate insulating film generated by plasma damage is smaller in the case of the sixth embodiment. The interface state density in the midgap is
In the case of Example 6 and Comparative Example 1, 2.3 x 10
^{It was 10} cm ⁻² eV ⁻¹ and 7.1 × 10 ¹¹ cm ⁻² eV ⁻¹ . In the case of Example 6, since the interface state density is small,
It can be seen that plasma damage to the gate insulating film is small.

The plasma shielding effect obtained by making the diameter of the opening provided in the mesh plate less than twice the Debye length does not apply only to the above-mentioned MIS capacitor (MIS diode), but also to MI such as TFT.
It goes without saying that this is an effect applied to the fabrication of S-transistors.

(Embodiment 7) Embodiment 7 also relates to a plasma processing method for forming a thin film on a substrate arranged in a plasma processing chamber. Furthermore, Example 7 relates to a method for manufacturing a semiconductor device according to the first aspect of the present invention. That is, Example 7 is
The present invention relates to a method for manufacturing a semiconductor device, in which the semiconductor device is an insulated gate field effect transistor (specifically, TFT), and an insulating film is formed on a substrate arranged in a plasma processing chamber. In Example 7, the insulating film was a gate insulating film made of a SiO ₂ film. Further, the substrate is composed of a polycrystalline silicon layer which is polycrystallized by heating with a laser.

In Example 7 as well, the plasma processing apparatus according to the first aspect of the present invention was used. That is, although the plasma processing apparatus including the parallel plate type plasma CVD apparatus having the structure described in the third embodiment is used, the plasma processing apparatus is not limited to such a plasma processing apparatus. Hereinafter, FIG. 9 and FIG.
A plasma processing method or a semiconductor device manufacturing method according to the seventh embodiment will be described with reference to process charts of No. 0. Example 7
In, no voltage is applied to the mesh plates 40A and 41A. In addition, the mesh plates 40A, 41
A has an opening 43 with a diameter of 0.5 mm (planar shape is circular).
Are provided on the vertices of an equilateral triangle having a side of 1.0 mm.

[Step-700] First, the glass substrate 100.
A first semiconductor layer 101 made of B (boron) -doped hydrogen-containing amorphous silicon (a-Si: H, B) or P (phosphorus) -doped hydrogen-containing amorphous silicon (a-Si: H, P). Was formed by the plasma CVD method. Next, the first semiconductor layer 101 was patterned by the photolithography technique and the etching technique, and the first semiconductor layer 101 was left on the regions where the source / drain regions were to be formed (see FIG. 9A).

[Step-710] Then, for example, non-doped hydrogen-containing amorphous silicon (a-) is formed on the first semiconductor layer 101 and the exposed glass substrate 100.
A second semiconductor layer 102 made of Si: H) is formed by a CVD method (see FIG. 9B).

[Step-720] Then, the second semiconductor layer 102 is polycrystallized by an excimer laser annealing method of irradiating the second semiconductor layer 102 with excimer laser light. At the same time, impurities are thermally diffused from the first semiconductor layer 101 to the second semiconductor layer 102, and the first semiconductor layer 10
A source / drain region 103 is formed by 1 and the second semiconductor layer 102 formed thereon. The second semiconductor layer 102 between the source / drain regions is the channel formation region 1
04 (see (C) of FIG. 9). The second semiconductor layer 102 becomes a polycrystalline silicon layer which is polycrystallized by heating with a laser and corresponds to a base.

[Step-730] Next, the substrate is placed on the object placing portion 24 in the plasma processing chamber 20 shown in FIG. 4 (specifically, the glass substrate 100 is placed), and SiO 2 is deposited. _A gate insulating film 105 composed of _{2 is} formed on the substrate. Gate insulating film 1 made of SiO ₂ on the channel formation region 104
The thickness of No. 05 was 0.2 μm (see FIG. 10A).

[Step-740] After that, an opening is formed in the gate insulating film 105 above the source / drain regions 103 by a photolithography technique and an etching technique, and then the gate insulating film 10 including the inside of the opening is formed.
A metal wiring material made of, for example, an aluminum alloy is formed on the film 5 by, for example, a sputtering method or a vacuum evaporation method, and the metal wiring material is patterned by a photolithography technique and an etching technique. At the same time, the metal wiring material above the channel formation region 104 is patterned.
Thus, the source / drain electrode 106 and the gate electrode 107 can be formed (see FIG. 10B). Thus, the TFT was completed.

[0078] The gate width (W) = 10μm, the p-channel type TFT having a gate length (L) = 10μm, the drain voltage (V _D) = - drain current at 1V (I _D) - the gate voltage (V _G) characteristics evaluated. The result is shown in FIG.

Further, as Comparative Example 2, a mesh plate in which a large number of circular openings having a diameter of 1.0 mm are arranged at the vertices of an equilateral triangle having a side of 2.0 mm is used, and the same procedure as in Example 7 is performed. A p-channel TFT was manufactured according to the method and conditions. Then, the drain current (I _D) - was assessed gate voltage (V _G) characteristics. The measurement results of Comparative Example 2 are shown in FIG.
1 (B). Example 7 (the diameter of the opening is 0.5
mm), the diameter of the opening is 1 mm
It is less than twice the Debye length λ _D of the plasma generated at 0. On the other hand, in Comparative Example 2 (the diameter of the opening is 1.0 mm), the diameter of the opening exceeds twice the Debye length.

As is clear from FIG. 11, in Example 7, the off-voltage, that is, the shift of the flat band voltage in the negative direction was −0.9 V, while Comparative Example 2
In, the negative shift of the flat band voltage was −2.0V. That is, when the diameter of the opening exceeds twice the Debye length, the negative shift of the flat band voltage is larger.

In the case of the seventh embodiment, the subthreshold swing value (subthreshold coefficient) is
While the voltage is 0.125 V / decade, the voltage of Comparative Example 2 is 0.23 V / decade. That is, it is shown that the rising characteristics of the transistor are better when the diameter of the opening is not more than twice the Debye length.

[0082] Further, the on-current is also the case of Example 7, whereas a 19.23μA (V _G = -5V),
In the case of Comparative Example 2, it is 4.76 μA (V _G = −7 V), and the ON current is larger when the diameter of the opening is twice the Debye length or less.

The field effect mobility is shown in Example 7 and Comparative Example 2.
In each of 400 cm ^{2 /} Vs and 88 cm ²
From these results, it can be seen from these results that when the diameter of the opening is twice the Debye length or less, plasma damage is less likely to occur and the gate insulating film / substrate interface characteristics are excellent.

Further, the plasma processing method or semiconductor device manufacturing method of the present invention applied to a TFT is not applied only to the above manufacturing steps or the above element structure.

(Embodiment 8) Embodiment 8 also relates to a plasma processing method for forming a thin film on a substrate arranged in a plasma processing chamber. Furthermore, Example 8 relates to a method for manufacturing a semiconductor device according to the second aspect of the present invention. That is, Example 8 is
The present invention relates to a method for manufacturing a semiconductor device in which the semiconductor device is a solar cell, and a protective insulating film is formed on a substrate arranged in a plasma processing chamber. The base body may be formed of, for example, a single crystal semiconductor material layer, an amorphous semiconductor material layer, or a polycrystalline semiconductor material layer formed on a glass substrate. The protective insulating film can be composed of a SiO ₂ film, a SiN film, a SiON film, or a laminated structure of these films.

Also in Example 8, the plasma processing apparatus according to the first aspect of the present invention was used. That is, although the plasma processing apparatus including the parallel plate type plasma CVD apparatus having the structure described in the third embodiment is used, the plasma processing apparatus is not limited to such a plasma processing apparatus. In the eighth embodiment, no voltage is applied to the mesh plates 40A and 41A. Further, in the mesh plates 40A and 41A, an opening 43 having a diameter of 0.5 mm (planar shape is circular),
Many are provided on the vertices of an equilateral triangle having a side of 1.0 mm.

FIG. 12 shows a schematic partial cross-sectional view of a solar cell which is a semiconductor device of Example 8. In the eighth embodiment, for example, after the lower electrode 201 is formed on the glass substrate 200, the first semiconductor layer 202 made of n-type amorphous silicon and the second semiconductor layer made of non-doped or intrinsic amorphous silicon are formed on the lower electrode 201. 203, a third semiconductor layer 204 made of p-type amorphous silicon,
The films are sequentially formed by, for example, a plasma CVD method based on the plasma processing method according to the first aspect of the present invention. Then, on the third semiconductor layer 203, for example, ITO (In
And a transparent oxide film 205 composed of a composite oxide film of Sn) is deposited. Then, each layer is patterned.

Next, based on the method for manufacturing a semiconductor device according to the second embodiment of the present invention, for example, SiO ₂ , S is formed on the entire surface.
Surface insulating film 20 made of iN or SiON
6 is formed. As described above, by applying the method for manufacturing a semiconductor device according to the second aspect of the present invention, a solar cell with high energy conversion efficiency can be manufactured without damaging the semiconductor layer.

Example 9 Example 9 also relates to a plasma processing method for forming a thin film on a substrate arranged in a plasma processing chamber. In Example 9, the thin film was a gate insulating film made of a SiO ₂ film. The base body is made of a single crystal semiconductor material, specifically, a silicon semiconductor substrate.

The ninth embodiment is different from the sixth embodiment in that the plasma processing apparatus according to the second aspect of the present invention is used. That is, in Example 9,
A plasma processing apparatus including a parallel plate type plasma CVD apparatus having the structure described in Example 5 was used. still,
A variable DC power supply 46 is provided on the mesh plates 40A and 41A.
Direct current is supplied from A and 47A. Mesh plate 4
By applying a voltage to 0A and 41A, the potential difference between the plasma space potential near the mesh plates 40A and 41A and the surface potential of the substrate approaches 0, and the charged particles in the plasma are accelerated between them and the substrate Alternatively, it effectively prevents collision with a thin film or an insulating film that is being formed. Then, the substrate placed on the object placing portion 24 is mainly irradiated with neutral radicals, that is, electrically neutral excited atomic species or excited molecular species. Therefore, it is possible to effectively prevent the surface of the substrate (for example, a silicon semiconductor substrate) or a thin film or an insulating film (for example, a gate insulating film made of SiO ₂ ) formed thereon from being damaged by charged particles. The plasma processing apparatus is not limited to the plasma processing apparatus described in the fifth embodiment.

In Example 9, as in Example 6,
A gate insulating film is formed on a silicon semiconductor substrate which is a base. In Example 9, specifically, as the base,
A p-type silicon single crystal substrate doped with 10 ¹⁵ atoms / cm ^{3 of} boron B was used. Then, on its one major surface, a substrate temperature of 270 ° C, and using the plasma processing apparatus comprising a parallel-plate type plasma CVD apparatus shown in FIG. 7, the gate insulating thickness 0.1μm made of SiO ₂ A film was formed. Then, a gate electrode made of a vapor deposited film of aluminum was formed on the gate insulating film to manufacture a MIS capacitor (MIS diode).

Various MIS capacitors (MIS diodes) were manufactured by changing the voltage (V ₀ ) applied to the mesh plates 40A and 41A. The same voltage (V ₀ ) was applied to the mesh plates 40A and 41A. Then, the interface between the gate insulating film and the gate electrode was evaluated by measuring the capacitance-voltage characteristic (CV characteristic) of the produced MIS capacitor (MIS diode) at a high frequency of 1 MHz.

The measurement results are shown in FIG. FIG. 13 (A)
Is when the voltage (V ₀ ) applied to the mesh plates 40A and 41A is + 15V, and FIG. 13B is when V ₀ is -45V. As is clear from FIG. 13, when V ₀ is +15 V, the flat band voltage is −0.89 V, and when V ₀ is −45 V, the flat band voltage is −4.44 V. That is, the flat band voltage shift is smaller when V ₀ is + 15V. In other words, due to plasma damage,
Generation of positive charges in the gate insulating film is small. The charge density of the gate insulating film is 5 × 10 ⁹ cm ^-2 when V ₀ is + 15V.
And when V ₀ is −45 V, 1.82 × 10 ¹² cm
It was ^-2 .

On the other hand, the interface state density of the midgap is
When V ₀ is -45V, 1.2 × 10 ¹² cm ^-2 eV ^-1 , V
_{When 0} was + 15V, it was 4.3 × 10 ¹⁰ cm ^-2 eV ^-1 . From this, + 15V voltage V on the mesh plate
By applying ₀ , the effect of reducing the interface state density can be obtained. In other words, for example, in a transistor, the subthreshold swing value (subthreshold coefficient) is small and the rising characteristics of the transistor are excellent.

FIG. 14 shows the relationship between the charge density of the gate insulating film and the voltage V ₀ applied to the mesh plate. Here, the voltage V equal to that of the mesh plates 40A and 41A
₀ was applied. As is clear from FIG. 14, V ₀ is +15.
At V, there is a minimum point in the charge density of the gate insulating film. Under this condition, the potential difference between the plasma space potential near the mesh plates 40A and 41A and the surface potential of the substrate is substantially zero.
(That is, substantially the same), and as a result, the occurrence of plasma damage to the gate insulating film is suppressed, and the charge density of the gate insulating film is considered to be suppressed low. As the potential difference between the plasma space potential in the vicinity of the mesh plates 40A and 41A and the surface potential of the substrate deviates from 0, the value of the charge density of the gate insulating film increases and its variation also increases. From FIG. 14, the voltage V applied to the mesh plate
₀ is 0 Volt <V ₀ ≦ 30 Volt, preferably 10 Volt ≦ V ₀ ≦ 30 Volt, more preferably 10 Volt ≦ V ₀
It can be seen that ≤20 volts. In general, if the charge density of the gate insulating film is evaluated, the strength of the electric field formed by the charges from the surface of the substrate toward the outside can be obtained. This makes it possible to determine the potential difference between the mesh plate and the base body according to the distance between them. Therefore, the voltage to be applied to the mesh plate is
The voltage may be set so as to cancel out the potential difference.

Although different voltages may be applied to the mesh plates 40A and 41A, when the difference between the voltages applied to the mesh plates 40A and 41A becomes large, the charged particles are greatly accelerated between the mesh plates 40A and 41A. Therefore, it is preferable that the voltages applied to the mesh plates 40A and 41A be the same as much as possible.

The reduction of the occurrence of plasma damage by controlling the voltage V ₀ applied to the mesh plate does not apply only to the above-mentioned MIS capacitor (MIS diode), and the effect applied to the production of MIS transistors including TFTs. Needless to say. For example,
A TFT can be manufactured in the same process as in Example 7 except that the plasma processing apparatus according to the second aspect of the present invention is used, or a solar cell is manufactured in the same process as in Example 8. be able to.

Although the present invention has been described based on the preferred embodiment, the present invention is not limited to this embodiment. The plasma discharge method may be any of DC, RF, VHF, microwave, ECR (electron cyclotron) plasma, and helicon wave.

In the examples, as a plasma processing apparatus, a remote plasma CVD exclusively for film formation is used.
The apparatus has been described, and as the plasma processing method, the method of forming a thin film on the substrate arranged in the plasma processing chamber by the plasma CVD method has been described. However, the plasma processing method can be a sputtering method using RF or DC plasma, and the plasma processing apparatus includes a bipolar sputtering apparatus, a multipolar sputtering apparatus, a magnetron sputtering apparatus, etc. suitable for the sputtering method. A DC sputtering device or an RF sputtering device can be mentioned.
In this case, by disposing the mesh plate, which is a feature of the present invention, between the target and the substrate,
Generation of plasma damage on the substrate can be suppressed.

Further, in the case where the etchant is a neutral radical in the etching process for manufacturing the semiconductor device, charged particles (ions) can be obtained by using the plasma processing apparatus of the present invention including a radical beam etching apparatus. Alternatively, dry etching can be performed while suppressing the occurrence of damage to the substrate due to (electrons). In this case, S is used as an etching gas (etchant).
Examples thereof include F ₆ , SiCl ₄ , CF ₄ , and NF ₃ .

Furthermore, in the photolithography process in various fields such as the fabrication of semiconductor devices, the plasma treatment apparatus of the present invention can be used to prevent plasma damage to the substrate even when the photoresist is ashed. Ashing (ashing) of the resist can be performed while suppressing the generation. In this case, in general, a silent discharge of oxygen gas is performed to generate ozone O ₃ which is a kind of oxygen radical.
Generate. Furthermore, in order to extend the life of ozone, a method of ashing the resist while irradiating an ultraviolet ray mercury lamp having a wavelength of 254 nm is often adopted.
For example, by disposing an ultraviolet mercury lamp on the side wall of the plasma processing chamber, it is possible to efficiently irradiate the oxygen radicals with ultraviolet rays.

There are no particular restrictions on the type of gas used for plasma discharge. As the source gas of Si, which is the source gas for forming the insulating film made of SiO ₂ described above, disilane Si ₂ H ₆ gas or higher order silane gas can be used in addition to monosilane SiH ₄ gas. In addition to oxygen gas, nitrogen oxide gas such as N ₂ O can be used as the oxidizing gas.

The insulating film or thin film is not limited to SiO ₂ and may be a single layer film of SiN or SiON or a laminated structure of these. When forming a nitride film (SiN) or an oxynitride film (SiON), ammonia gas, for example, is used in addition to the above-mentioned gas.

The plasma processing method or the semiconductor device manufacturing method of the present invention is not limited to the case of manufacturing the semiconductor device having the MIS type structure described in the embodiments, but is applied to the manufacture of other various semiconductor devices. can do. Further, the base body is not limited to silicon,
In the case of having a laminated thin film structure such as Ge, SiGe solid solution, or Si-Ge based superlattice, these single crystal materials, amorphous materials, polycrystalline materials and the like can be further mentioned. In addition to the gate insulating film, the insulating film may be an interlayer insulating film or a flattening insulating film.

For example, as shown in a schematic partial sectional view in FIG. 15, for the TFT shown in FIG. 10B, for example, the plasma processing method or the first method according to the first aspect of the present invention is performed. By applying the method for manufacturing a semiconductor device according to the aspect,
An interlayer insulating film 110 made of iN or SiON is formed on the entire surface. Next, an opening is formed in the interlayer insulating film 110,
After that, a metal wiring material made of, for example, an aluminum alloy is formed on the interlayer insulating film 110 including the inside of the opening by, for example, a sputtering method or a vacuum deposition method, and the metal wiring material is patterned by a photolithography technique and an etching technique. . Thereby, the upper wiring 111 can be formed. Further, for example, by applying the plasma processing method according to the first aspect of the present invention or the method for manufacturing a semiconductor device according to the first aspect, SiO ₂ or Si
An insulating film 112 made of N or SiON for surface protection or planarization is formed. In this way, the occurrence of plasma damage can be reduced, and a semiconductor device having excellent element characteristics can be manufactured.

The plasma processing apparatus of the present invention can also be applied to a plasma doping apparatus for performing various types of doping.

[0107]

In the plasma processing apparatus according to the first aspect of the present invention, or the plasma processing method using the plasma processing apparatus or the method for manufacturing a semiconductor device, an opening having a diameter not more than twice the Debye length is formed. By disposing the mesh plate having, it is possible to effectively shield the plasma, that is, shield charged particles such as electrons or positive and negative ions in the plasma. In the plasma processing apparatus according to the second aspect of the present invention, or the plasma processing method or semiconductor device manufacturing method using the plasma processing apparatus, the surface of the substrate is controlled by appropriately controlling the voltage applied to the mesh plate. Alternatively, it is possible to reduce the kinetic energy of the charged particles in the plasma that enter the thin film or the like during film formation. Due to these effects, it is possible to effectively suppress the generation of defects due to plasma damage, for example, at the insulating film / substrate interface and in the vicinity thereof.

As a result, the device characteristics of the MIS transistor are improved when, for example, a gate insulating film is formed. That is, since the generation of positive charges in the gate insulating film is reduced and the flat band voltage can be brought close to 0 V, n
It is possible to avoid the transition to the depletion type in the channel type MIS transistor and make it an enhancement type, or to avoid the increase of the threshold voltage V _th in the p channel MIS transistor. Therefore, M
Enables reliable operation of the IS transistor, CM of low voltage drive by MIS transistor of both conductivity type channels
An integrated circuit such as an OS can be easily formed.

Further, the plasma processing apparatus according to the first or second aspect of the present invention, or the plasma processing method using these plasma processing apparatuses is applicable to not only thin film formation but also plasma etching and resist ashing. It can also be applied to the same, and like the thin film formation, plasma damage is not given to the element or the substrate in each process. Therefore, for example, the shift of the flat band voltage can be effectively suppressed.

Further, since it is possible to reduce variations in element characteristics on the same base (eg, semiconductor substrate), circuit integration is facilitated. Further, in the MIS transistor, for example, improvement of interface characteristics between the semiconductor and the insulating film,
That is, the sub-threshold swing value can be lowered, the on-current can be increased, the off-voltage can be lowered, and the threshold voltage V _th can be lowered, and high-speed operation of the integrated circuit can be realized.

[Brief description of drawings]

FIG. 1 is a schematic view showing a structure of a plasma processing apparatus of Example 1.

FIG. 2 is a diagram showing the relationship between electron density and RF power in the plasma processing apparatus of Example 1.

FIG. 3 is a schematic diagram showing a structure of a plasma processing apparatus of a second embodiment.

FIG. 4 is a schematic diagram showing a structure of a plasma processing apparatus of a third embodiment.

FIG. 5 is a schematic view showing the structure of a plasma processing apparatus of Example 4.

FIG. 6 is a diagram showing a relationship between a plasma space potential and a voltage applied to a mesh plate and a relationship between an electron density and an RF power in a plasma processing apparatus of Example 4.

FIG. 7 is a schematic view showing the structure of a plasma processing apparatus of Example 5.

FIG. 8 is a diagram showing measurement results of electric capacity-voltage (CV) characteristics in Example 6 and Comparative Example 1.

FIG. 9 is a process diagram for explaining each step of the method for manufacturing the semiconductor device of Example 7;

FIG. 10 is a process diagram for explaining each step of the method for manufacturing the semiconductor device of the seventh embodiment, following FIG. 9;

Drain current (I _D) in FIG. 11 Example 7 and Comparative Example 2 - a diagram showing the gate voltage (V _G) characteristics result.

FIG. 12 is a schematic partial cross-sectional view of a solar cell that is a semiconductor device of Example 8.

FIG. 13 shows the capacitance-voltage (CV) in Example 9.
It is a figure which shows the characteristic measurement result.

FIG. 14 is a diagram showing the relationship between the charge density of the gate insulating film and the voltage V ₀ applied to the mesh plate in Example 9.

FIG. 15 is a diagram showing a method for manufacturing a semiconductor device according to the present invention,
It is a typical partial cross section figure of a MIS transistor which has a multilayer wiring structure.

[Explanation of symbols]

 10 Plasma generation chamber 11, 12, 12A, 21, 32, 33 Outer wall member 13 Power introduction terminal 14 Upper electrode 15, 22 Gas introduction part 17, 25, 27, 34 Gas exhaust part 16, 18, 26, 28, 35 Valve 20 Plasma Processing Chamber 23 Gas Diffuser 24 Treatment Target Placement 30, 31 Plasma Separation Chamber 40, 40A, 41, 41A, 42 Mesh Plate 43 Opening 44 Supporting Member 46 Variable DC Power Supply 50 Treatment Target 100, 200 Glass Substrate 101, 202 First semiconductor layer 102, 203 Second semiconductor layer 103 Source / drain region 104 Channel region 105 Gate insulating film 106 Source / drain electrode 107 Gate electrode 201 Lower electrode 204 Third semiconductor layer 205 Transparent electrode 206 Insulating film for surface protection

Claims (17)

[Claims] 1. A plasma processing apparatus comprising: a plasma generating chamber for generating plasma; and a plasma processing chamber for arranging an object to be plasma-processed, at least between the plasma generating chamber and the plasma processing chamber. One mesh plate for plasma separation is provided, the mesh plate is provided with a plurality of openings, and the diameter of the openings is not more than twice the Debye length of plasma. And a plasma processing apparatus. 2. Two or more mesh plates for plasma separation are arranged between the plasma generation chamber and the plasma processing chamber, and the diameter of the opening provided in each mesh plate is the same as that of the mesh plate. The plasma processing apparatus according to claim 1, wherein the debye length of the plasma in the space near the plasma generation chamber is equal to or less than twice the debye length of the plasma in the two partitioned spaces. 3. The electron density in the plasma generation chamber is n _e ,
When the electron temperature is T _e , the opening provided in the mesh plate adjacent to the plasma generation chamber is 2 (kT _e ε ₀ /
n _e e ² ) ^1/2 or less (where k is Boltzmann's constant,
3. The plasma processing apparatus according to claim 1, wherein ε ₀ is a vacuum permittivity and e is an electron charge. 4. A plasma processing apparatus comprising a plasma generating chamber for generating plasma and a plasma processing chamber for arranging an object to be plasma-processed, wherein at least one is provided between the generating chamber and the plasma processing chamber. A plurality of mesh plates for plasma separation are provided, the mesh plate is provided with a plurality of openings, and a voltage V ₀ of ₀ V <V ₀ ≦ 30 V can be applied to the mesh plate. A plasma processing apparatus characterized by the above. 5. The object to be processed so that the surface potential of the object to be plasma-treated in the plasma processing chamber and the plasma space potential near the mesh plate adjacent to the object to be treated are substantially the same. 5. The voltage V ₀ applied to the mesh plate adjacent to the object is controlled.
The plasma processing apparatus according to. 6. Two or more mesh plates for plasma separation are arranged between the plasma generation chamber and the plasma processing chamber, and the voltage V ₀ applied to each mesh plate is substantially the same. The plasma processing apparatus according to claim 4 or 5. 7. The plasma processing apparatus according to any one of claims 1 to 6, wherein the plasma processing apparatus is a remote plasma CVD apparatus or a sputtering apparatus for the purpose of forming a film. 8. The plasma processing apparatus according to any one of claims 1 to 6, wherein the plasma processing apparatus is a radical beam etching apparatus for the purpose of etching. 9. The plasma processing apparatus according to claim 1, wherein the plasma processing apparatus is an ashing apparatus for ashing a photoresist. 10. A plasma processing method using the plasma processing apparatus according to claim 1 to deposit a thin film on a substrate arranged in a plasma processing chamber. . 11. A plasma, characterized by using the plasma processing apparatus according to claim 1 to etch a thin film formed on a substrate placed in a plasma processing chamber. Processing method. 12. A method of ashing a photoresist formed on a substrate arranged in a plasma processing chamber, using the plasma processing apparatus according to claim 1. Description: Plasma treatment method. 13. The semiconductor device is an insulated gate field effect transistor, and is insulated on a substrate arranged in a plasma processing chamber by using the plasma processing device according to claim 1. Description: A method for manufacturing a semiconductor device, which comprises forming a film. 14. The insulating film is a SiO ₂ film, a SiN film, or a Si film.
14. The method of manufacturing a semiconductor device according to claim 13, comprising an ON film or a laminated structure of these films. 15. The method for manufacturing a semiconductor device according to claim 13, wherein the base is made of a single crystal semiconductor material, an amorphous semiconductor material, or a polycrystalline semiconductor material. 16. The method of manufacturing a semiconductor device according to claim 15, wherein the substrate is made of a polycrystalline silicon layer which is polycrystallized by heating with a laser. 17. The semiconductor device is a solar cell, and
7. A method of manufacturing a semiconductor device, comprising: forming a protective insulating film on a substrate arranged in a plasma processing chamber, using the plasma processing apparatus according to claim 6.