JP2001085701A - Element having multilayer structure, its manufacturing device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture the thin film transistor of a MOS-type structure corresponding to the forming condition of an amorphous semiconductor film by executing a first process, a measuring process and a second process respectively in prescribed cleaning atmosphere. SOLUTION: A valve V for supplying/interrupting gas and a pump P for forced exhaust are connected to a room 7. The valves V and the pumps P are similarly and individually installed in other rooms 1 to 6 except for the room 7. In a carry-in/out room 2, a treated substrate is taken in from outside and the atmosphere is vacuumed from air. In two film-forming rooms 3 and 4, amorphous silicon and the like are formed on the substrate by a plasma CVD method in the raw material gas atmosphere outside the rooms. The heat treatment room 6 heat-treats the respective thin films formed on the surface of the substrate at prescribed temperature and atmosphere. The measurement room 7 measures the prescribed value of physical property such as density and the like in the substrate itself in reduced pressure or in the prescribed atmosphere in accordance with the content.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a device having a multilayer structure, an apparatus for manufacturing the device, and a method for manufacturing the device.

More particularly, the present invention relates to a manufacturing apparatus and a manufacturing method which can be suitably implemented for modifying a thin film transistor using an excimer laser or the like. Also, an active matrix type liquid crystal display device, a sensor array,
The present invention relates to a top-gate thin film transistor applied to a RAM (Static Random Access Memory) and the like, a method of manufacturing the same, a manufacturing apparatus and a manufacturing method which can be suitably applied to a top-gate thin film transistor array.
Further, the present invention relates to a method for easily forming an amorphous silicon film having a low hydrogen concentration in a film at a low temperature by a plasma CVD method.

[0003]

2. Description of the Related Art As an example of an element having a multilayer structure, a thin film transistor (TFT, Thin film Trans) is used.
Sistor) will be described with respect to its background art.

(First Background Art and Problems) A thin film transistor (TFT, Thin) having a MOS type structure
As is particularly the case in filmtransistors, the major factors affecting its performance are (1)
Improvement of crystallinity of semiconductor (material) thin film (recovery of damage),
(2) Reduction of defects at the interface between the semiconductor thin film and the insulating film, and (3) Improvement of cleanliness at the interface between the semiconductor thin film and the insulating film.

LS such as using single crystal silicon for the substrate
In the manufacturing process of I, since a high-temperature process close to 1000 ° C. can be basically used, formation of polycrystalline silicon by an epitaxial growth method, recovery from damage by a high-temperature heat treatment, or formation of an insulating film by a thermal oxidation method,
Techniques for solving the above problems have been established.

On the other hand, in a liquid crystal display device, since a translucent glass is used for a substrate, a manufacturing process at a high temperature of 600 ° C. or more cannot be used for forming a TFT array. Therefore, a method such as a plasma CVD method or a normal pressure CVD method capable of forming a thin film at a low temperature is used for forming a semiconductor thin film or an insulating film.

[0007] With the recent increase in performance of TFTs, TFTs using polycrystalline silicon as a semiconductor thin film instead of conventional amorphous silicon have been developed.

As one method of forming the polycrystalline silicon, for example, an amorphous silicon film or a microcrystalline silicon film formed on a substrate by intense light absorbed by a semiconductor thin film such as excimer laser light. To melt them once and then crystallize them, or form a silicon film (polycrystalline silicon film) consisting of a single or large crystal, and further remove and reform the defects of the formed crystal grains. Technology is being developed.

Conventionally, an LSI for driving a TFT array is formed by using a technology such as TAB (IC is provided on an adhesive tape and the tape is attached to a substrate) or COG (IC is attached to a glass substrate). Although mounted on the periphery of the glass substrate, the LSI is expensive and the yield of the process is not so high. Therefore, instead of this mounting process, a method in which a drive circuit unit such as a pixel unit is directly formed on the glass substrate Have been tried.

Specifically, a semiconductor layer made of silicon is provided, and this semiconductor layer is isolated (so-called patterning) in accordance with the position of the pixel on the substrate and the position of its driving circuit.
Further, in a predetermined region of the isolated semiconductor, for example, at a connection portion with a source electrode, a drain electrode, or a gate electrode or in the vicinity thereof, boron (boron, B) is directly or through an insulating film or the like.
The n-type and p-type semiconductors are formed on the same substrate by injecting a specific impurity such as phosphorus or phosphorus (phosphorus, P) to form a MOS type semiconductor device.

By the way, in order to obtain a high-performance transistor (element) or a semiconductor (material) therefor,
As described above, (1) improving the crystallinity of the semiconductor thin film, (2)
It is important to reduce defects at the interface between the semiconductor thin film and the insulating film, and (3) to improve the cleanliness at the interface between the semiconductor thin film and the insulating film. However, the above-described conventional technology has the following problems.

When a polycrystalline silicon film is formed on a substrate and a large number of thin film transistors are manufactured (formed), an amorphous silicon film is first formed on the substrate by, for example, a plasma CVD method, and then a laser beam is formed. To convert the amorphous silicon film into a polycrystalline silicon film. This crystallization occurs when the energy of the laser light absorbed by the amorphous silicon film is converted into heat, so that the temperature inside the thin film rises, and the amorphous silicon melts once and solidifies again. This is considered to be a process of crystallization.

Therefore, the characteristics (crystallinity, crystal grain size, and field effect mobility, etc.) of the formed polycrystalline silicon film
Is the physical property of the silicon film that absorbs light (the physical property here refers to the property that affects the melting, solidification, and recrystallization by irradiation with laser light; specifically, the film thickness, atomic density, The concentration of impurities such as hydrogen contained therein). Specifically, for example, the film thickness and the atomic density are directly related to the heat required for melting, and if the content of hydrogen is large, scattering of silicon may occur even though it is a part.

Therefore, before irradiating the laser beam, the physical property value of each amorphous silicon film is inspected and measured in advance, and based on the result, the energy density and the like of the irradiating laser beam are optimized. It is necessary to take measures such as.

In many cases, if the film forming conditions are fixed, the atomic density and the impurity concentration do not change so much.
The film thickness directly related to melting varies in the range of a few percent.

In particular, it is necessary to optimize the energy density of the laser light to be applied in accordance with the thickness of the amorphous silicon film. However, the measurement of the thickness requires accuracy on the order of microns or Angstroms. In general, after the film is formed, the film is once taken out of the vacuum to the atmosphere.

However, no matter how much the measuring chamber etc. is cleaned with a high performance (HEPA) filter,
Once the amorphous silicon film is exposed to room air, a natural oxide film is formed on its surface or pollutants in the atmosphere, especially TF
Although a strong acid is absolutely used in the manufacture of the substrate on which T is formed, the glass fiber of the filter is attacked by the strong acid, and the boron contained therein is contaminated. For this reason, the crystallization process by laser irradiation becomes unstable, and boron as an unintended impurity is mixed into the polycrystalline film, thereby deteriorating the performance of the element.

In addition, when a gate insulating film is formed on the surface of a polycrystalline silicon film after the polycrystalline silicon film is formed, the conventional manufacturing apparatus is first exposed to the outside air and then transferred to a plasma CVD apparatus or the like to form an insulating film. Therefore, an unstable natural oxide film is formed on the surface of the polycrystalline silicon film during transfer, or is contaminated by impurities in the atmosphere. For this reason, the characteristics of the interface between the semiconductor and the insulating film are remarkably deteriorated also from this aspect, and this is one of the causes for lowering the performance of the thin film transistor.

On the other hand, as described above, in a liquid crystal display device, a technique has been developed in which n-type and p-type MOS transistors are formed on the same substrate to form a drive circuit and the like on the same substrate as the display portion. I have. This n-type or p-type semiconductor region is formed by injecting a so-called impurity such as phosphorus or boron (an additive for exerting a function of a semiconductor) into a predetermined semiconductor region. The characteristics of the n-type or p-type semiconductor region strongly depend on the concentration of these implanted impurities and the profile in the film thickness direction.

Conventionally, the impurity has been implanted through a gate insulating film of silicon as a semiconductor. However, as described above, the insulating film formed by the plasma CVD method or the like has a thickness variation in the range of several percent between the substrates. As a result, variations occur in the characteristics of the n-type or p-type semiconductor regions, causing variations in the characteristics of the transistors.

With the recent increase in the size of liquid crystal display panels and the increase in pixel density, thin-film transistors formed on glass substrates have become smaller and more precise, and the polycrystalline silicon film has been thinned to several hundred angstroms. It is becoming. Therefore, from this aspect, the adverse effects of surface contamination and deterioration are further increased.

For the reasons described above, the factors that degrade the performance of such a transistor become more serious as the characteristics of the TFT become higher such that the field-effect mobility exceeds 200 cm ² / V · sec. It has become.

Therefore, M produced by laser annealing
This is especially true for thin film transistors having an OS type structure. At the time of processing at each stage of manufacturing, there is no attachment of impurities to the thin film formed on the substrate, and as a result, the crystallinity is good, and defects at the interface are reduced. It has been desired to develop an apparatus and a method for manufacturing a device having a small amount and a small variation in characteristics.

(Second Background Art and Issues) To improve the characteristics of a MOS thin film transistor (TFT) formed on a glass substrate, it is essential to improve the interface characteristics between the semiconductor thin film and the gate insulating film.

By the way, the structure of the TFT is such that a gate electrode is formed first in accordance with the order of lamination of the electrodes and the semiconductor layers, and then the polycrystalline silicon (Polycrystalline silicon) is interposed via a gate insulating film.
silicon) a bottom gate type with a film formed on its top surface,
Conversely, it is classified as a top gate type in which a polycrystalline silicon film is formed first, and a gate electrode is formed on the upper surface via a gate insulating film. When both are compared, miniaturization and reduction of parasitic capacitance by a self-aligned structure can be easily achieved from the viewpoint of a device, and a top-gate type having less restrictions on a manufacturing process is advantageous. When considering a top gate type configuration that is advantageous from the viewpoint of such a device, after forming the semiconductor thin film, without exposing the surface to the air, holding in a high vacuum or a high-purity gas atmosphere,
It is desirable to form a gate insulating film continuously.

However, the conventional manufacturing process has a problem that the interface between the semiconductor thin film and the gate insulating film cannot be kept clean.

The details will be described below. A manufacturing process of a typical top gate type thin film transistor (referred to as a first conventional example) is shown in FIGS. FIG.
30, reference numeral 500 denotes an insulating substrate, 501 denotes a semiconductor thin film, 502 denotes a gate oxide film, 503 denotes a gate electrode, 504 denotes a source region, 505 denotes a drain region, and 50 denotes a drain region.
6 is a channel region, 507 is an interlayer insulating film, 508 is a source electrode, and 509 is a drain electrode. In this first conventional example, a state in which a gate insulating film 502 and a gate electrode 503 are formed on a semiconductor thin film 501 from the state shown in FIG. 29A in which a semiconductor thin film 501 is formed on an insulating substrate 500 is shown in FIG. In the state shown in FIG.
Is processed into an island shape by photolithography and etching. As described above, when the photolithography process is performed between the semiconductor thin film forming process and the gate insulating film process, the semiconductor thin film 501 and the gate insulating film 50 are formed.
Since the interface of No. 2 is exposed to the atmosphere, the cleanliness of the interface between the semiconductor thin film and the gate insulating film cannot be maintained.

In order to solve such a problem, FIG.
2 has been proposed. In the second conventional example, a semiconductor thin film 501 and a gate insulating film 502 are continuously formed (FIG. 31A), then both are processed into an island shape, and after the processing, a gate electrode 503 is formed. (FIG. 31
(B)).

As a result, the interface between the semiconductor thin film 501 and the gate insulating film 502 is not exposed to the atmosphere, and the cleanliness of the interface between the semiconductor thin film and the gate insulating film can be maintained. However, in the second conventional example, FIG.
As shown in FIG. 7, since the sloped surface 101a of the semiconductor thin film 501 that has been processed into an island shape is exposed, desired transistor characteristics can be obtained by electrical contact between the semiconductor thin film 501 and the gate electrode 503 on the sloped surface 101a. A new problem has arisen. FIG. 31 is a cross section perpendicular to the cross section including the source region, the channel region, and the drain region and including the channel region (for example, in FIG. (Corresponding to a cross section perpendicular to the paper surface).

Therefore, there has been a demand for a top-gate thin film transistor in which the interface between the semiconductor thin film and the gate insulating film is clean and which does not cause a problem of contact between the semiconductor thin film and the gate electrode.

(Third Background Art and Problems Thereof) A polysilicon film used for a thin film transistor (hereinafter referred to as “TFT”) intended for application to a car navigation or a monitor of a mobile tool is an amorphous silicon film. Is formed by irradiating the surface of the amorphous silicon film with a laser by a laser annealing method to melt-crystallize the film.

Here, it is desired that the amorphous silicon film irradiated with the laser has a hydrogen concentration in the film of 3 at% or less. The reason is that when laser annealing an amorphous silicon film containing a large amount of hydrogen in the film, the temperature of the amorphous silicon film rises rapidly due to laser irradiation, hydrogen in the film bumps, and the film surface becomes rough. This is because the film becomes inappropriate as a TFT.

The method of forming the amorphous silicon film includes:
There are a normal pressure CVD method, a low pressure CVD method, a plasma CVD method, and the like. Among them, the plasma CVD method is suitable in any point where a process at a low temperature of 400 ° C. or less can be performed. However, an amorphous silicon film formed at a substrate temperature of about 250 ° C. by the plasma CVD method has a thickness of 10 to 20 μm.
Therefore, a step of desorbing hydrogen from the amorphous silicon film is required before irradiating the amorphous silicon film with a laser by a laser annealing method to perform crystallization. I have.

Therefore, without performing the step of desorbing hydrogen in the amorphous silicon film, the plasma CV
A method of reducing the hydrogen content in the film by the method D is disclosed in Japanese Patent Application Laid-Open No. 9-134882. In this technique, the substrate is heated to 400 ° C., and hydrogen in the film is desorbed by thermal energy.

In general, the formation of an amorphous silicon film by the plasma CVD method is performed under conditions of a reaction law by sufficiently flowing SiH ₄ gas and keeping the high-frequency power at 13.56 MHz. This is because an amorphous silicon film with few dangling bonds is formed by selectively generating SiH ₃ radicals while suppressing powder generation due to a gas phase reaction.

In this case, since the dangling bond is terminated by hydrogen, a large amount of hydrogen is naturally contained in the film. Also, the outermost surface of the amorphous silicon film being formed is covered with hydrogen, but when the substrate temperature exceeds 300 ° C., hydrogen on the outermost surface is desorbed by thermal energy,
As a result, it is also known that dangling bonds increase.

When an amorphous silicon film is formed by a conventional plasma CVD method, if the substrate temperature is 300 ° C. or less, which is a general condition, 10 to 20 at% of hydrogen is contained in the amorphous silicon film. A step of desorbing hydrogen therein is required.

Further, when the substrate temperature is heated to about 400 ° C. and the source gas is highly diluted as in the technique disclosed in Japanese Patent Application Laid-Open No. 9-134882, an amorphous silicon film having a small hydrogen content is formed. Although the step of desorbing hydrogen from the obtained film becomes unnecessary, there is a problem that the amorphous silicon film is microcrystallized and the throughput is reduced. When the amorphous silicon film is microcrystallized, the microcrystallized film must be re-melted by laser annealing, and therefore requires higher energy than in the case of laser annealing of the amorphous film, resulting in lower production efficiency. You do it.

[0039]

SUMMARY OF THE INVENTION It is an object of the first invention to make it possible to manufacture a thin film transistor having a MOS structure in a clean atmosphere in accordance with the conditions for forming an amorphous semiconductor film. Things.

An object of the second invention group is to overcome the above-mentioned problems of the prior art, to have a clean interface between the semiconductor thin film and the gate insulating film and not to cause a problem of contact between the semiconductor thin film and the gate electrode. An object of the present invention is to provide a top gate type thin film transistor and a method for manufacturing the same.

Another object of the second invention is to provide a thin film transistor array which can reduce the resistance of wiring (particularly, signal lines) and can be suitably applied to a large liquid crystal panel or the like.

An object of the third invention group is to make it possible to reduce the hydrogen content in the amorphous silicon film even when the substrate temperature is low by utilizing the efficiently generated high energy particles. An object of the present invention is to provide a method for forming an amorphous silicon film.

[0043]

According to a first aspect of the present invention, there is provided a method for manufacturing an element having a multilayer structure by a plurality of film forming steps. A first film forming step of forming at least one film;
A measuring step of measuring a predetermined physical property value of the film obtained in the first film forming step; and a second step of processing the film according to measurement conditions determined based on a measurement result in the measuring step, The first step, the measurement step, and the second step are each performed in a predetermined clean atmosphere.

With the above configuration, even if there is a variation in the film thickness or the like in the first film forming step, the processing in the second step is performed in consideration of the variation. Therefore, the second process is performed under optimal conditions, and in addition, the first step, the measurement step, and the second step are performed in a clean atmosphere, so that the quality is improved. An element having a multilayer structure can be manufactured.

Examples of the device having a multilayer structure include a semiconductor device such as a TFT, a semiconductor device having an LDD (Lightly Doped Drain) structure, and a device having an optical multilayer film. For example, in the case of a TFT semiconductor element, the first step corresponds to a process of forming an amorphous silicon film, and the second step corresponds to a process of modifying a polysilicon film. LD
In the case of a semiconductor device having a D structure, the first step is L
A first ion implantation process for manufacturing a DD structure, and the second process corresponds to a second ion implantation process for manufacturing an LDD structure. In the case of an element having an optical multilayer film, the first step corresponds to a first film formation processing, and the second step corresponds to a second film formation processing.

According to a second aspect of the present invention, in the method of manufacturing an element having a multilayer structure according to the first aspect, the process in the second step is a film forming process.

According to a third aspect of the present invention, in the method for manufacturing an element having a multilayer structure according to the first aspect, the treatment in the second step is a film modification treatment.

According to a fourth aspect of the present invention, there is provided an apparatus for manufacturing an element having a multilayer structure, wherein a film forming means for forming at least one of a plurality of films, and the film forming means. Means for measuring a predetermined physical property value of the film, processing means for processing the film in accordance with measurement conditions determined based on the measurement results in the measurement means, and the film forming means, the measuring means, and the processing means And a transport unit for transporting between the respective units, wherein the film forming unit, the measuring unit, the processing unit, and the transport unit perform their respective processes under a predetermined clean atmosphere.

As described above, since the processing of the processing means is performed based on the measurement result of the measuring means, the processing can be performed with high accuracy. Further, since the treatment by each means is performed in a clean atmosphere, a high-quality device can be obtained.

According to a fifth aspect of the present invention, in the device for manufacturing an element having a multilayer structure according to the fourth aspect, the processing in the processing means is a film forming process.

According to a sixth aspect of the present invention, in the device for manufacturing an element having a multilayer structure according to the fourth aspect, the processing in the processing means is a film reforming processing.

According to a seventh or eighth aspect of the present invention, a substrate is placed in a predetermined clean atmosphere determined by the formation of a thin film, for example, at room temperature or under reduced pressure of hydrogen. A thin film forming means for forming an amorphous semiconductor thin film on a substrate using a semiconductor (more precisely, a raw material gas) supplied from a semiconductor supply means provided in an atmosphere place; Physical properties related to the modification (melting, crystallization, etc.) of the amorphous semiconductor thin film by irradiation with energy rays, for example, the film thickness, are represented by light (including ultraviolet light,
In a state where the substrate is installed under a predetermined clean atmosphere determined by a physical property value measuring method using infrared rays, for example, at room temperature and under reduced pressure, a predetermined light source (including laser light ( Source)) and a physical property value measuring means for measuring using a photodetector, and an energy beam for reforming having properties determined from the measured physical property values, for example, an excimer laser having an energy density of 300 mJ / cm ^{2 and} an energy density of 300 Hz, Energy beam irradiating means for irradiating the semiconductor for its modification, and receiving the substrate from outside to form an amorphous semiconductor layer on its surface, and thereafter performing thin film formation, physical property value measurement, energy beam irradiation The substrate is properly installed in the thin film forming means, the physical property value measuring means, and the energy ray irradiating means in this order without exposing the substrate to the external atmosphere, and a clean atmosphere is maintained to be removed after the processing. It is characterized in that it has a conveying means.

With the above configuration, the following operation is performed.

The thin-film forming means is provided in a state where the substrate is horizontally placed under a predetermined clean atmosphere determined by the thin-film formation, and in principle, the cleaning is performed only on a predetermined position on the entire surface of the substrate using a mask. An amorphous semiconductor thin film is formed by sputtering or the like using a semiconductor supplied from a semiconductor supply means provided in a room or an outside of the apparatus maintained in an atmosphere.

The physical property value measuring means measures the physical property values such as density and film thickness of the amorphous semiconductor thin film formed on the substrate, which are related to the modification by irradiation with energy rays, and measures the physical property values using laser light. The measurement is performed using a laser source, an L / E converter, or the like installed outside the measurement atmosphere, with the substrate placed horizontally in a predetermined clean atmosphere determined, for example, in a room temperature and vacuum.

The energy beam irradiating means is an energy beam having a property determined from the measured physical property values, for example, 300 mJ /
An excimer laser beam of cm ² is formed into a beam using, for example, an optical system, and this beam is applied to an amorphous semiconductor patterned as necessary on a substrate held in a predetermined state in a predetermined atmosphere. Irradiation is performed while sequentially scanning the substrate.

The transfer means having a clean atmosphere holding type having a so-called robot arm, an extruder, a motor, etc. receives a substrate directly from the outside or indirectly through an intermediary means to form a thin-film polycrystalline semiconductor layer on the surface thereof. Thereafter thin film formation, physical property value measurement, without exposing the substrate to at least a dirty external atmosphere during each treatment of energy ray irradiation, preferably while sequentially maintaining the appropriate atmosphere, the thin film forming means, physical property value, measuring means, energy Installed for each treatment with line irradiation means and removed after treatment. (Of course, after the end of the previous process, it may be installed in a device for the next process.) Therefore, if necessary, the transfer to the work room for the process and the unloading after the process are also performed.

Each of the above-mentioned means performs necessary exhaust or decompression of a room or space in which a substrate is installed, filling of an inert gas, hydrogen gas, or the like.

Further, the thin film transistor manufacturing apparatus also has means for patterning a silicon thin film, if necessary.

According to the ninth aspect of the present invention, good functions as a transistor element such as displacement of hydrogen from an amorphous semiconductor formed on a substrate and bonding of hydrogen to dangling bonds of a polycrystalline semiconductor are also exhibited. At a predetermined atmosphere determined by heat treatment for, for example, 500 ° C. in nitrogen gas at 1 atm for the former, and 350 ° C. in H _{2 for} the latter, for each substrate (including a plurality of substrates simultaneously). It has a heat treatment means for holding the thin film for a certain period of time and performing a heat treatment, and the clean atmosphere holding type transport means is not exposed to the external atmosphere at least after the processing such as the formation of the previous amorphous semiconductor thin film,
Further, the present invention is characterized in that it has a small heat treatment transport means capable of installing (including, for example, loading into a dedicated chamber for that purpose) the substrate in the heat treatment means and removing (unloading) after the heat treatment.

With the above configuration, the following operation is performed.

The heat treatment means has a heater, a predetermined atmosphere gas filling and exhausting means, etc., thereby driving out hydrogen from the amorphous semiconductor formed on the substrate and also to the dangling bond of the polycrystalline semiconductor. The semiconductor thin film for each substrate is heat-treated for a predetermined time in a predetermined atmosphere determined by a heat treatment for exhibiting a good function as a transistor element such as hydrogen bonding.

The heat treatment transfer means of the clean atmosphere holding type transfer means is not exposed to the external atmosphere at least, and is further provided with at least one (including, if necessary, a plurality) of heat treatment means.
It enables the installation of substrates and removal after heat treatment.

According to a tenth aspect of the present invention, there is provided an apparatus for forming a thin film transistor on a given substrate,
For example, it has a loading / unloading means for receiving a substrate as a target of processing to form a semiconductor thin film from a substrate cleaning apparatus or a manufacturing apparatus and transferring the processed substrate to the outside, and a clean atmosphere holding type transport means is provided. A centrally arranged type clean atmosphere holding type transport means having a structure having at least a thin film forming means, a physical property value measuring means, an energy ray irradiating means, a carry-in / out means or a heat treatment means in addition to these on the outer peripheral portion thereof; In order to smoothly perform installation and removal of the substrate to and from the respective units arranged on the outer peripheral portion, the device has rotatable small-sized conveyance means capable of holding and rotating the substrate, and the physical property value measuring means includes a physical property value of the substrate. It is a horizontal holding type physical property measuring means for accurately holding the substrate horizontally at the time of measurement.

With the above configuration, the following operation is performed.

The carrying-in / out means having a gate valve and, if necessary, a vacuum pump and the like are used to receive a substrate for forming a semiconductor thin film on the surface from the outside of the apparatus, to form the semiconductor thin film, and to carry out the processing associated therewith. Alternatively, the substrate after forming the transistor as an element is transferred to the outside.

The clean atmosphere holding type transport means is a centrally arranged type clean atmosphere holding type transport means. Therefore, a thin film forming means, a physical property value measuring means, an energy ray It has an irradiation unit, a carrying-in / out unit, or a heat treatment unit in addition thereto (or a room for installing a substrate as a part of the unit for that purpose).

Also, because of this arrangement, it is easy to attach a window for viewing, a window through which light for processing passes, and other valves to the side wall surface not facing the transfer chamber of each room.

Further, heat insulation between the chambers is facilitated by the presence of air therebetween.

Next, the rotatable transfer sub-means includes an arm, an extruder, a pull-out mechanism, and the like for installing or removing a substrate in each means for each processing or a chamber for the processing. The magic hand rotates while holding the substrate. Thus, unlike the linear arrangement type, convergence during processing by a plurality of means and devices on a plurality of substrates is reduced.

Further, since the physical property value measuring means is a mechanism for accurately holding the substrate horizontally when measuring the physical property value of the substrate, mounting of the apparatus itself, mounting of the substrate, and further, measurement itself are facilitated.

In the eleventh aspect of the present invention, the thin film forming means, the physical property measuring means, the energy ray irradiating means or the heat treatment means in addition to these are each formed as a semiconductor (in principle, formed on a non-alkali glass substrate). Silicon-based thin film forming means, silicon-based physical property value measuring means, silicon-based energy ray irradiating means for at least one of amorphous and ultrafine crystalline silicon, silicon-germanium, silicon-germanium-carbon layers It is characterized by a melting and recrystallization means or a heat treatment means for a silicon system in addition to these.

With the above configuration, the following operations are performed.

The thin film forming means, the physical property measuring means, the energy ray irradiating means or the heat treatment means in addition to these may be a silicon based thin film forming means, a silicon based physical property value measuring means, a silicon based energy ray irradiating means or in addition to these. Heat treatment means for a silicon system, and exhibits a function of forming at least one of silicon, silicon-germanium, and silicon-germanium-carbon as a semiconductor on a substrate.

According to the twelfth to sixteenth aspects of the invention, the same operations as those of the seventh to eleventh aspects are performed, and the effects are obtained.

According to a seventeenth aspect of the present invention, there is provided a semiconductor device comprising: a source region; a drain region; and a channel region interposed between the source region and the drain region. A semiconductor thin film, a gate electrode disposed immediately above the channel region, a gate insulating film interposed between the channel region and the gate electrode, a source electrode electrically connected to the source region, and an electrical connection to the drain region. And a drain electrode connected to the gate electrode, wherein the gate electrode is made of a refractory metal formed on the gate insulating film.
It is characterized by comprising a sub-gate electrode and a second sub-gate electrode made of a low-resistance metal formed on the first sub-gate electrode.

As described above, by forming the gate electrode in the two-layer structure of the first sub-gate electrode and the second sub-gate electrode, it becomes possible to form a semiconductor thin film and a gate insulating film continuously, and to obtain high performance and high reliability. Having a top gate type thin film transistor.

Further, since the first sub-gate electrode is made of a metal having a high melting point and the second sub-gate electrode is made of a low-resistance metal, melting of the gate electrode due to heat treatment for activation or the like is prevented. The reliability of the type thin film transistor is improved.

The invention according to claim 18 is the top gate thin film transistor according to claim 17, wherein the high melting point metal is molybdenum or an alloy containing molybdenum.

By using molybdenum or an alloy containing molybdenum as the high melting point metal, good transistor performance can be obtained.

According to a nineteenth aspect of the present invention, in the top gate thin film transistor according to the seventeenth aspect, the high melting point metal is tungsten or an alloy containing tungsten.

By using tungsten or an alloy containing tungsten as the high melting point metal, good transistor performance can be obtained.

According to a twentieth aspect of the present invention, in the top gate type thin film transistor according to the seventeenth aspect, polycrystalline silicon having a high impurity concentration is used in place of the refractory metal.

According to a twenty-first aspect of the present invention, in the top gate thin film transistor according to any one of the seventeenth to twentieth aspects, the low-resistance metal is aluminum or an alloy containing aluminum.

By using aluminum or an alloy containing aluminum as the low resistance metal, good transistor performance can be obtained.

The invention according to claim 22 is a method for manufacturing a top gate thin film transistor, comprising: a first step of forming a semiconductor thin film on an insulating substrate; and forming a gate insulating film on the semiconductor thin film; A second step of forming a first sub-gate electrode on the gate insulating film, and forming the first sub-gate electrode, the gate insulating film and the semiconductor thin film in a first island shape by a first patterning process by photolithography and etching. A fourth step of processing the first sub-gate electrode and the gate insulating film into a second island shape by a second patterning process using photography and etching; and As a mask, a source region and a drain are formed in the semiconductor thin film by implanting impurities into the semiconductor thin film. A fifth step of forming a region and a channel region, forming a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region, and electrically connecting the first sub-gate electrode A sixth step of forming a connected second sub-gate electrode.

According to the above manufacturing method, the interface between the semiconductor thin film and the gate insulating film is continuously formed. In addition, the island-shaped processed surface of the semiconductor thin film and the second gate electrode are insulated by the interlayer insulating film, and thus do not come into contact with each other. Therefore,
A top-gate thin film transistor with improved transistor characteristics can be manufactured.

According to a twenty-third aspect of the present invention, in the method of manufacturing a top-gate thin film transistor according to the twenty-second aspect, in place of the fourth step, only the first sub-gate electrode is subjected to the second step by photolithography and etching. It is characterized by being processed into an island shape.

According to the above-described manufacturing method, the ion implantation is performed through the gate insulating film, so that the island-shaped processed slope of the semiconductor thin film is less likely to be contaminated with impurities during the ion implantation, which is preferable.

According to a twenty-fourth aspect of the present invention, in the method for manufacturing a top gate type thin film transistor according to the twenty-second or twenty-third aspect, the first step comprises forming an amorphous silicon thin film on an insulating substrate, The method is characterized in that a crystalline silicon thin film is crystallized to form a crystalline silicon thin film as a semiconductor layer on an insulating substrate.

As described above, when a crystalline silicon thin film is used as a semiconductor layer, a TFT having good mobility and other characteristics can be obtained.
Can be produced.

According to a twenty-fifth aspect of the present invention, in the method of manufacturing a top-gate thin film transistor according to any one of the twenty-second to twenty-fourth aspects, the first sub-gate electrode is made of a high melting point metal, and The source electrode and the drain electrode are both made of a low-resistance metal.

According to the above manufacturing method, the first sub-gate electrode functions as a metal mask at the time of ion implantation for impurity implantation. In addition, since the first sub-gate electrode is made of a high melting point metal, partial melting of the first sub-gate electrode due to heat or the like generated at the time of ion implantation is prevented, and impurity contamination to the channel region does not occur. Further, the temperature of the activation treatment after the implantation can be set high within the range of the heat-resistant temperature of the glass substrate, which is preferable.

According to a twenty-sixth aspect of the present invention, in the method of manufacturing a top gate thin film transistor according to any one of the twenty-second to twenty-fifth aspects, the refractory metal is molybdenum or an alloy containing molybdenum. .

According to a twenty-seventh aspect, in the method of manufacturing a top gate thin film transistor according to any one of the twenty-second to twenty-fifth aspects, the refractory metal is tungsten or an alloy containing tungsten. .

According to a twenty-eighth aspect of the present invention, in the method of manufacturing a top gate thin film transistor according to any one of the twenty-second to twenty-fifth aspects, polycrystalline silicon having a high impurity concentration is used in place of the refractory metal. It is characterized by.

As described above, when the impurity concentration is high, the resistance becomes low, so that a thin film transistor having good characteristics can be manufactured. In addition, in the case of this configuration, when impurities are implanted into the source / drain regions, impurities may be implanted into polycrystalline silicon as a gate electrode at the same time, which facilitates manufacturing.

According to a twenty-ninth aspect of the present invention, in the method of manufacturing a top gate thin film transistor according to any one of the twenty-second to twenty-eighth aspects, the low-resistance metal is aluminum or an alloy containing aluminum. .

According to a thirtieth aspect of the present invention, a plurality of signal lines and a plurality of control lines intersecting the signal lines are wired, and each of the signal lines and the control lines is provided near each intersection. A gate type thin film transistor is arranged, each signal line is connected to a source electrode of the corresponding thin film transistor, each control line is connected to a gate electrode of the corresponding thin film transistor, and the control line and the signal line are formed on the same insulating substrate together with the thin film transistor. A top gate type thin film transistor array having a structure formed at least at the intersection of the control line and the signal line, wherein the control line is a four-layer stack of a semiconductor layer, an insulating layer, a refractory metal layer, and an interlayer insulating layer The signal line is made of a low-resistance metal layer.

With the above structure, all signal lines requiring a lower resistance are substantially wired with a low-resistance metal without losing continuity between the semiconductor layer and the gate insulating layer in the TFT portion. Also, since the wiring is made of a low-resistance metal except at the intersection with the signal line, it is preferable as a large and high-definition TFT array. Even if the low-resistance metal is a material having a low melting point, it may be formed after activation of the impurity ions after ion implantation, and thus has an optimal configuration for relaxing the upper limit of the heating temperature during activation.

The invention according to claim 31 is the top gate type thin film transistor array according to claim 30,
The refractory metal is molybdenum or an alloy containing molybdenum.

According to a thirty-second aspect of the present invention, in the top-gate thin film transistor array according to the thirty-third aspect, the high melting point metal is tungsten or an alloy containing tungsten.

According to a thirty-third aspect of the present invention, in the top-gate thin film transistor array according to the thirty-third aspect,
Polycrystalline silicon having a high impurity concentration is used in place of the high melting point metal.

According to a thirty-fourth aspect of the present invention, in the top gate thin film transistor array according to any one of the thirty to thirty-third aspects, the low-resistance metal is aluminum or an alloy containing aluminum.

The third invention group has been completed based on the following detailed studies by the present inventors. That is,
It has been newly found that hydrogen on the outermost surface of the amorphous silicon film can be desorbed by physicochemical energy from high-energy particles in plasma, in addition to thermal energy from the substrate. As means for efficiently generating high-energy particles in plasma,
There are methods of increasing the frequency of the high-frequency power supply to a frequency higher than the normal 13.56 MHz (for example, 27.12 MHz) or using low-pressure and high-density plasma (for example, inductively coupled plasma or electron cyclotron resonance plasma). Therefore, it is possible to reduce the hydrogen content in the amorphous silicon film even when the substrate temperature is low by using the efficiently generated high energy particles. Based on the above idea, a third invention group was made.
The specific configuration is as follows.

The invention according to claim 35 is a plasma CVD method.
In a method of introducing a film-forming gas containing at least a Si element into a vacuum vessel of an apparatus and reacting the film-forming gas by a plasma CVD method to form an amorphous silicon film on a substrate, It is characterized in that the reaction is carried out under supply rule conditions.

According to the above method, by setting the supply law condition (supply law region) where the film forming rate is controlled, the decomposition of the film forming gas is promoted and the high energy particles are contained in the plasma. To increase. Therefore, the physicochemical energy of the high-energy particles with respect to the film surface activates the outermost surface of the film at the time of film formation, thereby facilitating the desorption of hydrogen from the film surface. In this manner, an amorphous silicon film having a low hydrogen concentration in the film can be formed, and it is not necessary to perform a step of desorbing hydrogen in the amorphous silicon film as in the related art, and the manufacturing efficiency is improved.

According to a thirty-sixth aspect of the present invention, there is provided a plasma CVD method.
In a method of introducing a film-forming gas containing at least a Si element into a vacuum vessel of an apparatus and reacting the film-forming gas by a plasma CVD method to form an amorphous silicon film on a substrate, The method is characterized in that the film is diluted with a gas that does not contribute to film formation, and the film formation gas is reacted under supply rule conditions.

According to the above method, in addition to the functions and effects of the invention described in claim 35, polymerization in a gas phase under a plasma atmosphere is performed by diluting the film forming gas with a gas that does not contribute to film formation. The reaction can be suppressed. Therefore, it is possible to more efficiently form an amorphous silicon film having a low hydrogen concentration in the film.

According to a thirty-seventh aspect of the present invention, in the method for forming an amorphous silicon film according to the thirty-fifth or thirty-sixth aspect, the temperature of the substrate on which the amorphous silicon film is to be formed is set to three.
It is characterized in that the temperature is not higher than 00 ° C.

When the substrate temperature is higher than 300 ° C., hydrogen on the surface of the amorphous silicon film is desorbed by thermal energy and the hydrogen concentration in the film is reduced. However, the amorphous silicon film is microcrystallized and the throughput is reduced. However, according to the above method, since the amorphous silicon film is formed at a temperature of 300 ° C. or lower, the amorphous silicon film does not microcrystallize, the throughput does not decrease, and the manufacturing efficiency does not decrease. Also, 3
Since the amorphous silicon film is formed on the substrate at a temperature of 00 ° C. or lower, a material having low heat resistance can be used as the substrate. The lower limit of the substrate temperature is a normal temperature (about 25 ° C.) in consideration of an actual manufacturing process.

The invention according to claim 38 is the method for forming an amorphous silicon film according to any one of claims 35 to 37, wherein the film forming gas is SiH ₄ or Si It includes ₂ H _6,
The gas that does not contribute to the film formation contains at least Ar, and the ratio of the film formation gas is set to 5% or less.

The film-forming gas SiH ₄ or Si ₂
By reducing the concentration of H ₆ to 5% or less and increasing the concentration of Ar, which is a gas that does not contribute to the film formation, the film formation rate of the amorphous silicon film is reduced, and Ar and SiH ₂ excited in the plasma are reduced. Since high-energy particles such as radicals and SiH radicals increase, hydrogen existing on the outermost surface during the formation of the amorphous silicon film causes a physicochemical reaction by the high-energy particles (the kinetic energy and internal energy of the high-energy particles are reduced on the film surface). To form an amorphous silicon film having a hydrogen concentration of 3 at% or less in the film. Therefore, unlike the related art, there is no need to perform a step of desorbing hydrogen in the amorphous silicon film, and the manufacturing efficiency is improved.

The above-mentioned Ar is an inert gas which is likely to have a high energy state particularly in plasma, and therefore, the hydrogen existing on the outermost surface during the formation of the amorphous silicon film is physically affected by the Ar. Desorbed by chemical reaction.

The invention according to claim 39 is characterized in that, in the method for forming an amorphous silicon film according to claim 38, the gas that does not contribute to the film formation contains at least Ar and H ₂ .

According to the above method, hydrogen atoms and H +, which have become high-energy particles in the plasma, reach the surface of the amorphous silicon film, and the Si—H bond existing on the outermost surface during the formation of the amorphous silicon film is removed. It is thought that it is cut and becomes a hydrogen molecule and is desorbed from the film surface. Therefore, it is possible to further reduce the hydrogen concentration in the amorphous silicon film.

According to a forty-ninth aspect of the present invention, in the method for forming an amorphous silicon film according to the thirty-fifth or thirty-sixth aspect, a parallel plate type plasma CVD apparatus having a high-frequency electrode and a ground electrode opposed to each other is used as the plasma CVD apparatus. The frequency of the high-frequency power supply of the parallel plate type plasma CVD apparatus is set to 20 MHz or more and 100 MHz or less.

As described above, the parallel plate type plasma C
By setting the frequency of the high-frequency power supply higher than the normal 13.56 MHz in the vacuum vessel of the VD device, high-energy particles can be efficiently generated in the plasma,
Therefore, the hydrogen concentration in the amorphous silicon film on the substrate can be reduced by the physicochemical reaction by the high energy particles.

More specifically, the frequency of the high-frequency power supply of the plasma CVD apparatus is set to 20 MHz or more and 100 MHz or less, and the frequency of the high-frequency power supply is set to be higher than 13.56 MHz. High energy particles can be efficiently generated. In the region where the frequency of the high-frequency power source is lower than 20 MHz, high-energy particles are not efficiently generated. In the region where the frequency of the high-frequency power source is higher than 100 MHz, the dischargeable range is narrow, and the configuration of the device is more restricted. .
Therefore, the power supply frequency of the high-frequency power supply is
00 MHz or less. Preferably, the frequency of the high frequency power supply is 27.12 MHz.

The invention according to claim 41 is the method for forming an amorphous silicon film according to claim 35 or 36, wherein an inductively coupled plasma C is used as a plasma CVD apparatus.
It is characterized in that a VD device is used.

Even when the above-mentioned inductively coupled plasma CVD apparatus is used, high energy particles can be efficiently generated in the plasma, and the physicochemical energy of the high energy particles on the film surface makes it possible to form the amorphous silicon film. The hydrogen concentration in the film can be reduced.

The invention according to claim 42 is characterized in that, in the method for forming an amorphous silicon film according to claim 35 or 36, an electron cyclotron resonance type plasma CVD apparatus is used as the plasma CVD apparatus.

The electron cycloton resonance type plasma CV
Even when the D apparatus is used, similarly, high-energy particles can be efficiently generated in the plasma, and similarly, the hydrogen concentration in the amorphous silicon film can be reduced.

[0124]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Invention Group] A first invention group relates to a thin film transistor manufacturing apparatus and method.
In particular, the present invention relates to modification of a thin film transistor using an excimer laser or the like.

(Embodiment 1-1) FIG. 1 shows Embodiment 1
FIG. 2 is an overall configuration diagram of a thin-film transistor manufacturing apparatus according to Embodiment-1; FIG. 2 is a block diagram showing an electrical configuration of the thin-film transistor manufacturing apparatus according to Embodiment 1-1; In FIG. 1, a valve V for supplying and shutting off gas and a pump P for forcibly exhausting gas are illustrated only in the chamber 7. , 6
A similar valve V and pump P are provided separately.

As shown in FIG. 1, the present manufacturing apparatus is provided with a transfer chamber 1 provided with a robot 10 having a transfer roller for transferring a substrate, an extruder, a grip, etc., at the center.

The transfer chamber 1 has a gate valve 92 around it.
It has a structure in which the six chambers 2 to 7 are attached via -97. Further, the robot 10 is on a motorized base (not shown), and can rotate in the direction of the chamber in each process by rotating the motor, that is, can rotate. And by this, separate substrates in each room at the same time,
In this manufacturing apparatus, a plurality of substrates can be processed simultaneously.

Further, each of the chambers 2 to 7 has a function of exhausting at least the internal air and depressurizing the air, and a function of introducing and exhausting a specific gas determined by the processing depending on the processing performed in the chamber from the outside. Further, a substrate (not shown) carried in from the transfer chamber 1 by the robot 10 through the gate valves 92 to 97 is processed under predetermined or unique conditions in each of the chambers 2 to 7. And has the function of carrying out to the transfer chamber 1 again in cooperation with.

The loading / unloading chamber 2 takes a substrate to be processed by the present apparatus from the outside and reduces its atmosphere from the atmosphere to a reduced pressure.
Alternatively, it has a function of returning the atmosphere of the substrate, which has been processed by the present apparatus, from the reduced pressure state to the indoor atmosphere, or filling with nitrogen. For this purpose, it is connected to a pump P, a valve V and various gas supply mechanisms. The pump P, the valve V, and the various gas supply mechanisms are provided in the chambers 1, 3 to 3 other than the loading / unloading chamber 2.
7 are also provided individually.

The two film-forming chambers 3 and 4 are connected to a source (gas) supply source outside via a valve V. In this chamber, amorphous silicon or amorphous silicon is formed on the substrate by plasma CVD. It functions as a facility and a room for forming a microcrystalline silicon film, a silicon dioxide film as an insulating film, or the like.

The film forming method used in the film forming chambers 3 and 4 is as follows.
Nothing is limited to the plasma CVD method. ECR plasma CVD can be performed by connecting to necessary equipment.
, A remote plasma CVD method, a sputtering method, or the like can be used.

The laser annealing chamber 5 has a quartz window (not shown) on the upper surface through which laser light from outside can be introduced, and is used as an irradiation target for reforming carried into the room. The substrate on which the amorphous semiconductor thin film is formed is moved horizontally at a predetermined speed determined by processing conditions such as laser energy density.

Then, the laser light is applied to the outdoor reforming (melting,
After being emitted from a laser oscillation device 11 for crystallization under predetermined intensity and oscillation conditions, the beam is adjusted to a predetermined energy density and beam shape by an optical system 12 having a lens, a slit, and the like. When the substrate moves according to a predetermined program, this beam irradiates the entire surface of the substrate while sequentially scanning the surface of the substrate installed in the laser annealing chamber.

In some cases, the laser is irradiated only to a specific area without moving the substrate.

The heat treatment chamber 6 has a function to heat-treat the substrate, more precisely, each thin film formed on its surface at a predetermined temperature and atmosphere. Therefore, the side wall surface is insulated. Note that the heat treatment chamber 6 has an electric heater for heat treatment.

[0136] The measuring chamber 7 is used to increase the accuracy of the amorphous semiconductor thin film formed on the substrate, as well as the predetermined physical properties such as the density of the substrate itself in accordance with the contents thereof. Alternatively, it has means for measuring in a predetermined atmosphere. In addition, for this reason, a laser oscillator provided outside in consideration of maintenance and the like, a structure matched to the light receiver, etc., for example, a laser light introduction, has a quartz window and the like for derivation,
And has a function of holding the substrate accurately and horizontally to improve the measurement accuracy.

Based on the above, the contents of the processing performed in each chamber when manufacturing the thin film transistor will be described.

First, with respect to the so-called well-known techniques such as the formation of a thin film made of amorphous silicon on a substrate,
The description of the contents is omitted, and the indoor processing unique to the present apparatus will be described.

Specifically, first, the measured values of the physical properties in the measurement chamber 7 will be described.

There are several means for measuring physical properties provided in the measuring chamber 7, one example of which is shown in FIG.

In the present apparatus, a thin glass (naturally transparent) substrate 21 to be inspected is held horizontally so as not to be distorted, while a quartz window 31 is placed in a direction perpendicular to the surface, that is, from directly above. A film thickness measuring light source unit 13 for irradiating a laser beam 34 of a predetermined wavelength such as 350 or 420 nm through the light source, a reflecting mirror 32, and a quartz window 33 on the wall surface facing the irradiation direction of the film thickness measuring light source unit. Transmitted light detector 14
It has.

Thus, the substrate before and after the formation of the silicon thin film, and in the case of a large substrate such as 16 inches or 20 inches, are further moved by using the moving mechanism 71 to measure the change in transmittance of each part. Therefore, the thickness of the silicon thin film or the like formed on the substrate can be accurately obtained. It should be noted that since all the substrates are mounted horizontally (at any time), it is needless to say that adjustment or correction of the change in the thickness of each substrate is unnecessary.

It is also possible to accurately check whether or not the substrate itself is mounted horizontally by utilizing the interference of laser light.

Further, the light source unit 13 for film thickness measurement can change the wavelength of the irradiated light within a certain range by changing the optical system such as passing through a prism (not shown) or changing the light source. It is possible to perform measurement by changing the wavelength, and to measure physical properties other than the film thickness.

In addition, absorption by a special substance such as hydrogen,
It is also possible to irradiate light having a wavelength for exciting a special substance or the like, and to examine the concentration from the absorption rate or the intensity of the excitation light.

Next, an electrical configuration of the manufacturing apparatus will be briefly described with reference to FIG. In FIG.
Reference numeral 0 denotes a control circuit. The control circuit 70 is connected to a ROM 75 and a RAM 72 in which data such as a system program and laser output related to reforming are stored. The control circuit 70 is connected to the operation input unit 73 and the light detection unit 14, and receives an input from the operation input unit 73 and detection data from the light detection unit 14. The control circuit 70 includes a plurality of valves V,..., A plurality of pumps P,.
3. The oscillator 11 for irradiating the laser for annealing is connected, and the opening and closing of each valve V, the driving of the pump P, and the laser driving of the light source unit 13 and the oscillator 11 are controlled. In addition, on-off valves (not shown) are individually provided for various gas supply sources.
It is controlled by the control circuit 70. Although FIG. 2 mainly shows a control mechanism for reducing the pressure in the chambers 1 to 7 and a control mechanism for measuring and annealing, a predetermined processing apparatus in each chamber, for example, the film forming chamber 3 or the like. In 4, the operation of the film forming apparatus and the like is also controlled by the control circuit 70.

Next, the second measurement of the physical property value of the main measurement chamber 7 is performed.
4 is shown in FIG.

In this figure, quartz windows 35 and 36 are provided on a pair of opposing side surfaces not facing the transfer chamber of the measurement chamber. And, by this, the substrate 2 accurately placed horizontally
A light source unit 15 for measuring physical properties capable of irradiating light of a predetermined wavelength at a predetermined angle through a quartz window 35 with respect to the vertical direction of one surface, and the irradiating light reflected on the substrate surface is used as a quartz window. The physical property value can be measured by using the physical property value measuring light-receiving unit 16 detected through 36.

Specifically, it is possible to measure the thickness and the refractive index of the light transmitting film formed on the substrate surface by the ellipsometry method.

Next, a method of manufacturing a thin film transistor using the apparatus for manufacturing a thin film transistor having the above structure will be described.

FIG. 5 is a diagram showing how the cross-sectional structure changes as the manufacturing of thin film transistors (elements) progresses.

First, the translucent substrate 21 is loaded into the loading / unloading chamber 2 from outside.

At this time, the inside of the transfer chamber 1 and each of the chambers 2 to 7 disposed around the transfer chamber 1 are discharged in advance so that the pressure inside the transfer chamber 1 and the chamber 2 becomes a predetermined pressure or less.

After evacuating the loading / unloading chamber 2, the substrate 21 washed in the room which has been temporarily cleaned by the HEPA filter is removed.
The gate valve is opened and moved into the first film forming chamber 3 by the transfer robot 10.

In the film forming chamber 3, TEOS (Tetra
A mixed gas of Ethyl OrthoSilicate and oxygen is introduced, an undercoat film made of a silicon dioxide film is formed to a thickness of 400 nm on the surface of the substrate by a plasma CVD method, and then the substrate is moved to the measurement chamber 7 and its transmittance is measured. Measure.

Next, each processing shown in FIG. 5 is performed.

(A) The substrate 21 is moved to the second film forming chamber 4. In this film forming chamber, a mixed gas of silane and argon is introduced, and an amorphous silicon film 23 is further formed on the undercoat film 22 formed on the substrate to a thickness of about 50 nm.

Then, the substrate is moved to the measurement chamber 7 again, and the transmittance of the substrate after the formation of the amorphous silicon film is measured. Thereafter, the transmittance after the formation of the amorphous silicon film is compared with the transmittance measured before the formation, and based on the difference between the two values, the thickness of the formed amorphous silicon film is 1 nm. It is calculated with the following accuracy.

(B) The substrate is moved from the measurement chamber 7 to the laser annealing chamber 5, and the surface of the substrate is irradiated with a laser beam having conditions most suitable for the thickness of the amorphous silicon film previously obtained, particularly, energy density. This film is referred to as a polycrystalline silicon film 24. Note that, at this time, the relationship between the film thickness and the laser irradiation conditions is stored in the ROM 75 in advance, so that even if the thickness of the amorphous silicon film varies in the range of about 5 to 10%, Variations in the characteristics of silicon after recrystallization can be suppressed to about 2 to 3%. (In the past, this variation sometimes reached 10%.) (C) The substrate was moved from the laser annealing chamber 5 to the second film forming chamber 4 and a thickness of 30 nm was formed on the surface of the polycrystalline silicon film. A first gate insulating film 25 made of a silicon dioxide film is formed.

(D) The substrate is moved to the loading / unloading room 2.

Then, the gate valve 92 is closed, a clean nitrogen gas is introduced into the loading / unloading chamber 2 until the atmospheric pressure is reached, and the substrate is taken out.

Under these conditions, a resist having a predetermined pattern is formed on the substrate surface by using the photolithography technique, and then the polycrystalline silicon film and the polycrystalline silicon film are formed by a dry etching method using a mixed gas of carbon tetrafluoride and oxygen. One gate insulating film is isolated (formed into patterns 237 and 38) so as to have a shape and an arrangement according to a predetermined arrangement of transistor elements determined from a liquid crystal display panel as a product. Here, the reason why the etching is dry instead of wet is that the dimensioning is accurate.

(E) A second gate insulating film 26 made of a silicon dioxide film having a thickness of 60 nm is formed, and subsequently, a gate electrode film 27 made of an alloy of molybdenum and tungsten is formed.

Further, after this gate electrode film is formed in a predetermined pattern 39, boron (B) ions are implanted into the entire surface of the substrate using this pattern as a mask (shield), and a p-type conductive region is formed in a part of the polycrystalline silicon film. 40 is formed.

(F) After forming the gate electrode film in the predetermined pattern 41 again, phosphorus (P) ions are implanted into the entire surface of the substrate, and an n-type conductive region 42 is formed in a part of the polycrystalline silicon film 24.
To form

(G) After forming the interlayer insulating film 28, a heat treatment at 350 ° C. is performed in a hydrogen gas plasma atmosphere.
The defects in the polycrystalline silicon film are terminated with hydrogen atoms.

Thereafter, contact holes are formed in predetermined regions of the n-type and p-type semiconductors, and a source electrode 29 and a drain electrode 30 made of a laminated film of titanium and aluminum are formed to complete a thin film transistor.

As can be seen from the above description, in the embodiment of the present invention, during the process from the undercoat film to the first gate insulating film, the interface between the different layers is exposed to the polluted atmosphere or oxygen even once. Therefore, an extremely clean interface can be maintained during this step, thereby achieving excellent transistor characteristics.

Specifically, when an evaluation test of the characteristics of the thin film transistor manufactured by the manufacturing apparatus and method of the present embodiment was performed, it was found that an n-type semiconductor was 300 cm ² / V · sec.
As described above, the variation between substrates of the p-type semiconductor having a field-effect mobility of 150 cm ² / V · sec or more was 3% or less.

For the same reason, a threshold voltage of 1 V or less was realized with good reproducibility.

Further, as compared with the related art, it is possible to improve the resistance to the application of the stress by the AC voltage and the DC stress at the high temperature.

(Embodiment 1-2) Embodiment 1-2 of the apparatus and method for manufacturing a thin film transistor according to the present invention will be described.
This will be described with reference to FIGS.

FIG. 6 is a diagram showing how the cross-sectional structure changes as the manufacturing of the thin film transistor progresses.

FIG. 7 is an overall configuration diagram of the present manufacturing apparatus.
This apparatus has two heat treatment chambers 61 and 62 and has a preliminary chamber 8. Therefore, the arrangement of each chamber is not a circle centering on the transfer chamber 1 but an ellipse.
Is different from that shown in FIG. 1 in that not only rotation but also linear movement in the major axis direction of the ellipse is possible.

The two heat treatment chambers each have a side facing the air, thereby further insulating the other heat treatment chambers from the other heat treatment chambers.

Hereinafter, an embodiment will be described with reference to FIG.

(A) Formation of the undercoat film 22 on the substrate 21 in the first film forming chamber 3, measurement of transmittance in the measuring chamber 7,
The formation of the amorphous silicon film in the second film forming chamber 4 is sequentially performed.

Thereafter, in the first heat treatment chamber 61, at 450 ° C.
A heat treatment for purging hydrogen contained in the amorphous silicon film is performed in a nitrogen gas atmosphere at about 500 ° C. Here, the heat treatment in nitrogen gas is performed in order to uniformly heat the substrate, and if vacuum is applied, the substance adhering to the interior wall surface by van der Waals force jumps out at high temperature and becomes amorphous. This is to prevent adhesion to silicon. In addition, this heat treatment chamber can process a plurality of substrates at the same time because energy and work efficiency are improved and installation accuracy does not matter.

The substrate after the heat treatment was transferred to the measurement chamber 7 again, the thickness of the amorphous silicon film was measured based on the measurement of the transmittance, and then the substrate was transferred to the laser annealing chamber 5, and the laser light under the most suitable conditions was applied to the substrate. The polycrystalline silicon film 24 is formed by irradiating the surface.

(B) After forming the first gate insulating film in the first film forming chamber, heat treatment is performed in a hydrogen plasma atmosphere at 300 ° C. to 350 ° C. in the second heat treating chamber 62. By this processing, the defect dangling bonds existing in the polycrystalline silicon film are terminated by bonding of hydrogen atoms, and the occurrence of defects in the subsequent processing is suppressed.

Further, as in Embodiment 1-1, the substrate is taken out of the apparatus, and then the first gate insulating film and the polycrystalline silicon film are formed in a predetermined pattern by photolithography. After that, the second gate insulating film 26
Is formed, and subsequently, a gate electrode film is formed, and the formed gate electrode film is formed in a predetermined pattern 39.

Next, boron ions are implanted into the entire surface of the substrate to form a p-type conductive region 40 in a part of the polycrystalline silicon film. Then, after a gate electrode film is formed again in a predetermined pattern, phosphorus ions are formed all over the substrate. To form an n-type conductor region 42 in a part of the polycrystalline silicon film.

(C) After forming the interlayer insulating film 28 and forming contact holes in predetermined regions of the n-type and p-type semiconductors, the source electrode 29 and the drain electrode 30 are formed to complete the thin film transistor.

An evaluation test of the characteristics of the thin-film transistor manufactured in this embodiment mode was performed.
00cm ² / V · sec or more, 150cm with p-type semiconductor
^The variation between the substrates of the thin film transistors having a field effect mobility of ² / V · sec or more was 3% or less.

(Supplementary Information of Embodiments 1-1 and 1-2)
As described above, the present invention has been described based on some embodiments, but it is needless to say that the present invention is not limited to these embodiments. That is, for example, the following may be performed.

(1) The semiconductor is a material other than silicon, for example, silicon-germanium, silicon-germanium-carbon.

With the development of future technology, substrates are made of materials other than glass.

(2) With the development of future technology, energy rays for melting and recrystallizing silicon are other than laser beams such as electron beams.

The formation of each thin film is another means.

(3) It has a function of blowing contaminants adhered after the previous process with a clean gas.

(4) The quartz window (glass) can be replaced with one having a different thickness.

(5) Rubber gloves are attached to the side surfaces of the vacuum chamber so that a person can directly move the substrate.

(6) In Embodiments 1-1 and 1-2, the laser annealing chamber 5 is used to modify amorphous silicon into polycrystalline silicon. However, instead of this, a chamber for performing lamp annealing is used. May be used. As the laser annealing, a carbon dioxide laser, an argon (Ar) laser, an excimer laser, or the like may be used.

(7) Further, the manufacturing apparatus according to the present invention
It can be widely used not only for FT but also for other semiconductor devices. In addition, optical multilayer film formation processing, LDD
The present invention can also be suitably carried out for an ion implantation process in a device having a (Lightly Doped Drain) structure.

(8) In the laser annealing chamber 5, the degree of the crystal after the laser annealing may be measured by the measuring means, and the laser annealing may be performed again. Therefore, the laser annealing chamber 5 and the measurement chamber 7 may be configured to be the same chamber. In this case, the output of the laser may be changed depending on whether it is for measurement or for annealing.

[Form of the Second Invention Group] The second invention group includes:
The present invention relates to a top gate thin film transistor applied to an active matrix liquid crystal display device, a sensor array, a static random access memory (SRAM), and the like, a method of manufacturing the same, and a top gate thin film transistor array. The gist of the second invention group is as follows. That is, the second invention group is characterized in that a gate electrode can be manufactured continuously without exposing the surface of a semiconductor thin film to the atmosphere.

(Embodiment 2-1) [Structure of Thin Film Transistor] FIG. 8 is a sectional view showing a structure of a top gate type TFT according to Embodiment 2-1. The top gate type TFT 130 has a polycrystalline silicon layer 102 as a semiconductor thin film having a thickness of, for example, 50 nm on an insulating substrate 101 such as a glass substrate.
A gate insulating film 103 made of 00 nm SiO ₂ (silicon dioxide), a gate electrode 104, and a film having a thickness of, for example, 3
An interlayer insulating film 108 made of 00 nm SiO ₂ is sequentially laminated. The gate electrode 104 includes:
The first sub-gate electrode 114 is formed of a high melting point metal (for example, a molybdenum-tungsten alloy), and the second sub-gate electrode 115 is formed on the first sub-gate electrode 114 and is formed of a low-resistance metal (for example, aluminum). I have. The semiconductor thin film 102 has a source region 1
05, a drain region 106, and a channel region 107. The channel region 107 is interposed between the source region 105 and the drain region 106 and is located directly below the first sub-gate electrode 114 via the gate insulating film 103.

Further, contact holes 111a and 111b are formed in the interlayer insulating film 108. A source electrode 109 is electrically connected to the source region 105 through the contact holes 111a. The drain electrode 110 is electrically connected to the drain region 106 via. The source electrode 109 and the drain electrode 110 are made of a low-resistance metal (for example, aluminum).

The gate electrode 104 has a laminated structure including the first sub-gate electrode 114 made of a high melting point metal and the second sub-gate electrode 115 made of a low-resistance metal for the following reason.

That is, in recent years, there has been a demand for an increase in the size of a liquid crystal display, and accordingly, in order to prevent a signal voltage from dropping, it has been desired to use a low-resistance metal as an electrode material for a gate electrode. However, if the material has a low resistance but has a low melting point, the metal material of the gate electrode partially dissolves in the TFT manufacturing process, for example, during heat treatment for activating impurities after doping, and contacts the end face. Phenomenon, which has a significant effect on transistor performance. In order to solve such a problem, it is required that a material having a low resistance and a high melting point be used as the gate electrode material. However, within the range that can be used as a wiring material, a metal material having a low resistance and a high melting point is
not exist. Therefore, in the present embodiment, the gate electrode 1
04 to the first sub-gate electrode 114 made of a high melting point metal.
And a second sub-gate electrode 115 made of a low-resistance metal. Thereby, the first sub-gate electrode 114
If heat treatment is performed after the formation and before the formation of the second sub-gate electrode 115, partial melting of the gate electrode due to the heat treatment can be prevented. In addition, by forming the second sub-gate electrode 115 after the heat treatment step, the resistance of the entire gate electrode can be reduced.

With the above structure of the TFT, it is possible to form the wiring such as the signal line and the control line in the TFT array from a low-resistance metal material. This point will be described in detail in Embodiment 2-6 described later.

[Method of Manufacturing Thin-Film Transistor] FIGS. 9 and 10 are cross-sectional views showing steps of manufacturing a top-gate type TFT according to the embodiment 2-1. FIGS. It is a top view which shows the manufacturing process of such a top gate type TFT. 11 (a) corresponds to FIG. 9 (a), FIG. 11 (b) corresponds to FIG. 9 (b), and FIG.
9C corresponds to FIG. 9C, and FIG.
FIG. 12 (b) corresponds to FIG. 10 (b), and FIG. 12 (c) corresponds to FIG. 10 (c).

Hereinafter, a method of manufacturing the top gate type TFT 130 having the above configuration will be described with reference to FIGS.

First, a 50 nm-thick amorphous silicon thin film is formed on an insulating substrate 101 such as a glass substrate having a 400 nm-thick impurity diffusion preventing film (not shown) adhered to the surface, for example, with silane, argon and hydrogen. PECVD (Plasma Enhanced Chemical Vapor D)
eposition, plasma CVD) or the like. Then, after removing hydrogen in the amorphous silicon thin film to a few at% or less by heat treatment or the like, the amorphous silicon is crystallized by irradiating high energy density ultraviolet rays such as excimer laser light. A polycrystalline silicon layer 120 is formed.

Next, without exposing the surface of the polycrystalline silicon layer 120 to the atmosphere, a silicon oxide film 121 serving as the gate insulating film 103 is formed with a thickness of, for example, 100 nm.
Specifically, when forming the silicon oxide film 121, it is preferable to form the silicon oxide film 121 by PECVD using a mixed gas such as TEOS (tetraethoxysilane) vapor and oxygen.

Next, over the entire surface of the silicon oxide film 121, a high-melting point metal thin film 122 made of, for example, a molybdenum-tungsten alloy to be the first sub-gate electrode 114.
Is formed by a sputtering method or the like. Such a state is shown in FIGS. 9A and 11A.

Thus, on the insulating substrate 101,
By continuously forming the polycrystalline silicon layer 120 and the silicon oxide film 121, the cleanliness of the polycrystalline silicon layer 120 and the silicon oxide film 121 (therefore, the cleanliness of the polycrystalline silicon layer 102 and the gate insulating film 103). Is kept.
As a specific method of forming a film continuously, it may be performed by the cluster type film forming apparatus using the robot chamber shown in FIG. 1 or FIG.

Next, in order to separate elements, a high melting point metal thin film 122 is formed by using photolithography and etching techniques.
Processing from the surface to the polycrystalline silicon layer 120 is processed into a first island shape. Such a state is shown in FIG. 9B and FIG.
This is shown in (b).

Next, the refractory metal thin film 122 and the silicon oxide film 121 are processed into a second island shape again by photolithography and etching techniques, and the first sub-gate electrode 1 is formed.
14 and a gate insulating film 103 are formed. Then, in this state, the first sub-gate electrode 11 is formed by the ion implantation technique.
Using the mask 4 as a mask, phosphorus is implanted as impurity ions in the case of n-type and boron is implanted in the case of p-type as impurity ions. Since the ion implantation at this time may be performed by directly doping the polycrystalline silicon layer 120, the ion implantation is performed at a low acceleration voltage. Therefore, damage to the semiconductor layer during doping can be reduced as compared with ion implantation at a high acceleration voltage. Thereafter, impurity ions are activated by, for example, heat treatment, lamp heating, laser irradiation, or the like, so that the polycrystalline silicon layer 102 having the source region 105, the drain region 106, and the channel region 107 is formed. Such a state is shown in FIGS. 9C and 11C.
Is shown in

Next, a 300 nm-thick interlayer insulating film 108 made of a silicon oxide film or the like is formed on the entire surface of the insulating substrate 101 so as to cover the polycrystalline silicon layer 102 and the first sub-gate electrode 114. Such a state is shown in FIG.
(A) and FIG. 12 (a).

Next, the interlayer insulating film 108 is processed again using photolithography and etching techniques to form a contact hole 111a opened in the source region 105, a contact hole 111b opened in the drain region 106,
A contact hole 111c opened in the first sub-gate electrode 114 is provided. Such a state is shown in FIGS. 10B and 12B.

Next, a low-resistance metal thin film of, for example, aluminum is formed on the entire surface and processed again using photolithography and etching techniques to form a source electrode 109, a drain electrode 110, and a second sub-gate electrode 115. . Thereby, the first sub-gate electrode 114 made of a high melting point metal and the second sub-gate electrode 11 made of a low resistance metal
5 has been formed. Such a state is shown in FIGS. 10C and 12C. Thus, the top gate type TFT 130 according to Embodiment 2-1 is manufactured.

By the above manufacturing method, the polycrystalline silicon layer 1
Since the interface between the gate insulating film 02 and the gate insulating film 103 is formed continuously, the interface localization level is small and the cleanliness is high. Also,
The island-shaped processed surface of the polycrystalline silicon layer 102 and the first sub-gate electrode 114 are insulated by the interlayer insulating film 108 and thus do not come into contact with each other. Therefore, the TFT characteristics can be improved.

[0214] The semiconductor thin film and the gate insulating film are continuously formed by transporting the glass substrate between two PECVD chambers and a laser annealing chamber by a transport robot in a clean atmosphere such as a reduced-pressure atmosphere or a predetermined gas atmosphere. The so-called cluster type film forming apparatus shown in FIG. 1 or FIG.

(Embodiment 2-2) FIGS. 13 and 14 are cross-sectional views showing the steps of manufacturing a top-gate TFT according to Embodiment 2-2. The manufacturing method of the embodiment 2-2 is almost the same as the manufacturing method of the embodiment 2-1. That is, FIGS. 13A to 13C in Embodiment 2-2.
Each manufacturing process in FIG. 14C corresponds to each of the manufacturing processes in FIGS. 9A to 10C in Embodiment 2-1. Each manufacturing process is described in Embodiment 2-2.
And Embodiment 2-1 are basically the same, and a detailed description thereof will be omitted. However, in the manufacturing method according to the embodiment 2-1, in the second island processing (FIG. 9C), the refractory metal thin film 122 (corresponding to the first sub-gate electrode 114) and the silicon oxide film 121 (gate insulating film) (See FIG. 9 (c)). However, in the manufacturing method of the present embodiment 2-2, as shown in FIG. 13 (c), the refractory metal thin film 122 (first sub-gate electrode) is formed. 114)
Embodiment 2 is different from Embodiment 2-1 in that only the processing is performed. Therefore, in Embodiment 2-2, since the ion implantation is performed through the gate insulating film, the ion implantation can be performed at a high acceleration voltage. For this reason, compared to Embodiment 2-1 in which ion implantation is performed at a low acceleration voltage, in Embodiment 2-2, the linearity of flying ions is improved, and thus the island-like processing of the polycrystalline silicon layer 102 is performed. The resulting slope is less likely to be contaminated with impurity ions, preventing leakage between the semiconductor thin film and the gate electrode.
There is an advantage that T can be easily manufactured.

(Embodiments 2-1 and 2-2)
In the above Embodiments 2-1 and 2-2, only the case where a molybdenum-tungsten alloy is used as the refractory metal has been described. However, as for the material of the high melting point metal, another metal may be used as long as it is stable even at a temperature higher than the heat resistance temperature of the glass substrate. For example, molybdenum, tungsten, tantalum, titanium, vanadium,
Zirconium, niobium, nickel, chromium, an alloy thereof, or the like may be used.

Embodiment 2-1 and Embodiment 2
In -2, the first sub-gate electrode material is a high melting point metal, but polycrystalline silicon having a high impurity concentration may be used as the first sub-gate electrode material instead of the high melting point metal. As a method for forming such a first sub-gate electrode made of polycrystalline silicon, amorphous silicon is formed again on the gate insulating film 103, polycrystallized by irradiating ultraviolet rays, and the resistance is reduced by impurity implantation. What is necessary is just to make it a sub-gate electrode. When polycrystalline silicon having a high impurity concentration is used as the material of the first sub-gate electrode, the first sub-gate electrode is formed at the same time as the impurity is implanted into the source / drain in the manufacturing method of the embodiment 2-1. It is also possible to inject impurities into polycrystalline silicon,
It is particularly preferable because the production is easy.

Embodiment 2-1 and Embodiment 2
-2 describes the case where PECVD is used for forming amorphous silicon. However, these films are
Similar results can be obtained by performing WCVD (hot filament CVD).

Embodiment 2-1 and Embodiment 2
No.-2 describes the case where the crystallization of amorphous silicon is performed by irradiation with ultraviolet rays. However, the present invention is not limited to this, and a similar TFT can be manufactured by using another method such as a solid phase growth method.

Embodiment 2-1 and Embodiment 2
In -2, the case where a polycrystalline silicon thin film is used as the semiconductor thin film has been described. However, the present invention is not limited to this, and may be amorphous silicon or single crystal silicon, or may be other semiconductor materials other than silicon, such as polycrystalline silicon germanium.

Embodiment 2-1 and Embodiment 2
In -2, the gate electrode and the gate insulating film are processed into islands by patterning and then doped, but conversely, doping may be performed and then patterning may be performed. By performing the doping first as described above, it becomes possible to reliably implant impurity ions into the semiconductor layer. This is for the following reason. That is, if patterning is performed first, the end surfaces A and B of the gate electrode 114 and the gate insulating film 103 are formed as shown in FIG.
(See FIG. 11 (c)) is not a flat surface perpendicular to the substrate 101, but is a slight but slightly inclined surface. Therefore, if ions are implanted in this state, the ions enter obliquely and the gate insulating film 103
In addition, each end face of the semiconductor layer 102 is contaminated with impurities, which may cause deterioration of transistor performance. Therefore, it is desirable to perform patterning after doping.

Embodiment 2-1 and Embodiment 2
In No.-2, only the case where aluminum and its alloy are used as the low-resistance metal is described. However, with respect to the material of the low-resistance metal, resistivity 20μΩ · cm ² or less, preferably if 5μΩ · cm ^2, but may be other metals. For example, silver, copper, an alloy thereof, or the like may be used.

(Embodiment 2-3) FIGS. 16 and 17 show a CMOS-TF using a thin film transistor according to the present invention.
It is sectional drawing which shows the manufacturing process of T. This CMOS-TF
T is, as shown in FIG. 17B, LDD (Lightly Do
ped Drain) structure n-channel TFT 132 and LDD
(Lightly Doped Drain) Normal p-channel T without structure
FT133. p-channel TFT1
Reference numeral 33 denotes the TFT of the embodiment 2-1 (corresponding to a TFT when boron is doped as an impurity ion).
And the corresponding parts are denoted by the same reference numerals. An n-channel TFT 132 includes a polycrystalline silicon layer 140, a gate insulating film 103 made of SiO2, a gate electrode 142,
An interlayer insulating layer 108 made of O2 is laminated in order. The gate electrode 142 includes a first sub-gate electrode 143 made of a metal having a high melting point and a second sub-gate electrode 144 made of a low-resistance metal formed on the upper surface of the first sub-gate electrode 143. The polycrystalline silicon layer 140 includes a channel region 145 located immediately below the first sub-gate electrode 143, a source region (n + layer) 146 having a high impurity concentration, a drain region (n + layer) 147 having a high impurity concentration, And low-concentration impurity regions (LDD regions: n− layers) 148 and 149 having a low concentration. The low concentration impurity region 148 is interposed between the source region 146 and the channel region 145, and the low concentration impurity region 149 is interposed between the drain region 147 and the channel region 145. In addition, TFT13
2 is provided with a source electrode 150 and a drain electrode 151 made of a low-resistance metal.
Is connected to the source region 1 through the contact hole 152a.
The drain electrode 151 is connected to the drain region 147 through a contact hole 152b formed in the gate insulating film 141 and the interlayer insulating film 108.
It is connected to the.

[Production of CMOS-TFT]
A MOS-TFT was manufactured by the following method.

First, an amorphous silicon thin film having a thickness of, for example, 50 nm is formed on an insulating substrate 101 such as a glass substrate having an impurity diffusion preventing film (not shown) having a thickness of, for example, 400 nm. PECVD (Plasma Enhanced Chemical Vapor Dep.)
osition, plasma CVD) or the like. Then, after removing hydrogen in the amorphous silicon thin film to a few at% or less by heat treatment or the like, the amorphous silicon is crystallized by irradiating high energy density ultraviolet rays such as excimer laser light to crystallize the amorphous silicon. A crystalline silicon layer 120 is formed.

Next, without exposing the surface of the polycrystalline silicon layer 120 to the atmosphere, a silicon oxide film 121 serving as the gate oxide film 103 is formed with a thickness of, for example, 100 nm.
Next, over the entire surface of the silicon oxide film 121, the first
A high-melting-point metal thin film 122 such as a molybdenum-tantalum alloy to be the sub-gate electrodes 114 and 143 is formed by a sputtering method or the like. Such a state is shown in FIG.
This is shown in FIG.

Next, in order to separate the elements, a high melting point metal thin film 12 is formed by using photolithography and etching techniques.
The surface from the second surface to the polycrystalline silicon layer 120 is processed into a first island shape (FIG. 16B).

Next, using the photolithography and etching techniques, the refractory metal thin film 122 on the p-channel TFT 133 side is processed into a second island shape again to form the first sub-gate electrode 114 (FIG. 16 ( c)). Then, in this state, boron ions are doped on the n-channel TFT 132 side using the refractory metal thin film 122 as a mask and on the p-channel TFT 133 side using the first sub-gate electrode 114 as a mask (FIG. 16C). This gives n
On the channel TFT 132 side, the polycrystalline silicon layer 120 is not doped with impurities because it is covered with the refractory metal thin film 122. On the other hand, the p-channel TFT 13
On the third side, since the first sub-gate electrode 114 functions as a mask, the channel region 106 located immediately below the first sub-gate electrode 114 is a region not doped with impurities. Then, a region of the polycrystalline silicon layer 120 except for the channel region 106 is doped with impurities, and a source region (p + layer) 105 and a drain region (p + layer) 107
Is formed. Moreover, since the ions are doped using the first sub-gate electrode 114 as a mask, the channel region 106, the source region 105, and the drain region 107 can be formed in a self-aligned manner. Such a state is shown in FIG.

Next, the first sub-gate electrode 143 is formed by processing the refractory metal thin film 122 on the n-channel TFT 32 side into a second island shape using photolithography and etching techniques (FIG. 16D). . Then, in this state, phosphorus ions are doped through the gate oxide film using the refractory metal thin film 122 as a mask. Thus, on the n-channel TFT 132 side, the first sub-gate electrode 143
The channel region 145 located immediately below is a region not doped with impurities. Then, the polycrystalline silicon layer 12
Regions C and D excluding the channel region 145 of FIG.
(D) shows an n- layer doped with impurities.
On the other hand, on the p-channel TFT 123 side, phosphorus ions are implanted. As a result, both boron ions and phosphorus ions are implanted by the previous and current implantations, but boron ions are implanted so as to be relatively more. As a result, the device operates without any problem as a p-channel TFT. In addition, ion implantation at a high acceleration voltage is performed for ion implantation through the gate oxide film.

Next, an interlayer insulating film 108 is formed to cover the p-channel TFT 132 and the n-channel TFT 133 (FIG. 16E).

Next, contact holes 152a and 152b reaching the polycrystalline silicon layer 140 are formed in the interlayer insulating film 108 on the n-channel TFT 132 side. The opening of the contact hole 152a faces the remaining portion except for both sides of the region C (corresponding to the low-concentration region LDD), and the opening of the contact hole 152b covers both sides of the region D (the low-concentration region LDD). (Equivalent) except for the rest. Next, in this state, the interlayer insulating film 10
Using phosphorus 8 as a mask, phosphorus ions are again doped (FIG. 17A). Thereby, on the n-channel TFT 32 side, the interlayer insulating film 108 of the polycrystalline silicon layer 140 is formed.
Area not covered by the area (area facing the contact hole)
Is doped with ions. Therefore, of the regions C and D already doped with the impurity by the first phosphorus ion doping, the regions not covered with the interlayer insulating film 108 (corresponding to the source region and the drain region) are further doped with the impurity. That is, the impurity high concentration region (n +
Layer). On the other hand, among the regions A and B, the interlayer insulating film 10
8 (corresponding to the low-concentration impurity regions 48 and 49), the impurity is not doped by the second phosphorus ion doping, and the low-concentration impurity region (n
-Layer). Thus, the source region (n + layer) 146
Between the channel region 145 and the low-concentration impurity region (n-
Layer 148 is formed, and the drain region (n + layer) 1
A low concentration impurity region (n− layer) 149 can be formed between the channel region 147 and the channel region 145.

Next, contact holes 111a and 111b reaching the polycrystalline silicon layer 102 are formed in the interlayer insulating film 108 on the p-channel TFT 133 side. And
A low resistance metal thin film of aluminum is formed on the entire surface of both the n-channel TFT 132 and the p-channel TFT 133,
Again, using photolithography and etching techniques, the source electrodes 109, 150 and the drain electrodes 110, 151
And the second sub-gate electrodes 115 and 144 are processed. Thus, as shown in FIG. 17B, the n-channel TFT
A CMOS-TFT having an LDD structure on the side is manufactured.

Also according to the manufacturing method according to Embodiment 2-3, the interface between the polycrystalline silicon layer and the gate insulating film is formed continuously, so that the interface localization level is small,
High cleanliness. In addition, the island-shaped processed surface of the polycrystalline silicon layer and the first sub-gate electrodes 114 and 143 are insulated by the interlayer insulating film 108, and thus do not come into contact with each other. Therefore, a CMOS-TFT with improved TFT characteristics is manufactured.

(Embodiment 2-4) FIGS. 18 and 19 show a CMOS-TF using a thin film transistor according to the present invention.
It is sectional drawing which shows the process of another manufacturing method of T. The embodiment 2-4 is basically similar to the embodiment 2-4. However, in Embodiment 2-3, n + doping is performed after the formation of the interlayer insulating film 108. However, in Embodiment 2-4, doping is performed after etching for LDD is performed on the gate oxide film. It is different in that.

Hereinafter, description will be made with reference to FIGS. 18 and 19. First, in the same manner as in Embodiment 2-3, FIG.
8 (a) to 18 (d) are performed, and p + doping and n− doping are performed. The processing in FIG. 18A corresponds to FIG. 16A, and the processing in FIG.
18 (c) corresponds to FIG. 16 (b).
18 (d) corresponds to FIG. 16 (d).

Next, the silicon oxide film 121 on the n-channel TFT 132 side is processed into an island shape using photolithography and etching technology. And in this state, n
+ Doping is performed. Since the doping is directly performed on the polycrystalline silicon layer 140 on the n-channel TFT 132 side, the ion implantation is performed at a low acceleration voltage. Thus, on the n-channel TFT 132 side, of the regions A and B of the polycrystalline silicon layer 140 which are already doped with impurities by the first phosphorus ion doping, the regions (sources) not covered with the gate insulating film 103 (Corresponding to the region and the drain region), the impurities are further doped, and the region becomes a high impurity concentration region (n + layer). On the other hand, in the regions C and D, which are covered with the gate insulating film 103 (corresponding to the low-concentration impurity regions 148 and 149), the impurities are not doped by the second phosphorus ion doping, and the low-concentration impurities are not doped. Impurity region (n-
Layer). Thus, the low-concentration impurity region (n−) is located between the source region (n + layer) 146 and the channel region 145.
Layer 148 is formed, and the drain region (n + layer) 1
A low concentration impurity region (n− layer) 149 can be formed between the channel region 147 and the channel region 145. Such a state is shown in FIG.

Next, an interlayer insulating film 108 is formed.
9 (a)), contact holes 111a, 111b, 1
11c, 152a, 152b, and 152c are opened. Then, the n-channel TFT 132 and the p-channel TFT 1
33, a low-resistance metal thin film such as aluminum is formed on both surfaces, and the source electrodes 109 and 150 and the drain electrode 11 are again formed by photolithography and etching.
0, 151 and the second sub-gate electrodes 115, 144. Thus, as shown in FIG. 19B, a CMOS-TFT having an LDD structure on the n-channel TFT side is manufactured.

(Embodiment 2-5) FIG. 20 is a circuit diagram showing a configuration of a TFT array composed of TFTs according to the present invention. In the TFT array, a plurality of signal lines 155 and a plurality of control lines 156 are arranged in a matrix, and
The top gate type TFT 130 of the embodiment 2-1 is arranged near each intersection of the control line 55 and the control line 156. The TFT of Embodiment 2-2 may be used instead of the TFT of Embodiment 2-1.

The signal line 155 is connected to the source electrode 109 of the corresponding TFT, and the control line 156 is connected to the gate electrode 104 of the corresponding TFT. Note that the signal line 155 and the control line 156 are formed on the same insulating substrate 101 together with the TFT. And the signal line 1
As shown in FIG. 21, the 55 and the control line 156 are formed of a four-layered film including a semiconductor layer 157, an insulating film 121, a high-melting metal layer 122, and a low-resistance metal layer 158. Also, signal line 1
At the intersection of the control line 55 and the control line 156, as shown in FIG.
1, a high-melting-point metal layer 122 and a four-layer laminated film of an interlayer insulating layer 108, and the signal line 155 is a single-layered film of a low-resistance metal layer 158. With such a structure, the signal lines 155 requiring low resistance are substantially all low-resistance metals 15.
8 and the control line 156 is also connected to the signal line 15.
The wiring is made of the low-resistance metal 158 except for the intersection with 5. Therefore, this is a preferable configuration for a large and high-definition TFT array in which it is important to reduce the wiring resistance.

FIGS. 23 and 24 are cross-sectional views showing the steps of manufacturing a TFT array. 23 and 24, for convenience of explanation, one TFT portion and its TFT
Only the wiring structure related to the portion is shown. Hereinafter, a method for manufacturing a TFT array according to the present invention will be described with reference to the drawings. First, as shown in FIG. 23A, a three-layer laminated film of a semiconductor layer 157, an insulating layer 121, and a refractory metal layer 122 is formed on the insulating substrate 101 (FIG. 9A).
And FIG. 11A).

Next, as shown in FIG. 23B, the signal line 155 is formed by photolithography and etching in a state where the TFT 130, the control line 156, and the control line 156 are disconnected so as not to come into contact with each other. (Fig. 9
(Corresponds to (b) and FIG. 11 (b)).

Next, as shown in FIG.
The island-shaped processing of 130 is performed, and impurity implantation and activation are performed (corresponding to FIGS. 9C and 11C).

Next, as shown in FIG. 24A, an interlayer insulating layer 108 is formed on the entire surface (FIG. 10A and FIG.
2 (a)).

Next, as shown in FIG. 24B, a contact hole is opened in the interlayer insulating film 108 (FIG. 10B).
(Corresponding to (b) and FIG. 12 (b)). At this time, at least at the portion where the control line 156 and the signal line 155 intersect,
The interlayer insulating layer 108 is left so that the two lines do not contact each other, and the other parts on the control lines 156 and the signal lines 155
In the upper part, the interlayer insulating film 108 is removed.

Next, as shown in FIG. 24C, connection between the control line 156 and the gate electrode 104 and connection between the signal line 155 and the source (drain) region are performed using a low-resistance metal such as aluminum. 10 (c) and FIG. 12 (c)). At the same time, the low-resistance metal 158 is added to a portion of the control line 156 other than the intersection with the signal line 155 and to all the portions including the intersection on the signal line 155.
To form Thereby, the control line 156 and the signal line 1
55 basically consists of a four-layer laminated film of a semiconductor layer 157, an insulating film layer 121, a high melting point metal layer 122, and a low resistance metal layer 158. At the intersection of both lines, the control line 156 is connected to the semiconductor layer 157, The signal line 155 is a single-layer film of the low-resistance metal layer 158, and the signal line 155 is a single-layer film of the low-resistance metal layer 158.

With this structure, it is possible to manufacture a TFT array without losing continuity between the semiconductor layer of the TFT portion 130 and the gate insulating layer. Further, the signal lines 155 requiring a lower resistance are all substantially wired with the low-resistance metal 158, and the control lines 156 are also wired with the low-resistance metal 146 except at the intersections with the signal lines 155. Is done. Therefore, it is important to reduce the wiring resistance.
This is a preferred configuration for an FT array. Then, at the time of ion implantation, a high melting point metal is used as a mask, and the upper limit of the heating temperature and thermal shock at the time of activation is relaxed. Further, since the low-resistance metal is formed after activation, a low-melting-point material such as aluminum may be used.

In the above example, except for the intersection of the signal line and the control line, the signal line was formed of a four-layered film of a semiconductor layer, an insulating film layer, a high melting point metal layer and a low resistance metal layer. However, only the control lines are formed in FIG.
4 (c), the signal line may be formed of a low-resistance metal. By doing so, all the signal lines including the intersections of the signal lines and the control lines become one layer of a low-resistance metal layer, and the resistance of the signal lines can be further reduced.

[Form of the Third Invention Group] The third invention group includes:
The present invention relates to a method of forming an amorphous silicon film by a plasma CVD method, and more particularly to a method of easily forming an amorphous silicon film having a low hydrogen concentration in a film at a low temperature by a plasma CVD method. The gist of the third invention group is as follows.

That is, the third invention group is characterized in that an amorphous silicon film having a hydrogen concentration in the film of 3 at% or less can be easily formed at a low temperature by a plasma CVD method.

(Embodiment 3-1) Hereinafter, Embodiment 3
-1 will be described with reference to FIGS. In the present invention, a parallel plate type plasma CVD apparatus was used. FIG. 1 is a schematic view of a parallel plate type plasma CVD apparatus 210.

Gas introduction system 203 and evacuation system 202
An RF electrode 204 having a large number of holes on its lower surface is arranged at an upper position in a vacuum vessel 201 having
A ground electrode 205 is disposed at a lower position in 1 so as to face the electrode 204. A heater 207 is provided in the ground electrode 205.
Thereby, the substrate 206 disposed on the ground electrode 205 is heated. A high-frequency electrode 208 for applying a high-frequency voltage to the RF electrode 204 is provided.

The parallel plate type plasma CV having such a configuration is described below.
First, the pressure inside the vacuum vessel 201 is adjusted by the vacuum exhaust system 202 using the D apparatus 210. Next, a film-forming gas (raw material gas) contributing to film formation and a gas not contributing to film formation are jetted into the vacuum chamber 201 through a number of holes provided in the RF electrode 204 through the gas introduction system 203, and the RF electrode 20
RF plasma is generated by applying a high frequency power of 27.12 MHz to the substrate 4, and an amorphous silicon film is formed on the substrate 206. At this time, the substrate 2
No. 06 was heated to 250 to 300 ° C. by a heater 207 provided in the ground electrode 205. This temperature is a value measured by a thermocouple (not shown) provided on the back surface of the substrate 206. Hereinafter, a specific description will be given.

(Example 1) First, the substrate 206 was placed on the ground electrode 205, and the substrate 206 was heated to 300 ° C by the heater 207 provided in the ground electrode 205.

Next, the pressure in the vacuum vessel 201 was increased to 133P.
adjusted by the vacuum evacuation system 202 so that a, the vacuum chamber 201 through the gas introduction system 203, the flow rate of Ar is a gas that does not contribute to SiH ₄ and deposited a film forming gas 1
Introduced at 500 sccm, while changing the mixing ratio of SiH ₄ and Ar, the discharge frequency 2
An amorphous silicon film was formed on the substrate 206 by discharging at 7.12 MHz and RF power of 160 W. The thickness of the amorphous silicon film was adjusted to 300 nm by controlling the film formation time. The hydrogen concentration in the amorphous silicon film was analyzed by a Fourier transform infrared spectrometer (FTIR). The result is shown in FIG.

FIG. 26 is a graph showing the relationship between the SiH ₄ concentration and the hydrogen concentration in the amorphous silicon film.
The hydrogen concentration in the film decreases with decreasing SiH ₄ concentration,
An amorphous silicon film having an H ₄ concentration of 5% or less and a hydrogen concentration in the film of 3 at% or less is formed. This is because, while the SiH ₄ concentration decreases, the Ar concentration increases, so that the film formation rate decreases and hydrogen in the film is easily desorbed.
Ar having high energy in the plasma increases, and hydrogen existing on the outermost surface of the amorphous silicon film is reduced by the A.
The physicochemical reaction by r (the kinetic energy or the internal energy of Ar is given to the film surface by collision of Ar with the film surface, etc., thereby breaking the Si—H bond)
It is considered that this was due to detachment.

In the first embodiment, only Ar is used as a gas that does not contribute to film formation. However, by using a mixed gas of Ar and H ₂ (hydrogen) as a diluent gas, hydrogen in the amorphous silicon film can be reduced. The concentration can be further reduced.

This is because, in plasma, hydrogen atoms and H + more active than Ar reach the film forming surface, and the hydrogen atoms and H + break the Si—H bond on the surface of the amorphous silicon film to form hydrogen atoms. This is considered to be due to desorption from the film surface. In addition, since the amorphous silicon film is simultaneously etched by high energy hydrogen atoms and H + in the plasma, the S in the amorphous silicon film
It is considered that the bond of i-Si is broken, Si on the surface of the amorphous silicon film is detached from the film surface, and the deposition rate of the amorphous silicon film is reduced.

It is also known that when SiH ₄ is highly diluted only with H ₂ , an amorphous silicon film is not formed on the substrate 206 but a microcrystalline silicon film is formed. In order to form an amorphous silicon film, it is necessary to add Ar or the like at least as a gas that does not contribute to film formation, instead of diluting with only H ₂ .

(Example 2) Next, the flow rate of SiH _{4 was} 45 sc
The amorphous silicon film was formed on the substrate 206 while the SiH ₄ concentration was fixed at 3% and the RF power was changed in the range of 20 to 200 W while the Ar flow rate was 1 cm, the Ar flow rate was 1455 sccm. Other film forming conditions include a pressure of 133 Pa and a substrate temperature of 25.
0 ° C. FIG. 27 shows the relationship between the RF power and the deposition rate of the amorphous silicon film, and FIG. 28 shows the relationship between the RF power and the hydrogen concentration in the amorphous silicon film.

In FIG. 27, it can be seen that the film formation rate increases with an increase in the RF power, and after a certain value, it shows an almost saturated tendency. As described above, in the plasma CVD method, a region where the film forming speed increases in proportion to the RF power is called a reaction rule region, and a region where the film forming speed tends to be saturated with the RF power is called a supply rule region. In the reaction law region, the electron density in the plasma increases as the RF power increases, and the SiH
_Since the decomposition of ₄ is promoted, the deposition rate increases. When the RF power is further increased, SiH ₄ is almost completely decomposed,
It is a supply law area. In this region, since SiH ₄ is almost decomposed, the film forming rate hardly changes, the particle composition in the plasma changes, and particles having few hydrogen bonds such as SiH ₂ radicals and SiH radicals are present.

As shown in FIG. 28, the hydrogen concentration in the film is RF
It decreases with an increase in electric power, and the hydrogen concentration in the film becomes 3% or less when the electric power exceeds 100 W. This is because the electron density and the ion density in the plasma increase with the increase in RF power, so that Ar in the high energy state increases, and the A
It is considered that this is because hydrogen on the film surface is released by the physicochemical reaction of r to the film surface. Further, in a region where the hydrogen concentration in the film is 3 at% or less, the film formation rate is a region of the supply rule. In such a region, since the SiH ₄ is almost decomposed, the film formation speed hardly changes. Particles having small hydrogen bonds such as SiH ₂ radicals and SiH radicals due to a change in the particle composition therein serve as precursors for forming an amorphous silicon film. Therefore, it is considered that this greatly affects the reduction of the hydrogen concentration in the amorphous silicon film.

[0262] Example 3 In the Example 1, was used SiH ₄ as the film forming gas, which Si ₂
We examined the relationship between the RF power and Makuchu hydrogen concentration in the same manner as in Example 2 as H _6. The film forming gas (source gas) is S
An amorphous silicon film was formed under the same conditions as in Example 2 except that i ₂ H ₆ was used. FIG. 28 shows the result of examining the hydrogen concentration in the amorphous silicon film.

By changing the film forming gas from SiH ₄ to Si ₂ H ₆ , the hydrogen concentration in the film itself changes, but the tendency does not change (the hydrogen concentration in the film decreases when the RF power is increased). Understand. For this reason, it is conceivable that an amorphous silicon film having a low hydrogen concentration is formed by the same mechanism as in the case of SiH ₄ . Also, although not shown,
The same effect can be obtained by changing the film forming gas to Si ₃ H ₈ , SiH ₂ Cl ₂ , GeH ₄ or the like.

In Examples 1 to 3, Ar (argon) which is an inert gas is used as a gas which does not contribute to film formation.
Is used, for example, He gas which is the same inert gas
(Helium), Ne (neon), Kr (krypton),
Even when Xe (xenon) is used, a low hydrogen amorphous silicon film can be formed.

In the first to third embodiments, a parallel plate type plasma CVD apparatus as shown in FIG. 25 was used. However, according to the mechanism of the present invention, inductively coupled plasma (ICP) or electron cyclotron resonance is used. The same effect can be expected by using a plasma CVD apparatus using high-density plasma such as (ECR) plasma.

In order to manufacture a TFT using the method for forming amorphous silicon according to Embodiment 3-1 described above, for example, a cluster type film forming apparatus using the robot chamber shown in FIG. 1 described above may be used. Good.

The specific embodiments described above are for the purpose of illustration only.
The present invention clarifies the technical contents of the present invention, and should not be construed as being limited to such specific examples in a narrow sense. Instead, various modifications may be made within the spirit of the present invention and the scope of the claims. It can be implemented.

[0268]

As described above, according to the structure of the present invention, each object of the present invention can be sufficiently achieved. The details are as follows.

(1) According to the semiconductor manufacturing apparatus of the first invention group, while maintaining the cleanliness of the interface, the physical property value of the thin film formed on the substrate, particularly the physical property value related to the reforming of the thin film, is improved. It is possible to measure and then irradiate with a reforming energy beam. Therefore, it is possible to modify the thin film by the laser beam under the most suitable conditions according to the physical properties such as the film thickness.

Further, since the film formation in the next step can be performed without exposing the surface of the modified thin film to contaminated air or oxidizing air in a room, it is possible to realize a device having excellent characteristics. Become.

Also, by exposing to vacuum in the transfer chamber, the contaminants attached in the previous treatment can be naturally removed.

Further, since a semiconductor thin film having excellent interface characteristics can be formed, a thin film transistor (element) having extremely excellent characteristics can be manufactured with a very small variation range and high reproducibility.

For the same reason, a threshold voltage of 1 V or less can be realized with good reproducibility.

In addition, compared to the related art, it is possible to improve the resistance to stress application by AC voltage and DC stress at high temperature.

Also, since the laser oscillator is outside the room where the substrate is installed, various measurements and processes can be performed while the substrate and the like are kept clean by replacing it or by substantially replacing it by switching the lens system. It becomes possible. Specifically, for example, measurement of a substrate thickness, inspection of a material, and the like are performed.

Also, using the windows on the side walls of each clean room,
Laser irradiation is possible, and various measurements can be made.

Further, a device for mounting and transporting a substrate for original processing such as laser annealing and a device for mounting and transporting a substrate for measurement can be largely used.

(2) According to the second aspect of the invention, the gate insulating film is continuously formed without exposing the surface of the semiconductor thin film to the atmosphere, and the problem of contact between the semiconductor thin film and the gate electrode on the slope surface. In this case, top gate type TFTs can be manufactured without causing any problem. Thus, a top-gate thin film transistor having improved TFT characteristics can be obtained.

Further, it is possible to obtain a thin film transistor array which can reduce the resistance of a wiring (particularly, a signal line) and can be suitably applied to a large liquid crystal panel or the like.

(3) According to the third invention group, the plasma C
Using a VD apparatus, it is possible to form an amorphous silicon film having a hydrogen concentration of 3 at% or less without raising the substrate temperature to more than 300 ° C. Therefore, hydrogen desorption before laser irradiation by laser annealing is possible. The number of separation steps can be reduced, and the manufacturing steps can be simplified.
Therefore, the manufacturing cost of the low-temperature polysilicon TFT can be reduced,
Effects such as improvement in throughput can be expected.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of a manufacturing apparatus of a thin film transistor according to Embodiment 1-1.

FIG. 2 is a block diagram showing an electrical configuration of a thin film transistor manufacturing apparatus according to Embodiment 1-1.

FIG. 3 is a diagram illustrating an example of a configuration of a measurement chamber of the thin film transistor manufacturing apparatus according to Embodiment 1-1.

FIG. 4 is a diagram showing another example of the configuration of the measurement chamber of the thin film transistor manufacturing apparatus according to Embodiment 1-1.

FIG. 5 is a diagram showing a state of a change in a substrate, a cross section of a transistor, and a configuration accompanying progress of processing in a thin film transistor manufacturing apparatus and method according to Embodiment 1-1.

FIG. 6 is a diagram showing a change in a substrate, a cross section of a transistor, and a configuration accompanying progress of processing in a thin film transistor manufacturing apparatus and method according to Embodiment 1-1.

FIG. 7 is a diagram showing a schematic configuration of a manufacturing apparatus of a thin film transistor according to Embodiment 1-2.

FIG. 8 is a top-gate TFT according to Embodiment 2-1.
FIG. 3 is a cross-sectional view showing the structure of FIG.

FIG. 9 is a top-gate TFT according to Embodiment 2-1.
FIG. 6 is a cross-sectional view showing a manufacturing process of the second embodiment.

FIG. 10 is a top gate type TF according to the embodiment 2-1.
It is sectional drawing which shows the manufacturing process of T.

FIG. 11 is a top gate type TF according to the embodiment 2-1.
It is a top view which shows the manufacturing process of T.

FIG. 12 is a top gate type TF according to the embodiment 2-1.
It is a top view which shows the manufacturing process of T.

FIG. 13 is a top gate type TF according to the embodiment 2-2.
It is sectional drawing which shows the manufacturing process of T.

FIG. 14 is a top gate type TF according to the embodiment 2-2.
It is sectional drawing which shows the manufacturing process of T.

FIG. 15 is a sectional view showing end faces A and B of a gate electrode and a gate insulating film.

FIG. 16 is a cross-sectional view showing a manufacturing process of a CMOS-TFT using the thin film transistor according to Embodiment 2-3.

FIG. 17 is a cross-sectional view showing a manufacturing step of the CMOS-TFT using the thin-film transistor according to Embodiment 2-3.

FIG. 18 is a cross-sectional view showing a manufacturing step of a CMOS-TFT using the thin film transistor according to Embodiment 2-4.

FIG. 19 is a cross-sectional view showing a manufacturing step of a CMOS-TFT using the thin film transistor according to Embodiment 2-5.

FIG. 20 is a circuit diagram illustrating a configuration of a TFT array including thin film transistors according to Embodiment 2-5.

FIG. 21 is a cross-sectional view of a signal line 155 (control line 156) in Embodiment 2-5.

FIG. 22 is a cross-sectional view of an intersection of a signal line 155 and a control line 156 in Embodiment 2-5.

FIG. 23 is a cross-sectional view showing a step of manufacturing the TFT array according to Embodiment 2-5.

FIG. 24 is a cross-sectional view showing a step of manufacturing the TFT array according to Embodiment 2-5.

FIG. 25 is a schematic diagram showing a configuration of a parallel plate type plasma CVD apparatus used in the method according to Embodiment 3-1.

FIG. 26 is a graph showing the relationship between the concentration of SiH _{4 and the} concentration of hydrogen in the amorphous silicon film.

FIG. 27 is a graph showing the relationship between RF power and the deposition rate of an amorphous silicon film.

FIG. 28 is a graph showing the relationship between RF power and the hydrogen concentration in the amorphous silicon film.

FIG. 29 is a cross-sectional view showing a manufacturing step of the first conventional example.

FIG. 30 is a cross-sectional view showing a manufacturing step of the first conventional example.

FIG. 31 is a cross-sectional view showing a manufacturing step of the second conventional example.

[Explanation of symbols]

1: transfer chamber 2: carry-in / out chamber 3: first film formation chamber 4: second
Deposition chamber 5: Laser annealing chamber 6: Heat treatment chamber 61: First heat treatment chamber 62: Second heat treatment chamber 7: Measurement chamber 71: Moving mechanism for substrate 8: Preparatory chamber 10: Robot 11: Laser oscillation device for annealing 12: Annealing optical system 13: Light source unit for measuring film thickness 14: Transmitted light receiving unit for measuring film thickness 15: Light source unit for measuring property value 16: Light receiving unit for measuring property value 21: (light transmitting) substrate 22: Under Coat film 23: Amorphous silicon film 24:
Polycrystalline silicon film 38: Patterned polycrystalline silicon film 40:
P-type semiconductor region 42: N-type semiconductor region 25:
First gate insulating film 37: Patterned first gate insulating film 26:
Second gate insulating film 27: Gate electrode film 39: Patterned gate electrode film 41: Re-patterned gate electrode film 28:
Interlayer insulating film 29: source electrode 30:
Drain electrode 92-98: Gate valve 10
1: Insulating substrate 102, 140: Semiconductor thin film 10
3: Gate insulating film 104, 142: Gate electrode 105, 14
6: Source regions 106 and 147: Drain regions 107 and 14
5: channel region 108: interlayer insulating film 109, 15
0: Source electrode 110, 151: Drain electrode 114, 14
3: First sub-gate electrode 115, 144: Second sub-gate electrode 130:
Top gate type TFT 132: n-channel TFT 133:
p-channel TFT 148, 149: LDD region 155:
Signal line 156: Control line 201:
Vacuum container 202: Evacuation system 203:
Gas introduction system 204: RF electrode 205:
Ground electrode 206: Substrate 207:
Heater 208: High frequency power supply 210:
Plasma CVD equipment

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/205 G02F 1/136 500 27/08 331 H01L 29/78 617L 618A 624 627B 627E (72) Inventor Akira Nishitani Osaka 1006, Kadoma, Kadoma, Kadoma, Matsushita Electric Industrial Co., Ltd. Denki Sangyo Co., Ltd.

Claims (42)

[Claims] 1. A method for manufacturing an element having a multilayer structure by a plurality of film forming steps, wherein one of the plurality of film forming steps is a first step of forming at least one film. A film process, a measurement process of measuring predetermined physical properties of the film obtained in the first film formation process, and a second process of processing the film according to measurement conditions determined based on the measurement result in the measurement process. Wherein the first step, the measurement step, and the second step are each performed in a predetermined clean atmosphere. 2. The method according to claim 1, wherein the process in the second step is a film forming process. 3. The method according to claim 1, wherein the treatment in the second step is a film modification treatment. 4. An apparatus for manufacturing an element having a multilayer structure, comprising: a film forming means for forming at least one film of a plurality of films; and a predetermined physical property value of the film obtained by the film forming means. Measuring means, processing means for processing the film in accordance with a measurement condition determined based on the measurement result in the measuring means, and transport between the film forming means, the measuring means, and the processing means. A device for manufacturing a device having a multilayer structure, wherein the film forming device, the measuring device, the processing device, and the transporting device perform respective processes in a predetermined clean atmosphere. . 5. The apparatus for manufacturing an element having a multilayer structure according to claim 4, wherein the processing in said processing means is a film forming processing. 6. The apparatus for manufacturing a device having a multilayer structure according to claim 4, wherein the processing in said processing means is a film modification processing. 7. In a state where the substrate is installed in a predetermined clean atmosphere determined by the formation of a thin film, an amorphous film is formed on the substrate by using a semiconductor supplied from semiconductor supply means provided in a place outside the clean atmosphere. A thin film forming means for forming a semiconductor thin film, and a predetermined clean atmosphere determined by a physical property value measuring method using light to determine physical property values related to modification of the amorphous semiconductor thin film formed on the substrate by energy ray irradiation. In a state where the substrate is placed below, physical property value measuring means for measuring using a predetermined light source and a light receiver, and a reforming energy ray having a property determined from the measured physical property values, a predetermined energy determined from the reforming. Energy beam irradiation means for irradiating the amorphous semiconductor using a predetermined energy ray source provided in a place outside the clean atmosphere with the substrate installed in a clean atmosphere; In order to form a crystalline semiconductor layer, the thin film forming means, physical property value measuring means, energy ray An apparatus for manufacturing a thin film transistor, comprising: a cleaning atmosphere holding type transfer unit that is installed for each processing by an irradiation unit and removed after the processing. 8. In a state where the substrate is installed in a predetermined clean atmosphere determined by the formation of a thin film, an amorphous film is formed on the substrate by using a semiconductor supplied from a semiconductor supply means provided in a place outside the clean atmosphere. A thin film forming means for forming a semiconductor thin film, and a predetermined clean atmosphere determined by a physical property value measuring method using light to determine physical property values related to modification of the amorphous semiconductor thin film formed on the substrate by energy ray irradiation. Physical property value measuring means for measuring using a predetermined light source and a light receiver provided in a place outside the clean atmosphere, with the substrate placed below, for modifying properties determined from the measured physical property values An energy beam that irradiates an amorphous semiconductor with an energy beam using a predetermined energy beam source provided in a place outside the clean atmosphere in a state where the substrate is installed under a predetermined clean atmosphere determined by reforming Irradiation means, the substrate is received from the outside to form an amorphous semiconductor layer on the surface thereof, and thereafter, the thin film formation, physical property measurement, energy beam irradiation in each processing, without exposing the substrate to the external atmosphere at least in order An apparatus for manufacturing a thin film transistor, comprising: a thin-film forming means, a physical property value measuring means, and a clean atmosphere holding type transport means which is installed for each processing by an energy beam irradiation means and is removed after the processing. 9. A predetermined process determined from a process for exhibiting a good function as a transistor element, such as displacement of hydrogen from an amorphous semiconductor formed on a substrate and bonding of hydrogen to dangling bonds of a polycrystalline semiconductor. A heat treatment means for heat treating the semiconductor thin film together with the substrate in the atmosphere described above, and the clean atmosphere holding type transfer means is capable of further mounting the substrate on the heat treatment means and removing it after the treatment without exposing it to at least an external atmosphere. 8. A small heat transfer means for heat treatment.
Or a thin film transistor manufacturing apparatus according to 8. 10. A cleaning and atmosphere holding type transporting means for receiving and transferring a substrate from outside to the outside, wherein the clean atmosphere holding type transporting means has a thin film forming means, a physical property value measuring means, an energy ray A centrally located clean atmosphere holding type transporting means having a irradiating means, a carrying-in / out means or a heat treatment means in addition to them, and furthermore, the installation and removal of the substrate to and from the respective means arranged on the outer peripheral portion are smoothly performed. The physical property value measuring means is a horizontal holding type physical property measuring means for holding the substrate horizontally at the time of measuring the physical property value of the substrate. The thin film transistor manufacturing apparatus according to claim 7, wherein: 11. The thin film forming means, physical property measuring means, energy ray irradiating means or heat treatment means in addition to these means may be respectively silicon, silicon germanium as a semiconductor,
Silicon-based thin film forming means, silicon-based physical property value measuring means, silicon-based energy ray irradiating means or silicon-based heat treatment means in addition to these for at least one of silicon, germanium, and carbon. An apparatus for manufacturing a thin film transistor according to claim 7. 12. A state in which a substrate is installed in a predetermined clean atmosphere determined by the formation of a thin film, and a semiconductor supplied from semiconductor supply means provided outside the clean atmosphere is used to form an amorphous film on the substrate. A thin film forming step of forming a semiconductor thin film, and a physical property value related to the modification of the amorphous semiconductor thin film formed on the substrate by irradiation with a modification energy beam, a predetermined value determined from a physical property value measuring method using light. In a state where the substrate is placed in a clean atmosphere, a physical property value measuring step of measuring using a predetermined light source and a light receiver, and a reforming energy ray having a property determined from the measured physical property value, Energy beam irradiation for irradiating an amorphous semiconductor for reforming it using a predetermined energy ray source provided outside the clean atmosphere with the substrate installed in a predetermined clean atmosphere Step and receiving the substrate from the outside to form an amorphous semiconductor layer on its surface, and thereafter, in each step of thin film formation, physical property value measurement, energy beam irradiation, without exposing the substrate at least to the external atmosphere, A method for manufacturing a thin film transistor, comprising: a clean atmosphere holding type transporting step of performing installation required for each apparatus for forming, measuring physical properties, and irradiating energy rays, and performing removal after processing. 13. A state in which a substrate is installed in a predetermined clean atmosphere determined by the formation of a thin film, and an amorphous film is formed on the substrate by using a semiconductor supplied from semiconductor supply means provided in a place outside the clean atmosphere. A thin film forming step of forming a semiconductor thin film, and a physical property value related to the modification of the amorphous semiconductor thin film formed on the substrate by irradiation with a modification energy beam, a predetermined value determined from a physical property value measuring method using light. In a state where the substrate is installed in a clean atmosphere, a physical property value measuring step of measuring using a predetermined light source and a light receiver provided in a place outside the clean atmosphere, and a property determined from the measured physical property value The energy beam for reforming is applied to an amorphous semiconductor by using a predetermined energy ray source provided in a place outside the clean atmosphere in a state where the substrate is installed under a predetermined clean atmosphere determined by reforming. Energy beam irradiating step for irradiating the substrate, and receiving the substrate from the outside to form an amorphous semiconductor layer on its surface, and thereafter, at least performing the steps of thin film formation, physical property measurement, and energy beam irradiation, the substrate is exposed to at least It is characterized in that it has a clean atmosphere holding type transporting step for performing installation necessary for each device for the thin film formation, physical property value measurement, energy ray irradiation in order without exposing to an atmosphere, and removing after processing. A method for manufacturing a thin film transistor. 14. A predetermined process determined by a process for exhibiting a good function as a transistor element, such as a process of displacing hydrogen from an amorphous semiconductor formed on a substrate and a process of bonding hydrogen to dangling bonds of a polycrystalline semiconductor. A heat treatment step of heat-treating the semiconductor thin film together with the substrate in an atmosphere, wherein the clean atmosphere holding type transporting step does not expose the substrate to an external atmosphere at least, and further, in the heat treatment step, the substrate required for installation for an apparatus therefor; 14. The method of manufacturing a thin film transistor according to claim 12, further comprising a heat treatment small step for performing removal after the treatment. 15. A carrying-in / out step for receiving a substrate from outside and transferring it to the outside, wherein the clean atmosphere holding type carrying step includes the steps of: A central arrangement for carrying in and out a substrate to be processed between a central part and an outer peripheral part by having a device for a value measurement step, an energy beam irradiation step, a carry-in / out step, or additionally a heat treatment step. A formal clean atmosphere holding type transfer step, further comprising: a small rotation step of holding and rotating the substrate for smooth installation and removal after processing by each means of the substrate; and 4. The method according to claim 1, wherein the measuring step is a horizontal holding type physical property measuring step of measuring the physical property of the substrate while holding the substrate horizontally. Method for fabricating the thin film transistor according to any one of. 16. The thin film forming step, the physical property measuring step, the energy beam irradiating step or the heat treatment step in addition to these steps, wherein each of the semiconductor includes silicon, silicon germanium,
A silicon-based thin film forming step, a silicon-based physical property value measuring step, a silicon-based energy ray irradiation step, or a silicon-based heat treatment step in addition to these, which is directed to at least one of silicon, germanium, and carbon. A method for manufacturing a thin film transistor according to claim 12. 17. A semiconductor thin film formed on an insulating substrate and composed of a source region, a drain region, a channel region interposed between the source region and the drain region, and disposed immediately above the channel region. Top gate type including a gate electrode, a gate insulating film interposed between the channel region and the gate electrode, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region. In the thin film transistor, the gate electrode includes a first sub-gate electrode made of a high melting point metal formed on the gate insulating film, and a second sub-gate electrode made of a low resistance metal formed on the first sub-gate electrode A top gate type thin film transistor, characterized in that: 18. The top gate type thin film transistor according to claim 17, wherein the high melting point metal is molybdenum or an alloy containing molybdenum. 19. The top gate type thin film transistor according to claim 17, wherein the refractory metal is tungsten or an alloy containing tungsten. 20. The top-gate thin film transistor according to claim 17, wherein polycrystalline silicon having a high impurity concentration is used instead of said high melting point metal. 21. The thin film transistor according to claim 17, wherein the low resistance metal is aluminum or an alloy containing aluminum. 22. A first step of forming a semiconductor thin film on an insulating substrate; and a second step of forming a gate insulating film on the semiconductor thin film and forming a first sub-gate electrode on the gate insulating film. A third step of processing the first sub-gate electrode, the gate insulating film, and the semiconductor thin film into a first island shape by a first patterning process using photolithography and etching; and the first sub-gate electrode and the gate insulating film. A fourth step of processing the film into a second island shape by a second patterning process using photolithography and etching; and using the first sub-gate electrode as a mask, implanting impurities into the semiconductor thin film to thereby form a source in the semiconductor thin film. A fifth step of forming a region, a drain region and a channel region; Air connected to a source electrode, the drain region to form a drain electrically coupled electrode, a second electrically connected to the first sub-gate electrode
A method of manufacturing a top-gate thin film transistor, comprising: a sixth step of forming a sub-gate electrode. 23. The top gate type thin film transistor according to claim 22, wherein only the first sub-gate electrode is processed into a second island shape by photolithography and etching instead of the fourth step. Production method. 24. The first step comprises forming an amorphous silicon thin film on an insulating substrate, crystallizing the amorphous silicon thin film to form a crystalline silicon thin film as a semiconductor layer on the insulating substrate. 23. Forming
24. The method for manufacturing a top gate thin film transistor according to 23. 25. The semiconductor device according to claim 22, wherein the first sub-gate electrode is made of a metal having a high melting point, and the second sub-gate electrode, the source electrode and the drain electrode are both made of a low-resistance metal. 3. The method for manufacturing a top gate thin film transistor according to 1. 26. The method according to claim 22, wherein the refractory metal is molybdenum or an alloy containing molybdenum. 27. The method according to claim 22, wherein the refractory metal is tungsten or an alloy containing tungsten. 28. The method of manufacturing a top gate thin film transistor according to claim 22, wherein polycrystalline silicon having a high impurity concentration is used in place of said high melting point metal. 29. The method according to claim 22, wherein said low-resistance metal is aluminum or an alloy containing aluminum. 30. A plurality of signal lines and a plurality of control lines intersecting the signal lines are wired, and the top gate thin film transistor according to claim 1 is arranged near each intersection of the signal lines and the control lines. Each signal line is connected to the source electrode of the corresponding thin film transistor, each control line is connected to the gate electrode of the corresponding thin film transistor, and the control line and the signal line are formed on the same insulating substrate together with the thin film transistor. A top gate type thin film transistor array, wherein at least at an intersection of the control line and the signal line, the control line is formed of a four-layer laminated film of a semiconductor layer, an insulating layer, a refractory metal layer, and an interlayer insulating layer; A top gate type thin film transistor array, wherein the line is formed of a low resistance metal layer. 31. The top gate type thin film transistor array according to claim 30, wherein the high melting point metal is molybdenum or an alloy containing molybdenum. 32. The thin film transistor array according to claim 30, wherein the high melting point metal is tungsten or an alloy containing tungsten. 33. The top gate thin film transistor array according to claim 30, wherein polycrystalline silicon having a high impurity concentration is used in place of the high melting point metal. 34. The thin film transistor array according to claim 30, wherein the low resistance metal is aluminum or an alloy containing aluminum. 35. A method for forming an amorphous silicon film on a substrate by introducing a film forming gas containing at least Si element into a vacuum vessel of a plasma CVD apparatus and reacting the film forming gas by a plasma CVD method. A method for forming an amorphous silicon film, wherein the film forming gas is reacted under supply rule conditions. 36. A method for forming an amorphous silicon film on a substrate by introducing a film-forming gas containing at least Si element into a vacuum vessel of a plasma CVD apparatus and reacting the film-forming gas by a plasma CVD method. A method for forming an amorphous silicon film, comprising: diluting the film-forming gas with a gas that does not contribute to film-forming; and reacting the film-forming gas under a supply law condition. 37. The method according to claim 35, wherein the temperature of the substrate on which the amorphous silicon film is formed is set to 300 ° C. or less. 38. The film forming gas is SiH4 or Si2.
The gas containing H6 and not contributing to the film formation is at least A
The method for forming an amorphous silicon film according to any one of claims 35 to 37, wherein r is contained and the ratio of the film forming gas is 5% or less. 39. The method according to claim 38, wherein the gas that does not contribute to the film formation contains at least Ar and H ₂ . 40. A parallel-plate type plasma CVD apparatus in which a high-frequency electrode and a ground electrode are opposed to each other as the plasma CVD apparatus, wherein the frequency of a high-frequency power supply of the parallel-plate type plasma CVD apparatus is 20 MHz or more and 100 MHz.
The method for forming an amorphous silicon film according to claim 35 or 36, wherein: 41. The method for forming an amorphous silicon film according to claim 35, wherein an inductively coupled plasma CVD apparatus is used as said plasma CVD apparatus. 42. The method for forming an amorphous silicon film according to claim 35, wherein an electron cyclotron resonance type plasma CVD apparatus is used as said plasma CVD apparatus.