WO2000060647A1

WO2000060647A1 - Device having multi-layer structure, production device for the device, and production method for the device

Info

Publication number: WO2000060647A1
Application number: PCT/JP2000/002246
Authority: WO
Inventors: Makoto Yamamoto; Mikihiko Nishitani; Hikaru Nishitani; Masahiro Sakai; Masashi Goto
Original assignee: Matsushita Electric Industrial Co.,Ltd.
Priority date: 1999-04-06
Filing date: 2000-04-06
Publication date: 2000-10-12

Abstract

Two targets to be achieved during a thin-film transistor production, namely, keeping a cleanliness of an interface of an amorphous semiconductor thin film to be laminated on a substrate, and crystallizing with a high reliability an amorphous semiconductor thin film which is likely to vary in thickness between substrates. An amorphous semiconductor thin film is formed on a substrate in a clean atmosphere, physical property values relating to the crystallization of the formed thin film are measured, laser beams having features based on the measured physical property values are applied to the thin film for melt-recrystallizing, and, at the same time, substrates are carried or mounted with a clean atmosphere maintained between devices and rooms for the substrates.

Description

Description Element with multilayer structure, device for manufacturing the element, and method of manufacturing the element Technical field

The present invention relates to an element having a multilayer structure, an apparatus for manufacturing the element, and a method for manufacturing the element.

In particular, in particular, a manufacturing apparatus and a manufacturing method that can be suitably used for reforming a thin film transistor using an excimer laser or the like. About. Also, a top-gate type thin film transistor applied to an active matrix type liquid crystal display device, a sensor array, a static random access memory (SRAM), and the like. The present invention relates to a manufacturing apparatus and a manufacturing method which can be suitably applied to a transistor, a manufacturing method thereof, and a top gate type thin film transistor array. Also, the present invention relates to a method for easily forming an amorphous silicon film having a low hydrogen concentration in the film by a plasma CVD method at a low temperature. Background technology

As an example of an element having a multilayer structure, a thin film transistor (TFT, ThinlmTransissort) will be described, and the background art thereof will be described.

(First background technology and its issues)

This is especially true for thin film transistors (TFTs) with a MOS-type structure, but the major factors that affect their performance are: do it , CTJP00 / 02246

(1) Improvement of crystallinity of semiconductor (material) thin film (recovery of damage),

(2) Reduction of defects at the interface between the semiconductor thin film and the insulating film,

(3) Improvement of cleanliness at the interface between the semiconductor thin film and the insulating film,

Is mentioned.

In the process of manufacturing LSIs that use single crystal silicon for the substrate, it was basically possible to use a high-temperature process that is close to 100,000. To form polycrystalline silicon by epitaxial growth method, to recover damage by high-temperature heat treatment, or to form insulating film by thermal oxidation method. For example, methods to solve the above problems have been established.

On the other hand, in a liquid crystal display device, since a translucent glass is used for the substrate, T

It is not possible to use a high-temperature manufacturing process of 600 ° C or more to create an FT array. Therefore, methods such as plasma CVD and atmospheric pressure CVD that can form thin films at low temperatures are used for forming semiconductor thin films and insulating films.o

With the recent increase in the performance of TFTs, TFTs that use polycrystalline silicon instead of conventional amorphous silicon as semiconductor thin films have been developed. ing .

As one of the methods for forming this polycrystalline silicon, for example, strong light absorbed by a semiconductor thin film such as an excimer laser is used for a substrate. Irradiate the amorphous silicon film formed on the microcrystalline silicon film to once melt them and then crystallize or single-crystallize them. A silicon film consisting of a large or small crystal (polycrystalline silicon film), and furthermore, the defects of the formed crystal grains are removed to modify the silicon film. Quality technologies are being developed.

In addition, conventional LSIs for driving TFT arrays are called TAB (there is an IC on an adhesive tape, and the table is attached to a substrate) or COG (I (C is attached to the glass substrate) using a technology such as that described above, but the LSI is expensive and the process yield is high. As the height is not so high, instead of this mounting process, a method of directly forming a driving circuit portion such as a pixel portion on a glass substrate has been attempted.

Specifically, a semiconductor layer made of silicon is provided, and the semiconductor layer is isolated in accordance with the position of the pixels on the substrate and the driving circuit (so-called “Yuyu”). Patterning), and furthermore, at a predetermined region of the isolated semiconductor, for example, at or near a connection portion with a source electrode, a drain electrode, and a gate electrode. Injecting specific impurities such as boron (boron, B) and phosphorus (phosphorus, P) directly or through an insulating film, etc., to convert n-type and p-type semiconductors. These devices are formed on the same substrate to create MOS type semiconductor devices.

In order to obtain high-performance transistors (elements) or semiconductors (materials) therefor, as described above, it is necessary to (1) use semiconductor thin films. It is important to improve crystallinity, (2) reduce defects at the interface between the semiconductor thin film and the insulating film, and (3) improve cleanliness at the interface between the semiconductor thin film and the insulating film. There is such a problem.

When a polycrystalline silicon film is formed on a substrate and a large number of thin-film transistor elements are manufactured (formed), for example, an amorphous film is formed on the substrate by a plasma CVD method. After the amorphous silicon film is formed once, the amorphous silicon film is irradiated with laser light to convert the amorphous silicon film into a polycrystalline silicon film. This crystallization occurs because the energy of the laser light absorbed by the amorphous silicon film is converted into heat, and the temperature inside the thin film rises. This is considered to be a process in which amorphous silicon melts and crystallizes when it is solidified again.

Therefore, the characteristics (crystallinity, crystal grain size, and thus field-effect mobility, etc.) of the formed polycrystalline silicon film depend on the characteristics of the silicon film that absorbs light. Properties (The physical properties referred to here are the melting, solidification, and Properties that have an effect on the recrystallization of the material, and specifically depend on the film thickness, the atomic density, the concentration of impurities such as hydrogen contained, etc.) . Specifically, for example, the film thickness and atomic density are directly related to the heat required for melting, and if the hydrogen content is high, silicon scattering may occur, but not partially. I will.

Therefore, before irradiating a laser beam, the physical properties of each amorphous silicon film are inspected and measured in advance, and the results are based on the results. It is necessary to take measures such as optimizing the energy density of the laser light to be illuminated.

In many cases, the atomic density and the impurity concentration do not change so much if the deposition conditions are kept constant, but the film thickness directly related to melting varies within a range of several percent. You

In particular, it is necessary to optimize the energy density of the laser beam to be irradiated according to the thickness of the amorphous silicon film. In some cases, the accuracy of the order of the microclone or on-strom is required, and the film is usually discharged from the vacuum to the atmosphere once after film formation.

However, even though the measurement chamber is not cleaned with a high-performance (HEPA) filter, the amorphous silicon film is once exposed to room air. When exposed, a natural oxide film is formed on the surface of the substrate, or a contaminant in the air, especially a strong acid is used in the manufacture of a substrate on which a TFT is formed. The glass fiber in the field is eroded by the water, and the porosity in the glass fiber is contaminated. As a result, the crystallization process due to laser irradiation becomes unstable, and the polycrystalline film is mixed with pol as an unintended impurity, and the performance of the device is reduced. Or it may be degraded.

In addition, when forming a gate insulating film on the surface after forming a polycrystalline silicon film, the conventional manufacturing apparatus requires a plasma exposure after exposure to the outside air. Since the film is transferred to a CVD device to form an insulating film, an unstable natural oxide film is formed on the surface of the polycrystalline silicon film during transfer, and contamination by atmospheric impurities may occur. It will be done. For this reason, the characteristics of the semiconductor / insulating film interface are also significantly reduced from this aspect, and this is one of the causes of degrading the performance of the thin film transistor. Was.

On the other hand, as described above, in a liquid crystal display device, by forming n-type and p-type MOS transistors on the same substrate, a drive circuit and the like are formed on the same substrate as the display portion. The technology to make it is being developed. This n-type or p-type semiconductor region is formed by injecting so-called impurities (additives for exhibiting the function of a semiconductor) such as lipo-polon into a predetermined semiconductor region. . The characteristics of the n-type or p-type semiconductor region strongly depend on the concentration of these implanted impurities and the profile in the thickness direction.

Conventionally, this impurity has been implanted through the gate insulating film of silicon as a semiconductor. However, as described above, the insulating film formed by the plasma CVD method or the like varies in thickness between the substrates within a range of several percent. As a result, variations occur in the characteristics of the n-type or p-type semiconductor regions, causing variations in the characteristics of the transistor.

However, with the recent increase in the size of liquid crystal display panels and the increase in pixel density, thin-film transistors formed on glass substrates are becoming smaller and more precise. And the thickness of the polycrystalline silicon film is becoming thinner than several hundred Angstroms. Therefore, the adverse effects of surface contamination and deterioration are increasing from this aspect as well.

For this reason, the factor that degrades the performance of such a transistor is, for example, that the TFT characteristics exceed ²⁰⁰ cm ² / V'sec in the field-effect mobility. As they become more powerful, they become more critical. I came.

Therefore, this is especially true in the case of MOS-type thin film transistors manufactured by laser annealing, but the processing at each stage of manufacturing is particularly important. In this case, no impurities adhere to the thin film formed on the substrate, and as a result, the crystallinity is good, the number of interface defects is small, and the variation in characteristics is small. There was a need for the development of equipment and methods for manufacturing things.

(Second background technology and its issues)

To improve the characteristics of MOS thin film transistors (TFTs) fabricated on glass substrates, it is essential to improve the interface characteristics between the semiconductor thin film and the gate insulating film. It is.

At this point, the structure of the TFT is such that a gate electrode is formed first according to the order of lamination of electrodes and semiconductor layers, and a polycrystalline silicon is formed via a gate insulating film. A bottom gate type in which a film is formed on the upper surface, and conversely, a polycrystalline silicon film is formed first, and the upper surface is formed through a gate insulating film. The gate electrode is classified into a top gate type which forms a gate electrode. When the two are compared, miniaturization and reduction of parasitic capacitance by the cell line structure can be easily achieved from the viewpoint of the device, and the manufacturing process can be easily performed. The top-gate type, which has few restrictions on, is advantageous. Considering the top-gate type configuration, which is advantageous from the viewpoint of such devices, after the semiconductor thin film is formed, the surface is not exposed to the air and is in a high vacuum. Alternatively, it is desirable to maintain the gate insulating film in a high-purity gas atmosphere and form a gate insulating film continuously.

However, in the conventional manufacturing process, there has been a problem that the interface between the semiconductor thin film and the gate insulating film cannot be kept clean.

This will be specifically described below. A typical top gate type thin film transistor manufacturing process (referred to as the first conventional example) is shown in FIGS. 29 and 30. It is shown . In FIGS. 29 and 30, 500 is an insulating substrate, 501 is a semiconductor thin film, 502 is a gate oxide film, 503 is a gate electrode, and 504 is a semiconductor. Source region, 505 is a drain region, 506 is a channel region, 507 is an interlayer insulating film, 508 is a source electrode, and 509 is a drain. Indicates an electrode. In the first conventional example, a gate insulating film is formed on a semiconductor thin film 501 from the state shown in FIG. 29 (a) in which a semiconductor thin film 501 is formed on an insulating substrate 500. In the state shown in FIG. 29 (b) where the film 502 and the gate electrode 503 are formed, the semiconductor thin film 501 is removed from the photolithographic graph by etching. There is a process for processing islands by means of ching. As described above, when a photolithography process is performed between the semiconductor thin film forming process and the gate insulating film process, the semiconductor thin film 501 and the gate insulating film 502 are formed. Since the interface is exposed to the atmosphere, the interface between the semiconductor film and the gate insulating film cannot be kept clean.

In order to solve such a problem, a second conventional example shown in Fig. 31 has been proposed. In the second conventional example, a semiconductor thin film 501 and a gate insulating film 502 are formed continuously (FIG. 31 (a)), and then both are processed into an island shape. After the processing, a gate electrode 503 is formed (FIG. 31 (b)), whereby the interface between the semiconductor thin film 501 and the gate insulating film 502 is exposed to air. Thus, the interface between the semiconductor thin film and the gate insulating film can be kept clean without being exposed to the heat. However, in this second conventional example, as shown in FIG. 31 (b), the island-shaped slope 101a of the semiconductor thin film 501 is exposed. As a result, the desired transistor characteristics can be obtained by the electrical contact between the semiconductor thin film 501 and the gate electrode 503 on the slope 101a. A new problem has arisen. FIG. 31 is a cross section perpendicular to the cross section including the source region, the channel region, and the drain region, and including the channel region (see FIG. 30 (b) as an example). Then, the channel Figure 30 (b) shows a cross section perpendicular to the plane of the figure including the region).

Therefore, conventionally, a top gate in which the interface between the semiconductor thin film and the gate insulating film is clean and the problem of contact between the semiconductor thin film and the gate electrode does not occur. A type thin film transistor has been desired.

(Third background technology and its issues)

Thin-film transistors (hereinafter referred to as “TFTs”) for the purpose of applying cannabis and monofilaments to monitors. After the formation of the amorphous silicon film, the polysilicon film used is formed on the surface of the amorphous silicon film by a laser mask. It is formed by irradiating a laser beam by the Niel method and melting and crystallizing it.

Here, it is desired that the amorphous silicon film irradiated with the laser has a hydrogen concentration of 3 at% or less in the film. The reason for this is that when an amorphous silicon film containing a large amount of hydrogen in the film is laser-annealed, the laser irradiation causes The temperature of the polysilicon film rises rapidly, causing the hydrogen in the film to boil and the film surface to become rough, making the film unsuitable for a TFT. That's it.

The method of forming the amorphous silicon film includes a normal pressure CVD method, a reduced pressure CVD method, a plasma CVD method, and the like. Among them, the plasma CVD method is 40%. It is suitable in that processing at a low temperature of 0 ° C or less is possible. However, an amorphous silicon film formed at a substrate temperature of about 250 "C by the plasma CVD method has a hydrogen content of 10 to 20 at%. Therefore, before the crystallization is performed by irradiating the amorphous silicon film with the laser by the laser annealing method, the laser annealing method is used. In addition, a step of desorbing hydrogen from the amorphous silicon film is required, and thus, in order to simplify the manufacturing process, the above-mentioned step is required. Morphy Silicon A method for reducing the hydrogen content in a film by a plasma CVD method without performing a step of desorbing hydrogen in the film is disclosed in Japanese Patent Application Laid-Open No. Heisei 9-1134. 8 Disclosed in 8.2. In this technique, the substrate is heated to 400 ° C., and thermal energy is used to desorb hydrogen in the film.

Also, usually, formation of by that A molar off § mortal Li co down film plasmas CVD method, low-frequency power Shi sufficiently flow the S i H ₄ gas to 1 3. 5 6 MH z It is carried out under the conditions of the reaction rule. This suppresses powder generation due to the gas phase reaction, and at the same time, selectively generates SiH radicals, thereby reducing dangling ponds. This is because a non-amorphous silicon film is formed.

In this case, since the dangling ponds are terminated by hydrogen, a large amount of hydrogen is naturally contained in the film. Also, the outermost surface of the amorphous silicon film being formed is covered with hydrogen, but when the substrate temperature reaches 300 ° C or higher, the hydrogen on the outermost surface is converted to thermal energy. It is also known that desorption by energy leads to an increase in dangling ponds.

In summary, the following problems have been encountered in the past.

(1) When an amorphous silicon film is formed by a conventional plasma CVD method, when the substrate temperature, which is a general condition, is not more than 300, the amorphous silicon film is formed. Since the fluorine-containing silicon film may contain 10 to 20% of hydrogen, a step of desorbing hydrogen from the film is required.

(2) Also, as in the technology disclosed in Japanese Patent Application No. 9-1134882, the substrate temperature is heated to about 400 ° C to highly dilute the raw material gas. In this case, an amorphous silicon film having a low hydrogen content is obtained, and the step of desorbing hydrogen in the film is not required. The problem of low crystal silicon crystallinity and low slew rate There is. When the amorphous silicon film is microcrystallized, the microcrystallized film must be remelted by a laser anneal, and accordingly, As a result, higher energy is required than when laser annealing a film in an amorphous state, and the manufacturing efficiency is reduced. Disclosure of the invention

The first purpose of the present invention is to make it possible to manufacture a thin film transistor having a MOS type structure in a clean atmosphere by adapting to the conditions for forming an amorphous semiconductor film. This is what we did.

The purpose of the second invention group is to overcome the above-mentioned problems of the prior art, to clean the interface between the semiconductor thin film and the gate insulating film, and to solve the problem of contact between the semiconductor thin film and the gate electrode. An object of the present invention is to provide a top gate type thin film transistor which does not occur and a method for manufacturing the same.

Another object of the second invention group is to reduce the resistance of the wiring (especially, the signal line) and to carry out the thin film transistor suitably for a large liquid crystal panel or the like. This is to provide a language evening array.

The purpose of the third invention group is to make use of efficiently generated high energy particles so that even if the substrate temperature is low, the amorphous silicon is used. An object of the present invention is to provide a method of forming an amorphous silicon film which can reduce the hydrogen content in the film.

In order to achieve the above object, the invention according to claim 1 of the present invention relates to a method for manufacturing an element having a multilayer structure by a plurality of film forming steps. One of a plurality of film forming steps, wherein at least one film is formed by a first film forming step and a first film forming step is obtained by the first film forming step. Measuring the specified physical properties of the film, and processing the film according to the measurement conditions determined based on the measurement results in the measurement process. And wherein the first step, the measuring step, and the second step are each performed in a predetermined clean atmosphere.

According to the above configuration, even if there is a variation in the film thickness or the like in the first film forming step, the processing in the second step in consideration of the variation is not performed. It will be done. Therefore, the second process is performed under optimal conditions, and in addition, the first process, the measurement process, and the second process are performed in a clean atmosphere. As a result, it is possible to manufacture a device having a multilayer structure with improved quality.

Examples of the element having a multilayer structure include a semiconductor element such as TFT, a semiconductor element having an LDD (Lightly Doped Drain) structure, and an element having an optical multilayer film. For example, in the case of a TFT semiconductor device, the first step is a process of forming an amorphous silicon film, and the second step is a polysilicon process. This is applicable to the reforming treatment of the membrane. In the case of a semiconductor device having an LDD structure, the first step is a first ion implantation process for manufacturing an LDD structure, and the second step is a process for manufacturing an LDD structure. The second ion injection process is applicable. In the case of an element having an optical multilayer film, the first step corresponds to the first film formation processing, and the second step corresponds to the second film formation processing. You

The invention according to claim 2 is the method for manufacturing a device having a multilayer structure according to claim 1, wherein the process in the second step is a film forming process. And

According to a third aspect of the present invention, in the method for manufacturing an element having a multilayer structure according to the first aspect, the process in the second step is a film reforming process. It is characterized by

The invention according to claim 4 is an apparatus for manufacturing an element having a multilayer structure, and a film forming means for forming at least one of a plurality of films, Means for measuring predetermined physical properties of the film obtained by the film forming means, and processing of the film in accordance with measurement conditions determined based on the measurement results of the measuring means And a transport means for transporting the film forming means, the measuring means, and the processing means to each other, wherein the film forming means, the measuring means, and the processing means are provided. , And the transport means are characterized in that the respective processes are performed under a predetermined clean atmosphere.

As described above, since the processing of the processing means is performed based on the measurement result of the measuring means, the processing can be performed with high accuracy. Furthermore, since the treatment by each means is performed in a clean atmosphere, a high-quality element can be obtained.

According to a fifth aspect of the present invention, in the apparatus for manufacturing an element having a multilayer structure according to the fourth aspect, the processing in the processing means is a film forming processing. .

According to a sixth aspect of the present invention, in the apparatus for manufacturing an element having a multilayer structure according to the fourth aspect, the processing in the processing means is a film reforming processing. And

The invention according to claim 7 or claim 8 is a method in which the substrate is placed in a predetermined clean atmosphere determined from the formation of the thin film, for example, at room temperature or under reduced pressure of hydrogen. Semiconductors supplied from semiconductor supply means installed in a place outside the clean atmosphere or in a place with a clean atmosphere (more precisely, the raw material gas) are used on the substrate. Thin film forming means for forming a crystalline semiconductor thin film, and physical properties related to modification (melting, crystallization, etc.) of the amorphous semiconductor thin film formed on the substrate by irradiation with energy rays. For example, the substrate was placed in a predetermined clean atmosphere, for example, room temperature or vacuum, determined by a physical property measurement method using light (including ultraviolet rays and infrared rays). In a state where it is located outside the clean atmosphere, Sources (including, Les laser light (source)) and the property value measurement means you measured using the light receiving device, measuring The physical properties of Jo Luo or Ru nature modifying et, channel ghee line, eg if 3 0 0 m J / cm ² of d, channel ghee density 3 0 0 H z of d key sheet Ma les monodentate (1) an amorphous semi-conductor; an energy beam irradiating means for irradiating the conductor for its modification; and (3) receiving the substrate from the outside to form an amorphous semiconductor layer on its surface. Thereafter, the substrate is not exposed to the external atmosphere at least in each of the processes of forming a thin film, measuring physical properties, and irradiating with energy rays, and the thin film forming means, the physical property measuring means, and the energy It is characterized in that it is properly mounted on the ruby ray irradiation means, and has a clean atmosphere holding type transfer means to be removed after the treatment.

According to the above configuration, the following operation is performed.

The thin film forming means is, in a state where the substrate is horizontally set in a predetermined clean atmosphere determined by the thin film formation, and in principle, using a mask over the entire surface of the substrate, in some cases. Only at the predetermined position, the amorphous semiconductor thin film is formed by using a semiconductor supplied from a semiconductor supply means provided in a room kept in the clean atmosphere or a place outside the apparatus. It is formed by evening rings.

The physical property value measuring means measures physical property values such as density and film thickness related to modification of the amorphous semiconductor thin film formed on the substrate by irradiation with energy rays, and uses a laser beam. When the substrate is installed horizontally in a predetermined clean atmosphere, for example, at room temperature and in a vacuum, determined from the physical property measurement using the laser, the substrate is installed outside the measurement atmosphere. Measure using a laser source or L / E converter.

Enel ghee beam irradiation means, E Ne-saving clear distinction of the measured physical property value or Jo Luo or Ru nature, if example embodiment 3 0 0 m J / ^cm: example d key sheet Ma, single The first light of e For example, an optical system is used to form a beam, and an amorphous semiconductor patterned as necessary on a substrate held in a predetermined state in a predetermined atmosphere is used. Then, this beam is irradiated while scanning the substrate in order. A so-called clean-atmosphere-holding transporting device having a so-called port arm, push-out machine, motor, etc., forms a thin-film polycrystalline semiconductor layer on its surface. The substrate is received directly or indirectly from the outside via an intermediary means, and the substrate is contaminated at least in the subsequent processes of thin film formation, physical property measurement, and energy beam irradiation. In order to perform each of the treatments by the thin film forming means, physical property values, measuring means, and energy beam irradiation means in order while maintaining an appropriate atmosphere without exposing to an external atmosphere. Install and remove after processing. (Of course, after the previous processing is completed, it may be installed in the equipment for the next processing.) Therefore, if necessary, the work room for these processings It will be transported inside and unloaded after processing.

In addition, each of the above-mentioned means performs necessary exhaust and decompression of the room or space where the substrate is installed, and fills with an inert gas or hydrogen gas.

Further, the thin-film transistor manufacturing apparatus also has a means such as a silicon thin-film notating as necessary.

According to the ninth aspect of the present invention, hydrogen is expelled from the amorphous semiconductor formed on the substrate, and the hydrogen is similarly expelled to the dangling ponds of the polycrystalline semiconductor. A predetermined atmosphere determined by heat treatment to achieve good function as a transistor, such as hydrogen bonding, for example, in a nitrogen atmosphere at 1 atm. A heat treatment method in which a semiconductor thin film is held for a certain period of time at a temperature of 0 ° C (in the case of the latter, at 350 ° C in H ₂ ) for each substrate (including a plurality of substrates simultaneously). The clean atmosphere holding type transfer means does not expose to the external atmosphere at least after the previous processing such as the formation of the amorphous semiconductor thin film, and further mounts the substrate on the heat treatment means. And heat treatment that can be removed (unloaded) after the heat treatment. That features a and this you are have a transport small means.

According to the above configuration, the following operation is performed. The heat treatment means has a heater, a predetermined atmosphere gas filling and exhaust means, etc., thereby purging hydrogen from the amorphous semiconductor formed on the substrate. Predetermined atmosphere determined by heat treatment to achieve good function as a transistor element, such as bonding of hydrogen to the dangling band of a polycrystalline semiconductor. The semiconductor thin film is heat-treated by holding the semiconductor thin film for each substrate for a predetermined time.

The transfer means for heat treatment of the clean atmosphere holding type transfer means should not be exposed to the external atmosphere at least, and at least one (including, if necessary, a plurality of) substrates to the heat treatment means. Installation and removal after heat treatment are possible.

According to the invention as set forth in claim 10 or 11, there is provided a device for forming a thin film transistor on a given substrate, for example, a device for cleaning a substrate or a device for manufacturing a thin film transistor. It has a loading / unloading means for receiving the substrate as a target of processing to form a semiconductor thin film and passing the processed substrate to the outside. At the outer periphery, at least a thin film forming means, a physical property measuring means, an energy beam irradiating means, a carrying-in / out means or a heat treatment means in addition to these are provided. This is a clean atmosphere holding type transfer means, and holds the board to facilitate the installation and removal of the board to and from each means arranged on the outer periphery. A rotatable-type conveying small means rotatable and rotatable, and the physical property value measuring means Is characterized in that it is a horizontal holding type physical property measuring means for accurately holding the board horizontally when measuring the physical property values of the above-mentioned board.

According to the above configuration, the following operation is performed.

The loading / unloading means, which has a gate valve and, if necessary, a vacuum pump, is used to receive a substrate for forming a semiconductor thin film on its surface from the outside of the device. The formation of semiconductor thin films and the accompanying processing, or furthermore The substrate after forming a transistor as an element is transferred to the outside.

The clean atmosphere holding type transport means is a center-position type clean atmosphere holding type transport means.Thus, the thin film forming means and physical property value measurement are performed through a partition door or the like as necessary on the outer periphery of the conveyer. Means, energy beam irradiation means, loading / unloading means or, in addition to these, heat treatment means (and the room where the substrate is installed as a part of the means for that purpose) ).

In addition, due to such an arrangement, a viewing window, a window through which light beams for processing pass, and other valves will be installed on the side walls that do not face the transfer chamber of each room. It will be easier to kick.

Furthermore, insulation between the rooms is also facilitated by the presence of air between them. Next, the rotatable transfer sub-means installs or removes a substrate in each means for each processing, or in a room for the processing. The arm, push-out and pull-out mechanism and magic hand for this purpose are structured so that they rotate while holding the substrate. Thus, unlike the linear arrangement type, the convergence during processing by each means and apparatus of a plurality of substrates is reduced.

Also, since the physical property value measuring means is a mechanism that holds the board horizontally and accurately when measuring the physical property value of the board, it is necessary to attach the device itself, mount the board, Furthermore, the measurement itself becomes easier.

In the invention according to claims 12 to 14, the thin film forming means, the physical property measuring means, the energy beam irradiating means or the heat treatment means in addition to the thin film forming means, the physical property measuring means, the energy beam irradiating means, etc. Amorphous or ultrafine crystalline silicon (formed in principle on a non-alkali glass substrate), silicon 'germanium, silicon '' Silicon-based thin film forming means, silicon-based physical property value measuring means, silicon, targeting at least one of the germanium-carbon layers It is characterized in that it is a means for irradiating energy rays for energy systems, particularly a means for melting and recrystallization, or a heat treatment means for silicon systems in addition to these. . -With the above configuration, the following operations are performed.

The thin film forming means, the physical property measuring means, the energy beam irradiating means or the heat treatment means in addition thereto may be a silicon based thin film forming means, a silicon based physical property measuring means, a silicon based Energy irradiation means for the silicon system or heat treatment means for the silicon system in addition to these, each of which is made of silicon or silicon as a semiconductor 'Germanium, silicon' Exhibits functions such as forming at least one of germanium and carbon on a substrate.

In the inventions of claims 15 to 22, the same operations as those of the inventions of claims 7 to 14 are performed, and the effects are obtained. The invention according to claim 23 of the second invention is formed on an insulating substrate, and includes a source region, a drain region, a source region, and a drain. A semiconductor thin film composed of a channel region interposed between the regions, a gate electrode disposed immediately above the channel region, a channel region and the gate region; A gate insulating film interposed between the source electrodes, a source electrode electrically connected to the source region, and a drain electrically connected to the drain region. In a top gate type thin film transistor provided with a gate electrode, the gate electrode is made of a high melting point metal formed on the gate insulating film. A second electrode made of a low-resistance metal formed on the first electrode; and a second electrode made of a low-resistance metal formed on the first electrode. It characterized and this that is whether we structure a gate electrode.

As described above, the gate electrode has a two-layer structure of the first sub-gate electrode and the second sub-gate electrode, so that the semiconductor thin film and the gate insulating film are formed. Continuous film formation is possible, and a top-gate type thin film transistor having high performance and high reliability is configured.

In addition, the first sub-gate electrode is made of a high melting point metal and the second sub-gate electrode is made of a low-resistance metal, so that the gate caused by heat treatment for activation or the like can be obtained. Since the electrode is prevented from being dissolved, the reliability of the top gate type thin film transistor is improved.

The invention according to claim 24 is the top gate thin film transistor according to claim 23, wherein the refractory metal is molybdenum or molybdenum. It is characterized by being an alloy containing iron.

By using the high melting point metal as molybdenum or an alloy containing molybdenum, good transistor performance can be obtained.

According to a twenty-fifth aspect of the present invention, in the top gate thin film transistor according to the twenty-third aspect, the refractory metal is a tungsten or a tan. It is characterized by being an alloy containing dust.

By using the refractory metal as a tungsten or an alloy containing a tungsten, good transistor performance can be obtained.

An invention according to claim 26 is the top gate thin film transistor according to claim 23, wherein a polycrystalline silicon having a high impurity concentration is used instead of the refractory metal. It is characterized by the use of

The invention according to claim 27 is the top gate type thin film transistor according to claim 23, wherein the low-resistance metal is made of aluminum or aluminum. It is characterized by being an alloy containing aluminum.

Good transistor performance can be obtained by using low-resistance metal as aluminum or an alloy containing aluminum.

The invention according to claim 28 is a method of manufacturing a top gate type thin film transistor, wherein a first step of forming a semiconductor thin film on an insulating substrate is provided. A second step of forming a gate insulating film on the semiconductor thin film and forming a first subgate electrode on the gate insulating film; and a first step of forming a first subgate electrode on the gate insulating film. The first electrode, the gate insulating film, and the semiconductor thin film are subjected to a first notching process by photolithography and etching to form a first electrode. The third step of processing into an island shape, and the first subgate electrode and the gate insulating film are formed by photographing and etching. A fourth step for processing into a second island shape by a second, turning process, and the semiconductor thin film, wherein the first subgate electrode is used as a mask. By implanting impurities into the semiconductor thin film, a source region, a drain region, and a channel region are formed in the semiconductor thin film. Forming a fifth step, a source electrode electrically connected to the source region, and a drain electrode electrically connected to the drain region. And a sixth step of forming a second sub-gate electrode electrically connected to the first sub-gate electrode.

According to the above manufacturing method, the interface between the semiconductor thin film and the gate insulating film is manufactured continuously. Further, the island-shaped sloped surface of the semiconductor film and the second gate electrode are insulated from each other by the inter-layer insulating film, and thus do not come into contact with each other. Accordingly, it is possible to manufacture a top gate type thin film transistor having improved transistor characteristics.

An invention according to claim 29 is a method for manufacturing a top gate thin film transistor according to claim 28, wherein the fourth step is replaced with a photo transistor instead of the fourth step. In the lithography and the etching, only the first subgate electrode is processed into a second island shape.

According to the above-described manufacturing method, ion implantation is performed through the gate insulating film, so that the island-shaped sloped surface of the semiconductor thin film is not contaminated by impurities during ion implantation. It's good, it's good. The invention according to claim 30 or 31 is directed to a method of manufacturing a top gate type thin film transistor according to claim 28 or 29, wherein the first step is performed. Forming an amorphous silicon thin film on an insulating substrate, crystallizing the amorphous silicon thin film, and insulating the crystalline silicon thin film as a semiconductor layer. It is characterized in that it is formed on a conductive substrate.

As described above, when a crystalline silicon thin film is used as a semiconductor layer, a TFT having good mobility and other characteristics can be manufactured.

An invention according to claim 32 is a method for manufacturing a top-gate thin film transistor according to claim 28, wherein the first subgate electrode is a high melting point metal. Wherein the second sub-gate electrode, the source electrode, and the drain electrode are both made of a low-resistance metal.

According to the above-described manufacturing method, the first subgate electrode functions as a metal mask at the time of ion implantation for impurity implantation. In addition, since the first subgate electrode is made of a high melting point metal, partial melting of the first subgate electrode due to heat generated at the time of ion implantation is prevented. As a result, no impurity contamination occurs in the channel region. Further, the temperature of the activation treatment after the implantation can be set high within a range not higher than the heat-resistant temperature of the glass substrate.

The invention according to claim 33 is the method for manufacturing a top gate thin film transistor according to claim 28, wherein the refractory metal is molybdenum or molybdenum. It is characterized by being an alloy containing molybdenum.

The invention according to claim 34, in the method for manufacturing a top gate thin film transistor according to claim 28, wherein the refractory metal is a tungsten. Is characterized by being an alloy containing tungsten. The invention according to claim 35 provides a method of manufacturing a top gate type thin film transistor according to claim 28, wherein the high-melting-point metal is replaced by a metal. It is characterized by the use of polycrystalline silicon with a high purity.

As described above, when the impurity concentration is high, the resistance becomes low, so that a thin-film transistor having excellent characteristics can be manufactured. In addition, in the case of this configuration, when impurities are implanted into the source / drain region, the impurities can be implanted into the polycrystalline silicon as the gate electrode at the same time. It will be easier.

The invention according to claim 36 is the method for manufacturing a top gate thin film transistor according to claim 28, wherein the low-resistance metal is aluminum. Is characterized by being an alloy containing aluminum. In the invention according to claim 37, a plurality of signal lines and a plurality of control lines crossing the signal lines are wired, and each of the plurality of signal lines is arranged near each intersection of the signal lines and the control lines. Each of the signal lines is connected to the corresponding thin-film transistor source electrode, and each control line is connected to the corresponding thin-film transistor. A top gate type structure in which the control lines and signal lines are connected to the gate electrode of the transistor and the control line and the signal line are formed on the same insulating substrate together with the thin film transistor. In a thin film transistor array, at least at the intersection of the control line and the signal line, the control line is formed of a semiconductor layer, an insulating layer, a high melting point metal layer, and an inter-layer. The signal line is made of a four-layer laminated film of an insulating layer, and the signal line is made of a low-resistance metal layer. It shall be the feature. With the above structure, all signal lines requiring a lower resistance are substantially wired with a low-resistance metal without losing continuity between the semiconductor layer of the TFT portion and the gate insulating layer. In addition, since the control lines are also wired with a low-resistance metal except at the intersections with the signal lines, they are preferable as a large-sized and high-definition TFT array. Even if the low-resistance metal is a material having a low melting point, it may be formed only after the activation of impurity ions after ion implantation, so that the heating temperature during activation is low. This is an optimal configuration that relaxes the upper limit. An invention according to claim 38 is the top gate type thin film transistor array according to claim 37, wherein the refractory metal is molybdenum. Is characterized by being an alloy containing molybdenum.

The invention according to claim 39 is the top gate thin film transistor array according to claim 37, wherein the refractory metal is a tungsten or a tungsten alloy. It is characterized by being an alloy containing tungsten.

According to a 40th aspect of the present invention, there is provided a top gate type thin film transistor transistor array according to the 37th aspect, wherein a polycrystalline material having a high impurity concentration is used in place of the refractory metal. It is characterized by the use of silicon.

In the invention according to claim 41, in the top gate thin film transistor array according to claim 37, the low-resistance metal is aluminum. Or an alloy containing aluminum.

The third group of inventions has been completed based on the following detailed examination by the present inventors.

That is, the hydrogen on the outermost surface of the amorphous silicon film is not only absorbed by the thermal energy from the substrate, but also by the physicochemical energy from the high energy particles in the plasma. It has been newly found that desorption can be performed by energy. As a means for efficiently generating high energy particles in plasma, the frequency of the high frequency power supply is higher than the normal 13.56 MHz (for example, 2 MHz). 7.12 MHz) or using low-pressure, high-density plasma (for example, inductively coupled plasmas or electron cyclotron resonance plasmas). . Therefore, even if the substrate temperature is low, the hydrogen content in the amorphous silicon film can be improved even if the substrate temperature is low by using the efficiently generated high energy particles. It is possible to reduce the amount. Based on the above considerations, a third invention group has been made. The specific configuration is as follows. According to the invention of claim 42, a film forming gas containing at least Si element is introduced into a vacuum vessel of a plasma CVD apparatus, and the film forming gas is subjected to a plasma CVD method. A method of forming an amorphous silicon film on a substrate, wherein the film forming gas is reacted under supply rule conditions. .

According to the invention of claim 43, at least a film forming gas containing at least Si element is introduced into a vacuum vessel of a plasma CVD apparatus, and the film forming gas is subjected to a plasma CVD method. In the method of forming an amorphous silicon film on a substrate by reacting with each other, the film forming gas is diluted with a gas that does not contribute to the film formation. It is characterized by reacting gas under supply rule conditions.

By diluting the film forming gas with a gas that does not contribute to the film formation, a polymerization reaction in the gas phase under a plasma atmosphere can be suppressed, and the film forming speed is restricted. Due to the regulated supply law condition (supply law region), the decomposition of the film forming gas is promoted and the high energy particles are increased in the plasma. . Therefore, the physical surface of the high-energy particles with respect to the film surface activates the film-forming outermost surface during the film formation and removes hydrogen from the film surface. Separation can be promoted. In this way, an amorphous silicon film having a low hydrogen concentration in the film can be formed, and the conventional amorphous silicon film can be formed. This eliminates the need for performing a step of desorbing hydrogen from the film, thereby improving production efficiency.

The invention according to claim 44 or 45 is characterized in that the temperature of the substrate forming the amorphous silicon film is 300 ° C. or less.

When the substrate temperature becomes higher than 300 ° C, hydrogen on the surface of the amorphous silicon film is desorbed by the thermal energy, and the hydrogen concentration in the film is reduced. Although reduced, the amorphous silicon film is microcrystallized, and the throughput is reduced. Is reduced. However, according to the above method, an amorphous silicon film is formed at a temperature of 300 ° C. or less, so that the amorphous silicon film is finely formed. It does not crystallize, does not reduce throughput, and therefore does not reduce production efficiency. Also, since an amorphous silicon film is formed on the substrate at 300 ° C or lower, it is possible to use a material with low heat resistance as the substrate. Wear . The lower limit of the substrate temperature is room temperature (about 25 ° C.) in consideration of an actual manufacturing process.

The invention of claim 4 6-4 9 wherein, in Tsu Oh in A molar off § mortal Li co down film formation method, the film forming gas S i H ₄ or the S i ₂ H beta The gas that does not contribute to the film formation contains at least Ar, and the ratio of the gas for film formation is 5% or less.

Wherein the S i H ₄ or Ru Oh in the film forming gas is 5% or less concentration of S i ₂ Η _β, and this you increase the concentration of Oh Ru A r gas you do not want to contribute to the film formation and One by the, reduces the deposition rate of the a molar off § mortal Li co-down film, or, excited in the bra's Ma a r and S i H ₂ La di mosquito Lumpur and S i Since high energy particles such as H radicals increase, hydrogen present on the outermost surface during the formation of the amorphous silicon film is caused by the high energy particles. It is desorbed by a physicochemical reaction (providing the kinetic energy and internal energy of the high energy particles to the film surface), and the hydrogen concentration in the film is 3 at% or less. A silicon film can be formed. Therefore, it is not necessary to perform a step of desorbing hydrogen in the amorphous silicon film as in the conventional case, and the production efficiency is improved.

In addition, the above-mentioned Ar is a gas in the inert gas, in particular, a gas in which the state of energy tends to become high in the plasma, and accordingly, the amorphous gas is used. Hydrogen present on the outermost surface during the formation of the silicon film is desorbed by the physicochemical reaction by the Ar. The invention according to claim 50 or 51 is characterized in that the gas that does not contribute to the film formation contains at least Ar and H 2.

According to the above method, hydrogen atoms and Η +, which have become high energy particles in the plasma, reach the surface of the amorphous silicon film, and It is thought that the Si—Η bond existing on the outermost surface during the formation of the ruf-silicon film is cleaved and becomes a hydrogen molecule and is desorbed from the film surface. Therefore, the hydrogen concentration in the amorphous silicon film can be further reduced.

The invention according to claim 52 or 53 uses a parallel plate type plasma CVD device in which a high frequency electrode and a ground electrode are arranged to face each other as a plasma CVD device, wherein the parallel plate type plasma CVD device is used. The device is characterized in that the frequency of the high-frequency power supply of the device is set to 20 MHz or more and 100 MHz or less.

As in the above method, the frequency of the high-frequency power source is set higher than the normal 13.56 MHz in the vacuum vessel of the parallel plate type plasma CVD apparatus, so that plasma can be generated. Therefore, high energy particles can be efficiently generated, and the physicochemical reaction caused by the high energy particles can reduce the number of high-energy particles on the substrate. The hydrogen concentration in the silicon film can be reduced.

Specifically, the frequency of the high-frequency power supply of the plasma CVD apparatus is set to be 20 MHz or more and 100 MHz or less, and the frequency of the high-frequency power supply is set to be higher than the normal 13.56 MHz. As a result, the plasma density is increased, and high-energy particles in the plasma can be efficiently generated. In the region where the frequency of the high-frequency power supply is lower than 20 MHz, high-energy particles are not efficiently generated, and the frequency of the high-frequency power supply is lower than 100 MHz. In a higher region, the dischargeable range is narrow, and the device configuration Restrictions are increased. Therefore, the power supply frequency of the high-frequency power supply is not less than 20 MHz and not more than 100 MHz. Preferably, the high frequency power supply has a frequency of 27.12 MHz.

The invention according to claim 54 or 55 is characterized in that an inductively coupled plasma CVD device is used as the plasma CVD device.

Even with the use of the inductively coupled plasma CVD apparatus, high energy particles can be efficiently generated in plasma, and the physical properties of the high energy single particles on the film surface can be improved. The chemical energy can reduce the hydrogen concentration in the amorphous silicon film.

The invention according to claim 56 or 57 is characterized in that an electron cyclotron resonance type plasma CVD device is used as the plasma CVD device.

Similarly, even when the electron cyclotron resonance type plasma CVD apparatus is used, high energy particles can be efficiently generated in the plasma. The hydrogen concentration in the silicon film can be reduced. Brief explanation of drawings

FIG. 1 is a diagram showing a schematic configuration of a thin-film transistor manufacturing apparatus according to Embodiment 11;

FIG. 2 is a block diagram showing an electric configuration of a thin-film transistor manufacturing apparatus according to Embodiment 1-1.

FIG. 3 is a diagram showing an example of a configuration of a measurement chamber of the thin-film transistor manufacturing apparatus according to Embodiment 11-11.

FIG. 4 is a diagram showing another example of the configuration of the measurement chamber of the thin-film transistor manufacturing apparatus according to the embodiment 11; FIG. 5 shows changes in the cross-section and configuration of the substrate and the transistor as the processing progresses in the thin-film transistor manufacturing apparatus and method according to Embodiment 11-11. FIG.

FIG. 6 shows a change in a substrate, a cross-section of a transistor, and a configuration as the processing in the thin-film transistor manufacturing apparatus and method according to the embodiment 1-1 proceeds. It is a figure.

FIG. 7 is a diagram showing a schematic configuration of a thin-film transistor manufacturing apparatus according to the first to eleventh embodiments.

FIG. 8 is a sectional view showing the structure of the top gate type TFT according to the embodiment 2-1.

FIG. 9 is a cross-sectional view showing a manufacturing process of the top gate type TFT according to the embodiment 2-1.

FIG. 10 is a cross-sectional view showing a manufacturing step of the top gate type TFT according to the embodiment 2-1.

FIG. 11 is a plan view showing a manufacturing process of the top gate type TFT according to the embodiment 2-1.

FIG. 12 is a plan view showing a manufacturing process of the top gate type TFT according to the embodiment 2-1.

FIG. 13 is a cross-sectional view showing a manufacturing process of the top gate type TFT according to the embodiment 2-2.

FIG. 14 is a cross-sectional view showing a manufacturing step of the top gate type TFT according to the embodiment 2-2.

Figure 15 is a cross-sectional view showing the end surfaces A and B of the gate electrode and the gate insulating film.

FIG. 16 is a cross-sectional view showing a manufacturing process of a CM0S-TFT using the thin-film transistor according to Embodiment 2-3. FIG. 17 shows a CM using the thin-film transistor according to the second to third embodiments.

FIG. 3 is a cross-sectional view showing a manufacturing process of OS—TFT.

FIG. 1.8 is a cross-sectional view showing a manufacturing process of CMSOTSFT using the thin-film transistor according to Embodiment 2-4.

FIG. 19 is a cross-sectional view showing a manufacturing process of CMOS-TFT using the thin-film transistor according to Embodiments 2-5.

FIG. 20 is a circuit diagram showing a configuration of a TFT array composed of thin-film transistors according to Embodiments 2-5.

FIG. 21 is a cross-sectional view of a signal line 15 5 (control line 15 6) in Embodiment 2-5.

FIG. 22 is a cross-sectional view of an intersection of a signal line 15 5 and a control line 15 6 in Embodiment 2-5.

FIG. 23 is a cross-sectional view showing a manufacturing process of the TFT array according to Embodiment 2-5.

FIG. 24 is a cross-sectional view showing a manufacturing process of the TFT array according to Embodiment 2-5.

FIG. 25 is a schematic diagram showing the configuration of a parallel plate type plasma CVD apparatus used in the method according to Embodiment 3-1.

FIG. 26 is a graph showing the relationship between the concentration of SiH 4 and the concentration of hydrogen in the amorphous silicon film.

Figure 27 is a graph showing the relationship between the RF power and the deposition rate of the amorphous silicon film.

Figure 28 is a graph showing the relationship between the RF power and the hydrogen concentration in the amorphous silicon film.

FIG. 29 is a cross-sectional view showing a manufacturing process of the first conventional example.

FIG. 30 is a cross-sectional view showing a manufacturing process of the first conventional example. FIG. 31 is a cross-sectional view showing a manufacturing process of the second conventional example.

BEST MODE FOR CARRYING OUT THE INVENTION

[First invention group]

The first invention relates to a thin film transistor manufacturing apparatus and manufacturing method, particularly to the reforming of a thin film transistor using an excimer laser or the like. About.

(Embodiment 11)

FIG. 1 is an overall configuration diagram of an apparatus for manufacturing a thin film transistor according to Embodiment 11; FIG. 2 is a thin film transistor according to Embodiment 11; FIG. 2 is a block diagram showing an electrical configuration of the manufacturing apparatus of FIG. In addition, in Fig. 1, the valve V for supplying and shutting off gas and the pump P for forced exhaust are shown only for the room 7; The other chambers 1, 2, 3, 4, 5, and 6 are also provided with similar valves, valves V and pumps P, respectively.

As shown in Fig. 1, this manufacturing apparatus was equipped with a transport roller for transporting the substrate, a push-out device, and a mouth port 10 having a gripping hand at the center. Transport room 1 is installed.

The transfer chamber 1 has a structure in which six chambers 2 to 7 can be attached around the transfer chamber 1 via gates 92 to 97. In addition, the mouth port 10 is on a motor-equipped base (not shown), and is rotated in the direction of the room for each processing by the rotation of the motor. It is capable of combing, that is, rotatable. As a result, it is possible to simultaneously process different substrates in each room, and to simultaneously process a plurality of substrates in the present manufacturing apparatus.

In addition, each of the chambers 2 to 7 has a function of exhausting at least the internal air to reduce the pressure, and the processing performed in that room depends on the processing. It has a function to introduce a specific gas from the outside of the room and exhaust it, and also to transfer the gas from the transfer room 1 to the gate 1 through the gate pulp 92-97. The substrate (not shown) carried in by the processing unit 0 is processed under predetermined or unique conditions in each of the chambers 2 to 7, and is again transferred to the transfer chamber 1 in cooperation with the robot 10. It has a function to carry it out.

The loading / unloading chamber 2 takes in the substrate to be processed by this equipment from the outside and reduces its atmosphere from the atmosphere, or depressurizes the atmosphere of the substrate that has been processed by this equipment. It has the function of returning from the state to the indoor air and filling with nitrogen. For this purpose, it is connected to pump P, valve V, and various gas supply mechanisms. The pump P, the valve V, and the various gas supply mechanisms are provided separately in the chambers 1, 3 to 7 other than the loading / unloading chamber 2.

The two film forming chambers 3 and 4 are connected to a source (gas) supply source outside of the room via a valve V, so that the chamber can be connected to the outside by a plasma CVD method. It functions as a facility and a room for forming an amorphous silicon-microcrystalline silicon film on a substrate or a silicon dioxide film or the like as an insulating film. The deposition methods used in the deposition chambers 3 and 4 are not limited to the plasma CVD method, but must be connected to necessary equipment. It is also possible to use an ECR plasma CVD method, a remote plasma CVD method, or a snow ring ring method.

The laser chamber 5 has a quartz window (not shown) on the upper surface through which laser light from the outside can be introduced, and the reforming chamber brought into the room. The substrate on which the amorphous semiconductor thin film is to be irradiated for this purpose is held horizontally, and is determined by the processing conditions such as the density of the laser-energy. It has a function to move at a predetermined speed.

The laser light is used for laser reforming (melting, crystallization) for outdoor use. After the light is emitted from the device 11 under the specified intensity and oscillation conditions, the specified energy density and beam shape is obtained by the optical system 12 having a lens, slit, etc. Is adjusted to As the board moves along a predetermined program, the beam sequentially scans the board surface installed in the laser annealing chamber. Each time the entire surface is illuminated.

Further, in some cases, the laser is irradiated only in a specific area without moving the substrate.

The heat treatment chamber 6 has a function to heat-treat the substrate, or more precisely, each thin film formed on its surface at a predetermined temperature and atmosphere. For this reason, the side wall surface is insulated. The heat treatment chamber 6 has an electric heater for heat treatment.

In addition, the measurement chamber 7 measures predetermined physical properties such as the density of the substrate itself in order to increase the accuracy of the amorphous semiconductor thin film formed on the substrate. According to the contents, there is a means to measure during depressurization or in a predetermined atmosphere. For this reason, considering the maintenance and maintenance, etc., the structure is matched to the laser-oscillator and the receiver installed outside the room, for example, quartz for laser light introduction and derivation. It has a window, etc., and has a function to hold the substrate accurately and horizontally to further improve the measurement accuracy. The details of the processing performed in each room when manufacturing a transistor are described.

First, the description of the so-called well-known techniques such as the formation of a thin film made of amorphous silicon on a substrate is omitted, and the description of the content is omitted. Explains the indoor processing unique to the installation.

Specifically, first, the measured values of the physical properties in the measurement room 7 will be described. There are several methods for measuring the physical properties provided in the measurement chamber 7, and FIG. 3 shows an example. In this device, the thin glass (transparent by nature) substrate 21 to be inspected is held horizontally so as not to be distorted, and the substrate 21 in the direction perpendicular to the surface, That is, a light source 1 for film thickness measurement that irradiates a laser beam 34 of a predetermined wavelength such as 350 or 420 nm from directly above through a quartz window 31. 3 and a reflecting mirror 32 and a transmitted light detecting unit 14 provided on the wall surface facing the irradiation direction of the light source unit for film thickness measurement via a quartz window 33.

As a result, the substrate before and after the silicon thin film is formed, and in the case of a large substrate such as 16 inches or 20 inches, the moving mechanism 71 is further used. It is possible to measure the change in the transmittance of each part by moving the substrate, and to accurately measure the thickness of the silicon thin film etc. formed on the substrate. It is possible to ask for it. Note that all the boards are mounted (always) at 7j flat, so there is no need to adjust or correct any changes in the thickness of each board. No.

In addition, it is possible to accurately check whether or not the substrate itself is mounted horizontally by utilizing the interference of laser light.

Further, the light source section 13 for film thickness measurement changes the wavelength of light to be irradiated within a certain range by changing the optical system, such as passing through a prism (not shown), or changing the light source. It is also possible to change the wavelength for accurate measurement, and it is also possible to measure physical properties other than film thickness.

In addition, irradiation with light of a wavelength that is absorbed by a special substance such as hydrogen or that excites a special substance is performed, and the concentration is determined from the absorption rate and the intensity of the excitation light. It is also possible.

Next, with reference to FIG. 2, the electrical configuration of the manufacturing apparatus will be briefly described. In FIG. 2, reference numeral 70 denotes a control circuit. The control circuit 70 includes a system program, a laser output, and other data relating to reforming. Stored ROM 75 and RAM 72 are connected. Ma An operation input means 73 and a light detection section 14 are connected to the control circuit 70. The input from the operation input means 73 and the input from the light detection section 14 are provided. Detected. Data is given. The control circuit 70 includes a plurality of valves V,..., A plurality of pumps P,..., A light source unit 13 for irradiating a single laser beam for measurement, and an anneal Oscillator 11 that irradiates the laser for operation is connected, opens and closes each valve V, drives pump P, lasers the light source section 13 and the oscillator 11 One drive etc. is controlled. Each of the gas supply sources is provided with an on-off valve (not shown), and the on-off valve is controlled by the control circuit 70. ing . FIG. 2 mainly shows a control mechanism for reducing the pressure in the chambers 1 to 7 and a control mechanism for measuring the anneal. However, in a predetermined processing apparatus in each chamber, for example, in the film forming chambers 3 and 4, the operation of the film forming apparatus and the like is controlled by the control circuit 70. .

Next, FIG. 4 shows a second example of measuring the physical properties of the main measuring chamber 7. In this figure, quartz windows 35 and 36 are provided on one pair of opposing side surfaces not facing the transfer room of the measurement room. With this, light of a predetermined wavelength is irradiated at a certain angle through a quartz window 35 in a direction perpendicular to the surface of the substrate 21 accurately placed in a horizontal plane. The physical property measurement light source section 15 that can be used and the physical property measurement light receiving section 16 that detects the irradiating light reflected on the substrate surface through the quartz window 36 are provided. It can be used to measure physical properties.

Specifically, it is possible to measure the thickness and the refractive index of a light-transmitting film formed on the substrate surface by the ellipsometry method.

Next, a method of manufacturing a thin-film transistor using the apparatus for manufacturing a thin-film transistor having the above configuration will be described.

Figure 5 shows the cross-sectional structure of a thin film transistor (element) as it is manufactured. It is a figure showing a state of change.

First, the translucent substrate 21 is loaded into the loading / unloading chamber 2 from the outside. At this time, the gas inside the transfer chamber 1 and each of the chambers 2 to 7 arranged around the transfer chamber 1 are exhausted so that the pressure becomes lower than the predetermined pressure in advance except for the transfer chamber 2. It has been done.

After evacuating the loading / unloading chamber 2, the substrate 21 cleaned in the room, which has been once cleaned by the HEPA filter, is opened, the gate valve is opened, and the transport port 10 is used. It is moved into the first film forming chamber 3.

A gas mixture of TEOS (Tetra Ethyl 0 rtho Si i icate) and oxygen is introduced into the film forming chamber 3, and an underlayer made of a silicon dioxide film is formed on the substrate surface by a plasma CVD method. After forming the coat film to a thickness of 40 O nm, the substrate is moved to the measurement chamber 7 and its transmittance is measured.

Next, each processing shown in FIG. 5 is performed.

(a) The substrate 21 is moved to the second film forming chamber 4. In this film forming chamber, a mixed gas of silane and argon is introduced, and an amorphous silicon film is further formed on the undercoat film 22 formed on the substrate. The film 23 is formed with a thickness of about 5 O nm.

After that, the substrate is moved to the measurement chamber 7 again, and the transmittance of the substrate after the formation of the amorphous silicon film is measured. Thereafter, the transmittance after the formation of the amorphous silicon film is compared with the transmittance measured before the formation of the amorphous silicon film, and based on the difference between the two values, the formed amorphous silicon film is formed. The thickness of the high-quality silicon film can be calculated with an accuracy of 1 nm or less.

(b) The substrate is moved from the measurement chamber 7 to the laser annealing chamber 5, and the conditions most suitable for the previously determined thickness of the amorphous silicon film, particularly the energy density, are determined. By irradiating the substrate surface with laser light, this film is converted to a polycrystalline silicon film. And In this case, the relationship between the film thickness and the laser irradiation conditions is stored in the ROM 75 in advance, and the thickness of the amorphous silicon film is reduced. Even if it is in the range of about 5 to 10%, the variation in silicon properties after melting and recrystallization by irradiation should be suppressed to about 2 to 3%. Is possible. (In the past, this variation could reach 10%.)

(c) The substrate is transferred from the laser annealing chamber 5 to the second film forming chamber 4, and the first silicon nitride film of 30 nm thick is formed on the surface of the polycrystalline silicon film. A second insulating film 25 is formed.

(d) The substrate is moved to the loading / unloading room 2.

Then, the gate valve 92 is closed, clean nitrogen gas is introduced into the loading / unloading chamber 2 until the pressure reaches atmospheric pressure, and then the substrate is taken out.

Based on this, a resist of a predetermined pattern is formed on the substrate surface using photolithography technology, and then a mixed gas of carbon tetrafluoride and oxygen is used. In accordance with the conventional driving method, a predetermined transistor determined from a liquid crystal display panel using a polycrystalline silicon film and a first gate insulating film as a product. Isolate (form patterns 2337 and 38) so that they have a shape and an array according to the arrangement of the elements. Here, the reason that the etching is dry rather than dry is that the dimensions are accurately determined.

(e) A second gate insulating film 26 made of a silicon dioxide film having a thickness of 60 nm is formed, followed by a gate made of an alloy of molybdenum and evening stainless steel. G. An electrode film 27 is formed.

Further, after the gate electrode film is formed in a predetermined pattern 39, this pattern is used as a mask (shield) to cover the entire surface of the substrate with a poly (B) ion. Is formed to form a P-type conductive region 40 in a part of the polycrystalline silicon film.

(f) Again, after the gate electrode film is formed in the predetermined pattern 41, the entire substrate is Lin (P) ions are implanted into the surface to form an _n- type conductor region 42 in a part of the polycrystalline silicon film 24.

(g) After the inter-layer insulating film 28 is formed, a heat treatment at 350 ° C. is performed in a plasma atmosphere of hydrogen gas to remove defects in the polycrystalline silicon film with hydrogen atoms. Terminate.

After that, contact holes are formed in predetermined regions of the n-type and p-type semiconductors, and the source electrode 29 made of a laminated film of titanium and aluminum is connected to the source electrode 29. By forming the lane electrode 30, a thin-film transistor is completed. As can be seen from the above description, in the embodiment of the present invention, during the process from the undercoat film to the first gate insulating film, the interface between the different layers is not so high. The process is also not exposed to contaminated atmospheres or oxygen, which allows it to maintain a very clean interface during the process, which results in better transients. Evening characteristics were achieved.

Specifically, when an evaluation test of the characteristics of the thin film transistor manufactured by the manufacturing apparatus and method of the present embodiment was performed, it was found that 300 cm ² / V · The inter-substrate dispersion of the film transistor, which has a field-effect mobility of 150 cm ² / V or more for p-type semiconductors of more than 1 sec and a p-type semiconductor of less than 3% Was

For the same reason, a threshold voltage of 1 V or less was realized with good reproducibility.

In addition, compared to the conventional technology, it was possible to improve the resistance to stress applied by the AC voltage and to DC stress at high temperatures.

(Embodiments 1-2)

Embodiments 12 and 13 of an apparatus and a method for manufacturing a thin film transistor according to the present invention will be described with reference to FIGS. 6 and 7. FIG.

Figure 6 shows the change in cross-sectional structure due to the progress of thin film transistor manufacturing. This is a diagram showing the situation.

FIG. 7 is an overall configuration diagram of the present manufacturing apparatus. This equipment has two heat treatment chambers 61 and 62, and has a spare chamber 8, so that the arrangement of each chamber is circular with the transfer chamber 1 as the center. Figure 1 shows that the mouth port 10 can not only rotate but also move linearly in the direction of the long axis of the ellipse. It is different from the one.

Each of the two heat treatment chambers has a side facing the air, which further insulates it from other chambers.

Hereinafter, embodiments will be described with reference to FIG. .

(a) Formation of the undercoat film 22 on the substrate 21 in the first film forming chamber 3, measurement of transmittance in the measuring chamber 7, amorphous in the second film forming chamber 4. The silicon film is sequentially formed.

After that, in the first heat treatment chamber 61, the hydrogen contained in the amorphous silicon film is removed in a nitrogen gas atmosphere at 450 to 500 ° C. Heat treatment. Here, the heat treatment in nitrogen gas is performed in order to uniformly heat the substrate, and if vacuum is applied, vanadulous calcium adheres to the indoor wall surface. This is to prevent the substance that had been released from jumping out at high temperature and attaching to the amorphous silicon. In addition, the heat treatment room can process multiple substrates at the same time because energy and work efficiency are improved, and installation accuracy is not a problem. What is it.

The heat-treated substrate was transferred to the measurement chamber 7 again, and the thickness of the amorphous silicon film was measured based on the transmittance measurement.Then, the substrate was transferred to the laser annealing chamber 5 and was most suitable. A polycrystalline silicon film 24 is formed by irradiating the substrate surface with laser light under the conditions.

(b) After the first gate insulating film is formed in the first film forming chamber, the first gate insulating film is formed in the second heat treatment chamber 62 at 300 ° (in a hydrogen plasma atmosphere of up to 350 ° C.). Heat treatment with U. By this treatment, the defect dangling bond present in the polycrystalline silicon film is terminated by bonding of hydrogen atoms, and the defect in the subsequent treatment is reduced. Will be suppressed.

Further, the substrate is taken out of the apparatus in the same manner as in Embodiment 11 and the first gate insulation is performed using the photolithographic branching technique. After the film and the polycrystalline silicon film are formed in a predetermined pattern, a second gate insulating film 26 is formed, and subsequently, a gate electrode film is formed. The gate electrode film thus formed is formed in a predetermined pattern 39.

Next, a polysilicon film is implanted over the entire surface of the substrate to form a p-type conductive region 40 in a part of the polycrystalline silicon film. After the formation of the turn, ion implantation is performed on the entire surface of the substrate to form an n-type conductive region 42 in a part of the polycrystalline silicon film.

(c) After forming an interlayer insulating film 28 and forming contact holes in predetermined regions of the n-type and p-type semiconductors, the source electrode 29 and the drain electrode are formed. By forming the pole 30, a thin-film transistor is completed.

When an evaluation test was performed on the characteristics of the thin film transistor manufactured in the form of this embodiment, it was found that the n-type semiconductor had a thickness of 300 cm ² / V-sec or more, and the p-type semiconductor had an The inter-substrate variation of the thin film transistor having a field effect mobility of 50 cm ² / V · sec or more was less than 3%.

(Supplementary information on Embodiments 1-1 and 1-2)

As described above, the present invention has been described based on several embodiments. However, it goes without saying that the present invention is not limited to these embodiments. That is, for example, the following may be performed.

(1) Semiconductors are substances other than silicon, such as silicon 'germanium' and silicon 'germanium' carbon.

With the development of future technologies, substrates are made of materials other than glass. (2) With the development of technology in the future, the energy used to melt and recrystallize silicon is something other than laser light, such as electron beams.

The formation of each thin film is another means.

(3) It has a function to blow off contaminants adhering after the previous treatment with clean gas.

(4) Quartz windows (glass) can be replaced with objects of different thicknesses.

(5) Rubber gloves are attached to the side of the vacuum chamber so that people can directly move the substrate.

(6) In the above-mentioned Embodiments 11 and 112, since the amorphous silicon is modified into polycrystalline silicon, the laser annealing chamber 5 is provided. Alternatively, a room for lamp annealing may be used instead. In addition, as a laser anneal, a carbon dioxide gas laser, an argon (Ar) laser, an excimer laser, or the like may be used.

(7) Further, the manufacturing apparatus according to the present invention can be widely used not only for TFT but also for other semiconductor elements. In addition, the present invention can be suitably applied to a film forming process of an optical multilayer film and an ion implantation process in an element having an LDD (Lightly Doped Drain) structure.

(8) In laser anneal chamber 5, the degree of crystal after laser anneal may be measured by a measuring means, and laser anneal may be performed again. No. Therefore, the laser annealing room 5 and the measuring room 7 may be configured to be the same room. In this case, the output of the laser should be changed depending on whether it is for measurement or for annealing.

[Form of the second invention group]

The second invention group is applied to an active matrix type liquid crystal display device, a sensor array, an SRAM (Static Random Access Memory) and the like. The present invention relates to a top gate type thin film transistor, a method of manufacturing the same, and a top gate type thin film transistor array. The summary of the second invention group is as follows.

That is, the second invention group is characterized in that a gate electrode can be continuously produced without exposing a semiconductor thin film surface to the atmosphere. (Embodiment 2 — 1)

[Structure of thin-film transistor]

FIG. 8 is a sectional view showing the structure of the top gate type TFT according to the embodiment 2-1. A top-gate TFT 130 is formed on an insulating substrate 101 such as a glass substrate, for example, on a polycrystalline silicon film having a film thickness of 50 nm, for example. Li co down layer 1 0 2, the film if the thickness is eg 1 0 O nm of S i 0 ₂ (dioxide Shi Li co down) or Ru Naru Luo gate insulating film 1 0 3, gate electrodes 1 0 4, and 0 3 when example thickness example O nm of S i 0 ₂ or Ru Naru Luo interlayer insulation Enmaku 1 0 8, that is formed by laminating in this order. The gate electrode 104 includes a first subgate electrode 114 made of a high melting point metal (for example, a molybdenum-tungsten alloy), and the first subgate electrode 104. A second sub-electrode 115 made of a low-resistance metal (for example, aluminum) is formed on the electrode 114. The semiconductor thin film 102 is composed of a source region 105, a drain region 106, and a channel region 107. The channel region 107 is interposed between the source region 105 and the drain region 106 and the first subgate electrode is interposed via the gate insulating film 103. It is located directly below 1 1 4.

A contact hole 111a and 11 lb are formed in the interlayer insulating film 108, and the contact hole 111a is formed through the contact hole 111a. Then, the source electrode 109 is electrically connected to the source region 105, and the drain electrode 110 is connected via the contact hole 11 lb. Drain It is electrically connected to area 106. The source electrode 109 and the drain electrode 110 are made of a low-resistance metal (for example, aluminum).

Here, the gate electrode 104 is composed of a first sub-gate electrode 114 made of a high melting point metal and a second sub-gate electrode 115 made of a low-resistance metal. The reason why such a laminated structure is adopted is as follows.

In other words, in recent years, there has been a demand for a larger liquid crystal display. In order to prevent a drop in signal voltage accompanying this, it has been used as an electrode material for a gate electrode. There is a need to use low resistance metals. However, if the material has a low resistance but a low melting point, the gate electrode may be used in the TFT manufacturing process, for example, during a heat treatment to activate impurities after doping. This phenomenon occurs when the metal material partially dissolves and comes into contact with the end face, which has a serious effect on the transistor performance. Therefore, in order to solve such a problem, it is required to use a material having a low resistance but a high melting point as a gate electrode material. However, there is no metal material having a low resistance and a high melting point within a range that can be used as a wiring material. Therefore, in the present embodiment, the gate electrode 104 is formed of a first sub-gate electrode 114 made of a high melting point metal and a second sub-gate electrode made of a low resistance metal. A laminated structure of 1 and 15 was adopted. Thus, if heat treatment is performed after the formation of the first sub-gate electrode 114 and before the formation of the second sub-gate electrode 115, partial melting of the gate electrode due to the heat treatment can be achieved. Can be prevented. Further, after the heat treatment step, the second sub-gate electrode 115 is formed, so that the resistance of the entire gate electrode can be reduced. With the TFT having the above configuration, it is possible to configure wiring such as signal lines and control lines using a low-resistance metal material in the TFT array. . This point is described in Embodiments 2-6 described later. It will be described in detail.

[Production method of thin film transistor]

FIGS. 9 and 10 are cross-sectional views showing a manufacturing process of the top gate type TFT according to the embodiment 2-1. FIGS. 11 and 12 are related to the embodiment 2-1. FIG. 4 is a plan view showing a manufacturing process of a top-gate type TFT. Note that Fig. 11 (a) corresponds to Fig. 9 (a), Fig. 11 (b) corresponds to Fig. 9 (b), and Fig. 11 (c) corresponds to Fig. 9 (c). , Fig. 12 (a) corresponds to Fig. 10 (a), Fig. 12 (b) corresponds to Fig. 10 (b), and Fig. 12 (c) corresponds to Fig. 10 (c). You

Hereinafter, a method of manufacturing the top gate type TFT 130 having the above configuration will be described with reference to FIGS. 9 to 12.

First, on an insulating substrate 101 such as a glass substrate on which an impurity diffusion preventing film (not shown) having a thickness of, for example, 400 nm is adhered, for example, a non-conductive film having a thickness of, for example, 5 O nm A crystalline silicon thin film is formed by plasma enhanced chemical vapor deposition (PECVD) using a mixed gas such as silane, argon, and hydrogen. . Then, after removing the hydrogen in the amorphous silicon thin film to several at% or less by heat treatment or the like, a high energy density such as excimer laser light is removed. The polycrystalline silicon layer 120 is formed by crystallizing the amorphous silicon by irradiating ultraviolet rays or the like.

Next, without exposing the surface of the polycrystalline silicon layer 120 to the atmosphere, a silicon oxide film 121 serving as a gate insulating film 103 is formed by, for example, 1 The film is formed to a thickness of 100 nm. Specifically, in forming the silicon oxide film 121, a mixed gas such as TEOS (tetraethoxysilane) vapor and oxygen is used. It is preferable to form the film by PECVD, etc. Next, the first sub-gate electrode 114 is formed over the entire surface of the silicon oxide film 121. For example, a high melting point such as a molybdenum-tungsten alloy. The metal thin film 122 is formed by a sputtering method or the like. Such a state is shown in FIGS. 9 (a) and 11 (a).

In this way, the polycrystalline silicon layer 120 and the silicon oxide film 122 are continuously formed on the insulating substrate 101. The cleanliness of the polycrystalline silicon layer 120 and silicon oxide film 121 (accordingly, the polycrystalline silicon layer 102 and the gate insulating film Cleanliness) is maintained. As a specific method for forming a continuous film, a cluster-type film forming apparatus using a mouth potchumper can be used as described later. You should.

Next, photolithography and etching technology are used to separate the elements, and a polycrystalline silicon layer is formed from the surface of the high-melting metal film 122. Process up to 120 into a first island. Such a state is shown in FIG. 9 (b) and FIG. 11 (b).

Next, using the photolithography and etching techniques, the high melting point metal thin film 122 and the silicon oxide film 122 are formed into a second island shape again. By processing, a first subgate electrode 114 and a gate insulating film 103 are formed. Then, in this state, the first sub-electrode 114 is used as a mask by the ion implantation technique, and the n-type is used as an impurity ion in a self-aligned manner. If phosphorus or p-type is used, boron is injected. In this case, the ion implantation can be performed by directly doping the polycrystalline silicon layer 120. Therefore, the ion implantation is performed at a low accelerating voltage. It is. Therefore, damage to the semiconductor layer during doping can be reduced as compared with ion implantation at a high accelerating voltage. Thereafter, the impurity ions are activated by, for example, heat treatment, lamp heating, or laser irradiation, and the source region 105 and the drain region are activated. Polycrystalline silicon with region 106 and channel region 107 A layer 102 is formed. Such a state is shown in Fig. 9 (c) and Fig. 1.

It is shown in 1 (c).

Next, a silicon oxide film or the like is formed on the entire surface of the insulating substrate 101 so as to cover the polycrystalline silicon layer 102 and the first sub-gate electrode 114. An interlayer insulating film 108 having a thickness of 300 nm is formed. Such a state is shown in FIGS. 10 (a) and 12 (a).

Next, the interlayer insulating film 108 was processed again using photolithography and etching techniques, and the source region 105 was opened. Contact hole 11 la, contact hole 11 1 lb related to drain region 106, contact hole opened to first subgate electrode 114 To Hall

1 1 1 c is provided. Such a state is shown in FIGS. 10 (b) and 12 (b).

Next, a low-resistance metal thin film such as aluminum is formed on the entire surface, and processed again using photolithography and etching techniques. Source electrode 109, drain electrode 110 and second subgate electrode 11

Form 5. As a result, a laminated structure composed of the first sub-gate electrode 114 made of a high-melting-point metal and the second sub-electrode 115 made of a low-resistance metal is used. This means that the gate electrode 104 having the structure is formed. Such a state is shown in FIGS. 10 (c) and 12 (c). Thus, a top gate type TFT 130 according to the present embodiment 2-1 is manufactured.

According to the above-described manufacturing method, the interface between the polycrystalline silicon layer 102 and the gate insulating film 103 is formed continuously. High in nature. Also, since the island-shaped sloped surface of the polycrystalline silicon layer 102 and the first sub-gate electrode 114 are insulated by the inter-layer insulating film 108, contact is made. There is nothing to do. Therefore, it is possible to improve the TFT characteristics. .

In addition, the continuous deposition of the semiconductor thin film and the gate insulating film is performed by transporting a glass substrate between two PECVD channels and a laser channel by a transport robot. It can be realized by a so-called cluster type film forming apparatus that can perform the process in a vacuum.

(Embodiment 2-2)

FIGS. 13 and 14 are cross-sectional views showing the steps of manufacturing the top gate type TFT according to Embodiment 2-2. The manufacturing method of the present embodiment 2-2 is almost the same as the manufacturing method of the above-mentioned embodiment 2-1. That is, each of the manufacturing processes shown in FIGS. 13 (a) to 14 (c) in Embodiment 2-2 is the same as that shown in FIG. 9 (a) in Embodiment 2-1. )-It corresponds to each manufacturing process of Fig. 10 (c). In addition, each manufacturing process is basically the same as the embodiment 2-2 and the embodiment 2-1 and the detailed description is omitted. However, in the manufacturing method of Embodiment 2-1, the refractory metal thin film 1 2 2 (the first subgate electrode 1 1 4) is used in the second island processing (FIG. 9C). (See FIG. 9 (c)) and silicon oxide film 12 1 (corresponding to gate insulating film 103) (see FIG. 9 (c)). As shown in Fig. 13 (c), only the high melting point metal thin film 1 2 2 (corresponding to the first sub-gate electrode 1 14) is processed as shown in Fig. 13 (c). Embodiment 2 is different from Embodiment 2-1. Therefore, in Embodiment 2-2, since ion implantation is performed through the gate insulating film, ion implantation can be performed at a high acceleration voltage. For this reason, compared to Embodiment 2-1 in which ion injection is performed at a low accelerating voltage, in Embodiment 2-2, the linearity of flying ions is improved. This prevents the island-shaped slope of the polycrystalline silicon layer 102 from being contaminated with impurity ions and prevents leakage between the semiconductor thin film and the gate electrode. As a result of this, This has the advantage of making it easier to fabricate TFTs with good characteristics.

(Supplementary explanation of Embodiment 2-1 and Embodiment 2-2)

(1) In the above Embodiments 2-1 and 2-2, only the case where a molybdenum-tan tungsten alloy is used as the high melting point metal has been described. . However, as long as the material of the high melting point metal is stable at a temperature higher than the heat resistance temperature of the glass substrate, other metals may be used. For example, Moribden, Tungsten, Tantalum, Titanium, No, Nadium, Zirconium, Niob, Nickel, Chrome It is also acceptable to use alloys and their alloys.

(2) In Embodiments 2-1 and 2-2, although the first subgate electrode material is made of a high melting point metal, the concentration of impurities is high in place of the high melting point metal. Polycrystalline silicon may be used as the first subgate electrode material. As a method of forming such a first subgate electrode made of polycrystalline silicon, an amorphous silicon is formed again on the gate insulating film 103. Then, polycrystallization by ultraviolet irradiation and low resistance by impurity implantation may be used as the first subgate electrode. In the case where polycrystalline silicon having a high impurity concentration is used as the first subgate electrode material, particularly, in the manufacturing method of Embodiment 2-1, the source '' At the time of impurity injection into the drain, it is also possible to simultaneously implant impurities into the polycrystalline silicon that constitutes the first sub-gate electrode. Particularly preferred for ease of use.

(3) In the above Embodiments 2-1 and 2-2, the description has been given of the case where PECVD is used for forming an amorphous silicon film. However, similar results can be obtained even if these films are formed by HW CVD (thermal filament CVD).

で In the above Embodiment 2-1 and Embodiment 2-2, the amorphous silicon The case where the crystallization of the component is performed by ultraviolet irradiation has been described. However, the present invention is not limited to this, and similar TFTs can be manufactured using other methods such as solid phase growth.

⑤ In the above Embodiments 2-1 and 2-2, the case where a polycrystalline silicon thin film is used as the semiconductor thin film has been described. However, the present invention is not limited to this, and may be an amorphous silicon, a single crystal silicon, or a polycrystalline silicon. Other semiconductor materials other than silicon, such as germanium, may be used.

⑥ In the above Embodiments 2-1 and 2-2, the gate electrode and the gate insulating film are processed into islands by patterning, and then the doping is performed. However, on the other hand, doping was done, and then there was no? You can use the tuning process. By performing the doping first, the impurity ions can be reliably implanted into the semiconductor layer. This is for the following reasons. Immediately, if notning is performed first, as shown in FIG. 15, the end surfaces A and B of the gate electrode 114 and the gate insulating film 103 (FIG. 11 (c ) Is not a flat surface perpendicular to the substrate 101, but a slight, but inclined, protruding surface. Therefore, if ion is implanted in this state, the ion enters obliquely, and each end face of the gate insulating film 103 and the semiconductor layer 102 becomes an impurity. It can be contaminated and cause degradation of transistor performance. Therefore, it is desirable to do notching after doping.

⑦ In the above Embodiments 2-1 and 2-2, only the case where aluminum or an alloy thereof is used as the low-resistance metal has been described. However, in and about the material of the low-resistance metal, specific resistance of ² 0 u Q · cm 2 or less, Nozomi or was rather Oh in · cm ² is lever, configured in other metal I don't know. For example, silver, copper, and alloys thereof may be used.

(Embodiment 2-3)

FIG. 1.6 and FIG. 17 are cross-sectional views showing the steps of manufacturing CMOS-TFT using the thin film transistor according to the present invention. As shown in Fig. 17 (b), this CMOS-TFT has an n-channel TFT 1332 with an LDD (Lightly Doped Drain) structure and a non-LDD (Lightly Doped Drain) structure. And a P-channel TFT 133. The p-channel TFT 1313i and the TFT of the above-described embodiment 2-1 (corresponding to a TFT when boron is doped as an impurity ion). It has a similar configuration, and corresponding parts are denoted by the same reference numerals.

The n-channel TFT 1332 is composed of a gate insulating film 103 composed of a polycrystalline silicon layer 140 and Si02 on an insulating substrate 101, and a gate electrode. An interlayer insulating layer 108 made of 142 and Si 02 is laminated in this order. The gate electrode 144 includes a first subgate electrode 144 made of a high melting point metal and a low resistance metal formed on the upper surface of the first subgate electrode 144. And a second sub-gate electrode 144 composed of the same. The polycrystalline silicon layer 140 includes a channel region 144 directly below the first subgate electrode 144 and a source region (high impurity concentration). n + layer 146, high impurity concentration drain region (n + layer) 147, low impurity concentration low concentration impurity region (LDD region: n-layer) 148, 14 It consists of nine. The low-concentration impurity region 148 is interposed between the source region 146 and the channel region 145, and the low-concentration impurity region 149 is connected to the drain region 147. It is interposed between the channel regions 144. In addition, the TFT 1332 is provided with a source electrode 150 and a drain electrode 151 made of a low-resistance metal, and the source electrode 150 is , Contact hole 15 2 a The drain electrode 15 1 is connected to the source region 14 6 via the gate insulating film 14 1 and the interlayer insulating film 10 8. It is connected to the drain region 147 via a contact hole 152b.

[Fabrication of CMOS-TFTT]

CMOS—TFT having the above configuration was produced by the following method.

First, on a surface of an insulating substrate 101 such as a glass substrate having an impurity diffusion preventing film (not shown) having a thickness of, for example, 400 nm, a surface of, for example, 5 nm thick. An amorphous silicon thin film is formed by plasma enhanced chemical vapor deposition (PECVD) using a mixed gas of silane, argon and hydrogen. Then, after removing hydrogen in the amorphous silicon thin film to several at% or less by heat treatment or the like, ultraviolet rays of high energy density such as excimer laser light are irradiated. Irradiation is performed to crystallize the amorphous silicon to form a polycrystalline silicon layer 120.

Next, without exposing the surface of the polycrystalline silicon layer 120 to the atmosphere, a silicon oxide film 121 serving as a gate oxide film 103 is formed by, for example, 1 The film is formed to a thickness of 100 nm. Next, over the entire surface of the silicon oxide film 121, a high melting point such as a molybdenum-tantalum alloy serving as the first sub-gate electrodes 114, 144 is formed. The metal thin film 122 is formed by a snout ring method or the like. Such a state is shown in FIG. 16 (a). Next, photolithography and etching techniques were used to separate the elements, and the polycrystalline silicon layer 122 from the surface of the refractory metal thin film 122 The first part is processed into the first island shape (Fig. 16 (b)).

Next, again, using the photolithography and the etching technology, the refractory metal thin film 122 on the P-channel TFT 133 side is formed into a second island shape. In addition to Then, a first sub-gate electrode 114 is formed (FIG. 16 (c)). In this state, on the n-channel TFT 1332 side, the refractory metal thin film 122- is used as a mask, and on the p-channel TFT 133 side, the first channel is used. Using the sub-electrode 114 as a mask, the polon ion is doped (Fig. 16 (c)). As a result, since the n-channel TFT 1332 side is covered with the refractory metal thin film 122, the polycrystalline silicon layer 120 is not covered by the refractory metal thin film 122. Impurities are not dropped. On the other hand, on the p-channel TFT 133 side, since the first sub-gate electrode 114 acts as a mask, it is located immediately below the first sub-gate electrode 114. The channel region 106 is a region where impurities are not dropped. Then, the polycrystalline silicon layer 1

Impurities are implanted in the region except for the channel region 106 of 20 and the source region (P + layer) 105 and the drain region (p + layer) 10 7 is formed. However, since the first sub-gate electrode 114 is used as a mask to dope the ion, the channel region 106, The source region 105 and the drain region 107 can be formed in a self-aligned manner. Such a state is shown in FIG. 16 (c).

Next, using a photolithography and an etching technique, the refractory metal thin film 122 on the n-channel TFT 32 side is processed into a second island shape. Then, a first sub-gate electrode 144 is formed (FIG. 16 (d)). Then, in this state, the high-melting point metal thin film 122 is used as a mask, and the ion is doped through the gate oxide film. As a result, the n channel T F T 1

On the 32 side, the channel region 144 immediately below the first sub-electrode 144 is a region where impurities are not doped. The regions C and D (see FIG. 16 (d)) except for the channel region 144 of the polycrystalline silicon layer 120 are doped with impurities. n — layer. While p At the channel TFT 123 side, a line ion is implanted, and as a result, the boron ion and the line ion are formed by the previous and current ion implantations. Both are implanted, but because the boron ion is implanted so as to be relatively large, p It works without problems as a channel TFT. In addition, ion implantation is performed at a high accelerating voltage for ion implantation through a gate oxide film.

Next, an inter-layer insulating film 108 is formed to cover the p-channel TFT 13 and the n-channel relay TFT 13 (FIG. 16E).

Next, the contact holes reaching the polycrystalline silicon layer 140 are provided on the interlayer insulation layer 108 on the n-channel TFT 1332 side, and the contact holes 15 2 a and 1 Form 5 2 b. The opening of the contact hole 1552a faces the remaining part except for both sides of the area C (corresponding to the low-concentration area LDD). The outline of the hole 152b faces the remaining part except for both sides of the region D (corresponding to the low concentration region LDD). Next, in this state, the inter-layer insulating film 108 is used as a mask, and the ion is again doped (FIG. 17 (a)). As a result, on the n-channel TFT 32 side, a region of the polycrystalline silicon layer 140 that is not covered by the inter-layer insulating film 108 (con The ion is doped in the area that faces the contact hole. Therefore, in the regions C and D where impurities have already been doped by the first ion implantation, the inter-layer insulating film 108 is formed. In the uncovered region (corresponding to the source region and the drain region), the impurity is further doped, and the region with a high impurity concentration (the n + layer) is removed. ). On the other hand, in the regions A and B, which are covered with the inter-layer insulating film 108 (corresponding to the low-concentration impurity regions 48 and 49), the second line connection is performed. Depending on the on doping, the impurity is not doped, resulting in a low-concentration impurity region (n-layer). In this way, the source area (n + layer) A low-concentration impurity region (n-layer) 148 is formed between 146 and the channel region 145, and a drain region (n + layer) 147 and the channel are formed. A low-concentration impurity region (n-layer) 149 can be formed between the channel regions 145.

Next, in the p-channel TFT 133 on the side of the interlayer insulating film 108, the contact holes reaching the polycrystalline silicon layer 102 are placed on the lanes 11 la and 11 lb. To form. Then, an aluminum low-resistance metal thin film is formed on the entire surface of both the n-channel TFT 13 and the p-channel TFT 13, and the photolithography is performed again. Using graphing and etching techniques, source electrodes 109, 150, drain electrodes 110, 151, and second subgate electrode 11 It is processed into 5, 14 4. In this way, as shown in FIG. 17 (b), a CMOS-TFT having an LDD structure on the n-channel TFT side is produced.

Also according to the manufacturing method according to Embodiments 2-3, since the interface between the polycrystalline silicon layer and the gate insulating film is formed continuously, interface localization is performed. Low level and high cleanliness. Also, since the island-shaped sloped surface of the polycrystalline silicon layer and the first sub-gate electrodes 114 and 144 are insulated by the interlayer insulating film 108, contact is made. Nothing to do. Therefore, a CMOS-TFT having improved TFT characteristics is produced.

(Embodiment 2 — 4)

FIGS. 18 and 19 are cross-sectional views showing steps of another method for manufacturing a CMOS-TFT using the thin-film transistor according to the present invention. This Embodiment 2-4 is basically similar to Embodiment 2-4. However, in Embodiments 2 to 3, n + doping is performed after the formation of the interlayer insulating film 108. However, in Embodiments 2 to 4, the LDD is not used. After etching for the gate oxide film, doping is performed. Then, they are different.

This will be described below with reference to FIGS. 18 and 19. First, the processing shown in FIGS. 18 (a) to 18 (d) is performed in the same manner as in Embodiments 2 to 3 above, and P + doping and n—doping are performed. I do . Note that the processing in FIG. 18 (a) corresponds to FIG. 16 (a), the processing in FIG. 18 (b) corresponds to FIG. 16 (b), and the processing in FIG. 18 (c) This corresponds to FIG. 16 (c), and the processing of FIG. 18 (d) corresponds to FIG. 16 (d).

Next, using a photolithography and an etching technique, the silicon oxide film 121 on the n-channel TFT 1332 side is processed into an island shape. Then, in this state, n + doping is performed. In addition, n channel T F T

On the 132 side, since ion doping is directly performed to the polycrystalline silicon layer 140, ion implantation should be performed at a low accelerating voltage. As a result, on the n-channel TFT 1332 side, the first line ion doping of the polycrystalline silicon layer 140 depends on the doping of the first line ion. Of the region AB where impurities have already been doped, and which are not covered with the gate insulating film 103 (corresponding to the source region and drain region). In this case, the impurities are further doped, which results in a high impurity concentration region (n + layer). On the other hand, of the regions C and D, the regions covered with the gate insulating film 103 (low-concentration impurity regions 148,

149), the impurity is not doped by the second line ion doping, and the low-concentration impurity region (n-layer) is formed. It becomes. In this way, a low-concentration impurity region (n-layer) 148 is formed between the source region (n + layer) 146 and the channel region 145, and A low-concentration impurity region (n-layer) 149 can be formed between the drain region (n + layer) 147 and the channel region 144. Such a state is shown in FIG. 11 (d).

Next, an interlayer insulating film 108 is formed (FIG. 19 (a)), and the contact is formed. Open the halls llla, 11 1b, 11 1c, 15 2a, 15 2b, 15 2c. Then, a low-resistance metal thin film such as aluminum is formed on the entire surface of both the n-channel TFT 13 and the p-channel TFT 13, and the photo is formed again. Using lithography and etching techniques, the source electrodes 109, 150, the drain electrodes 110, 151, and the second sub-electrode 1 Process into 15 and 14 4. Thus, as shown in FIG. 19 (b), a CMOS-TFT having an LDD structure on the n-channel TFT side is manufactured.

(Embodiment 2 — 5)

FIG. 20 is a circuit diagram showing a configuration of a TFT array composed of TFTs according to the present invention. In the TFT array, a plurality of signal lines 155 and a plurality of control lines 156 are arranged in a matrix, and each intersection of the signal line 155 and the control line 156 is formed. In the vicinity, the top gate type TFT 130 according to the embodiment 2-1 is disposed. Instead of the TFT of the embodiment 2-1, the TFT of the embodiment 2-2 may be used.

The signal line 155 is connected to the source electrode 109 of the corresponding TFT, and the control line 156 is connected to the gate electrode 104 of the corresponding TFT. Note that the signal line 155 and the control line 156 are formed on the same insulating substrate 101 together with the TFT. As shown in FIG. 21, the signal line 155 and the control line 156 are composed of a semiconductor layer 157, an insulating film 121, a high melting point metal layer 122, and a low resistance metal layer. It consists of a four-layer laminated film of layers 158. At the intersection of the signal line 155 and the control line 156, as shown in FIG. 22, the control line 156 is composed of the semiconductor layer 157, the insulating layer 122, and the high layer. The four-layer laminated film of the melting point metal layer 122 and the inter-layer insulating layer 108 is formed, and the signal line 155 is formed of the low-resistance metal layer 158 as a single layer film. Due to such a structure, all the signal lines 155 requiring low resistance are provided. In effect, the wiring is made of low-resistance metal 158, and the control line 156 is also wired with low-resistance metal 158 except at the intersection with the signal line 155. It is. Therefore, it is a preferable configuration for a large and high-definition TFT array in which it is important to reduce the wiring resistance.

FIGS. 23 and 24 are cross-sectional views showing the manufacturing process of the TFT array. In FIGS. 23 and 24, for convenience of explanation, one TFT part and its TFT part are shown. Only the wiring structure related to the TFT part is shown. Hereinafter, a method for manufacturing a TFT array according to the present invention will be described with reference to the drawings. First, as shown in FIG. 23 (a), a three-layer laminated film of a semiconductor layer 157, an insulating layer 122, and a refractory metal layer 122 is formed on an edge substrate 101. Formed (corresponding to Figs. 9 (a) and 11 (a)).

Next, as shown in FIG. 23 (b), the TFT 130, the control line 156, and the control line 1 are formed by photolithography and etching. The signal line 1555 is formed with the wire broken at the intersection so that it does not touch 56 (corresponding to Figs. 9 (b) and 11 (b)).

Next, as shown in FIG. 23 (c), the TFT 130 is processed into islands, and impurities are implanted and activated (FIG. 9 (c) and FIG. 11 (c)). Corresponding).

Next, as shown in FIG. 24 (a), an interlayer insulating layer 108 is formed on the entire surface (corresponding to FIGS. 10 (a) and 12 (a)).

Next, as shown in FIG. 24 (b), contact holes are opened in the interlayer insulating film 108 (FIGS. 10 (b) and 12 (b)). Corresponding to). At this time, at least at a portion where the control line 156 and the signal line 155 intersect, leave the interlayer insulating layer 108 so that the two lines do not contact each other. In the other portions on the control line 156 and the portions on the signal line 155, the inter-layer insulating film 108 is removed. Next, as shown in FIG. 24 (c), the connection between the control line 1556 and the gate electrode 104 by a low-resistance metal such as aluminum is performed. Connect the signal line 155 to the source (drain) area (corresponding to Figures 10 (c) and 12 (c)). At the same time, the low-resistance metal 1558 is applied to the portion other than the intersection with the signal line 1555 on the control line 1556 and to all the portions including the intersection on the signal line 1555. To form. As a result, the control line 156 and the signal line 155 are basically composed of the semiconductor layer 157, the insulating film layer 121, the high melting point metal layer 122, and the low resistance. At the intersection of both lines, the control line 156 is composed of the semiconductor layer 157, the insulating layer 122, the refractory metal layer 122, and the inter-layer. The insulating layer 108 becomes a four-layer laminated film, and the signal line 155 becomes a low-resistance metal layer 158 as a single-layer film.

With this structure, it is possible to manufacture a TFT array without losing continuity between the semiconductor layer of the TFT section 130 and the gate insulating layer. All of the signal lines 155 that require a lower resistance are practically all wired with low-resistance metal 158, and the control lines 156 are also connected to the signal line 155. Except for the intersection with 55, wiring is made of low-resistance metal 144. Therefore, it is a preferable configuration for a large, high-definition TFT array in which it is important to reduce the wiring resistance. At the time of ion implantation, a high-melting-point metal is used as a mask to relax the heating temperature and the upper limit of thermal shock during activation. Further, since the above-described low-resistance metal is formed after activation, it may be a low-melting-point material such as aluminum.

Also, in the above example, except for the intersection of the signal line and the control line, the signal line is composed of a four-layer laminated film of a semiconductor layer, an insulating film layer, a high melting point metal layer and a low resistance metal layer. However, in FIG. 23 (b), only the control lines are formed, and in FIG. 24 (c), the signal lines are formed of a low-resistance metal. You may do it. In this way, all the signal lines including the intersections of the signal lines and the control lines become one layer of a low-resistance metal layer, and the resistance of the signal lines is further reduced. I can do it.

[Third invention group form]

The third invention relates to a method of forming an amorphous silicon film by a plasma CVD method. More specifically, the hydrogen concentration in the film is determined by a plasma CVD method. The present invention relates to a method for easily forming a low-temperature amorphous silicon film at a low temperature. The summary of the third invention group is as follows.

In other words, the third invention group makes it possible to easily form an amorphous silicon film having a hydrogen concentration of 3 at% or less at a low temperature by a plasma CVD method. It is characterized by the following.

(Embodiment 3-1)

Hereinafter, Embodiment 3-1 will be described with reference to FIGS. 25 to 28. FIG. In the present invention, a parallel plate type plasma CVD device is used. Figure 1 shows a schematic diagram of a parallel plate type plasma CVD device 210.

An RF electrode 204 having a large number of holes on its lower surface is arranged at an upper position in a vacuum vessel 201 having a gas introduction system 203 and a vacuum evacuation system 202. A ground electrode 205 is arranged at a lower position in the container 201 so as to face the electrode 204. A heater 200 is provided in the ground electrode 205, and the substrate 200 arranged on the ground electrode 205 by the heater 210 is provided. 6 is heated, and a high-frequency electrode 208 for applying a high frequency voltage to the RF electrode 204 is provided.

Instead of using the parallel plate type plasma CVD apparatus 210 having such a configuration, the pressure inside the vacuum vessel 201 is adjusted by the vacuum exhaust system 202. Next, deposition gas (raw material gas) that contributes to film formation and does not contribute to film formation Gas is blown out through a number of holes provided in the RF electrode 204 through the gas introduction system 203 into the vacuum vessel 201, and is supplied to the RF electrode 204 with a 27.12 MHz frequency. RF plasma is generated by applying high-frequency power of z, and an amorphous silicon film is formed on the substrate 206. . At this time, the substrate 206 was heated to 250 to 300 by a heater 107 provided in the ground electrode 205. This temperature is a value measured by a thermocouple (not shown) installed on the back surface of the substrate 206. The details are described below.

(Example 1)

First, the substrate 206 is placed on the ground electrode 205, and the substrate 206 is heated by a heater 206 provided in the ground electrode 205 to 300 °. C

Next, the pressure inside the vacuum vessel 201 is adjusted by the vacuum exhaust system 202 so as to be 133 Pa, and the pressure in the vacuum vessel 201 is changed from the gas introduction system 203 to the vacuum vessel 201. In the chamber, SiH 4, a gas for film formation, and Ar, a gas not contributing to film formation, were introduced at a flow rate of 1500 sccm, and the SiH ₄ and Ar While changing the mixing ratio, the discharge was performed at a discharge frequency of 27.12 MHz and RF power of 160 W from the high frequency power supply 208, and the substrate was placed on the substrate 206. An amorphous silicon film was formed. The thickness of the amorphous silicon film was adjusted to 300 nm by controlling the film formation time. The hydrogen concentration in the amorphous silicon film was analyzed by Fourier transform infrared spectroscopy (FTIR). Figure 26 shows the results.

2 6, S i H ₄ concentration and Ammo Le off § mortal Ri Ah in Li co down film in the film shown immediately La off the relationship between the hydrogen concentration, film hydrogen concentration, S i H ₄ With the decrease in the concentration, an amorphous silicon film having a SiH ₄ concentration of 5% or less and a hydrogen concentration in the film of 3 at% or less is formed. This is S i H ₄ On the other hand, as the Ar concentration increases, the deposition rate decreases due to an increase in the Ar concentration, so that hydrogen in the film is easily desorbed. Ar with energy increases, and the hydrogen present on the outermost surface of the amorphous silicon film is converted into a physicochemical reaction by the Ar (the surface of the Ar film). The kinetic energy or internal energy of the Ar is applied to the membrane surface by a collision or the like, and the Si—H bond is cut off. It is thought that this was due to the detachment.

In the first embodiment, only Ar was used as a gas not contributing to film formation. However, a mixed gas of Ar and H 2 (hydrogen) was used as a diluent gas. By using this, the hydrogen concentration in the amorphous silicon film can be further reduced.

This is because, in the plasma, hydrogen atoms and H + that are more active than Ar reach the film forming surface, and the hydrogen atoms and H + reach the surface of the amorphous silicon film Si. This is thought to be because the 1 H bond is cleaved and converted to hydrogen molecules and released from the film surface. In addition, the etching of the amorphous silicon film is simultaneously caused by the hydrogen atoms and H + having high energy in the plasma. The bond between Si-Si in the amorphous silicon film is broken, and Si on the surface of the amorphous silicon film is desorbed from the film surface. It is considered that the film formation rate of the amorphous silicon film is reduced.

Also, S when the i H ₄ you highly diluted with only H _2, on the substrate 2 0 6 Amo le off § mortal of the can rather than re co down film Ru is formed, microcrystalline It is known that a silicon film is formed, and to form an amorphous silicon film with low hydrogen concentration, dilute only with H2. However, it is necessary to add Ar or the like as a gas which does not contribute to film formation at least.

(Example 2) In the following, S i H ₄ flow rate 4 5 sccm, and an A r flow 1 4 5 5 sccm were fixed with 3% S i H ₄ concentration, vary the RF power range of 2 0 ~ 2 0 0 W is allowed by other film formation conditions _c its depositing the Amo le full § mortal Li co down film on the substrate 2 0 6 Ru Oh pressure 1 3 3 P a, the substrate temperature 2 5 0 ° C . Figure 27 shows the relationship between the RF power and the deposition rate of the amorphous silicon film. Figure 28 shows the relationship between the RF power and the hydrogen content in the amorphous silicon film. Shows the relationship with concentration.

In Figure 27, it can be seen that the deposition rate increases with increasing RF power, and after a certain value it shows a near-saturating tendency. As described above, in the plasma CVD method, the region where the deposition rate increases in proportion to the RF power is defined as the reaction law region, and the region where the deposition rate shows a saturation tendency with respect to the RF power. This is called the supply law area. Wherein in the reaction law law region, because deposition rate degradation was Ru promoted the S i H ₄ electron density in plasmas have name also to an increase in RF power increased it increased. If you increase the RF power to is found, S i H ₄ is decomposed etc. No O and Ho, ing a supply law law region. In this area S i H ₄ does not change etc. does almost because the deposition rate that has been degraded Ho O, the particle composition in the plasmas is changed, Ya S i H ₂ La di mosquito Lumpur There are particles with few hydrogen bonds, such as SiH radicals.

As shown in Fig. 28, the hydrogen concentration in the film decreases with the increase in RF power, and the hydrogen concentration in the film becomes 3% or less per 100 W or more. This is because the increase in the electron and ion densities in the plasma along with the increase in RF power increases the Ar in the high energy state and increases the Ar This is thought to be due to the elimination of hydrogen on the film surface by the physicochemical reaction on the film surface. In the region where the hydrogen concentration in the film is 3 at% or less, the deposition rate is in the region of the supply rule, and in such a region, SiH ₄ is almost decomposed. As a result, the deposition rate hardly changed, Particle composition in the La Zuma is changed in S丄11 ₂ la di Ca Ruya 3 i H La di Ca Le and have Tsu was small had particles of the hydrogen bonds A molar off § mortal Li co down film formation It is a precursor. Therefore, it is considered that this has a great effect on the reduction of the hydrogen concentration in the amorphous silicon film.

(Example 3)

And have you in Example 1, 2 is had use the S i H ₄ as a film formation gas, and RF the Re this as the S i ₂ H ₆ in the same manner as in Example 2 Power The relationship of hydrogen concentration in the film was examined. Also, an amorphous silicon film was formed under the same conditions as in Example 2 except that the film forming gas (source gas) was Si ₂ H ₆ . Figure 28 shows the results of examining the hydrogen concentration in the film of the amorphous silicon film.

The film-forming gas the S i H ₄ or et al. S i ₂ H ₆ to ging Ru this and to'm Ri film hydrogen concentration itself, but that will change, trends in the Soviet Union do not want to change (RF As the power increases, the hydrogen concentration in the film decreases.) Me other this, S i H ₄ when the same menu crab's arm and this low hydrogen concentration Amo le off § mortal Li co down films that have been formed is thinking et is Ru. Although not shown, the same effect can be obtained by changing the film forming gas to Si ₃ H ₈ , Si H ₂ Cl ₂ , Ge H ₄ , or the like.

In Examples 1 to 3, the inert gas Ar (argon) is used as the gas that does not contribute to the film formation. For example, the same gas is used. Even when the inert gases He (helium), Ne (neon), Kr (cribton), and Xe (xenon) are used, low hydrogen An amorphous silicon film can be formed.

Further, in the first to third embodiments, a parallel plate type plasma CVD apparatus as shown in FIG. 25 was used. However, according to the mechanism of the present invention, an induction method is used. Coupled plasma (ICP) and electron cyclotron resonance (ECR) Similar effects can be expected by using a plasma CVD system that uses high-density plasma such as plasma.

The specific embodiments described above are intended to clarify the technical contents of the present invention, and are to be interpreted in a narrow sense by limiting only to such specific examples. Rather than to be done, various modifications may be made within the spirit of the invention and the scope of the claims. Industrial applicability

As described above, according to the configuration of the present invention, each subject of the present invention can be sufficiently achieved. Specifically, it is as follows.

According to the semiconductor manufacturing apparatus according to the first invention group, while maintaining the cleanliness of the interface, the physical properties of the thin film formed on the substrate, particularly the physical properties related to the reforming of the film are improved. Can be measured and then irradiated with a reforming energy beam. Therefore, it becomes possible to modify the thin film by laser light under the most suitable conditions according to the physical properties such as the film thickness. In addition, it has excellent properties because it can perform film formation in the next process without exposing the surface of the modified thin film to indoor contaminated air or oxidizing air. Device creation becomes feasible. Exposure to vacuum in the transfer chamber also naturally removes contaminants that have adhered to the previous process. In addition, since a semiconductor thin film having excellent interface characteristics can be formed, a thin film transistor (element) having extremely excellent characteristics must be extremely small. It can be manufactured with good reproducibility in the following range. For the same reason, a threshold voltage of IV or lower can be realized with good reproducibility. In addition, compared to the related art, it is possible to improve resistance to stress applied by AC voltage and DC stress at high temperature. Also, since the laser oscillator is located outside the room where the circuit board is installed, it can be replaced or used as a lens system. By performing the actual replacement by switching the substrate, various types of measurement and processing can be performed while the substrate and the like are kept clean. Specifically, for example, measurement of the thickness of a substrate, inspection of a material, and the like are performed. In addition, it is possible to irradiate the laser using the window on the side wall of each clean room, and to perform various measurements.

In addition, the board will be installed for the original processing, such as laser annealing, and the equipment to be transported and the equipment to be installed and transported for measurement will also be used largely.

According to the second invention, the gate insulating film is continuously formed without exposing the semiconductor thin film surface to the atmosphere, and the contact between the semiconductor thin film and the gate electrode at the slope of the gate electrode is made. It is possible to manufacture a top-gate type TFT without any problem. As a result, it is possible to obtain a top gate type thin film transistor having improved TFT characteristics. Also, by reducing the resistance of wiring (especially signal lines), a thin-film transistor array that can be suitably used for large-sized liquid crystal panels can be obtained. be able to .

According to the third invention group, a plasma CVD apparatus is used to keep a substrate temperature from being higher than 300 ° C. and a film concentration of hydrogen at 3 at% or less in a film. A silicon film can be formed, thus reducing the number of hydrogen desorption steps before laser irradiation by the laser annealing method. As a result, the manufacturing process can be simplified. Therefore, effects such as a reduction in the production cost of the low-temperature polysilicon TFT and an improvement in the throughput can be expected.

Claims

The scope of the claims

1. In a method of manufacturing a device having a multilayer structure by a plurality of film forming steps,

A first film forming step of forming at least one film, which is one of the plurality of film forming steps,

A measuring step of measuring predetermined physical properties of the film obtained in the first film forming step;

A second step of treating the film in accordance with measurement conditions determined based on the measurement results in the measurement step;

The method of manufacturing an element having a multilayer structure, wherein the first step, the measuring step, and the second step are each performed in a predetermined clean atmosphere.

2. The method for manufacturing an element having a multilayer structure according to claim 1, wherein the treatment in the second step is a film formation treatment.

3. The method for manufacturing an element having a multilayer structure according to claim 1, wherein the treatment in the second step is a film modification treatment.

4. A device for manufacturing an element having a multilayer structure,

A film forming means for forming at least one of the plurality of films, a means for measuring a predetermined physical property of the film obtained by the film forming means, and a measuring means. Processing means for processing the film in accordance with measurement conditions determined based on the measurement results obtained; and

Transfer between the film forming means, the measuring means, and the processing means. Transport means for sending

With

An apparatus for manufacturing an element having a multilayer structure, characterized in that the film forming means, the measuring means, the processing means, and the transporting means perform each processing under a predetermined clean atmosphere. .

5. The device for manufacturing a device having a multilayer structure according to claim 4, wherein the processing in the processing means is a film forming processing.

6. The device for manufacturing a device having a multilayer structure according to claim 4, wherein the treatment in the treatment means is a film modification treatment.

7. With the substrate installed in a predetermined clean atmosphere determined by the thin film formation, use the semiconductor supplied from the semiconductor supply means provided outside the clean atmosphere. Thin film forming means for forming an amorphous semiconductor thin film on a substrate by

The physical property value related to the modification of the amorphous semiconductor thin film formed on the substrate by irradiation with energy rays is determined by a method for measuring physical properties using light. Physical property measurement means for measuring using a predetermined light source and a receiver while the substrate is placed in an atmosphere;

When the substrate is installed in a predetermined clean atmosphere determined by the reforming, a reforming energy wire having the property determined from the physical properties measured above is removed from the clean atmosphere. Energy beam irradiating means for irradiating an amorphous semiconductor using a predetermined energy beam source provided at a predetermined location;

The above substrate is received from outside to form an amorphous semiconductor layer on its surface, and is used for thin film formation, physical property measurement, and energy beam irradiation. At this time, the substrate should be installed and processed in order for each processing by the thin film forming means, the physical property value measuring means, and the energy ray irradiating means without exposing the substrate to at least the outside atmosphere. An apparatus for manufacturing a thin-film transistor, characterized by having a clean atmosphere holding type transfer means to be removed later.

8. With the substrate installed in a predetermined clean atmosphere determined by the formation of the thin film, use the semiconductor supplied from the semiconductor supply means provided outside the clean atmosphere. Film forming means for forming an amorphous semiconductor thin film on a substrate by

The physical property value related to the modification of the amorphous semiconductor thin film formed on the substrate by irradiation of energy is determined by a physical property measurement method using light. With the substrate installed in an atmosphere, physical property value measuring means for measuring using a predetermined light source and a light receiver provided in a place outside the clean atmosphere,

When a substrate is installed in a predetermined clean atmosphere defined by the reforming, a reforming energy wire having the property determined from the physical properties measured above is taken out of the clean atmosphere. Energy beam irradiation means for irradiating the amorphous semiconductor by using a predetermined energy beam source provided at the place;

The above substrate is received from the outside to form an amorphous semiconductor layer on its surface, and a small amount of substrate is used in each of the subsequent thin film formation, physical property measurement, and energy beam irradiation processes. Are installed in order for the thin film forming means, physical property measurement means, and energy beam irradiation means in order without exposing them to the external atmosphere, and are removed after the processing. An apparatus for manufacturing a thin-film transistor, characterized by having a clean atmosphere holding type transport means.

9. Expulsion of hydrogen from the amorphous semiconductor formed on the substrate. In a given atmosphere, which is determined by the process for achieving good function as a transistor, such as the bonding of hydrogen to the dangling bond of a polycrystalline semiconductor. A heat treatment means for heat treating the semiconductor thin film with each substrate;

The clean atmosphere holding type transfer means,

At least there is a small heat treatment transport means capable of mounting the substrate on the heat treatment means and removing it after the treatment without being exposed to the external atmosphere. An apparatus for manufacturing a thin-film transistor according to claim 8, which is characterized in that:

10 0. There is a loading / unloading means for receiving and transferring the board from outside,

The clean atmosphere holding type transfer means,

The center of the structure having the thin film forming means, the physical property value measuring means, the energy beam irradiating means, the carry-in / out means, and the heat treatment means in addition to the thin-film forming means, the physical property value measuring means, and the heat treatment means on its outer periphery It is a type of clean atmosphere holding type transfer means.

Furthermore, in order to facilitate the installation and removal of the substrate to and from the means arranged on the outer peripheral part, there is provided a rotatable transfer means that can rotate while holding the substrate. ,

The physical property value measuring means,

9. The apparatus for manufacturing a thin film transistor according to claim 8, wherein the apparatus is a horizontal holding type physical property measuring means for holding the substrate horizontally when measuring the physical property value of the substrate.

1 1. There is a loading / unloading means for receiving and transferring the board from the outside to the outside,

The clean atmosphere holding type transfer means, The center of the structure having the thin film forming means, the physical property value measuring means, the energy beam irradiating means, the carrying-in / out means or the heat treatment means in addition to the thin-film forming means, the physical property value measuring means, and the like at the outer peripheral portion thereof. Arrangement type Clean atmosphere holding type transport means,

In addition, there is a rotatable transfer means that can hold and rotate the substrate to facilitate the installation and removal of the substrate to and from the means arranged on the outer periphery. Then

The physical property value measuring means,

10. The thin film transistor manufacturing apparatus according to claim 9, wherein the apparatus is a horizontal holding type physical property measuring means for holding the substrate horizontally when measuring the physical property value of the substrate.

12. The thin film forming means, the physical property measuring means, the energy beam irradiating means or the heat treatment means in addition to them.

Silicon-based thin films for silicon, silicon, germanium, silicon'germanium, and at least one of carbon as semiconductors Means for forming, means for measuring physical properties of silicon system, means for irradiating energy for silicon system or heat treatment means for silicon system in addition to these. 9. The apparatus for manufacturing a thin film transistor according to claim 8, wherein:

13. The thin film forming means, physical property measuring means, energy beam irradiating means, or heat treatment means in addition to them.

Silicon-based thin films for silicon, silicon, germanium, silicon'germanium, and at least one of the carbon semiconductors Forming means, means for measuring physical properties of silicon system, means for irradiating energy rays for silicon system, or heat treatment means for silicon system in addition to these. 10. The apparatus for manufacturing a thin film transistor according to claim 9, wherein: 14. The thin film forming means, the physical property measuring means, the energy beam irradiating means or the heat treatment means in addition thereto

Silicon-based thin film forming means for silicon, silicon 'germanium, silicon, germanium, and at least one of carbon as semiconductors Means for measuring the physical properties of the silicon system, means for irradiating the silicon system with energy rays, or heat treatment means for the silicon system in addition to these. thin preparative run-g is te manufacturing apparatus _c 1 5 according to claim 1 0, wherein you characterized. in a state of a thin film formation or Jo Luo or Ru substrate under predetermined clean atmosphere was placed, clean atmosphere outside of that A thin film forming step of forming an amorphous semiconductor thin film on a substrate using a semiconductor supplied from a semiconductor supply means provided at

The physical property values related to the reforming of the amorphous semiconductor thin film formed on the above substrate by the energy ray irradiation for the reforming are determined from the physical property measuring method using light. The physical property measurement step is performed by using a predetermined light source and a light receiver while the substrate is installed in a predetermined clean atmosphere.

When the substrate is installed in a predetermined clean atmosphere determined by the reforming, the energy beam for reforming having the properties determined from the physical properties measured above is removed from the clean atmosphere. An energy beam irradiation step for irradiating the amorphous semiconductor for the purpose of reforming it using a predetermined energy beam source provided at

The above substrate is received from the outside to form an amorphous semiconductor layer on its surface, and is then used for each step of thin film formation, physical property measurement, and energy beam irradiation. In order to expose the substrate to the outside atmosphere at least, install the necessary equipment for each of the thin film formation, physical property measurement, and energy beam irradiation equipment in this order. A method for manufacturing a thin-film transistor, characterized by having a clean atmosphere holding type transfer step for carrying out removal after treatment.

16 6. With the substrate installed in a predetermined clean atmosphere determined by the thin film formation, use the semiconductor supplied from the semiconductor supply means provided outside the clean atmosphere. A thin film forming step of forming an amorphous semiconductor thin film on a substrate by

The physical property values related to the reforming of the amorphous semiconductor thin film formed on the above substrate by the energy beam irradiation for the reforming are determined by the physical property measuring method using light. With the substrate installed in a predetermined clean atmosphere, a physical property measurement step is performed by using a specified light source and receiver installed outside the clean atmosphere.

With the reforming energy wire having the property determined from the physical properties measured above, the substrate was placed in a predetermined clean atmosphere determined by the reforming, and the substrate was placed outside the clean atmosphere. An energy beam irradiation step for irradiating the amorphous semiconductor for the purpose of reforming it using a predetermined energy beam source provided at

The above substrate is received from the outside to form an amorphous semiconductor layer on its surface, and is then used for each step of thin film formation, physical property measurement, and energy beam irradiation. The required installation and equipment for the thin film formation, physical property measurement, and energy beam irradiation should be performed in order without exposing the substrate to the external atmosphere. A method for manufacturing a thin film transistor, characterized by having a clean atmosphere holding type transfer step for carrying out a process. 17 7. Eliminate hydrogen from the amorphous semiconductor formed on the substrate, and similarly transfer hydrogen to the dangling band of the polycrystalline semiconductor. A heat treatment step for heat treating the substrate and the semiconductor thin film in a predetermined atmosphere determined by a process for exhibiting a good function as a discharge element, and having a clean atmosphere holding type transfer. The steps are

At least do not expose to the external atmosphere, and in the heat treatment step, perform the necessary installation and removal of the substrate after the processing for the equipment for performing the heat treatment step. 17. The method for producing a thin-film transistor according to claim 16, wherein the method includes a heat-transfer small step.

1 8. There is a loading / unloading step for receiving the board from outside and transferring it to the outside.

The clean atmosphere holding type transfer step includes:

The thin film formation step, physical property measurement step, energy beam irradiation step, loading / unloading step, or updating are provided on the outer peripheral portion of the apparatus for performing the step. In addition to these, there is an apparatus for heat treatment step, which allows the substrate to be processed to be carried in and out between the center and the outer periphery. This is a clean-atmosphere-preserving transfer step.

In addition, there is a small rotating step that holds and rotates the substrate so that the substrate can be installed for processing by each means and removed after processing smoothly. And

The physical property measurement step

17. The thin film transistor according to claim 16, characterized in that it is a horizontally held physical property measuring step for measuring the physical properties of the substrate while holding the substrate horizontally. Star manufacturing method.

1 9, with a loading / unloading step for receiving and transferring the board from outside, The clean atmosphere holding type transfer step includes:

The thin film formation step, physical property measurement step, energy beam irradiation step, carry-in / out step or In addition to these, there is an apparatus for heat treatment step, which allows the substrate to be processed to be carried in and out between the center and the outer periphery. Arrangement type Clean atmosphere holding type transfer step,

In addition, there is a small rotating step that holds the substrate and rotates it to facilitate the removal after processing by installing the substrate for processing by each means. And

The physical property measurement step

18. The thin film transistor according to claim 17, wherein the step is a horizontally held physical property measurement step for measuring the physical property value of the substrate while holding the substrate horizontally. Manufacturing method. 20. The thin film formation step, physical property measurement step, energy beam irradiation step or heat treatment step in addition to these steps are performed as follows.

Silicon-based thin film forming stages for silicon, silicon, germanium, silicon, germanium, and at least one of carbon as semiconductors. Step, silicon system physical property measurement step, silicon system energy irradiation step or silicon system in addition to these 17. The method for producing a thin film transistor according to claim 16, wherein the method is a heat treatment step.

21. The thin film formation step, physical property measurement step, energy beam irradiation step or heat treatment step in addition to these steps

Each of the semiconductors is silicon, silicon 'gel-manium, silicon Silicon system thin film formation step for at least one of germanium and carbon, silicon system physical property measurement step, silicon system The thin film transistor according to claim 17, characterized in that it is an energy irradiation step or a heat treatment step for a silicon system in addition thereto. The manufacturing method of the language.

22. The thin film formation step, physical property measurement step, energy beam irradiation step or heat treatment step in addition to these steps are performed as follows.

Silicon-based thin film for silicon, silicon'germanium, silicon, germanium, and at least one of carbon as semiconductors Forming Step, Silicon System Physical Property Measurement Step, Silicon System Energy Line Irradiation Step or Silicon In addition 19. The method for producing a thin film transistor according to claim 18, wherein the method is a heat treatment step for a power system.

23. A source region formed on an insulating substrate and composed of a drain region, a channel region interposed between the source region and the drain region. Semiconductor thin film

A gate electrode disposed directly above the channel region;

A gate insulating film interposed between the channel region and the gate electrode, a source electrode electrically connected to the source region,

In a top gate type thin film transistor having a drain electrode electrically connected to a drain region,

The gate electrode comprises a first sub-gate electrode formed of a high melting point metal formed on the gate insulating film, and a low-resistance metal formed on the first sub-gate electrode. And the second subgate electrode Top gate type thin film transistor characterized by the following characteristics.

24. The top gate thin film transistor according to claim 23, wherein the refractory metal is molybdenum or an alloy containing molybdenum. Transistor.

25. The top gate type according to claim 23, wherein the high melting point metal is a tungsten or an alloy containing the tungsten. Thin-film transistor.

26. The top gate thin film transistor according to claim 23, wherein a polycrystalline silicon having a high impurity concentration is used in place of the high melting point metal. Star.

27. The top gate according to claim 23, wherein the low-resistance metal is aluminum or an alloy containing aluminum. Type thin film transistor.

28. A first step of forming a semiconductor thin film on an insulating substrate, and forming a gate insulating film on the semiconductor thin film and forming a first sub-gate on the gate insulating film. A second step for forming the electrodes;

The first sub-gate electrode, the gate insulating film, and the semiconductor thin film are subjected to a first patterning process by photolithography and etching. A third step of machining into a first island shape by

The first sub-gate electrode and the gate insulating film are formed on a second island by a second non-photographing process by photographing and etching. Condition And the fourth step

By using the first subgate electrode as a mask and implanting impurities into the semiconductor thin film, a source region, a drain region, and a channel are formed in the semiconductor thin film. A fifth step to form the cell region,

Forming a source electrode electrically connected to the source region, a drain electrode electrically connected to the drain region, the first subgate electrode A sixth step of forming a second subgate electrode electrically connected to the

A method for manufacturing a top gate type thin film transistor, characterized by comprising:

29. Instead of the fourth step, in photolithography and etching, only the first sub-gate electrode is replaced with a second island-shaped electrode. 29. The method for producing a top gate type thin film transistor according to claim 28, characterized by being processed into a thin film.

30. The first step forms an amorphous silicon thin film on an insulating substrate, and crystallizes the amorphous silicon thin film to form a semiconductor layer. 29. The method for manufacturing a top gate type thin film transistor according to claim 28, wherein all the crystalline silicon thin films are formed on an insulating substrate.

3 1. The first step forms an amorphous silicon thin film on an insulating substrate, and crystallizes the amorphous silicon thin film to form a semiconductor layer. 30. The method for producing a top gate type thin film transistor according to claim 29, wherein all the crystalline silicon thin films are formed on an insulating substrate.

3 2. The first subgate electrode is made of a high melting point metal, and the second subgate electrode, the source electrode and the drain electrode are both made of a low resistance metal. 29. The method for producing a top gate type film transistor according to claim 28, characterized by:

33. The top gate thin film transistor according to claim 28, wherein the refractory metal is molybdenum or an alloy containing molybdenum. Method of manufacturing transistors.

34. The method according to claim 28, wherein the refractory metal is a tungsten or an alloy containing the tungsten. Method of manufacturing thin film transistor.

35. The top gate thin film transistor according to claim 28, wherein a polycrystalline silicon having a high impurity concentration is used in place of the refractory metal. Star manufacturing method.

36. The topgate type according to claim 28, wherein the low-resistance metal is aluminum or an alloy containing aluminum. Manufacturing method of thin film transistor.

37. The top according to claim 1, wherein a plurality of signal lines and a plurality of control lines intersecting the signal lines are arranged, and each of the tops according to claim 1 is located near each intersection of the signal lines and the control lines. A gate type thin film transistor is arranged, each signal line is connected to the source electrode of the corresponding thin film transistor, and each control line is connected to the corresponding thin film transistor. The control line and the signal line are connected to the gate electrode of the A top-gate thin-film transistor array having a structure formed on the same insulating substrate together with the thin-film transistor.

At least at the intersection of the control line and the signal line, the control line comprises a four-layer laminated film of a semiconductor layer, an insulating layer, a refractory metal layer, and an interlayer insulating layer. A top gate type thin film transistor array, wherein the top gate type thin film transistor array is characterized by comprising a low resistance metal layer.

38. The top gate thin film transistor according to claim 37, wherein the high melting point metal is molybdenum or an alloy containing molybdenum. Transistor array.

39. The top gate according to claim 37, wherein the refractory metal is a tungsten or an alloy containing the tungsten. Type thin film transistor array.

40. The top gate type thin film transistor according to claim 37, wherein polycrystalline silicon having a high impurity concentration is used in place of the high melting point metal. Transistor array.

41. The top gate type according to claim 37, wherein the low-resistance metal is aluminum or an alloy containing aluminum. Thin film transistor array.

4 2. At least a film forming gas containing at least Si element is introduced into the vacuum chamber of the plasma CVD device, and the film forming gas is reacted by the plasma CVD method. How to form an amorphous silicon film on a substrate And

A method for forming an amorphous silicon film, characterized by reacting the film forming gas under supply rule conditions. 4 3. A film forming gas containing at least Si element is introduced into the vacuum vessel of the plasma CVD apparatus, and the film forming gas is reacted by plasma CVD to form a gas on the substrate. In the method of forming an amorphous silicon film on a substrate,

The above-mentioned film forming gas is diluted with a gas that does not contribute to film forming, and the film forming gas is reacted under supply rule conditions. A method for forming a silicon film.

43. The amorphous structure according to claim 42, wherein the temperature of the substrate on which the amorphous silicon film is formed is set to 300 ° C. or less. A method of forming the silicon film.

45. The amorphous material according to claim 43, wherein the temperature of the substrate on which the amorphous silicon film is formed is set to 300 ° C. or less. A method for forming a silicon film.

46. The film forming gas contains SiH 4 or Si 2H 6, the gas not contributing to the film formation contains at least Ar, and the ratio of the film forming gas is The method for forming an amorphous silicon film according to claim 42, wherein the rate is set to 5% or less.

47. The film forming gas contains SiH4 or Si2H6, 44. The amorphous film according to claim 43, wherein the gas that does not contribute to the film contains at least Ar, and the ratio of the film forming gas is 5% or less. A method for forming a silicon film. 48. The film forming gas contains SiH 4 or Si 2H 6, the gas not contributing to the film formation contains at least Ar, and the ratio of the film forming gas is The method for forming an amorphous silicon film according to claim 44, wherein the rate is set to 5% or less. 49. The film forming gas contains SiH 4 or Si 2H 6, the gas not contributing to the film formation contains at least Ar, and the gas for film formation contains The method for forming an amorphous silicon film according to claim 45, wherein the ratio is set to 5% or less. 50. The amorphous silicon film according to claim 46, wherein the gas not contributing to the film formation contains at least Ar and H2. Forming method.

51. The amorphous silicon film according to claim 47, wherein the gas not contributing to the film formation contains at least Ar and H2. Forming method.

5 2. As the plasma CVD device, a parallel plate type plasma CVD device in which a high frequency electrode and a ground electrode are arranged to face each other is used, and the height of the parallel plate type plasma CVD device is increased. 43. The ammo according to claim 42, wherein the frequency of the frequency power supply is not less than 20 MHz and not more than 100 MHz. A method of forming a silicon film.

5 3. As the plasma CVD device, a parallel plate type plasma CVD device in which a high-frequency electrode and a ground electrode are arranged to face each other is used, and the frequency of the high-frequency power supply of the parallel plate type plasma CVD device is adjusted. The method for forming an amorphous silicon film according to claim 43, wherein the film thickness is not less than 20 MHz and not more than 100 MHz.

54. The method of forming an amorphous silicon film according to claim 42, wherein an inductively-coupled plasma CVD apparatus is used as the plasma CVD apparatus. .

55. The method for forming an amorphous silicon film according to claim 43, wherein an inductively coupled plasma CVD apparatus is used as the plasma CVD apparatus. .

56. The amorphous silicon according to claim 42, wherein an electron cyclotron resonance type plasma CVD apparatus is used as the plasma CVD apparatus. A method for forming a capacitor film.

57. The amorphous fabric according to claim 43, wherein an electron cyclotron resonance type plasma CVD device is used as the plasma CVD device. A method of forming a silicon film.