WO2000060647A1 - Dispositif a structure multicouche, appareil et procede de production de ce dispositif - Google Patents

Dispositif a structure multicouche, appareil et procede de production de ce dispositif Download PDF

Info

Publication number
WO2000060647A1
WO2000060647A1 PCT/JP2000/002246 JP0002246W WO0060647A1 WO 2000060647 A1 WO2000060647 A1 WO 2000060647A1 JP 0002246 W JP0002246 W JP 0002246W WO 0060647 A1 WO0060647 A1 WO 0060647A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
substrate
film
silicon
forming
Prior art date
Application number
PCT/JP2000/002246
Other languages
English (en)
Japanese (ja)
Inventor
Makoto Yamamoto
Mikihiko Nishitani
Hikaru Nishitani
Masahiro Sakai
Masashi Goto
Original Assignee
Matsushita Electric Industrial Co.,Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co.,Ltd. filed Critical Matsushita Electric Industrial Co.,Ltd.
Publication of WO2000060647A1 publication Critical patent/WO2000060647A1/fr

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/54—Apparatus specially adapted for continuous coating

Definitions

  • the present invention relates to an element having a multilayer structure, an apparatus for manufacturing the element, and a method for manufacturing the element.
  • a manufacturing apparatus and a manufacturing method that can be suitably used for reforming a thin film transistor using an excimer laser or the like.
  • a top-gate type thin film transistor applied to an active matrix type liquid crystal display device, a sensor array, a static random access memory (SRAM), and the like.
  • the present invention relates to a manufacturing apparatus and a manufacturing method which can be suitably applied to a transistor, a manufacturing method thereof, and a top gate type thin film transistor array.
  • the present invention relates to a method for easily forming an amorphous silicon film having a low hydrogen concentration in the film by a plasma CVD method at a low temperature. Background technology
  • TFT thin film transistor
  • TFTs that use polycrystalline silicon instead of conventional amorphous silicon as semiconductor thin films have been developed. ing .
  • this polycrystalline silicon for example, strong light absorbed by a semiconductor thin film such as an excimer laser is used for a substrate. Irradiate the amorphous silicon film formed on the microcrystalline silicon film to once melt them and then crystallize or single-crystallize them. A silicon film consisting of a large or small crystal (polycrystalline silicon film), and furthermore, the defects of the formed crystal grains are removed to modify the silicon film. Quality technologies are being developed.
  • a semiconductor layer made of silicon is provided, and the semiconductor layer is isolated in accordance with the position of the pixels on the substrate and the driving circuit (so-called “Yuyu”). Patterning), and furthermore, at a predetermined region of the isolated semiconductor, for example, at or near a connection portion with a source electrode, a drain electrode, and a gate electrode. Injecting specific impurities such as boron (boron, B) and phosphorus (phosphorus, P) directly or through an insulating film, etc., to convert n-type and p-type semiconductors. These devices are formed on the same substrate to create MOS type semiconductor devices.
  • an amorphous film is formed on the substrate by a plasma CVD method.
  • the amorphous silicon film is irradiated with laser light to convert the amorphous silicon film into a polycrystalline silicon film. This crystallization occurs because the energy of the laser light absorbed by the amorphous silicon film is converted into heat, and the temperature inside the thin film rises. This is considered to be a process in which amorphous silicon melts and crystallizes when it is solidified again.
  • the characteristics (crystallinity, crystal grain size, and thus field-effect mobility, etc.) of the formed polycrystalline silicon film depend on the characteristics of the silicon film that absorbs light.
  • Properties The physical properties referred to here are the melting, solidification, and Properties that have an effect on the recrystallization of the material, and specifically depend on the film thickness, the atomic density, the concentration of impurities such as hydrogen contained, etc.) .
  • the film thickness and atomic density are directly related to the heat required for melting, and if the hydrogen content is high, silicon scattering may occur, but not partially. I will.
  • the physical properties of each amorphous silicon film are inspected and measured in advance, and the results are based on the results. It is necessary to take measures such as optimizing the energy density of the laser light to be illuminated.
  • the atomic density and the impurity concentration do not change so much if the deposition conditions are kept constant, but the film thickness directly related to melting varies within a range of several percent.
  • the energy density of the laser beam it is necessary to optimize the energy density of the laser beam to be irradiated according to the thickness of the amorphous silicon film.
  • the accuracy of the order of the microclone or on-strom is required, and the film is usually discharged from the vacuum to the atmosphere once after film formation.
  • the amorphous silicon film is once exposed to room air.
  • a natural oxide film is formed on the surface of the substrate, or a contaminant in the air, especially a strong acid is used in the manufacture of a substrate on which a TFT is formed.
  • the glass fiber in the field is eroded by the water, and the porosity in the glass fiber is contaminated.
  • the crystallization process due to laser irradiation becomes unstable, and the polycrystalline film is mixed with pol as an unintended impurity, and the performance of the device is reduced. Or it may be degraded.
  • the conventional manufacturing apparatus when forming a gate insulating film on the surface after forming a polycrystalline silicon film, the conventional manufacturing apparatus requires a plasma exposure after exposure to the outside air. Since the film is transferred to a CVD device to form an insulating film, an unstable natural oxide film is formed on the surface of the polycrystalline silicon film during transfer, and contamination by atmospheric impurities may occur. It will be done. For this reason, the characteristics of the semiconductor / insulating film interface are also significantly reduced from this aspect, and this is one of the causes of degrading the performance of the thin film transistor. Was.
  • n-type and p-type MOS transistors on the same substrate, a drive circuit and the like are formed on the same substrate as the display portion.
  • This n-type or p-type semiconductor region is formed by injecting so-called impurities (additives for exhibiting the function of a semiconductor) such as lipo-polon into a predetermined semiconductor region. .
  • impurities additive for exhibiting the function of a semiconductor
  • the characteristics of the n-type or p-type semiconductor region strongly depend on the concentration of these implanted impurities and the profile in the thickness direction.
  • this impurity has been implanted through the gate insulating film of silicon as a semiconductor.
  • the insulating film formed by the plasma CVD method or the like varies in thickness between the substrates within a range of several percent. As a result, variations occur in the characteristics of the n-type or p-type semiconductor regions, causing variations in the characteristics of the transistor.
  • the factor that degrades the performance of such a transistor is, for example, that the TFT characteristics exceed 200 cm 2 / V'sec in the field-effect mobility. As they become more powerful, they become more critical. I came.
  • TFTs MOS thin film transistors
  • the structure of the TFT is such that a gate electrode is formed first according to the order of lamination of electrodes and semiconductor layers, and a polycrystalline silicon is formed via a gate insulating film.
  • a bottom gate type in which a film is formed on the upper surface, and conversely, a polycrystalline silicon film is formed first, and the upper surface is formed through a gate insulating film.
  • the gate electrode is classified into a top gate type which forms a gate electrode. When the two are compared, miniaturization and reduction of parasitic capacitance by the cell line structure can be easily achieved from the viewpoint of the device, and the manufacturing process can be easily performed.
  • the top-gate type which has few restrictions on, is advantageous.
  • the surface is not exposed to the air and is in a high vacuum.
  • FIGS. 29 and 30 A typical top gate type thin film transistor manufacturing process (referred to as the first conventional example) is shown in FIGS. 29 and 30. It is shown .
  • 500 is an insulating substrate
  • 501 is a semiconductor thin film
  • 502 is a gate oxide film
  • 503 is a gate electrode
  • 504 is a semiconductor.
  • Source region, 505 is a drain region
  • 506 is a channel region
  • 507 is an interlayer insulating film
  • 508 is a source electrode
  • 509 is a drain.
  • a gate insulating film is formed on a semiconductor thin film 501 from the state shown in FIG.
  • FIG. 29 (a) in which a semiconductor thin film 501 is formed on an insulating substrate 500.
  • the semiconductor thin film 501 is removed from the photolithographic graph by etching. There is a process for processing islands by means of ching.
  • the semiconductor thin film 501 and the gate insulating film 502 are formed. Since the interface is exposed to the atmosphere, the interface between the semiconductor film and the gate insulating film cannot be kept clean.
  • a second conventional example shown in Fig. 31 has been proposed.
  • a semiconductor thin film 501 and a gate insulating film 502 are formed continuously (FIG. 31 (a)), and then both are processed into an island shape.
  • a gate electrode 503 is formed (FIG. 31 (b)), whereby the interface between the semiconductor thin film 501 and the gate insulating film 502 is exposed to air.
  • the interface between the semiconductor thin film and the gate insulating film can be kept clean without being exposed to the heat.
  • the island-shaped slope 101a of the semiconductor thin film 501 is exposed.
  • FIG. 31 is a cross section perpendicular to the cross section including the source region, the channel region, and the drain region, and including the channel region (see FIG. 30 (b) as an example). Then, the channel Figure 30 (b) shows a cross section perpendicular to the plane of the figure including the region).
  • TFTs Thin-film transistors
  • the polysilicon film used is formed on the surface of the amorphous silicon film by a laser mask. It is formed by irradiating a laser beam by the Niel method and melting and crystallizing it.
  • the amorphous silicon film irradiated with the laser has a hydrogen concentration of 3 at% or less in the film.
  • the reason for this is that when an amorphous silicon film containing a large amount of hydrogen in the film is laser-annealed, the laser irradiation causes The temperature of the polysilicon film rises rapidly, causing the hydrogen in the film to boil and the film surface to become rough, making the film unsuitable for a TFT. That's it.
  • the method of forming the amorphous silicon film includes a normal pressure CVD method, a reduced pressure CVD method, a plasma CVD method, and the like.
  • the plasma CVD method is 40%. It is suitable in that processing at a low temperature of 0 ° C or less is possible.
  • an amorphous silicon film formed at a substrate temperature of about 250 "C by the plasma CVD method has a hydrogen content of 10 to 20 at%. Therefore, before the crystallization is performed by irradiating the amorphous silicon film with the laser by the laser annealing method, the laser annealing method is used.
  • Morphy Silicon A method for reducing the hydrogen content in a film by a plasma CVD method without performing a step of desorbing hydrogen in the film is disclosed in Japanese Patent Application Laid-Open No. Heisei 9-1134. 8 Disclosed in 8.2. In this technique, the substrate is heated to 400 ° C., and thermal energy is used to desorb hydrogen in the film.
  • the amorphous silicon film is formed by a conventional plasma CVD method, when the substrate temperature, which is a general condition, is not more than 300, the amorphous silicon film is formed. Since the fluorine-containing silicon film may contain 10 to 20% of hydrogen, a step of desorbing hydrogen from the film is required.
  • the substrate temperature is heated to about 400 ° C to highly dilute the raw material gas.
  • an amorphous silicon film having a low hydrogen content is obtained, and the step of desorbing hydrogen in the film is not required.
  • the microcrystallized film must be remelted by a laser anneal, and accordingly, As a result, higher energy is required than when laser annealing a film in an amorphous state, and the manufacturing efficiency is reduced. Disclosure of the invention
  • the first purpose of the present invention is to make it possible to manufacture a thin film transistor having a MOS type structure in a clean atmosphere by adapting to the conditions for forming an amorphous semiconductor film. This is what we did.
  • the purpose of the second invention group is to overcome the above-mentioned problems of the prior art, to clean the interface between the semiconductor thin film and the gate insulating film, and to solve the problem of contact between the semiconductor thin film and the gate electrode.
  • An object of the present invention is to provide a top gate type thin film transistor which does not occur and a method for manufacturing the same.
  • Another object of the second invention group is to reduce the resistance of the wiring (especially, the signal line) and to carry out the thin film transistor suitably for a large liquid crystal panel or the like. This is to provide a language evening array.
  • the purpose of the third invention group is to make use of efficiently generated high energy particles so that even if the substrate temperature is low, the amorphous silicon is used.
  • An object of the present invention is to provide a method of forming an amorphous silicon film which can reduce the hydrogen content in the film.
  • the invention according to claim 1 of the present invention relates to a method for manufacturing an element having a multilayer structure by a plurality of film forming steps.
  • One of a plurality of film forming steps wherein at least one film is formed by a first film forming step and a first film forming step is obtained by the first film forming step.
  • the first step, the measuring step, and the second step are each performed in a predetermined clean atmosphere.
  • the processing in the second step in consideration of the variation is not performed. It will be done. Therefore, the second process is performed under optimal conditions, and in addition, the first process, the measurement process, and the second process are performed in a clean atmosphere. As a result, it is possible to manufacture a device having a multilayer structure with improved quality.
  • the element having a multilayer structure examples include a semiconductor element such as TFT, a semiconductor element having an LDD (Lightly Doped Drain) structure, and an element having an optical multilayer film.
  • the first step is a process of forming an amorphous silicon film
  • the second step is a polysilicon process. This is applicable to the reforming treatment of the membrane.
  • the first step is a first ion implantation process for manufacturing an LDD structure
  • the second step is a process for manufacturing an LDD structure.
  • the second ion injection process is applicable.
  • the first step corresponds to the first film formation processing
  • the second step corresponds to the second film formation processing.
  • the invention according to claim 2 is the method for manufacturing a device having a multilayer structure according to claim 1, wherein the process in the second step is a film forming process.
  • the process in the second step is a film reforming process. It is characterized by
  • the invention according to claim 4 is an apparatus for manufacturing an element having a multilayer structure, and a film forming means for forming at least one of a plurality of films, Means for measuring predetermined physical properties of the film obtained by the film forming means, and processing of the film in accordance with measurement conditions determined based on the measurement results of the measuring means And a transport means for transporting the film forming means, the measuring means, and the processing means to each other, wherein the film forming means, the measuring means, and the processing means are provided. , And the transport means are characterized in that the respective processes are performed under a predetermined clean atmosphere.
  • the processing of the processing means is performed based on the measurement result of the measuring means, the processing can be performed with high accuracy. Furthermore, since the treatment by each means is performed in a clean atmosphere, a high-quality element can be obtained.
  • the processing in the processing means is a film forming processing.
  • the processing in the processing means is a film reforming processing.
  • the invention according to claim 7 or claim 8 is a method in which the substrate is placed in a predetermined clean atmosphere determined from the formation of the thin film, for example, at room temperature or under reduced pressure of hydrogen.
  • Semiconductors supplied from semiconductor supply means installed in a place outside the clean atmosphere or in a place with a clean atmosphere (more precisely, the raw material gas) are used on the substrate.
  • the substrate was placed in a predetermined clean atmosphere, for example, room temperature or vacuum, determined by a physical property measurement method using light (including ultraviolet rays and infrared rays).
  • a physical property measurement method using light including ultraviolet rays and infrared rays.
  • Sources including, Les laser light (source)
  • the property value measurement means you measured using the light receiving device measuring The physical properties of Jo Luo or Ru nature modifying et, channel ghee line, eg if 3 0 0 m J / cm 2 of d, channel ghee density 3 0 0 H z of d key sheet Ma les monodentate (1) an amorphous semi-conductor; an energy beam irradiating means for irradiating the conductor for its modification; and (3) receiving the substrate from the outside to form an amorphous semiconductor layer on its surface.
  • the substrate is not exposed to the external atmosphere at least in each of the processes of forming a thin film, measuring physical properties, and irradiating with energy rays, and the thin film forming means, the physical property measuring means, and the energy It is characterized in that it is properly mounted on the ruby ray irradiation means, and has a clean atmosphere holding type transfer means to be removed after the treatment.
  • the thin film forming means is, in a state where the substrate is horizontally set in a predetermined clean atmosphere determined by the thin film formation, and in principle, using a mask over the entire surface of the substrate, in some cases. Only at the predetermined position, the amorphous semiconductor thin film is formed by using a semiconductor supplied from a semiconductor supply means provided in a room kept in the clean atmosphere or a place outside the apparatus. It is formed by evening rings.
  • the physical property value measuring means measures physical property values such as density and film thickness related to modification of the amorphous semiconductor thin film formed on the substrate by irradiation with energy rays, and uses a laser beam.
  • the substrate is installed horizontally in a predetermined clean atmosphere, for example, at room temperature and in a vacuum, determined from the physical property measurement using the laser, the substrate is installed outside the measurement atmosphere. Measure using a laser source or L / E converter.
  • Enel ghee beam irradiation means E Ne-saving clear distinction of the measured physical property value or Jo Luo or Ru nature, if example embodiment 3 0 0 m J / cm: example d key sheet Ma, single
  • the first light of e For example, an optical system is used to form a beam, and an amorphous semiconductor patterned as necessary on a substrate held in a predetermined state in a predetermined atmosphere is used. Then, this beam is irradiated while scanning the substrate in order.
  • a so-called clean-atmosphere-holding transporting device having a so-called port arm, push-out machine, motor, etc., forms a thin-film polycrystalline semiconductor layer on its surface.
  • the substrate is received directly or indirectly from the outside via an intermediary means, and the substrate is contaminated at least in the subsequent processes of thin film formation, physical property measurement, and energy beam irradiation.
  • the substrate is contaminated at least in the subsequent processes of thin film formation, physical property measurement, and energy beam irradiation.
  • physical property values, measuring means, and energy beam irradiation means in order while maintaining an appropriate atmosphere without exposing to an external atmosphere. Install and remove after processing. (Of course, after the previous processing is completed, it may be installed in the equipment for the next processing.) Therefore, if necessary, the work room for these processings It will be transported inside and unloaded after processing.
  • each of the above-mentioned means performs necessary exhaust and decompression of the room or space where the substrate is installed, and fills with an inert gas or hydrogen gas.
  • the thin-film transistor manufacturing apparatus also has a means such as a silicon thin-film notating as necessary.
  • hydrogen is expelled from the amorphous semiconductor formed on the substrate, and the hydrogen is similarly expelled to the dangling ponds of the polycrystalline semiconductor.
  • a predetermined atmosphere determined by heat treatment to achieve good function as a transistor, such as hydrogen bonding, for example, in a nitrogen atmosphere at 1 atm.
  • a heat treatment method in which a semiconductor thin film is held for a certain period of time at a temperature of 0 ° C (in the case of the latter, at 350 ° C in H 2 ) for each substrate (including a plurality of substrates simultaneously).
  • the clean atmosphere holding type transfer means does not expose to the external atmosphere at least after the previous processing such as the formation of the amorphous semiconductor thin film, and further mounts the substrate on the heat treatment means. And heat treatment that can be removed (unloaded) after the heat treatment. That features a and this you are have a transport small means.
  • the heat treatment means has a heater, a predetermined atmosphere gas filling and exhaust means, etc., thereby purging hydrogen from the amorphous semiconductor formed on the substrate.
  • Predetermined atmosphere determined by heat treatment to achieve good function as a transistor element, such as bonding of hydrogen to the dangling band of a polycrystalline semiconductor.
  • the semiconductor thin film is heat-treated by holding the semiconductor thin film for each substrate for a predetermined time.
  • the transfer means for heat treatment of the clean atmosphere holding type transfer means should not be exposed to the external atmosphere at least, and at least one (including, if necessary, a plurality of) substrates to the heat treatment means. Installation and removal after heat treatment are possible.
  • a device for forming a thin film transistor on a given substrate for example, a device for cleaning a substrate or a device for manufacturing a thin film transistor. It has a loading / unloading means for receiving the substrate as a target of processing to form a semiconductor thin film and passing the processed substrate to the outside.
  • a thin film forming means At the outer periphery, at least a thin film forming means, a physical property measuring means, an energy beam irradiating means, a carrying-in / out means or a heat treatment means in addition to these are provided.
  • This is a clean atmosphere holding type transfer means, and holds the board to facilitate the installation and removal of the board to and from each means arranged on the outer periphery.
  • a rotatable-type conveying small means rotatable and rotatable, and the physical property value measuring means Is characterized in that it is a horizontal holding type physical property measuring means for accurately holding the board horizontally when measuring the physical property values of the above-mentioned board.
  • the loading / unloading means which has a gate valve and, if necessary, a vacuum pump, is used to receive a substrate for forming a semiconductor thin film on its surface from the outside of the device.
  • the clean atmosphere holding type transport means is a center-position type clean atmosphere holding type transport means.Thus, the thin film forming means and physical property value measurement are performed through a partition door or the like as necessary on the outer periphery of the conveyer. Means, energy beam irradiation means, loading / unloading means or, in addition to these, heat treatment means (and the room where the substrate is installed as a part of the means for that purpose) ).
  • a viewing window, a window through which light beams for processing pass, and other valves will be installed on the side walls that do not face the transfer chamber of each room. It will be easier to kick.
  • the rotatable transfer sub-means installs or removes a substrate in each means for each processing, or in a room for the processing.
  • the arm, push-out and pull-out mechanism and magic hand for this purpose are structured so that they rotate while holding the substrate.
  • the physical property value measuring means is a mechanism that holds the board horizontally and accurately when measuring the physical property value of the board, it is necessary to attach the device itself, mount the board, Furthermore, the measurement itself becomes easier.
  • Amorphous or ultrafine crystalline silicon formed in principle on a non-alkali glass substrate
  • the thin film forming means, the physical property measuring means, the energy beam irradiating means or the heat treatment means in addition thereto may be a silicon based thin film forming means, a silicon based physical property measuring means, a silicon based Energy irradiation means for the silicon system or heat treatment means for the silicon system in addition to these, each of which is made of silicon or silicon as a semiconductor 'Germanium, silicon' Exhibits functions such as forming at least one of germanium and carbon on a substrate.
  • the invention according to claim 23 of the second invention is formed on an insulating substrate, and includes a source region, a drain region, a source region, and a drain.
  • a semiconductor thin film composed of a channel region interposed between the regions, a gate electrode disposed immediately above the channel region, a channel region and the gate region;
  • a gate insulating film interposed between the source electrodes, a source electrode electrically connected to the source region, and a drain electrically connected to the drain region.
  • the gate electrode is made of a high melting point metal formed on the gate insulating film.
  • a second electrode made of a low-resistance metal formed on the first electrode; and a second electrode made of a low-resistance metal formed on the first electrode. It characterized and this that is whether we structure a gate electrode.
  • the gate electrode has a two-layer structure of the first sub-gate electrode and the second sub-gate electrode, so that the semiconductor thin film and the gate insulating film are formed. Continuous film formation is possible, and a top-gate type thin film transistor having high performance and high reliability is configured.
  • the first sub-gate electrode is made of a high melting point metal and the second sub-gate electrode is made of a low-resistance metal, so that the gate caused by heat treatment for activation or the like can be obtained. Since the electrode is prevented from being dissolved, the reliability of the top gate type thin film transistor is improved.
  • the invention according to claim 24 is the top gate thin film transistor according to claim 23, wherein the refractory metal is molybdenum or molybdenum. It is characterized by being an alloy containing iron.
  • the high melting point metal as molybdenum or an alloy containing molybdenum, good transistor performance can be obtained.
  • the refractory metal is a tungsten or a tan. It is characterized by being an alloy containing dust.
  • the refractory metal as a tungsten or an alloy containing a tungsten, good transistor performance can be obtained.
  • An invention according to claim 26 is the top gate thin film transistor according to claim 23, wherein a polycrystalline silicon having a high impurity concentration is used instead of the refractory metal. It is characterized by the use of
  • the invention according to claim 27 is the top gate type thin film transistor according to claim 23, wherein the low-resistance metal is made of aluminum or aluminum. It is characterized by being an alloy containing aluminum.
  • Good transistor performance can be obtained by using low-resistance metal as aluminum or an alloy containing aluminum.
  • the invention according to claim 28 is a method of manufacturing a top gate type thin film transistor, wherein a first step of forming a semiconductor thin film on an insulating substrate is provided. A second step of forming a gate insulating film on the semiconductor thin film and forming a first subgate electrode on the gate insulating film; and a first step of forming a first subgate electrode on the gate insulating film.
  • the first electrode, the gate insulating film, and the semiconductor thin film are subjected to a first notching process by photolithography and etching to form a first electrode.
  • the third step of processing into an island shape, and the first subgate electrode and the gate insulating film are formed by photographing and etching.
  • a source region, a drain region, and a channel region are formed in the semiconductor thin film.
  • the interface between the semiconductor thin film and the gate insulating film is manufactured continuously. Further, the island-shaped sloped surface of the semiconductor film and the second gate electrode are insulated from each other by the inter-layer insulating film, and thus do not come into contact with each other. Accordingly, it is possible to manufacture a top gate type thin film transistor having improved transistor characteristics.
  • An invention according to claim 29 is a method for manufacturing a top gate thin film transistor according to claim 28, wherein the fourth step is replaced with a photo transistor instead of the fourth step. In the lithography and the etching, only the first subgate electrode is processed into a second island shape.
  • ion implantation is performed through the gate insulating film, so that the island-shaped sloped surface of the semiconductor thin film is not contaminated by impurities during ion implantation. It's good, it's good.
  • the invention according to claim 30 or 31 is directed to a method of manufacturing a top gate type thin film transistor according to claim 28 or 29, wherein the first step is performed. Forming an amorphous silicon thin film on an insulating substrate, crystallizing the amorphous silicon thin film, and insulating the crystalline silicon thin film as a semiconductor layer. It is characterized in that it is formed on a conductive substrate.
  • a TFT having good mobility and other characteristics can be manufactured.
  • An invention according to claim 32 is a method for manufacturing a top-gate thin film transistor according to claim 28, wherein the first subgate electrode is a high melting point metal. Wherein the second sub-gate electrode, the source electrode, and the drain electrode are both made of a low-resistance metal.
  • the first subgate electrode functions as a metal mask at the time of ion implantation for impurity implantation.
  • the first subgate electrode is made of a high melting point metal, partial melting of the first subgate electrode due to heat generated at the time of ion implantation is prevented. As a result, no impurity contamination occurs in the channel region.
  • the temperature of the activation treatment after the implantation can be set high within a range not higher than the heat-resistant temperature of the glass substrate.
  • the invention according to claim 33 is the method for manufacturing a top gate thin film transistor according to claim 28, wherein the refractory metal is molybdenum or molybdenum. It is characterized by being an alloy containing molybdenum.
  • the invention according to claim 34 in the method for manufacturing a top gate thin film transistor according to claim 28, wherein the refractory metal is a tungsten. Is characterized by being an alloy containing tungsten.
  • the invention according to claim 35 provides a method of manufacturing a top gate type thin film transistor according to claim 28, wherein the high-melting-point metal is replaced by a metal. It is characterized by the use of polycrystalline silicon with a high purity.
  • the impurity concentration when the impurity concentration is high, the resistance becomes low, so that a thin-film transistor having excellent characteristics can be manufactured.
  • the impurities when impurities are implanted into the source / drain region, the impurities can be implanted into the polycrystalline silicon as the gate electrode at the same time. It will be easier.
  • the invention according to claim 36 is the method for manufacturing a top gate thin film transistor according to claim 28, wherein the low-resistance metal is aluminum. Is characterized by being an alloy containing aluminum.
  • a plurality of signal lines and a plurality of control lines crossing the signal lines are wired, and each of the plurality of signal lines is arranged near each intersection of the signal lines and the control lines.
  • Each of the signal lines is connected to the corresponding thin-film transistor source electrode, and each control line is connected to the corresponding thin-film transistor.
  • a top gate type structure in which the control lines and signal lines are connected to the gate electrode of the transistor and the control line and the signal line are formed on the same insulating substrate together with the thin film transistor.
  • the control line is formed of a semiconductor layer, an insulating layer, a high melting point metal layer, and an inter-layer.
  • the signal line is made of a four-layer laminated film of an insulating layer, and the signal line is made of a low-resistance metal layer. It shall be the feature.
  • control lines are also wired with a low-resistance metal except at the intersections with the signal lines, they are preferable as a large-sized and high-definition TFT array.
  • the low-resistance metal is a material having a low melting point, it may be formed only after the activation of impurity ions after ion implantation, so that the heating temperature during activation is low. This is an optimal configuration that relaxes the upper limit.
  • An invention according to claim 38 is the top gate type thin film transistor array according to claim 37, wherein the refractory metal is molybdenum. Is characterized by being an alloy containing molybdenum.
  • the invention according to claim 39 is the top gate thin film transistor array according to claim 37, wherein the refractory metal is a tungsten or a tungsten alloy. It is characterized by being an alloy containing tungsten.
  • a top gate type thin film transistor transistor array according to the 37th aspect, wherein a polycrystalline material having a high impurity concentration is used in place of the refractory metal. It is characterized by the use of silicon.
  • the low-resistance metal is aluminum. Or an alloy containing aluminum.
  • the hydrogen on the outermost surface of the amorphous silicon film is not only absorbed by the thermal energy from the substrate, but also by the physicochemical energy from the high energy particles in the plasma. It has been newly found that desorption can be performed by energy.
  • the frequency of the high frequency power supply is higher than the normal 13.56 MHz (for example, 2 MHz). 7.12 MHz) or using low-pressure, high-density plasma (for example, inductively coupled plasmas or electron cyclotron resonance plasmas). . Therefore, even if the substrate temperature is low, the hydrogen content in the amorphous silicon film can be improved even if the substrate temperature is low by using the efficiently generated high energy particles. It is possible to reduce the amount.
  • a third invention group has been made.
  • the specific configuration is as follows.
  • a film forming gas containing at least Si element is introduced into a vacuum vessel of a plasma CVD apparatus, and the film forming gas is subjected to a plasma CVD method.
  • At least a film forming gas containing at least Si element is introduced into a vacuum vessel of a plasma CVD apparatus, and the film forming gas is subjected to a plasma CVD method.
  • the film forming gas is diluted with a gas that does not contribute to the film formation. It is characterized by reacting gas under supply rule conditions.
  • a polymerization reaction in the gas phase under a plasma atmosphere can be suppressed, and the film forming speed is restricted. Due to the regulated supply law condition (supply law region), the decomposition of the film forming gas is promoted and the high energy particles are increased in the plasma. . Therefore, the physical surface of the high-energy particles with respect to the film surface activates the film-forming outermost surface during the film formation and removes hydrogen from the film surface. Separation can be promoted. In this way, an amorphous silicon film having a low hydrogen concentration in the film can be formed, and the conventional amorphous silicon film can be formed. This eliminates the need for performing a step of desorbing hydrogen from the film, thereby improving production efficiency.
  • the invention according to claim 44 or 45 is characterized in that the temperature of the substrate forming the amorphous silicon film is 300 ° C. or less.
  • an amorphous silicon film is formed at a temperature of 300 ° C. or less, so that the amorphous silicon film is finely formed. It does not crystallize, does not reduce throughput, and therefore does not reduce production efficiency. Also, since an amorphous silicon film is formed on the substrate at 300 ° C or lower, it is possible to use a material with low heat resistance as the substrate. Wear .
  • the lower limit of the substrate temperature is room temperature (about 25 ° C.) in consideration of an actual manufacturing process.
  • the invention of claim 4 6-4 9 wherein, in Tsu Oh in A molar off ⁇ mortal Li co down film formation method, the film forming gas S i H 4 or the S i 2 H beta
  • the gas that does not contribute to the film formation contains at least Ar, and the ratio of the gas for film formation is 5% or less.
  • the S i H 4 or Ru Oh in the film forming gas is 5% or less concentration of S i 2 ⁇ ⁇ , and this you increase the concentration of Oh Ru A r gas you do not want to contribute to the film formation and One by the, reduces the deposition rate of the a molar off ⁇ mortal Li co-down film, or, excited in the bra's Ma a r and S i H 2 La di mosquito Lumpur and S i Since high energy particles such as H radicals increase, hydrogen present on the outermost surface during the formation of the amorphous silicon film is caused by the high energy particles.
  • the hydrogen concentration in the film is 3 at% or less.
  • a silicon film can be formed. Therefore, it is not necessary to perform a step of desorbing hydrogen in the amorphous silicon film as in the conventional case, and the production efficiency is improved.
  • the above-mentioned Ar is a gas in the inert gas, in particular, a gas in which the state of energy tends to become high in the plasma, and accordingly, the amorphous gas is used.
  • Hydrogen present on the outermost surface during the formation of the silicon film is desorbed by the physicochemical reaction by the Ar.
  • the invention according to claim 50 or 51 is characterized in that the gas that does not contribute to the film formation contains at least Ar and H 2.
  • the invention according to claim 52 or 53 uses a parallel plate type plasma CVD device in which a high frequency electrode and a ground electrode are arranged to face each other as a plasma CVD device, wherein the parallel plate type plasma CVD device is used.
  • the device is characterized in that the frequency of the high-frequency power supply of the device is set to 20 MHz or more and 100 MHz or less.
  • the frequency of the high-frequency power source is set higher than the normal 13.56 MHz in the vacuum vessel of the parallel plate type plasma CVD apparatus, so that plasma can be generated. Therefore, high energy particles can be efficiently generated, and the physicochemical reaction caused by the high energy particles can reduce the number of high-energy particles on the substrate. The hydrogen concentration in the silicon film can be reduced.
  • the frequency of the high-frequency power supply of the plasma CVD apparatus is set to be 20 MHz or more and 100 MHz or less, and the frequency of the high-frequency power supply is set to be higher than the normal 13.56 MHz.
  • the plasma density is increased, and high-energy particles in the plasma can be efficiently generated.
  • the frequency of the high-frequency power supply is lower than 20 MHz, high-energy particles are not efficiently generated, and the frequency of the high-frequency power supply is lower than 100 MHz.
  • the dischargeable range is narrow, and the device configuration Restrictions are increased. Therefore, the power supply frequency of the high-frequency power supply is not less than 20 MHz and not more than 100 MHz.
  • the high frequency power supply has a frequency of 27.12 MHz.
  • the invention according to claim 54 or 55 is characterized in that an inductively coupled plasma CVD device is used as the plasma CVD device.
  • the invention according to claim 56 or 57 is characterized in that an electron cyclotron resonance type plasma CVD device is used as the plasma CVD device.
  • FIG. 1 is a diagram showing a schematic configuration of a thin-film transistor manufacturing apparatus according to Embodiment 11;
  • FIG. 2 is a block diagram showing an electric configuration of a thin-film transistor manufacturing apparatus according to Embodiment 1-1.
  • FIG. 3 is a diagram showing an example of a configuration of a measurement chamber of the thin-film transistor manufacturing apparatus according to Embodiment 11-11.
  • FIG. 4 is a diagram showing another example of the configuration of the measurement chamber of the thin-film transistor manufacturing apparatus according to the embodiment 11;
  • FIG. 5 shows changes in the cross-section and configuration of the substrate and the transistor as the processing progresses in the thin-film transistor manufacturing apparatus and method according to Embodiment 11-11.
  • FIG. 4 is a diagram showing another example of the configuration of the measurement chamber of the thin-film transistor manufacturing apparatus according to the embodiment 11;
  • FIG. 5 shows changes in the cross-section and configuration of the substrate and the transistor as the processing progresses in the thin-film transistor manufacturing apparatus and method according to Embodiment 11-11.
  • FIG. 6 shows a change in a substrate, a cross-section of a transistor, and a configuration as the processing in the thin-film transistor manufacturing apparatus and method according to the embodiment 1-1 proceeds. It is a figure.
  • FIG. 7 is a diagram showing a schematic configuration of a thin-film transistor manufacturing apparatus according to the first to eleventh embodiments.
  • FIG. 8 is a sectional view showing the structure of the top gate type TFT according to the embodiment 2-1.
  • FIG. 9 is a cross-sectional view showing a manufacturing process of the top gate type TFT according to the embodiment 2-1.
  • FIG. 10 is a cross-sectional view showing a manufacturing step of the top gate type TFT according to the embodiment 2-1.
  • FIG. 11 is a plan view showing a manufacturing process of the top gate type TFT according to the embodiment 2-1.
  • FIG. 12 is a plan view showing a manufacturing process of the top gate type TFT according to the embodiment 2-1.
  • FIG. 13 is a cross-sectional view showing a manufacturing process of the top gate type TFT according to the embodiment 2-2.
  • FIG. 14 is a cross-sectional view showing a manufacturing step of the top gate type TFT according to the embodiment 2-2.
  • Figure 15 is a cross-sectional view showing the end surfaces A and B of the gate electrode and the gate insulating film.
  • FIG. 16 is a cross-sectional view showing a manufacturing process of a CM0S-TFT using the thin-film transistor according to Embodiment 2-3.
  • FIG. 17 shows a CM using the thin-film transistor according to the second to third embodiments.
  • FIG. 3 is a cross-sectional view showing a manufacturing process of OS—TFT.
  • FIG. 1.8 is a cross-sectional view showing a manufacturing process of CMSOTSFT using the thin-film transistor according to Embodiment 2-4.
  • FIG. 19 is a cross-sectional view showing a manufacturing process of CMOS-TFT using the thin-film transistor according to Embodiments 2-5.
  • FIG. 20 is a circuit diagram showing a configuration of a TFT array composed of thin-film transistors according to Embodiments 2-5.
  • FIG. 21 is a cross-sectional view of a signal line 15 5 (control line 15 6) in Embodiment 2-5.
  • FIG. 22 is a cross-sectional view of an intersection of a signal line 15 5 and a control line 15 6 in Embodiment 2-5.
  • FIG. 23 is a cross-sectional view showing a manufacturing process of the TFT array according to Embodiment 2-5.
  • FIG. 24 is a cross-sectional view showing a manufacturing process of the TFT array according to Embodiment 2-5.
  • FIG. 25 is a schematic diagram showing the configuration of a parallel plate type plasma CVD apparatus used in the method according to Embodiment 3-1.
  • FIG. 26 is a graph showing the relationship between the concentration of SiH 4 and the concentration of hydrogen in the amorphous silicon film.
  • Figure 27 is a graph showing the relationship between the RF power and the deposition rate of the amorphous silicon film.
  • Figure 28 is a graph showing the relationship between the RF power and the hydrogen concentration in the amorphous silicon film.
  • FIG. 29 is a cross-sectional view showing a manufacturing process of the first conventional example.
  • FIG. 30 is a cross-sectional view showing a manufacturing process of the first conventional example.
  • FIG. 31 is a cross-sectional view showing a manufacturing process of the second conventional example.
  • the first invention relates to a thin film transistor manufacturing apparatus and manufacturing method, particularly to the reforming of a thin film transistor using an excimer laser or the like. About.
  • FIG. 1 is an overall configuration diagram of an apparatus for manufacturing a thin film transistor according to Embodiment 11;
  • FIG. 2 is a thin film transistor according to Embodiment 11;
  • FIG. 2 is a block diagram showing an electrical configuration of the manufacturing apparatus of FIG.
  • the valve V for supplying and shutting off gas and the pump P for forced exhaust are shown only for the room 7;
  • the other chambers 1, 2, 3, 4, 5, and 6 are also provided with similar valves, valves V and pumps P, respectively.
  • this manufacturing apparatus was equipped with a transport roller for transporting the substrate, a push-out device, and a mouth port 10 having a gripping hand at the center. Transport room 1 is installed.
  • the transfer chamber 1 has a structure in which six chambers 2 to 7 can be attached around the transfer chamber 1 via gates 92 to 97.
  • the mouth port 10 is on a motor-equipped base (not shown), and is rotated in the direction of the room for each processing by the rotation of the motor. It is capable of combing, that is, rotatable. As a result, it is possible to simultaneously process different substrates in each room, and to simultaneously process a plurality of substrates in the present manufacturing apparatus.
  • each of the chambers 2 to 7 has a function of exhausting at least the internal air to reduce the pressure, and the processing performed in that room depends on the processing. It has a function to introduce a specific gas from the outside of the room and exhaust it, and also to transfer the gas from the transfer room 1 to the gate 1 through the gate pulp 92-97.
  • the substrate (not shown) carried in by the processing unit 0 is processed under predetermined or unique conditions in each of the chambers 2 to 7, and is again transferred to the transfer chamber 1 in cooperation with the robot 10. It has a function to carry it out.
  • the loading / unloading chamber 2 takes in the substrate to be processed by this equipment from the outside and reduces its atmosphere from the atmosphere, or depressurizes the atmosphere of the substrate that has been processed by this equipment. It has the function of returning from the state to the indoor air and filling with nitrogen. For this purpose, it is connected to pump P, valve V, and various gas supply mechanisms.
  • the pump P, the valve V, and the various gas supply mechanisms are provided separately in the chambers 1, 3 to 7 other than the loading / unloading chamber 2.
  • the two film forming chambers 3 and 4 are connected to a source (gas) supply source outside of the room via a valve V, so that the chamber can be connected to the outside by a plasma CVD method. It functions as a facility and a room for forming an amorphous silicon-microcrystalline silicon film on a substrate or a silicon dioxide film or the like as an insulating film.
  • the deposition methods used in the deposition chambers 3 and 4 are not limited to the plasma CVD method, but must be connected to necessary equipment. It is also possible to use an ECR plasma CVD method, a remote plasma CVD method, or a snow ring ring method.
  • the laser chamber 5 has a quartz window (not shown) on the upper surface through which laser light from the outside can be introduced, and the reforming chamber brought into the room.
  • the substrate on which the amorphous semiconductor thin film is to be irradiated for this purpose is held horizontally, and is determined by the processing conditions such as the density of the laser-energy. It has a function to move at a predetermined speed.
  • the laser light is used for laser reforming (melting, crystallization) for outdoor use.
  • the specified energy density and beam shape is obtained by the optical system 12 having a lens, slit, etc. Is adjusted to As the board moves along a predetermined program, the beam sequentially scans the board surface installed in the laser annealing chamber. Each time the entire surface is illuminated.
  • the laser is irradiated only in a specific area without moving the substrate.
  • the heat treatment chamber 6 has a function to heat-treat the substrate, or more precisely, each thin film formed on its surface at a predetermined temperature and atmosphere. For this reason, the side wall surface is insulated.
  • the heat treatment chamber 6 has an electric heater for heat treatment.
  • the measurement chamber 7 measures predetermined physical properties such as the density of the substrate itself in order to increase the accuracy of the amorphous semiconductor thin film formed on the substrate.
  • predetermined physical properties such as the density of the substrate itself in order to increase the accuracy of the amorphous semiconductor thin film formed on the substrate.
  • the structure is matched to the laser-oscillator and the receiver installed outside the room, for example, quartz for laser light introduction and derivation. It has a window, etc., and has a function to hold the substrate accurately and horizontally to further improve the measurement accuracy. The details of the processing performed in each room when manufacturing a transistor are described.
  • FIG. 3 shows an example.
  • the thin glass (transparent by nature) substrate 21 to be inspected is held horizontally so as not to be distorted, and the substrate 21 in the direction perpendicular to the surface, That is, a light source 1 for film thickness measurement that irradiates a laser beam 34 of a predetermined wavelength such as 350 or 420 nm from directly above through a quartz window 31. 3 and a reflecting mirror 32 and a transmitted light detecting unit 14 provided on the wall surface facing the irradiation direction of the light source unit for film thickness measurement via a quartz window 33.
  • the substrate before and after the silicon thin film is formed and in the case of a large substrate such as 16 inches or 20 inches, the moving mechanism 71 is further used. It is possible to measure the change in the transmittance of each part by moving the substrate, and to accurately measure the thickness of the silicon thin film etc. formed on the substrate. It is possible to ask for it. Note that all the boards are mounted (always) at 7j flat, so there is no need to adjust or correct any changes in the thickness of each board. No.
  • the light source section 13 for film thickness measurement changes the wavelength of light to be irradiated within a certain range by changing the optical system, such as passing through a prism (not shown), or changing the light source. It is also possible to change the wavelength for accurate measurement, and it is also possible to measure physical properties other than film thickness.
  • irradiation with light of a wavelength that is absorbed by a special substance such as hydrogen or that excites a special substance is performed, and the concentration is determined from the absorption rate and the intensity of the excitation light. It is also possible.
  • reference numeral 70 denotes a control circuit.
  • the control circuit 70 includes a system program, a laser output, and other data relating to reforming.
  • Stored ROM 75 and RAM 72 are connected.
  • Ma An operation input means 73 and a light detection section 14 are connected to the control circuit 70. The input from the operation input means 73 and the input from the light detection section 14 are provided. Detected. Data is given.
  • the control circuit 70 includes a plurality of valves V,..., A plurality of pumps P,..., A light source unit 13 for irradiating a single laser beam for measurement, and an anneal Oscillator 11 that irradiates the laser for operation is connected, opens and closes each valve V, drives pump P, lasers the light source section 13 and the oscillator 11 One drive etc. is controlled.
  • Each of the gas supply sources is provided with an on-off valve (not shown), and the on-off valve is controlled by the control circuit 70. ing .
  • FIG. 2 mainly shows a control mechanism for reducing the pressure in the chambers 1 to 7 and a control mechanism for measuring the anneal. However, in a predetermined processing apparatus in each chamber, for example, in the film forming chambers 3 and 4, the operation of the film forming apparatus and the like is controlled by the control circuit 70. .
  • FIG. 4 shows a second example of measuring the physical properties of the main measuring chamber 7.
  • quartz windows 35 and 36 are provided on one pair of opposing side surfaces not facing the transfer room of the measurement room. With this, light of a predetermined wavelength is irradiated at a certain angle through a quartz window 35 in a direction perpendicular to the surface of the substrate 21 accurately placed in a horizontal plane.
  • the physical property measurement light source section 15 that can be used and the physical property measurement light receiving section 16 that detects the irradiating light reflected on the substrate surface through the quartz window 36 are provided. It can be used to measure physical properties.
  • Figure 5 shows the cross-sectional structure of a thin film transistor (element) as it is manufactured. It is a figure showing a state of change.
  • the translucent substrate 21 is loaded into the loading / unloading chamber 2 from the outside.
  • the gas inside the transfer chamber 1 and each of the chambers 2 to 7 arranged around the transfer chamber 1 are exhausted so that the pressure becomes lower than the predetermined pressure in advance except for the transfer chamber 2. It has been done.
  • the substrate 21 cleaned in the room, which has been once cleaned by the HEPA filter, is opened, the gate valve is opened, and the transport port 10 is used. It is moved into the first film forming chamber 3.
  • a gas mixture of TEOS (Tetra Ethyl 0 rtho Si i icate) and oxygen is introduced into the film forming chamber 3, and an underlayer made of a silicon dioxide film is formed on the substrate surface by a plasma CVD method. After forming the coat film to a thickness of 40 O nm, the substrate is moved to the measurement chamber 7 and its transmittance is measured.
  • TEOS Tetra Ethyl 0 rtho Si i icate
  • the substrate 21 is moved to the second film forming chamber 4.
  • a mixed gas of silane and argon is introduced, and an amorphous silicon film is further formed on the undercoat film 22 formed on the substrate.
  • the film 23 is formed with a thickness of about 5 O nm.
  • the substrate is moved to the measurement chamber 7 again, and the transmittance of the substrate after the formation of the amorphous silicon film is measured. Thereafter, the transmittance after the formation of the amorphous silicon film is compared with the transmittance measured before the formation of the amorphous silicon film, and based on the difference between the two values, the formed amorphous silicon film is formed.
  • the thickness of the high-quality silicon film can be calculated with an accuracy of 1 nm or less.
  • the substrate is moved from the measurement chamber 7 to the laser annealing chamber 5, and the conditions most suitable for the previously determined thickness of the amorphous silicon film, particularly the energy density, are determined.
  • this film is converted to a polycrystalline silicon film.
  • the relationship between the film thickness and the laser irradiation conditions is stored in the ROM 75 in advance, and the thickness of the amorphous silicon film is reduced. Even if it is in the range of about 5 to 10%, the variation in silicon properties after melting and recrystallization by irradiation should be suppressed to about 2 to 3%. Is possible. (In the past, this variation could reach 10%.)
  • the substrate is transferred from the laser annealing chamber 5 to the second film forming chamber 4, and the first silicon nitride film of 30 nm thick is formed on the surface of the polycrystalline silicon film.
  • a second insulating film 25 is formed.
  • the gate valve 92 is closed, clean nitrogen gas is introduced into the loading / unloading chamber 2 until the pressure reaches atmospheric pressure, and then the substrate is taken out.
  • a resist of a predetermined pattern is formed on the substrate surface using photolithography technology, and then a mixed gas of carbon tetrafluoride and oxygen is used.
  • a predetermined transistor determined from a liquid crystal display panel using a polycrystalline silicon film and a first gate insulating film as a product. Isolate (form patterns 2337 and 38) so that they have a shape and an array according to the arrangement of the elements.
  • the reason that the etching is dry rather than dry is that the dimensions are accurately determined.
  • a second gate insulating film 26 made of a silicon dioxide film having a thickness of 60 nm is formed, followed by a gate made of an alloy of molybdenum and evening stainless steel. G. An electrode film 27 is formed.
  • this pattern is used as a mask (shield) to cover the entire surface of the substrate with a poly (B) ion. Is formed to form a P-type conductive region 40 in a part of the polycrystalline silicon film.
  • Lin (P) ions are implanted into the surface to form an n- type conductor region 42 in a part of the polycrystalline silicon film 24.
  • the source electrode 29 made of a laminated film of titanium and aluminum is connected to the source electrode 29.
  • the lane electrode 30 By forming the lane electrode 30, a thin-film transistor is completed.
  • the interface between the different layers is not so high.
  • the process is also not exposed to contaminated atmospheres or oxygen, which allows it to maintain a very clean interface during the process, which results in better transients. Evening characteristics were achieved.
  • Embodiments 12 and 13 of an apparatus and a method for manufacturing a thin film transistor according to the present invention will be described with reference to FIGS. 6 and 7.
  • FIG. 12 Embodiments 12 and 13 of an apparatus and a method for manufacturing a thin film transistor according to the present invention will be described with reference to FIGS. 6 and 7.
  • FIG. 12 Embodiments 12 and 13 of an apparatus and a method for manufacturing a thin film transistor according to the present invention will be described with reference to FIGS. 6 and 7.
  • Figure 6 shows the change in cross-sectional structure due to the progress of thin film transistor manufacturing. This is a diagram showing the situation.
  • FIG. 7 is an overall configuration diagram of the present manufacturing apparatus.
  • This equipment has two heat treatment chambers 61 and 62, and has a spare chamber 8, so that the arrangement of each chamber is circular with the transfer chamber 1 as the center.
  • Figure 1 shows that the mouth port 10 can not only rotate but also move linearly in the direction of the long axis of the ellipse. It is different from the one.
  • Each of the two heat treatment chambers has a side facing the air, which further insulates it from other chambers.
  • the hydrogen contained in the amorphous silicon film is removed in a nitrogen gas atmosphere at 450 to 500 ° C.
  • Heat treatment the heat treatment in nitrogen gas is performed in order to uniformly heat the substrate, and if vacuum is applied, vanadulous calcium adheres to the indoor wall surface. This is to prevent the substance that had been released from jumping out at high temperature and attaching to the amorphous silicon.
  • the heat treatment room can process multiple substrates at the same time because energy and work efficiency are improved, and installation accuracy is not a problem. What is it.
  • the heat-treated substrate was transferred to the measurement chamber 7 again, and the thickness of the amorphous silicon film was measured based on the transmittance measurement.Then, the substrate was transferred to the laser annealing chamber 5 and was most suitable.
  • a polycrystalline silicon film 24 is formed by irradiating the substrate surface with laser light under the conditions.
  • the first gate insulating film is formed in the first film forming chamber, the first gate insulating film is formed in the second heat treatment chamber 62 at 300 ° (in a hydrogen plasma atmosphere of up to 350 ° C.). Heat treatment with U. By this treatment, the defect dangling bond present in the polycrystalline silicon film is terminated by bonding of hydrogen atoms, and the defect in the subsequent treatment is reduced. Will be suppressed.
  • the substrate is taken out of the apparatus in the same manner as in Embodiment 11 and the first gate insulation is performed using the photolithographic branching technique.
  • a second gate insulating film 26 is formed, and subsequently, a gate electrode film is formed.
  • the gate electrode film thus formed is formed in a predetermined pattern 39.
  • a polysilicon film is implanted over the entire surface of the substrate to form a p-type conductive region 40 in a part of the polycrystalline silicon film.
  • ion implantation is performed on the entire surface of the substrate to form an n-type conductive region 42 in a part of the polycrystalline silicon film.
  • the n-type semiconductor had a thickness of 300 cm 2 / V-sec or more
  • the p-type semiconductor had an The inter-substrate variation of the thin film transistor having a field effect mobility of 50 cm 2 / V ⁇ sec or more was less than 3%.
  • the present invention has been described based on several embodiments. However, it goes without saying that the present invention is not limited to these embodiments. That is, for example, the following may be performed.
  • Semiconductors are substances other than silicon, such as silicon 'germanium' and silicon 'germanium' carbon.
  • substrates are made of materials other than glass.
  • the energy used to melt and recrystallize silicon is something other than laser light, such as electron beams.
  • each thin film is another means.
  • Quartz windows (glass) can be replaced with objects of different thicknesses.
  • Rubber gloves are attached to the side of the vacuum chamber so that people can directly move the substrate.
  • the laser annealing chamber 5 is provided.
  • a room for lamp annealing may be used instead.
  • a laser anneal a carbon dioxide gas laser, an argon (Ar) laser, an excimer laser, or the like may be used.
  • the manufacturing apparatus according to the present invention can be widely used not only for TFT but also for other semiconductor elements.
  • the present invention can be suitably applied to a film forming process of an optical multilayer film and an ion implantation process in an element having an LDD (Lightly Doped Drain) structure.
  • LDD Lightly Doped Drain
  • the degree of crystal after laser anneal may be measured by a measuring means, and laser anneal may be performed again. No. Therefore, the laser annealing room 5 and the measuring room 7 may be configured to be the same room. In this case, the output of the laser should be changed depending on whether it is for measurement or for annealing.
  • the second invention group is applied to an active matrix type liquid crystal display device, a sensor array, an SRAM (Static Random Access Memory) and the like.
  • the present invention relates to a top gate type thin film transistor, a method of manufacturing the same, and a top gate type thin film transistor array.
  • the summary of the second invention group is as follows.
  • the second invention group is characterized in that a gate electrode can be continuously produced without exposing a semiconductor thin film surface to the atmosphere. (Embodiment 2 — 1)
  • FIG. 8 is a sectional view showing the structure of the top gate type TFT according to the embodiment 2-1.
  • a top-gate TFT 130 is formed on an insulating substrate 101 such as a glass substrate, for example, on a polycrystalline silicon film having a film thickness of 50 nm, for example.
  • Li co down layer 1 0 2 the film if the thickness is eg 1 0 O nm of S i 0 2 (dioxide Shi Li co down) or Ru Naru Luo gate insulating film 1 0 3, gate electrodes 1 0 4, and 0 3 when example thickness example O nm of S i 0 2 or Ru Naru Luo interlayer insulation Enmaku 1 0 8, that is formed by laminating in this order.
  • the gate electrode 104 includes a first subgate electrode 114 made of a high melting point metal (for example, a molybdenum-tungsten alloy), and the first subgate electrode 104.
  • a second sub-electrode 115 made of a low-resistance metal (for example, aluminum) is formed on the electrode 114.
  • the semiconductor thin film 102 is composed of a source region 105, a drain region 106, and a channel region 107.
  • the channel region 107 is interposed between the source region 105 and the drain region 106 and the first subgate electrode is interposed via the gate insulating film 103. It is located directly below 1 1 4.
  • a contact hole 111a and 11 lb are formed in the interlayer insulating film 108, and the contact hole 111a is formed through the contact hole 111a. Then, the source electrode 109 is electrically connected to the source region 105, and the drain electrode 110 is connected via the contact hole 11 lb. Drain It is electrically connected to area 106.
  • the source electrode 109 and the drain electrode 110 are made of a low-resistance metal (for example, aluminum).
  • the gate electrode 104 is composed of a first sub-gate electrode 114 made of a high melting point metal and a second sub-gate electrode 115 made of a low-resistance metal.
  • the reason why such a laminated structure is adopted is as follows.
  • the gate electrode 104 is formed of a first sub-gate electrode 114 made of a high melting point metal and a second sub-gate electrode made of a low resistance metal.
  • a laminated structure of 1 and 15 was adopted.
  • the second sub-gate electrode 115 is formed, so that the resistance of the entire gate electrode can be reduced.
  • FIGS. 9 and 10 are cross-sectional views showing a manufacturing process of the top gate type TFT according to the embodiment 2-1.
  • FIGS. 11 and 12 are related to the embodiment 2-1.
  • FIG. 4 is a plan view showing a manufacturing process of a top-gate type TFT.
  • Fig. 11 (a) corresponds to Fig. 9 (a)
  • Fig. 11 (b) corresponds to Fig. 9 (b)
  • Fig. 11 (c) corresponds to Fig. 9 (c).
  • Fig. 12 (a) corresponds to Fig. 10 (a)
  • Fig. 12 (b) corresponds to Fig. 10 (b)
  • Fig. 12 (c) corresponds to Fig. 10 (c).
  • top gate type TFT 130 having the above configuration will be described with reference to FIGS. 9 to 12.
  • an insulating substrate 101 such as a glass substrate on which an impurity diffusion preventing film (not shown) having a thickness of, for example, 400 nm is adhered, for example, a non-conductive film having a thickness of, for example, 5 O nm
  • a crystalline silicon thin film is formed by plasma enhanced chemical vapor deposition (PECVD) using a mixed gas such as silane, argon, and hydrogen. .
  • PECVD plasma enhanced chemical vapor deposition
  • a mixed gas such as silane, argon, and hydrogen.
  • a high energy density such as excimer laser light is removed.
  • the polycrystalline silicon layer 120 is formed by crystallizing the amorphous silicon by irradiating ultraviolet rays or the like.
  • a silicon oxide film 121 serving as a gate insulating film 103 is formed by, for example, 1
  • the film is formed to a thickness of 100 nm.
  • a mixed gas such as TEOS (tetraethoxysilane) vapor and oxygen is used. It is preferable to form the film by PECVD, etc.
  • the first sub-gate electrode 114 is formed over the entire surface of the silicon oxide film 121.
  • a high melting point such as a molybdenum-tungsten alloy.
  • the metal thin film 122 is formed by a sputtering method or the like. Such a state is shown in FIGS. 9 (a) and 11 (a).
  • the polycrystalline silicon layer 120 and the silicon oxide film 122 are continuously formed on the insulating substrate 101.
  • the cleanliness of the polycrystalline silicon layer 120 and silicon oxide film 121 (accordingly, the polycrystalline silicon layer 102 and the gate insulating film Cleanliness) is maintained.
  • a specific method for forming a continuous film a cluster-type film forming apparatus using a mouth potchumper can be used as described later. You should.
  • the high melting point metal thin film 122 and the silicon oxide film 122 are formed into a second island shape again.
  • a first subgate electrode 114 and a gate insulating film 103 are formed.
  • the first sub-electrode 114 is used as a mask by the ion implantation technique, and the n-type is used as an impurity ion in a self-aligned manner. If phosphorus or p-type is used, boron is injected. In this case, the ion implantation can be performed by directly doping the polycrystalline silicon layer 120. Therefore, the ion implantation is performed at a low accelerating voltage. It is.
  • the impurity ions are activated by, for example, heat treatment, lamp heating, or laser irradiation, and the source region 105 and the drain region are activated.
  • Polycrystalline silicon with region 106 and channel region 107 A layer 102 is formed. Such a state is shown in Fig. 9 (c) and Fig. 1.
  • a silicon oxide film or the like is formed on the entire surface of the insulating substrate 101 so as to cover the polycrystalline silicon layer 102 and the first sub-gate electrode 114.
  • An interlayer insulating film 108 having a thickness of 300 nm is formed. Such a state is shown in FIGS. 10 (a) and 12 (a).
  • the interlayer insulating film 108 was processed again using photolithography and etching techniques, and the source region 105 was opened.
  • the interface between the polycrystalline silicon layer 102 and the gate insulating film 103 is formed continuously. High in nature. Also, since the island-shaped sloped surface of the polycrystalline silicon layer 102 and the first sub-gate electrode 114 are insulated by the inter-layer insulating film 108, contact is made. There is nothing to do. Therefore, it is possible to improve the TFT characteristics. .
  • the continuous deposition of the semiconductor thin film and the gate insulating film is performed by transporting a glass substrate between two PECVD channels and a laser channel by a transport robot. It can be realized by a so-called cluster type film forming apparatus that can perform the process in a vacuum.
  • FIGS. 13 and 14 are cross-sectional views showing the steps of manufacturing the top gate type TFT according to Embodiment 2-2.
  • the manufacturing method of the present embodiment 2-2 is almost the same as the manufacturing method of the above-mentioned embodiment 2-1. That is, each of the manufacturing processes shown in FIGS. 13 (a) to 14 (c) in Embodiment 2-2 is the same as that shown in FIG. 9 (a) in Embodiment 2-1. )-It corresponds to each manufacturing process of Fig. 10 (c).
  • each manufacturing process is basically the same as the embodiment 2-2 and the embodiment 2-1 and the detailed description is omitted.
  • the refractory metal thin film 1 2 2 (the first subgate electrode 1 1 4) is used in the second island processing (FIG. 9C).
  • FIG. 9 (c) See FIG. 9 (c)
  • silicon oxide film 12 1 corresponding to gate insulating film 103 (see FIG. 9 (c)
  • Fig. 13 (c) only the high melting point metal thin film 1 2 2 (corresponding to the first sub-gate electrode 1 14) is processed as shown in Fig. 13 (c).
  • Embodiment 2 is different from Embodiment 2-1. Therefore, in Embodiment 2-2, since ion implantation is performed through the gate insulating film, ion implantation can be performed at a high acceleration voltage.
  • Embodiment 2-2 Compared to Embodiment 2-1 in which ion injection is performed at a low accelerating voltage, in Embodiment 2-2, the linearity of flying ions is improved. This prevents the island-shaped slope of the polycrystalline silicon layer 102 from being contaminated with impurity ions and prevents leakage between the semiconductor thin film and the gate electrode. As a result of this, This has the advantage of making it easier to fabricate TFTs with good characteristics.
  • the first subgate electrode material is made of a high melting point metal
  • the concentration of impurities is high in place of the high melting point metal.
  • Polycrystalline silicon may be used as the first subgate electrode material.
  • an amorphous silicon is formed again on the gate insulating film 103. Then, polycrystallization by ultraviolet irradiation and low resistance by impurity implantation may be used as the first subgate electrode.
  • the source '' At the time of impurity injection into the drain, it is also possible to simultaneously implant impurities into the polycrystalline silicon that constitutes the first sub-gate electrode. Particularly preferred for ease of use.
  • Embodiment 2-1 and Embodiment 2-2 the amorphous silicon The case where the crystallization of the component is performed by ultraviolet irradiation has been described.
  • the present invention is not limited to this, and similar TFTs can be manufactured using other methods such as solid phase growth.
  • the present invention is not limited to this, and may be an amorphous silicon, a single crystal silicon, or a polycrystalline silicon.
  • Other semiconductor materials other than silicon, such as germanium, may be used.
  • the gate electrode and the gate insulating film are processed into islands by patterning, and then the doping is performed.
  • doping was done, and then there was no? You can use the tuning process.
  • the impurity ions can be reliably implanted into the semiconductor layer. This is for the following reasons. Immediately, if notning is performed first, as shown in FIG. 15, the end surfaces A and B of the gate electrode 114 and the gate insulating film 103 (FIG. 11 (c ) Is not a flat surface perpendicular to the substrate 101, but a slight, but inclined, protruding surface.
  • FIG. 1.6 and FIG. 17 are cross-sectional views showing the steps of manufacturing CMOS-TFT using the thin film transistor according to the present invention.
  • this CMOS-TFT has an n-channel TFT 1332 with an LDD (Lightly Doped Drain) structure and a non-LDD (Lightly Doped Drain) structure. And a P-channel TFT 133.
  • the p-channel TFT 1313i and the TFT of the above-described embodiment 2-1 (corresponding to a TFT when boron is doped as an impurity ion). It has a similar configuration, and corresponding parts are denoted by the same reference numerals.
  • the n-channel TFT 1332 is composed of a gate insulating film 103 composed of a polycrystalline silicon layer 140 and Si02 on an insulating substrate 101, and a gate electrode.
  • An interlayer insulating layer 108 made of 142 and Si 02 is laminated in this order.
  • the gate electrode 144 includes a first subgate electrode 144 made of a high melting point metal and a low resistance metal formed on the upper surface of the first subgate electrode 144. And a second sub-gate electrode 144 composed of the same.
  • the polycrystalline silicon layer 140 includes a channel region 144 directly below the first subgate electrode 144 and a source region (high impurity concentration).
  • n + layer 146 high impurity concentration drain region (n + layer) 147, low impurity concentration low concentration impurity region (LDD region: n-layer) 148, 14 It consists of nine.
  • the low-concentration impurity region 148 is interposed between the source region 146 and the channel region 145, and the low-concentration impurity region 149 is connected to the drain region 147. It is interposed between the channel regions 144.
  • the TFT 1332 is provided with a source electrode 150 and a drain electrode 151 made of a low-resistance metal, and the source electrode 150 is , Contact hole 15 2 a
  • the drain electrode 15 1 is connected to the source region 14 6 via the gate insulating film 14 1 and the interlayer insulating film 10 8. It is connected to the drain region 147 via a contact hole 152b.
  • CMOS—TFT having the above configuration was produced by the following method.
  • an insulating substrate 101 such as a glass substrate having an impurity diffusion preventing film (not shown) having a thickness of, for example, 400 nm, a surface of, for example, 5 nm thick.
  • An amorphous silicon thin film is formed by plasma enhanced chemical vapor deposition (PECVD) using a mixed gas of silane, argon and hydrogen. Then, after removing hydrogen in the amorphous silicon thin film to several at% or less by heat treatment or the like, ultraviolet rays of high energy density such as excimer laser light are irradiated. Irradiation is performed to crystallize the amorphous silicon to form a polycrystalline silicon layer 120.
  • PECVD plasma enhanced chemical vapor deposition
  • a silicon oxide film 121 serving as a gate oxide film 103 is formed by, for example, 1
  • the film is formed to a thickness of 100 nm.
  • a high melting point such as a molybdenum-tantalum alloy serving as the first sub-gate electrodes 114, 144 is formed.
  • the metal thin film 122 is formed by a snout ring method or the like. Such a state is shown in FIG. 16 (a).
  • photolithography and etching techniques were used to separate the elements, and the polycrystalline silicon layer 122 from the surface of the refractory metal thin film 122
  • the first part is processed into the first island shape (Fig. 16 (b)).
  • the refractory metal thin film 122 on the P-channel TFT 133 side is formed into a second island shape.
  • a first sub-gate electrode 114 is formed (FIG. 16 (c)).
  • the refractory metal thin film 122- is used as a mask, and on the p-channel TFT 133 side, the first channel is used.
  • the sub-electrode 114 is a mask, the polon ion is doped (Fig. 16 (c)).
  • the polycrystalline silicon layer 120 is not covered by the refractory metal thin film 122. Impurities are not dropped.
  • the first sub-gate electrode 114 acts as a mask, it is located immediately below the first sub-gate electrode 114. The channel region 106 is a region where impurities are not dropped. Then, the polycrystalline silicon layer 1
  • Impurities are implanted in the region except for the channel region 106 of 20 and the source region (P + layer) 105 and the drain region (p + layer) 10 7 is formed.
  • the first sub-gate electrode 114 is used as a mask to dope the ion, the channel region 106, The source region 105 and the drain region 107 can be formed in a self-aligned manner. Such a state is shown in FIG. 16 (c).
  • the refractory metal thin film 122 on the n-channel TFT 32 side is processed into a second island shape. Then, a first sub-gate electrode 144 is formed (FIG. 16 (d)). Then, in this state, the high-melting point metal thin film 122 is used as a mask, and the ion is doped through the gate oxide film. As a result, the n channel T F T 1
  • the channel region 144 immediately below the first sub-electrode 144 is a region where impurities are not doped.
  • the regions C and D (see FIG. 16 (d)) except for the channel region 144 of the polycrystalline silicon layer 120 are doped with impurities.
  • n layer.
  • a line ion is implanted, and as a result, the boron ion and the line ion are formed by the previous and current ion implantations. Both are implanted, but because the boron ion is implanted so as to be relatively large, p It works without problems as a channel TFT.
  • ion implantation is performed at a high accelerating voltage for ion implantation through a gate oxide film.
  • an inter-layer insulating film 108 is formed to cover the p-channel TFT 13 and the n-channel relay TFT 13 (FIG. 16E).
  • the contact holes reaching the polycrystalline silicon layer 140 are provided on the interlayer insulation layer 108 on the n-channel TFT 1332 side, and the contact holes 15 2 a and 1 Form 5 2 b.
  • the opening of the contact hole 1552a faces the remaining part except for both sides of the area C (corresponding to the low-concentration area LDD).
  • the outline of the hole 152b faces the remaining part except for both sides of the region D (corresponding to the low concentration region LDD).
  • the inter-layer insulating film 108 is used as a mask, and the ion is again doped (FIG. 17 (a)).
  • the inter-layer insulating film 108 As a result, on the n-channel TFT 32 side, a region of the polycrystalline silicon layer 140 that is not covered by the inter-layer insulating film 108 (con The ion is doped in the area that faces the contact hole. Therefore, in the regions C and D where impurities have already been doped by the first ion implantation, the inter-layer insulating film 108 is formed. In the uncovered region (corresponding to the source region and the drain region), the impurity is further doped, and the region with a high impurity concentration (the n + layer) is removed. ).
  • the second line connection is performed.
  • the impurity is not doped, resulting in a low-concentration impurity region (n-layer).
  • the source area (n + layer) A low-concentration impurity region (n-layer) 148 is formed between 146 and the channel region 145, and a drain region (n + layer) 147 and the channel are formed.
  • a low-concentration impurity region (n-layer) 149 can be formed between the channel regions 145.
  • the contact holes reaching the polycrystalline silicon layer 102 are placed on the lanes 11 la and 11 lb. To form. Then, an aluminum low-resistance metal thin film is formed on the entire surface of both the n-channel TFT 13 and the p-channel TFT 13, and the photolithography is performed again. Using graphing and etching techniques, source electrodes 109, 150, drain electrodes 110, 151, and second subgate electrode 11 It is processed into 5, 14 4. In this way, as shown in FIG. 17 (b), a CMOS-TFT having an LDD structure on the n-channel TFT side is produced.
  • FIGS. 18 and 19 are cross-sectional views showing steps of another method for manufacturing a CMOS-TFT using the thin-film transistor according to the present invention.
  • This Embodiment 2-4 is basically similar to Embodiment 2-4.
  • n + doping is performed after the formation of the interlayer insulating film 108.
  • the LDD is not used. After etching for the gate oxide film, doping is performed. Then, they are different.
  • FIGS. 18 (a) to 18 (d) is performed in the same manner as in Embodiments 2 to 3 above, and P + doping and n—doping are performed. I do .
  • the processing in FIG. 18 (a) corresponds to FIG. 16 (a)
  • the processing in FIG. 18 (b) corresponds to FIG. 16 (b)
  • the processing in FIG. 18 (c) This corresponds to FIG. 16 (c)
  • the processing of FIG. 18 (d) corresponds to FIG. 16 (d).
  • the silicon oxide film 121 on the n-channel TFT 1332 side is processed into an island shape. Then, in this state, n + doping is performed. In addition, n channel T F T
  • the first line ion doping of the polycrystalline silicon layer 140 depends on the doping of the first line ion.
  • the region AB where impurities have already been doped and which are not covered with the gate insulating film 103 (corresponding to the source region and drain region). In this case, the impurities are further doped, which results in a high impurity concentration region (n + layer).
  • the regions C and D the regions covered with the gate insulating film 103 (low-concentration impurity regions 148,
  • the impurity is not doped by the second line ion doping, and the low-concentration impurity region (n-layer) is formed. It becomes.
  • a low-concentration impurity region (n-layer) 148 is formed between the source region (n + layer) 146 and the channel region 145, and A low-concentration impurity region (n-layer) 149 can be formed between the drain region (n + layer) 147 and the channel region 144.
  • FIG. 11 (d) Such a state is shown in FIG. 11 (d).
  • an interlayer insulating film 108 is formed (FIG. 19 (a)), and the contact is formed. Open the halls llla, 11 1b, 11 1c, 15 2a, 15 2b, 15 2c. Then, a low-resistance metal thin film such as aluminum is formed on the entire surface of both the n-channel TFT 13 and the p-channel TFT 13, and the photo is formed again. Using lithography and etching techniques, the source electrodes 109, 150, the drain electrodes 110, 151, and the second sub-electrode 1 Process into 15 and 14 4. Thus, as shown in FIG. 19 (b), a CMOS-TFT having an LDD structure on the n-channel TFT side is manufactured.
  • FIG. 20 is a circuit diagram showing a configuration of a TFT array composed of TFTs according to the present invention.
  • a TFT array a plurality of signal lines 155 and a plurality of control lines 156 are arranged in a matrix, and each intersection of the signal line 155 and the control line 156 is formed.
  • the top gate type TFT 130 according to the embodiment 2-1 is disposed.
  • the TFT of the embodiment 2-2 may be used.
  • the signal line 155 is connected to the source electrode 109 of the corresponding TFT, and the control line 156 is connected to the gate electrode 104 of the corresponding TFT.
  • the signal line 155 and the control line 156 are formed on the same insulating substrate 101 together with the TFT.
  • the signal line 155 and the control line 156 are composed of a semiconductor layer 157, an insulating film 121, a high melting point metal layer 122, and a low resistance metal layer. It consists of a four-layer laminated film of layers 158.
  • the control line 156 is composed of the semiconductor layer 157, the insulating layer 122, and the high layer.
  • the four-layer laminated film of the melting point metal layer 122 and the inter-layer insulating layer 108 is formed, and the signal line 155 is formed of the low-resistance metal layer 158 as a single layer film. Due to such a structure, all the signal lines 155 requiring low resistance are provided. In effect, the wiring is made of low-resistance metal 158, and the control line 156 is also wired with low-resistance metal 158 except at the intersection with the signal line 155. It is. Therefore, it is a preferable configuration for a large and high-definition TFT array in which it is important to reduce the wiring resistance.
  • FIGS. 23 and 24 are cross-sectional views showing the manufacturing process of the TFT array.
  • FIGS. 23 and 24 for convenience of explanation, one TFT part and its TFT part are shown. Only the wiring structure related to the TFT part is shown.
  • a method for manufacturing a TFT array according to the present invention will be described with reference to the drawings.
  • a three-layer laminated film of a semiconductor layer 157, an insulating layer 122, and a refractory metal layer 122 is formed on an edge substrate 101. Formed (corresponding to Figs. 9 (a) and 11 (a)).
  • the TFT 130, the control line 156, and the control line 1 are formed by photolithography and etching.
  • the signal line 1555 is formed with the wire broken at the intersection so that it does not touch 56 (corresponding to Figs. 9 (b) and 11 (b)).
  • the TFT 130 is processed into islands, and impurities are implanted and activated (FIG. 9 (c) and FIG. 11 (c)). Corresponding).
  • an interlayer insulating layer 108 is formed on the entire surface (corresponding to FIGS. 10 (a) and 12 (a)).
  • contact holes are opened in the interlayer insulating film 108 (FIGS. 10 (b) and 12 (b)). Corresponding to). At this time, at least at a portion where the control line 156 and the signal line 155 intersect, leave the interlayer insulating layer 108 so that the two lines do not contact each other. In the other portions on the control line 156 and the portions on the signal line 155, the inter-layer insulating film 108 is removed.
  • FIG. 24 (c) the connection between the control line 1556 and the gate electrode 104 by a low-resistance metal such as aluminum is performed. Connect the signal line 155 to the source (drain) area (corresponding to Figures 10 (c) and 12 (c)).
  • the low-resistance metal 1558 is applied to the portion other than the intersection with the signal line 1555 on the control line 1556 and to all the portions including the intersection on the signal line 1555.
  • the control line 156 and the signal line 155 are basically composed of the semiconductor layer 157, the insulating film layer 121, the high melting point metal layer 122, and the low resistance.
  • the control line 156 is composed of the semiconductor layer 157, the insulating layer 122, the refractory metal layer 122, and the inter-layer.
  • the insulating layer 108 becomes a four-layer laminated film
  • the signal line 155 becomes a low-resistance metal layer 158 as a single-layer film.
  • the signal line is composed of a four-layer laminated film of a semiconductor layer, an insulating film layer, a high melting point metal layer and a low resistance metal layer.
  • the signal lines are formed of a low-resistance metal. You may do it. In this way, all the signal lines including the intersections of the signal lines and the control lines become one layer of a low-resistance metal layer, and the resistance of the signal lines is further reduced. I can do it.
  • the third invention relates to a method of forming an amorphous silicon film by a plasma CVD method. More specifically, the hydrogen concentration in the film is determined by a plasma CVD method.
  • the present invention relates to a method for easily forming a low-temperature amorphous silicon film at a low temperature.
  • the summary of the third invention group is as follows.
  • the third invention group makes it possible to easily form an amorphous silicon film having a hydrogen concentration of 3 at% or less at a low temperature by a plasma CVD method. It is characterized by the following.
  • FIG. 1 shows a schematic diagram of a parallel plate type plasma CVD device 210.
  • An RF electrode 204 having a large number of holes on its lower surface is arranged at an upper position in a vacuum vessel 201 having a gas introduction system 203 and a vacuum evacuation system 202.
  • a ground electrode 205 is arranged at a lower position in the container 201 so as to face the electrode 204.
  • a heater 200 is provided in the ground electrode 205, and the substrate 200 arranged on the ground electrode 205 by the heater 210 is provided. 6 is heated, and a high-frequency electrode 208 for applying a high frequency voltage to the RF electrode 204 is provided.
  • the pressure inside the vacuum vessel 201 is adjusted by the vacuum exhaust system 202.
  • deposition gas raw material gas
  • deposition gas that contributes to film formation and does not contribute to film formation Gas
  • RF plasma is generated by applying high-frequency power of z, and an amorphous silicon film is formed on the substrate 206.
  • the substrate 206 was heated to 250 to 300 by a heater 107 provided in the ground electrode 205. This temperature is a value measured by a thermocouple (not shown) installed on the back surface of the substrate 206. The details are described below.
  • the substrate 206 is placed on the ground electrode 205, and the substrate 206 is heated by a heater 206 provided in the ground electrode 205 to 300 °. C
  • the pressure inside the vacuum vessel 201 is adjusted by the vacuum exhaust system 202 so as to be 133 Pa, and the pressure in the vacuum vessel 201 is changed from the gas introduction system 203 to the vacuum vessel 201.
  • SiH 4 a gas for film formation, and Ar, a gas not contributing to film formation, were introduced at a flow rate of 1500 sccm, and the SiH 4 and Ar While changing the mixing ratio, the discharge was performed at a discharge frequency of 27.12 MHz and RF power of 160 W from the high frequency power supply 208, and the substrate was placed on the substrate 206.
  • An amorphous silicon film was formed.
  • the thickness of the amorphous silicon film was adjusted to 300 nm by controlling the film formation time.
  • the hydrogen concentration in the amorphous silicon film was analyzed by Fourier transform infrared spectroscopy (FTIR). Figure 26 shows the results.
  • FTIR Fourier transform infrared spectroscopy
  • Example 2 In the following, S i H 4 flow rate 4 5 sccm, and an A r flow 1 4 5 5 sccm were fixed with 3% S i H 4 concentration, vary the RF power range of 2 0 ⁇ 2 0 0 W is allowed by other film formation conditions c its depositing the Amo le full ⁇ mortal Li co down film on the substrate 2 0 6 Ru Oh pressure 1 3 3 P a, the substrate temperature 2 5 0 ° C .
  • Figure 27 shows the relationship between the RF power and the deposition rate of the amorphous silicon film.
  • Figure 28 shows the relationship between the RF power and the hydrogen content in the amorphous silicon film. Shows the relationship with concentration.
  • the hydrogen concentration in the film decreases with the increase in RF power, and the hydrogen concentration in the film becomes 3% or less per 100 W or more. This is because the increase in the electron and ion densities in the plasma along with the increase in RF power increases the Ar in the high energy state and increases the Ar This is thought to be due to the elimination of hydrogen on the film surface by the physicochemical reaction on the film surface. In the region where the hydrogen concentration in the film is 3 at% or less, the deposition rate is in the region of the supply rule, and in such a region, SiH 4 is almost decomposed.
  • Example 2 is had use the S i H 4 as a film formation gas, and RF the Re this as the S i 2 H 6 in the same manner as in Example 2 Power
  • the relationship of hydrogen concentration in the film was examined.
  • an amorphous silicon film was formed under the same conditions as in Example 2 except that the film forming gas (source gas) was Si 2 H 6 .
  • Figure 28 shows the results of examining the hydrogen concentration in the film of the amorphous silicon film.
  • the inert gas Ar argon
  • He helium
  • Ne neon
  • Kr cribton
  • Xe xenon
  • a parallel plate type plasma CVD apparatus as shown in FIG. 25 was used.
  • an induction method is used. Coupled plasma (ICP) and electron cyclotron resonance (ECR) Similar effects can be expected by using a plasma CVD system that uses high-density plasma such as plasma.
  • each subject of the present invention can be sufficiently achieved. Specifically, it is as follows.
  • the physical properties of the thin film formed on the substrate are improved. Can be measured and then irradiated with a reforming energy beam. Therefore, it becomes possible to modify the thin film by laser light under the most suitable conditions according to the physical properties such as the film thickness. In addition, it has excellent properties because it can perform film formation in the next process without exposing the surface of the modified thin film to indoor contaminated air or oxidizing air. Device creation becomes feasible. Exposure to vacuum in the transfer chamber also naturally removes contaminants that have adhered to the previous process.
  • a semiconductor thin film having excellent interface characteristics can be formed, a thin film transistor (element) having extremely excellent characteristics must be extremely small. It can be manufactured with good reproducibility in the following range. For the same reason, a threshold voltage of IV or lower can be realized with good reproducibility.
  • the laser oscillator since the laser oscillator is located outside the room where the circuit board is installed, it can be replaced or used as a lens system. By performing the actual replacement by switching the substrate, various types of measurement and processing can be performed while the substrate and the like are kept clean. Specifically, for example, measurement of the thickness of a substrate, inspection of a material, and the like are performed. In addition, it is possible to irradiate the laser using the window on the side wall of each clean room, and to perform various measurements.
  • the board will be installed for the original processing, such as laser annealing, and the equipment to be transported and the equipment to be installed and transported for measurement will also be used largely.
  • the gate insulating film is continuously formed without exposing the semiconductor thin film surface to the atmosphere, and the contact between the semiconductor thin film and the gate electrode at the slope of the gate electrode is made. It is possible to manufacture a top-gate type TFT without any problem. As a result, it is possible to obtain a top gate type thin film transistor having improved TFT characteristics. Also, by reducing the resistance of wiring (especially signal lines), a thin-film transistor array that can be suitably used for large-sized liquid crystal panels can be obtained. be able to .
  • a plasma CVD apparatus is used to keep a substrate temperature from being higher than 300 ° C. and a film concentration of hydrogen at 3 at% or less in a film.
  • a silicon film can be formed, thus reducing the number of hydrogen desorption steps before laser irradiation by the laser annealing method.
  • the manufacturing process can be simplified. Therefore, effects such as a reduction in the production cost of the low-temperature polysilicon TFT and an improvement in the throughput can be expected.

Landscapes

  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

Lors de la production d'un transistor à couche mince, deux objectifs sont à atteindre, à savoir, maintenir propre l'interface d'une couche mince semi-conductrice amorphe à plaquer sur un substrat et cristalliser avec une grande fiabilité une couche mince semi-conductrice amorphe dont l'épaisseur entre les substrats est susceptible de varier. On forme sur un substrat, dans une atmosphère non perturbée, une couche mince semi-conductrice amorphe. On mesure les valeurs des caractéristiques physiques en rapport avec la cristallisation de cette couche mince. On soumet cette couche mince à l'action de faisceaux lasers dont les caractéristiques sont fonction des valeurs mesurées et ce, afin de recristalliser par fusion la couche mince. En même temps, on monte des substrats, en maintenant en l'état une atmosphère non perturbée entre les dispositifs et les chambres pour substrats.
PCT/JP2000/002246 1999-04-06 2000-04-06 Dispositif a structure multicouche, appareil et procede de production de ce dispositif WO2000060647A1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP9849299 1999-04-06
JP11/98492 1999-04-06
JP19609099 1999-07-09
JP11/196090 1999-07-09
JP11/198388 1999-07-13
JP19838899 1999-07-13

Publications (1)

Publication Number Publication Date
WO2000060647A1 true WO2000060647A1 (fr) 2000-10-12

Family

ID=27308688

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/002246 WO2000060647A1 (fr) 1999-04-06 2000-04-06 Dispositif a structure multicouche, appareil et procede de production de ce dispositif

Country Status (1)

Country Link
WO (1) WO2000060647A1 (fr)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04372118A (ja) * 1991-06-20 1992-12-25 Canon Inc 非晶質半導体薄膜の製造法
JPH08116065A (ja) * 1994-10-12 1996-05-07 Sony Corp 薄膜半導体装置
JPH09156916A (ja) * 1995-11-29 1997-06-17 Semiconductor Energy Lab Co Ltd 多結晶珪素作製装置およびその動作方法
JPH09213652A (ja) * 1996-02-01 1997-08-15 Semiconductor Energy Lab Co Ltd レーザーアニール装置
JPH10149984A (ja) * 1996-11-20 1998-06-02 Ulvac Japan Ltd 多結晶シリコンの形成方法及び形成装置
JPH10223909A (ja) * 1997-02-08 1998-08-21 Semiconductor Energy Lab Co Ltd 半導体装置
JPH10247733A (ja) * 1997-03-04 1998-09-14 Matsushita Electric Ind Co Ltd 薄膜トランジスタ及びその製造方法
JPH10284433A (ja) * 1997-04-09 1998-10-23 Seiko Epson Corp レーザアニール装置およびレーザアニール方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04372118A (ja) * 1991-06-20 1992-12-25 Canon Inc 非晶質半導体薄膜の製造法
JPH08116065A (ja) * 1994-10-12 1996-05-07 Sony Corp 薄膜半導体装置
JPH09156916A (ja) * 1995-11-29 1997-06-17 Semiconductor Energy Lab Co Ltd 多結晶珪素作製装置およびその動作方法
JPH09213652A (ja) * 1996-02-01 1997-08-15 Semiconductor Energy Lab Co Ltd レーザーアニール装置
JPH10149984A (ja) * 1996-11-20 1998-06-02 Ulvac Japan Ltd 多結晶シリコンの形成方法及び形成装置
JPH10223909A (ja) * 1997-02-08 1998-08-21 Semiconductor Energy Lab Co Ltd 半導体装置
JPH10247733A (ja) * 1997-03-04 1998-09-14 Matsushita Electric Ind Co Ltd 薄膜トランジスタ及びその製造方法
JPH10284433A (ja) * 1997-04-09 1998-10-23 Seiko Epson Corp レーザアニール装置およびレーザアニール方法

Similar Documents

Publication Publication Date Title
US6972433B2 (en) Fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal display, and electronic device
US9847355B2 (en) Silicon nitride film, and semiconductor device
US7485553B2 (en) Process for manufacturing a semiconductor device
US6905920B2 (en) Method for fabrication of field-effect transistor to reduce defects at MOS interfaces formed at low temperature
WO2004079826A1 (fr) Procede servant a fabriquer un transistor a couches minces, ecran et dispositif electronique
US20100301342A1 (en) Increased grain size in metal wiring structures through flash tube irradiation
JP4101340B2 (ja) 半導体装置の作製方法
JP3927634B2 (ja) レーザーアニール方法及び薄膜トランジスタの作製方法
JP2001085701A (ja) 多層構造を有する素子、その素子の製造装置、及びその素子の製造方法
US7374976B2 (en) Method for fabricating thin film transistor
JP4558140B2 (ja) 半導体装置の作製方法
JP2003224117A (ja) 絶縁膜の製造装置
JP4476984B2 (ja) 半導体装置の作製方法
WO2000060647A1 (fr) Dispositif a structure multicouche, appareil et procede de production de ce dispositif
JP3680677B2 (ja) 半導体素子製造装置および半導体素子の製造方法
JP2003037064A (ja) 半導体装置の作製方法および半導体製造装置
JP4472313B2 (ja) 薄膜トランジスタの作製方法
JP4461731B2 (ja) 薄膜トランジスタの製造方法
JP2004119645A (ja) 薄膜トランジスタおよびその製造方法
JP2002237598A (ja) 薄膜トランジスタの製造方法
JPH118195A (ja) 薄膜トランジスタの製造方法
JP2002208707A (ja) 薄膜トランジスタの製造方法
JPH06273799A (ja) マトリクス型表示基板の製造方法および多層薄膜製造方法および製造装置
JP2005197576A (ja) 薄膜トランジスタの製造方法、電気光学装置及び電子機器
JP2002237599A (ja) 薄膜トランジスタの製造方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase