JP3125981B2 - Insulated gate field effect semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
The present invention relates to an insulated gate field effect semiconductor device used for a liquid crystal display panel or the like. 2. Description of the Related Art In a field effect transistor disclosed in Japanese Patent Application Laid-Open No. 58-2073, a source region and a drain region are selectively annealed to form a polycrystalline region, and a channel forming region is made amorphous. Quality area. That is, the field effect transistor disclosed in the publication is
A part of the amorphous region is selectively made into a polycrystalline region by annealing. As described above, in a conventional insulated gate field effect semiconductor device, a channel forming region contains 1 to 3 × 10 ²⁰ cm ^{− of} oxygen, carbon, and nitrogen. ^It consisted of a non-single-crystal semiconductor layer containing about ^three . When any of oxygen, carbon, and nitrogen is contained at such a high concentration, the insulated gate field-effect semiconductor device is turned on and off when switching.
F "characteristic was bad. For example, as described above, in an insulated gate field effect semiconductor device using a non-single-crystal semiconductor containing oxygen, carbon, and nitrogen at such a high concentration, good “ON” and “OFF” The frequency characteristic showing the characteristic was about 1 KHz. In the conventional insulated gate field effect semiconductor device, since the source region and the drain region are selectively annealed, an uncrystallized portion always remains in the non-single-crystal semiconductor layer. When an uncrystallized region remains in the insulated gate field effect semiconductor device as described above, a part of the current also flows in the amorphous portion when the device operates as an insulated gate field effect semiconductor device. Since the amorphous part has a higher resistance than the crystallized part,
The current is difficult to flow, and once it flows in, it is stored and flows out slowly. That is, the insulated gate field-effect semiconductor device in the conventional example has a long lifetime in which current flows, and exhibits hysteresis characteristics. [0005] In order to solve the above problems, an object of the present invention is to provide an insulated gate field effect semiconductor device which has good switching characteristics and can be used at a high frequency. In order to achieve the above object, an insulated gate field effect semiconductor device according to the present invention comprises a quartz or glass substrate (1) and the quartz or glass substrate.
(1) At least a channel forming region and a source region (7)
, A drain region (8) and oxygen, carbon and nitrogen
A non-single-crystal semiconductor layer made of polycrystalline silicon or microcrystalline silicon, each having a concentration of 5 × 10 ¹⁸ cm ⁻³ or less
(2), a gate electrode (4) formed at a position aligned with the channel formation region, and a gate insulation formed between the non-single-crystal semiconductor layer (2) and the gate electrode (4). film
(3), wherein the source region (7) and the drain region (8) have strong ultraviolet light except for the channel formation region.
In this case, the crystallization is promoted, and the gate insulating film (3) includes a silicon nitride film. According to the present invention, a gate insulating film is formed on a non-single-crystal semiconductor to which no or very few impurities are added (hereinafter, a non-single-crystal semiconductor to which hydrogen or a halogen element is added is simply referred to as a semiconductor or a non-single-crystal semiconductor). An object and a gate electrode were selectively provided thereon. Further, using the gate electrode as a mask, impurities for the source region and the drain region, for example, phosphorus or arsenic for the N-channel type and boron for the P-channel type are added to the inside of the non-single-crystal semiconductor by an ion implantation method or the like. Thereafter, the region to which the inert impurities are added is irradiated with strong light at a temperature of 400 ° C. or less, and is subjected to strong light annealing (hereinafter, simply referred to as light annealing), so that hydrogen or a halogen element is added. In addition, the semiconductor is characterized by being transformed into a semiconductor whose crystallinity is promoted more than that of the channel formation region, particularly, a semiconductor having a remarkably polycrystalline or single crystal structure. That is,
The present invention does not perform laser annealing after ion implantation on a conventionally known single crystal semiconductor to which hydrogen or a halogen element is not added, but the hydrogen or halogen element is 1 atomic% or more—generally 5 atomic%. Or 20 atomic%
Is implanted into the non-single-crystal semiconductor added at a concentration of 0.1%, high-intensity annealing is performed on the non-single-crystal semiconductor, and preferably, the light is scanned from one end to the other end of the substrate surface to control crystal growth. In this case, the crystallinity is promoted to form an impurity region. [0008] All of the source and drain regions other than the channel formation region in the insulated gate field effect semiconductor device of the embodiment of the present invention is a crystallized by intense ultraviolet light
It has a higher degree of crystallinity than the channel formation region. As a result, the source region and the drain region can have lower electric resistance than the channel formation region, and can improve the ON characteristics of the insulated gate field effect semiconductor device. The source region and the drain region each have a concentration of 5 × 10 ¹⁸ cm ⁻³ or less in oxygen, carbon, and nitrogen excluding a channel formation region, and are formed of non-crystalline silicon or microcrystalline silicon. Since the entire region of the single crystal semiconductor layer contains impurities, there is a region with a low electric resistance over a wide area, and there is no amorphous portion where current does not easily flow. Therefore, current flows easily and does not flow during switching. The insulated gate field effect semiconductor device of the present invention has an oxygen, carbon and nitrogen concentration of 5 × 10 ¹⁸ each.
cm ^-3 or less, that is, polycrystalline silicon in which the element is reduced as much as possible, or a non-single-crystal semiconductor layer made of microcrystalline silicon is irradiated with strong ultraviolet light to promote crystallization ,
A source region and a drain region are formed. The insulated gate field effect semiconductor device having such a configuration is
Conventional non-single-crystal semiconductors, such as oxygen, carbon,
Alternatively, the switching characteristics of a non-single-crystal semiconductor containing 1 to 3 × 10 ²⁰ cm ⁻³ of nitrogen were sufficient to follow a frequency of 1 KHz, but good switching characteristics were obtained even at a frequency of 1 MHz. In the insulated gate field effect semiconductor device, the concentration of oxygen, carbon and nitrogen in a non-single-crystal semiconductor layer made of polycrystalline silicon or microcrystalline silicon is reduced.
Each of the non-single-crystal semiconductor layers except for the channel formation region is formed from a source region and a drain region which promoted crystallization by irradiating strong ultraviolet light, which is extremely small, 5 × 10 ¹⁸ cm ⁻³ or less. Therefore, the switching characteristics at higher frequencies are improved. In particular, since the source region and the drain region are not selectively annealed, all the non-single-crystal semiconductor layers other than the channel formation region can be easily recrystallized and formed. That is, the insulated gate field effect semiconductor device according to the present invention has a high concentration of oxygen, carbon and nitrogen.
Since each region except for the channel formation region in the non-single-crystal semiconductor layer made of polycrystalline silicon or microcrystalline silicon is a source region and a drain region at a density of 5 × 10 ¹⁸ cm ⁻³ or less, No high-resistance region is left in the crystalline part. As a result, in the insulated gate field effect semiconductor device of the present invention, the gate electrode is formed of oxygen, carbon, and nitrogen constituting the channel formation region on the substrate.
Each of them has a concentration of 5 × 10 ¹⁸ cm ⁻³ or less and is provided above a non-single-crystal semiconductor layer made of polycrystalline silicon or microcrystalline silicon. The optical energy gap (in the case of a silicon semiconductor) of the non-single-crystal semiconductor layer is
It not 1.7eV whereas a 1.8 eV, optical energy gap of the source and drain regions has almost the same optical energy gap and 1.6eV a stone 1.8 eV. In addition, the source region and the drain region have the same energy gap as that of the non-single-crystal semiconductor layer, and an active impurity region can be obtained. Since the source region and the drain region have the same or substantially the same energy gap as the channel formation region, “ON” and “O” of the insulated gate field effect semiconductor device are used.
FF ", the ON current does not flow at the time of rising,
On the other hand, when the current falls, there is no rattling. That is, the insulated gate field effect semiconductor device of the present invention is:
The off current was small, and "ON" and "OFF" could be performed with high speed response. Further, since the crystallinity of the source region and the drain region is higher than that of the channel formation region, the sheet resistance is clearly reduced, and large-area large-scale integration can be performed on one substrate. The gate insulating film has a concentration of 5 × each of oxygen, carbon and nitrogen.
At 10 ¹⁸ cm ^-3 or less, a silicon nitride film is formed in contact with a non-single-crystal semiconductor layer made of polycrystalline silicon or microcrystalline silicon, so that hydrogen in the non-single-crystal semiconductor is hardly degassed and In addition, moisture does not easily enter the non-single-crystal semiconductor. FIG. 1A to FIG. 1C are longitudinal sectional views of an insulated gate field effect semiconductor device according to one embodiment of the present invention. In FIG. 1, a substrate (1) is made of, for example, quartz glass and has a thickness of 1.1 m as shown in FIG.
m and the size was 10 cm × 10 cm. This board (1)
The upper surface of the substrate is plasma CVD of silane (SiH ₄ ) (high frequency 13.5
At 6 MHz and a substrate temperature of 210 ° C.), a non-single-crystal semiconductor (2) having an amorphous structure to which hydrogen was added at a concentration of 1 atomic% or more was formed to a thickness of 0.2 μm. Further, a gate insulating film (3) made of, for example, a silicon nitride film was formed on the upper surface of the non-single-crystal semiconductor (2) by a photo-CVD method.
That is, the gate insulating film (3) is made of disilane (Si ₂ H ₆ ) and ammonia (NH ₃ ) or hydrazine (N ₂ H ₄ ).
Reaction (low pressure mercury lamp with wavelength of 2537Å, substrate temperature 25
0 ° C) to convert Si ₃ N ₄ without using mercury sensitization.
It was made to a thickness of 1000 mm. Thereafter, portions other than the region (5) for forming the insulated gate field effect semiconductor device were removed by a plasma etching method. Plasma etching reaction is CF
₄ + O ₂ (5%) reactive gas was introduced, and a frequency of 13.56 MHz was applied to a parallel plate electrode (not shown).
Performed at room temperature. On the gate insulating film (3), a microcrystalline or polycrystalline semiconductor of N ⁺ conductivity type was laminated to a thickness of 0.3 μm. Undesired portions of the N ⁺ semiconductor film were removed by a photoetching method using the resist film (6). After that, this resist film (6) and the gate electrode of N ⁺ semiconductor (4)
Using the gate portion comprising as a mask, a region serving as a source and a drain is ion-implanted at 1 × 10 ²⁰ cm ^−3.
As shown in FIG. 1 (B), phosphorus was added to this concentration to form a pair of impurity regions (7) and (8). Further, after the resist film (6) of the gate electrode (4) is removed from the entire substrate (1), the substrate (1) is exposed to strong light (1).
Light annealing of 0) was performed. In other words, for an ultra-high pressure mercury lamp (output 5 KW, wavelength 250 to 600 nm, light diameter 15 mm, length 180 mm), use a parabolic reflector on the back side and use a quartz cylindrical lens (focal length 150 cm,
The light-irradiating portion was constituted by a light-collecting portion having a width of 2 mm and a length of 180 mm). The irradiation surface of the substrate (1) is 5
Scanning was performed at a speed of 50 cm / min to 50 cm / min, and the entire surface of the substrate 10 cm × 10 cm was irradiated with strong light (10). Thus, the gate electrode (4) absorbed light sufficiently and was polycrystallized because a large amount of phosphorus was added to the gate electrode (4) side. Further, the impurity regions (7) and (8) are scanned once by melting and recrystallizing, that is, X direction.
The melting and recrystallization were shifted (moved) in the directions. As a result, the crystal grain size could be increased due to the addition of a growth mechanism, compared to simply heating or irradiating the entire surface uniformly. The region crystallized by this intense light annealing is:
It is not necessary to reach all the regions under the impurity regions (7) and (8). In FIG. 1, as shown by broken lines (11) and (11 '), only the upper layer is crystallized at least and the impurity region is removed.
It is important to activate (7) and (8). Further, the ends (15) and (15 ') of the source region and the drain region correspond to the ends (16) and (1) of the gate electrode.
6 ') is provided so as to enter the channel region side. The channel forming region including the N-type impurity regions (7) and (8), the I-type non-single-crystal semiconductor region (2), the junction interface (17) and (17 ') is a non-single-crystal region in the I-type semiconductor region. It has a hybrid structure composed of a semiconductor and a crystallized semiconductor entering from an impurity region. The degree of the crystallized semiconductor in the I-type semiconductor region is determined by the scanning speed and intensity (illuminance) of the optical annealing. After the step of FIG. 1B, the polyimide resin is coated on the entire surface to a thickness of 2 μm. Then, after the electrode holes (13) and (13 ') are formed in the polyimide resin,
Aluminum ohmic contacts and their leads (1)
4) and (14 ') are formed. This second layer leads (14), (1
4 ′) may be connected to the gate electrode (4) when formed. The result of this light annealing is that the sheet resistance is 4 × 10 ⁻³ (ohm cm) ⁻¹ to 1 × 10 ⁺² (ohm cm) before light irradiation.
It became ^-1 , and the electric conductivity characteristics were improved compared to before the light annealing. FIG. 2 is a graph showing characteristics of drain current / gate voltage according to the embodiment of the present invention. When the length of the channel forming region is 3 μm and 10 μm, the channel width is 1 μm.
2 under the condition of mm.
As shown by 1) and (22), V _th = + 2V, V _DD =
A current of 1 × 10 ⁻⁵ A and 2 × 10 ⁻⁵ A was obtained at 10V. In addition,
The off-state current was (V _GG = 0 V) 10 ^-10 to 10 ^-11 (A), which was smaller by a factor of 10 ^-4 than 10 ^-6 (A) of a single crystal semiconductor. This embodiment employs a manufacturing process in which a film is gradually formed and processed from below, so that large-area large-scale integration can be performed. Therefore, large area, for example, 30
It is possible to manufacture even 500 × 500 insulated gate field effect semiconductor devices in a cm × 30 cm panel, and it can be applied as an insulated gate field effect semiconductor device for controlling liquid crystal display elements. Was. Since the low-temperature treatment is performed at a temperature of 400 ° C. or less by the photo-anneal process, it is possible to prevent the polycrystallized or single-crystallized semiconductor from releasing hydrogen or a halogen element therein. The optical annealing was not performed simultaneously on the entire surface of the substrate, but was scanned from one end to the other end. Therefore, light emitted from the cylindrical ultra-high pressure mercury lamp was condensed linearly by a parabolic mirror and a quartz lens. Then, the light condensed in the form of a line could scan the substrate in a direction perpendicular to the linear direction, thereby optically annealing the surface of the non-single-crystal semiconductor. This photo annealing is performed by using ultraviolet rays.
The crystallization from the surface of the non-single-crystal semiconductor to the inside was promoted. For this reason, in the impurity region near the surface that has been sufficiently polycrystallized or monocrystallized, it is possible to control the current flowing very close to the gate insulating film in the channel formation region without any trouble. Light irradiation annealing - Upon le step, hydrogen or a halogen element added to the channel formation region is not affected at all, since it is possible to hold the non-single-crystal semiconductor state, the off-current to 1/10 ^{3 to} the single crystal semiconductor
Can be 1/10 ⁵ Since the source region and the drain region are formed by photo annealing after forming the gate electrode, the characteristics are stabilized without contamination adhered to the gate insulator interface. Further, as compared with a conventionally known method, not only quartz glass as a substrate material but also a source
Douglas and heat-resistant organic films can also be used. The formation of the non-single-crystal semiconductor, the gate insulator, and the gate electrode that form the channel formation region, which is the interface between dissimilar materials, can be made without exposure to the atmosphere by a process in the same reaction furnace. The feature is that there is little. In this embodiment, it is important that all of oxygen, carbon and nitrogen in the non-single-crystal semiconductor in the channel formation region have an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ or less. That is, in the conventionally known insulated gate field effect semiconductor device, 1 to 3 ×
It is mixed to a concentration of 10 ²⁰ cm ^-3 . The P-channel insulated-gate field-effect semiconductor device using a non-single-crystal semiconductor according to the conventional example flows only a current of 1/3 or less of the characteristics of the insulated-gate field-effect transistor device according to the present embodiment. The hysteresis characteristic of the insulated gate field effect semiconductor device using a non-single-crystal semiconductor in the above-described conventional example is such that the drain electric field is 2 × 10 in the I _DD ─V _GG characteristic.
It was observed when applying more than ⁶ V / cm. Also,
As in this embodiment, oxygen in the non-single-crystal semiconductor is reduced to 5 × 10 ¹⁸
At a voltage of 3 cm ³ or less, no hysteresis was observed even at a voltage of 3 × 10 ⁶ V / cm. According to the present invention, since the source region and the drain region have a higher degree of crystallinity than the channel forming region, the ON characteristics of the insulated gate field effect semiconductor device can be improved. Can be. According to the invention, quartz or
Has at least a channel formation region , a source region , and a drain region on a glass substrate, and has a concentration of oxygen, carbon, and nitrogen.
Degree is in 5 × 10 ¹⁸ cm ^-3 or less, and polycrystalline silicon, or made of microcrystalline silicon non-single-crystal semiconductor layer
As a result , the current easily flows, and the switching does not flow during switching. According to the present invention, oxygen on the insulating substrate surface,
Since a channel formation region is provided in a non-single-crystal semiconductor layer made of polycrystalline silicon or microcrystalline silicon in which both the concentrations of carbon and nitrogen are 5 × 10 ¹⁸ cm ⁻³ or less, the gate voltage-drain current characteristics There was no hysteresis, and good switching characteristics at high frequencies were obtained. According to the present invention, as compared with the channel formation region,
Der those polycrystalline of the source region and the drain region
That reason, the sheet resistance is lowered, it was possible to carry out a large-area large-scale integration. According to the present invention, the concentration of oxygen, carbon and nitrogen is 5 × 10 ¹⁸ cm ⁻³ or less, respectively , and the non-single-crystal semiconductor layer made of polycrystalline silicon or microcrystalline silicon and the gate electrode Including the silicon nitride film formed between
No gate insulating film, degassing of hydrogen in the non-single-crystal semiconductor, and moisture penetration are hardly comb.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are longitudinal sectional views of an insulated gate field effect semiconductor device according to one embodiment of the present invention. FIG. 2 is a graph showing characteristics of drain current─gate voltage according to an embodiment of the present invention. [Description of Signs] 1 ... Substrate 2 ... Non-single-crystal semiconductor layer 3 ... Gate insulating film 4 ... Gate electrode 5 ... Area 6 for forming an insulated gate type field effect semiconductor device ... Resist films 7, 8 Impurity region 10 Strong light 11, 11 'Broken line 13, 13' Hole 14, 14 'Lead 15, 15' Source region And end portions 16 and 16 'of the drain region and end portions 17 and 17' of the gate electrode.

   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-59-75670 (JP, A)                 JP-A-59-35423 (JP, A)                 JP-A-55-50663 (JP, A)                 JP-A-58-197775 (JP, A)                 JP-A-56-108231 (JP, A)                 JP-A-58-2073 (JP, A)

Claims (1)

(57) [Claims] It includes a quartz or glass substrate, at least the channel formation region on the quartz or glass substrate, a source region, a drain region, oxygen, our carbon
And the concentration of nitrogen in the 5 × 10 ¹⁸ cm ^-3 or less, the polycrystalline silicon and or microcrystalline composed of silicon non-single-crystal semiconductor layer, a gate electrode formed on the aligned position in the channel formation region, wherein A gate insulating film formed between the non-single-crystal semiconductor layer and the gate electrode, wherein the source region and the drain region excluding the channel formation region Crystallization promoted by strong ultraviolet light
And the gate insulating film includes a silicon nitride film.