JP3393535B2 - LCD panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] [0001] The present invention relates to a semiconductor integrated circuit,
Insulated gate field effect semiconductor devices, or having them
Related to a liquid crystal display panel. [0002] 2. Description of the Related Art Japanese Patent Laid-Open Publication No.
Field-effect transistor has a source region and a drain
Selective annealing of the active region
In addition, the channel formation region is an amorphous region. Sand
That is, the field-effect transistor disclosed in the publication is
Selectively anneal a part of amorphous region to polycrystalline region
Area. [0003] As described above, the conventional
Channel formation in insulated gate field effect semiconductor devices
The region is one in which oxygen, carbon, and nitrogen are all 1 to
3 × 10²⁰cm^-3It was composed of a non-single crystal containing a certain amount. acid
Elemental, carbon and nitrogen all have such high concentrations
Insulated gate field effect semiconductor device
Means that the "ON" and "OFF" characteristics when switching
It was bad. For example, oxygen, carbon, and
Non-nitrogen containing all of nitrogen at such high concentration
Insulated gate field effect semiconductor device using single crystal semiconductor
At a frequency that exhibits good "ON" and "OFF" characteristics.
Numerical characteristics were about 1 KHz. A conventional insulated gate field effect semiconductor
The device selectively anisolates the source and drain regions.
Is crystallized into a non-single-crystal semiconductor layer.
Missing parts always remain. Insulated gate field effect
If uncrystallized regions remain in the semiconductor device
When operating as an insulated gate field effect semiconductor device
Then, a part of the current also flows through this amorphous portion. Amorphous part
Has a higher resistance than the crystallized part,
It is difficult for current to flow, and once it flows in, it is stored and flows out
Is slow. In other words, the insulated gate type electric field effect
As a result, semiconductor devices have a long
Sterisis characteristics appear. To solve the above problems, the present invention
Ming has good switching characteristics and can be used at high frequencies.
To provide an insulated gate field effect semiconductor device
Target. [0006] [MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
The insulated gate field effect semiconductor device of the present invention
A substrate (1) having a surface and at least
Channel formation region, source region (7), drain region (8)
A plurality of island-shaped non-single-crystal semiconductor layers (2) having
Gate electrode formed at a position matching channel formation area
(4) the non-single-crystal semiconductor layer (2) and the gate electrode
(4) a gate insulating film (3) formed between
The source region (7) and the drain region (8)
Is a non-single-crystal semiconductor layer excluding the channel formation region
(2) The source region is formed so as to contain impurities in the entire region,
(7) and the gate close to the drain region (8)
In the insulating film (3), the source region (7) and the drain region
Contains the same type of impurities as the region (8), and
The gate insulating film (3) contains silicon nitride.
I do. The liquid crystal display panel of the present invention comprises a substrate having an insulating surface.
The plate (1) is an organic film. The present invention
Liquid crystal display panel is a substrate (1) having an insulating surface.
It is also possible to use a substrate containing silicon oxide as a main component.
You. In the insulated gate field effect semiconductor device of the present invention
The non-single-crystal semiconductor layer (2) contains 5 oxygen, carbon, or nitrogen.
× 10¹⁸cm^-3It is characterized by the following. Of the present invention
Non-single-crystal semiconductor in insulated-gate field-effect semiconductor devices.
The body layer (2) may be amorphous, polycrystalline, or microcrystalline.
It is characterized by that. [0007] The present invention relates to a method without or with the addition of impurities.
Very few non-single-crystal semiconductors (hereinafter referred to as hydrogen or halogen
Non-single-crystal semiconductor with added element
Abbreviated as non-single-crystal semiconductor)
A gate electrode was selectively provided on the substrate. In addition, this game
Source region by ion implantation using the
And impurity for drain region, for example, N channel
In the case of the type, phosphorus or arsenic is used.
It was added inside the crystalline semiconductor. After this, this inert impurity
At a temperature of 400 ° C or less,
Irradiation with light and intense light annealing (hereinafter simply referred to as light annealing)
), And hydrogen or halogen elements are added.
Semiconductor with higher crystallinity than channel forming region
Bodies, especially semiconductors with a markedly polycrystalline or monocrystalline structure
It is characterized by being transformed. That is,
In the present invention, a conventionally known hydrogen or halogen element is added.
After ion implantation for a single crystal semiconductor
Do not perform hydrogen annealing or hydrogen source
At least 1 atom%-generally 5 atom% to 20 atom%
Non-single-crystal semiconductor added at a concentration of
Implant, intense light anneal to it, and preferably
Scans the substrate surface from one end to the other.
Crystal growth in the process and promote crystallinity to improve
It is a pure region. In the liquid crystal display panel of the present invention, the channel
Morphological field over the interior of the
The depth of the surface should be 0.3 μm to 3.0 μm.
Features. [0009] DETAILED DESCRIPTION OF THE INVENTION The insulated gate field effect half of the present invention
The conductor device contains 5 × 10 oxygen, carbon or nitrogen.¹⁸cm
^-3The following, that is, non-unit
P-type or N-type impurities are added to the crystalline semiconductor layer.
You. Then, crystallization of only the region to which this impurity is added
The source and drain regions are formed
I have. In addition, hydrogen or halogen is formed in the channel formation region.
Element and P-type or N-type impurities are added
There is a feature in the point. Close to source and drain regions
In the gate insulating film formed by
And the same impurity as the drain region
Hydrogen or halogen elements in the non-single-crystal semiconductor layer
It is hard to notice. Insulated gate field effect with this configuration
The semiconductor device is a conventional non-single-crystal semiconductor, for example,
If oxygen, carbon or nitrogen is 1 to 3 × 10²⁰cm^-3
Can follow the frequency of 1 KHz
Switching characteristics of about 1MHz
Good switching characteristics were obtained even at the frequency of Also, an insulated gate field effect semiconductor device
Represents oxygen, carbon, or nitrogen in the non-single-crystal semiconductor layer
Is 5 × 10¹⁸cm^-3The following and extremely few channels
All non-single-crystal semiconductor layers excluding the formation region promote crystallization
Source and drain regions
Switching characteristics at higher frequencies.
I liked it. In particular, select source and drain regions
Channel formation region
Promotes crystallization of all non-single-crystal semiconductor layers except for
Can be made. That is, the insulating gate in the present invention
The field-effect semiconductor device has a
All regions except the channel formation region are the source region and
Because of the drain region, high resistance
Area is not left. Insulated gate field effect of the present invention
In semiconductor devices, the gate electrode is
Provided above the non-single-crystal semiconductor layer forming the region.
You. In addition, the optical energy of the non-single-crystal semiconductor layer
The gap (in the case of a silicon semiconductor) ranges from 1.7 eV to 1.
8 eV, while the source region and the drain region
Optical energy gap between 1.6 eV and 1.
Has almost the same optical energy gap as 8 eV
You. In addition, the source and drain regions are non-single-crystal
It is the same as the energy gap of the semiconductor layer,
A highly impurity region was obtained. Source area and
The drain region is the same or almost the same as the channel forming region
Due to energy gap, insulated gate field effect
ON current and ON current of semiconductor device
It does not flow when rising, and on the other hand, current falls
At the time, it doesn't run. Therefore, the insulating layer of the present invention
Gate type field effect semiconductor devices have no hysteresis characteristics.
Low off current and high ON and OFF
It could be done with a quick response. Also, the source area and
The crystallinity of the drain region is higher than that of the channel formation region.
The sheet resistance is clearly lower, and one board
It has become possible to perform large-area large-scale integration on top. Ma
In addition, current flow is difficult in the source and drain regions.
Since there is no amorphous part, current flows easily,
It doesn't flow when you run it. Gate insulating film is non-single crystal
Since the silicon nitride film is formed in contact with the semiconductor layer,
Hydrogen or halogen elements in single crystal semiconductors are difficult to degas
At the same time, moisture does not easily enter the non-single-crystal semiconductor. [0011] [Embodiment] FIGS. 1A to 1C show an embodiment of the present invention.
Longitudinal sectional view of an insulated gate field effect semiconductor device according to an embodiment.
Is shown. In FIG. 1, a substrate (1) is, for example, a quartz glass.
As shown in FIG. 1 (A), the thickness is 1.1 m.
m and the size was 10 cm × 10 cm. This board (1)
Silane (SiH_Four) Plasma CVD (high frequency 13.5
6 MHz, substrate temperature 210 ° C)
Non-single-crystal semiconducting with highly doped amorphous structure
The body (2) was formed, for example, to a thickness of 0.2 μm. Further
Then, the upper surface of this non-single-crystal semiconductor (2) is
A gate insulating film (3) made of, for example, a silicon nitride film.
Layered. That is, the gate insulating film (3) is
(Si_TwoH₆) And ammonia (NH_Three) Or hydrazine
(N_TwoH_Four) With low pressure mercury including wavelength of 2537Å
Lamp, substrate temperature 250 ° C)_ThreeN_FourUsing the mercury sensitization method
It was made to a thickness of 1000 mm without being. After that, an insulated gate field effect semiconductor device
Excluding the region (5) where
It was removed by the rubbing method. Plasma etching reaction is CF
_Four+ O_Two(5%) reactive gas is introduced and shown
13.56MHz frequency is applied to the parallel plate electrode which is not
Performed at room temperature. Gate insulation film (3)
Thus, it is formed over the entire surface of the substrate (1). Soshi
N on the gate insulating film (3)⁺Microcrystals of the conductivity type
Alternatively, a polycrystalline semiconductor was laminated to a thickness of 0.3 μm. this
N⁺The semiconductor film is photo-etched using a resist film (6).
Undesired portions are removed by the etching method, and the gate electrode (4) and
Become. Thereafter, the resist film (6) and N⁺semiconductor
Gate electrode (4) and gate insulating film (3)
Using the gate part as a mask,
Is 1 × 10²⁰cm^-3Figure 1
As shown in (B), impurities of one conductivity type, for example, phosphorus
As a result, a pair of impurity regions (7) and (8) are formed. Further
In addition, the substrate (1) has its entire gate electrode (4)
After the distaste film (6) is removed, the light is irradiated with strong ultraviolet light (10).
Processing was performed. That is, an ultra-high pressure mercury lamp (output 5K
W, wavelength 250-600 nm, light diameter 15 mm, length 180 m
m) On the other side, use a parabolic reflector for quartz
Cylindrical lens (focal length 150 cm, condensing part width
(2 mm, length 180 mm)
Was. The irradiation surface of the substrate (1) irradiates a linear irradiation
5 to 50 cm / min in a direction perpendicular to the part
Is scanned (scanned) over the entire surface of the substrate 10cm x 10cm.
Intense ultraviolet light (10) was applied. The gate electrode (4) is connected to the gate electrode (4) side.
Light is absorbed in a large amount,
It has become. The impurity regions (7) and (8) are once melted and
Scanning direction by crystallization, ie, X direction
And the recrystallization was shifted (moved). As a result,
Growth compared to just heating or irradiating the entire surface uniformly
Because of the additional mechanism, the crystal grain size could be increased.
A non-single-crystal semiconductor is selectively formed on an insulating substrate.
Channel type covered with non-single-crystal semiconductor gate electrode (4)
Except for the source region, the other part of the non-single-crystal semiconductor
Or the crystallization of all non-single-crystal semiconductors in the drain region
Can be lengthened. With this strong ultraviolet light annealing
The polycrystallized region is the entire region below the impurity regions (7) and (8).
There is no need to extend to the area. In FIG. 1, as shown by lines (11) and (11 ')
In particular, only the upper layer crystallizes at least, and impurity regions
It is important to activate regions (7) and (8). further,
Ends (15), (15 ') of its source and drain regions
Is the channel area with respect to the gate electrode edges (16) and (16 ').
It is provided to enter the area side. And N-type
Pure region (7), (8), I-type semiconductor region (2), junction interface (1
The channel formation region consisting of 7) and (17 ') is an I-type semiconductor region.
Non-single-crystal semiconductor in region (2) and impurity region
Hybrid structure composed of embedded crystallized semiconductor
It is made. The crystallization half in the I-type semiconductor region (2)
The degree of the conductor is determined by the scanning speed of the optical annealing and the intensity (illumination).
Degree). After the step of FIG. 1B, the polyimide resin
Is coated on the entire surface to a thickness of 2 μm. And poly
After the electrode holes (13) and (13 ') are formed in the imide resin,
Aluminum ohmic contacts and their leads (1)
4) and (14 ') are formed. One of these contacts is
On the upper surface of the source region, and
It is formed on the side. This contact is partially glass
It is provided over the substrate, and the electrode holes (13), (1
3 ′) can be formed large. Because of this, the source
There is no unnecessary amorphous region outside the region and the drain region.
It is a characteristic. Also, a liquid crystal display in a liquid crystal display
Insulated gate type field-effect semiconductor device for controlling devices
To reduce the execution area, and consequently improve the aperture ratio
Can be Second layer leads (14) and (14 ') are formed
At this time, it may be connected to the gate electrode (4). This light
The result of the nail is that the sheet resistance is 4 × 10 before light irradiation.^-3(E
Cm)^-1From 1 × 10⁺²(Ohm cm)^-1Become light
The electrical conductivity characteristics were improved compared to before annealing. FIG. 2 shows a drain current according to an embodiment of the present invention.
FIG. 4 is a diagram showing characteristics of a drain voltage. Channel formation area
When the area length is 10 μm, the channel width is 1 mm
Was able to make up to 60V. This is the gate
Voltage V_GG= 10V. This is this connection
Conventional insulated gate electric field with an amorphous structure
Effect semiconductor devices vary widely from 30V to 50V
That was a big step forward. In this embodiment, a film is gradually formed from the lower side and added.
Large-scale large-scale collection
It is now possible to perform integration. Therefore, large area,
For example, 500 pieces x 50 in a 30cm x 30cm panel
Even manufacture of zero insulated gate field effect semiconductor devices is possible
Insulated gate for controlling liquid crystal display elements
It could be applied as a type field effect semiconductor device. light
Low temperature treatment of 400 ° C or less by annealing process.
The polycrystallized or single-crystallized semiconductor is
Release of elemental or halogen elements
Came. Also, light annealing is performed simultaneously on the entire surface of the substrate.
Instead of scanning, scanning was performed from one end to the other. For this reason, irradiation from a cylindrical ultra-high pressure mercury lamp
The collected light is collected linearly by a parabolic mirror and a quartz lens.
It was light. And the light condensed in this linear shape
Non-single-crystal semiconducting by scanning the substrate in orthogonal directions
The body surface could be photo-annealed. This light annealing
Is performed with ultraviolet light, so that the
Partial crystallization was promoted. For this reason,
Impurity regions near the crystallized or single crystallized surface
Flow near the gate insulating film in the channel formation region
Current control without any trouble. Light
Added to the channel formation region during the annealing process
Hydrogen or halogen elements are not affected at all,
Single state of off-state current can be maintained because the state of a single crystal semiconductor can be maintained
1/10 of crystalline semiconductor^ThreeOr 1/10^FiveCan be The source region and the drain region are formed by a gate.
After the electrodes have been made, the gate is
Stability is maintained without the attachment of dirt to the edge interface. Further
In addition, as compared with a conventionally known method, quartz glass is used as a substrate material.
Not only glass, but also any substrate, soda glass, heat resistance
Organic films can also be used. At the interface between dissimilar materials
Non-single-crystal semiconductor gate forming a certain channel formation region
Insulators and gate electrodes are formed in a single reactor.
Because it can be made without touching the atmosphere,
It has the feature that the generation of interface levels is small. In this embodiment, the channel forming region
Oxygen, carbon and nitrogen in the non-single crystal semiconductor
Is 5 × 10¹⁸cm^-3It is important that the impurity concentration below
is there. That is, these are conventionally known insulated gate electric fields.
In an effect semiconductor device, 1 to 3 ×
Ten²⁰cm^-3Mixed to a concentration of. In this conventional example
P-channel insulated-gate electric field using non-single-crystal semiconductor
The effect semiconductor device is an insulated gate type electric field in this embodiment.
Only a current of 1/3 or less of the characteristics of the semiconductor device flows
Not. Then, the non-single-crystal semiconductor in the above conventional example is
Of insulated gate field effect semiconductor device used
The characteristic is I_DD─V_GG2 × 10 drain electric field⁶V / c
It was observed when adding more than m. In addition, this implementation
As in the example, oxygen in the non-single-crystal semiconductor is 5 × 10¹⁸cm^-3
The following is 3 × 10⁶Hysteresis even at a voltage of V / cm
No lysis was observed. [0023] According to the present invention, an acid is deposited on the surface of an insulating substrate.
Elemental, carbon or nitrogen is 5 × 10¹⁸cm ^-3Less than
At least a few non-single-crystal semiconductor layers are provided,
Adding a P-type or N-type impurity to a non-single-crystal semiconductor layer;
Crystallization only in the region where the gate voltage
No hysteresis in drain current characteristics, high frequency
Good switching characteristics. According to the present invention
If a non-single-crystal semiconductor layer other than the channel formation region is further formed,
Insulation gate type field effect half
The switching characteristics of conductor devices are
Even better. According to the present invention, a channel forming region
Crystallinity of source and drain regions compared to
The sheet resistance is reduced due to the
The integration could be performed. According to the invention, the source region
And the presence of a gate insulating film on the drain region,
Even if annealing is performed through the gate insulating film, hydrogen
Or the halogen element is difficult to degas. According to the present invention,
Hydrogen or halogen elements and P-type
Or high conductivity due to the addition of N-type impurities.
A channel formation region was obtained. According to the present invention
For example, a silicon nitride film is formed in contact with the non-single-crystal semiconductor layer.
Gate insulating film is made of hydrogen or hydrogen in a non-single-crystal semiconductor.
It is difficult for degassing of the logogen element and hardly for moisture to enter.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are longitudinal sectional views of an insulated gate field effect semiconductor device according to one embodiment of the present invention. FIG. 2 is a graph showing characteristics of drain current─drain voltage according to an embodiment of the present invention. [Description of Signs] 1 ... Substrate 2 ... Non-single-crystal semiconductor layer 3 ... Gate insulating film 4 ... Gate electrode 5 ... Area 6 for forming an insulated gate field effect semiconductor device ... Resist films 7, 8 Impurity region 10 Strong ultraviolet light 11, 11 'Lines 13, 13' Electrode holes 14, 14 'Leads 15, 15' Ends 16 and 16 'of source and drain regions Ends 17 and 17' of gate electrode Junction interface

────────────────────────────────────────────────── ⁷ Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/78 626C 619A (56) References JP-A-55-50663 (JP, A) JP-A-56-108231 (JP, A) JP-A-57-91517 (JP, A) JP-A-58-2073 (JP, A) JP-A-58-27364 (JP, A) JP-A-58-27364 28867 (JP, A) JP-A-58-93277 (JP, A) JP-A-58-127382 (JP, A) JP-A-58-192379 (JP, A) JP-A-58-197775 (JP, A) JP-A-58-206121 (JP, A) JP-A-59-35423 (JP, A) JP-A-59-75670 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21/20 H01L 21/205 H01L 21/265-21/268 G02F 1/1368

Claims (1)

(57) [Claims] A liquid crystal display panel having an insulated gate field effect semiconductor device formed on an organic film, wherein the insulated gate field effect semiconductor device includes a source region, a drain region, and a channel formation region.
Except for the channel forming region,
A non-single-crystal semiconductor layer that promotes crystallization, a gate electrode formed at a position aligned with the channel formation region, and a gate insulating film formed between the channel formation region and the gate electrode. The channel formation region has an oxygen concentration, a nitrogen concentration,
The element concentration is 5 × 10 ¹⁸ cm ⁻³ or less, and the channel formation region, the source region, the drain region,
Above the gate electrode and the gate insulating film, a resin layer coated with the organic film over the entire surface is provided. On the resin layer, a lead electrode is provided, and the lead electrode is provided on the resin layer. through electrode holes formed, wherein
A liquid crystal display panel connected to a source region or the drain region . 2. 2. The liquid crystal display panel according to claim 1, wherein the gate insulating film is made of silicon nitride.