JP3383262B2 - Driving method of insulated gate field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] The present invention relates to a personal computer.
Display devices for computers, word processors, or electronic devices.
The present invention relates to a liquid crystal display panel used for a display. [0002] 2. Description of the Related Art Japanese Patent Laid-Open Publication No.
Field-effect transistor has a source region and a drain
Selective annealing of the active region
In addition, the channel formation region is an amorphous region. Sand
That is, the field-effect transistor disclosed in the publication is
Selectively anneal a part of amorphous region to polycrystalline region
Area. [0003] As described above, the conventional
Channel formation in insulated gate field effect semiconductor devices
The region is one in which oxygen, carbon, and nitrogen are all 1 to
3 × 10²⁰cm^-3Composed of non-single-crystal semiconductor layers containing
Was. All of oxygen, carbon, and nitrogen are
If it is contained at a high concentration, the
The conductor device is set to “ON” or “OF” when switching.
F "characteristic was bad. For example, as described above, oxygen, carbon, and
And nitrogen at such high concentrations
Insulated gate field effect semiconductor device using non-single-crystal semiconductor
In the device, a circuit that shows good "ON" and "OFF" characteristics
The wave number characteristic was about 1 KHz. To solve the above problems, the present invention
Ming has good switching characteristics and can be used at high frequencies.
To provide an insulated gate field effect semiconductor device
Target. [0006] [MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
In particular, the liquid crystal display panel of the present invention has a channel forming region,
Contact the source region, the drain region, and the channel forming region.
A gate insulating film, and a gate electrode in contact with the gate insulating film.
An insulated gate having a pole and provided on an insulating surface on the substrate
-Type field effect semiconductor device, wherein the channel forming region
Is provided on the patterned non-single-crystal semiconductor film,
Element is 5 × 10¹⁸m^-3The following, hydrogen or halogen
The electric field between the gate electrode and the drain region is 3
× 10⁶Drain current-gate voltage characteristics in the range of V / cm or less
No hysteresis is observed in the sex. [0007] DESCRIPTION OF THE PREFERRED EMBODIMENTS Insulated gate type electric field in the present invention
Effect semiconductor devices include, for example, quartz, glass, or
Source area on the insulating surface on the substrate
Non-single-crystal semiconductors including rain regions and channel formation regions
A gate insulating film formed and in contact with the channel forming region
And a gate electrode in contact with the gate insulating film.
ing. According to the present invention, oxygen is contained in 5 × 10¹⁸cm^-3Less than
No or very few non-
Crystal semiconductor (hereinafter, hydrogen or halogen element is added
Non-single-crystal semiconductor simply as a semiconductor or non-single-crystal semiconductor
Abbreviated) on the gate insulator and the gate electrode on it
Was selectively provided. Furthermore, this gate electrode is used as a mask.
Source region and drain region by ion implantation
Region impurities, such as phosphorus or
Arsenic, boron in P-channel type, inside non-single-crystal semiconductor
Was added. Thereafter, this inert impurity is added.
Intense light irradiation at a temperature of 400 ° C. or less
Light annealing (hereinafter simply referred to as light annealing)
Element or halogen element remains and the crystallinity
Semiconductors that have been promoted more than channel-forming regions, especially significantly
Has been transformed into a polycrystalline or single crystal semiconductor
It is characterized by the following. 10cm to the above substrate
Irradiate linear ultraviolet light of the above length,
5cm / min from one end to the other in a substantially right angle direction
Then scan at a scanning speed of 50 cm / min. Running as above
In the inspection process, the amorphous structure of the non-single-crystal semiconductor
The structure changes to a polycrystalline structure. A conventional insulated gate field effect semiconductor device
Selectively anneals source and drain regions
Is not crystallized in the non-single-crystal semiconductor layer
Part always remains. As described above, the insulated gate field effect half
If there is an uncrystallized area in the conductor device,
When operating as an insulated gate field effect semiconductor device,
Part of the current also flows through this amorphous portion. The amorphous part is compared with the crystallized part.
Current is difficult to flow and flows once
And it is slow to flow out. That is, in the conventional example,
Gate type field effect semiconductor device in which current flows
Long lifetime and hysteresis characteristics. Accordingly, the present invention relates to a conventionally known hydrogen or hydrogen.
Is for single crystal semiconductors to which no halogen element is added.
After the ion implantation, instead of performing laser annealing,
1 atomic% or more of hydrogen or halogen element, generally 5
Non-single crystal added at a concentration of 20% to 20% by atom
Ion implantation into semiconductors and strong light annealing
And, preferably, this light is directed from one end of the substrate surface to the other.
Include crystal growth in the process by scanning the edges,
The impurity regions are formed by promoting the crystallinity. The insulated gate type fabricated by the above method
The field effect semiconductor device has a source region and a drain region.
Have higher crystallinity than the channel formation region. That
As a result, the source and drain regions form a channel.
The electric resistance can be lower than the
ON characteristics of the field effect semiconductor device can be improved.
You. In addition, the source region and the drain region
The entire region of the non-single-crystal semiconductor layer except for the formation region contains impurities.
Area with low electrical resistance over a large area.
Current does not flow.
Easy, no wobble during switching. The insulated gate field effect semiconductor according to the present invention
The body device is oxygen 5 × 10¹⁸cm^-3The following is more preferable
Is 5 × 10 for carbon or nitrogen¹⁸cm^-3The following
That is, a non-single-crystal semiconductor in which the above elements are reduced as much as possible
P-type or N-type impurities are added to the layer. And
The crystallization of only the region to which this impurity is added is promoted,
A source region and a drain region. This
Insulated gate field effect semiconductor devices with such a configuration
Non-single-crystal semiconductors such as oxygen, carbon, or
Or 1 to 3 × 10²⁰cm^-3Is a non-single crystal half
Switch that conductor can follow the frequency of 1KHz
At 1MHz frequency
Also obtained good switching characteristics. Also, an insulated gate field effect semiconductor device
Means that oxygen in the non-single-crystal semiconductor layer is 5 × 10¹⁸cm^-3
Hereinafter, more preferably, carbon or nitrogen is also 5 × 10¹⁸c
m^-3With the following, these impurities are extremely reduced and the channel
All non-single-crystal semiconductor layers excluding the formation region are irradiated with strong ultraviolet light.
Source regions that promoted crystallization by
Higher frequency because it is formed from the drain region
Switching performance in number was improved. In particular, saw
Selective annealing of the source and drain regions
All non-channel regions except for the channel formation region
Crystallization can be promoted in the single crystal semiconductor layer. That is, the liquid crystal display panel of the present invention
Insulated gate field-effect semiconductor device is a non-single-crystal semiconductor
All regions of the layer except the channel formation region are source
Amorphous region
No high-resistance area is left. As a result, the present invention
Gate-type field-effect semiconductor in LCD panels of Japan
In the device, the gate electrode forms the channel formation area on the substrate
Above the non-single-crystal semiconductor layer. Further, the optical energy of the non-single-crystal semiconductor layer is
The energy gap (in the case of a silicon semiconductor) is 1.7 eV
Although the source voltage is 1.8 eV, the source region and the
The optical energy gap in the rain region is 1.6 eV
Almost the same optical energy gap as 1.8 eV
Have. The source region and the drain region are
It is the same as the energy gap of the non-single-crystal semiconductor layer.
In both cases, active impurity regions could be obtained. The source and drain regions are channel
Energy gap that is the same or nearly the same as the
Therefore, the "ON" of the insulated gate field effect semiconductor device,
On-current did not flow at the time of rise for "OFF"
On the other hand, when the current falls,
No. That is, the insulated gate field effect semiconductor device of the present invention
The device has low off-current and “ON” and “OFF”
High-speed response was possible. In addition, the connection between the source region and the drain region
Because the crystallinity was higher than the channel formation area,
Resistance is clearly lower, large area and large scale on one board
Integration has become possible. The gate insulating film is non-
A silicon nitride film is formed in contact with the single crystal semiconductor layer.
Degass hydrogen or halogen elements in non-single-crystal semiconductors
In addition, it is difficult for moisture to enter the non-single-crystal semiconductor. [0020] [Embodiment] FIGS. 1A to 1C show an embodiment of the present invention.
Longitudinal sectional view of an insulated gate field effect semiconductor device according to an embodiment.
Is shown. In FIG. 1, a substrate (1) is, for example, a quartz glass.
As shown in FIG. 1 (A), the thickness is 1.1 m.
m and the size was 10 cm × 10 cm. This board (1)
Silane (SiH_Four) Plasma CVD (high frequency 13.5
(6 MHz, substrate temperature 210 ° C)
Non-single-crystal semiconducting with highly doped amorphous structure
The body (2) was formed to a thickness of 0.2 μm. Further, the upper surface of the non-single-crystal semiconductor (2)
Is a gate made of, for example, a silicon nitride film by an optical CVD method.
The insulating film (3) is laminated. That is, the gate insulating film
(3) is disilane (Si_TwoH₆) And ammonia (NH_Three),
Or hydrazine (N_TwoH_Four) Reaction (wavelength of 2537Å)
Low-pressure mercury lamp with a substrate temperature of 250 ° C)_ThreeN_FourTo
Fabricated to a thickness of 1000 mm without using mercury sensitization
Was. Thereafter, an insulated gate field effect semiconductor device
Excluding the region (5) where
It was removed by the rubbing method. Plasma etching reaction is CF
_Four+ O_Two(5%) reactive gas is introduced and shown
13.56MHz frequency is applied to the parallel plate electrode which is not
Performed at room temperature. On the gate insulating film (3), N⁺Of conductivity type
Microcrystalline or polycrystalline semiconductor layered to a thickness of 0.3 μm
Was. This N⁺The semiconductor film is formed using a resist film (6).
Undesired portions were removed by photo etching. That
Later, this resist film (6) and N⁺Semiconductor gate electrode (4) and
Using the gate portion consisting of
1 × 10²⁰cm^-3of
Phosphorus was added to the concentration as shown in FIG.
Pure areas (7) and (8). Further, the substrate (1) is
After the resist film (6) on the gate electrode (4) is removed,
Light annealing of 0) was performed. That is, an ultra-high pressure mercury lamp
(Output 5KW, wavelength 250-600nm, light diameter 15mm, length
(180 mm) on the back side using a parabolic reflector.
Towards a quartz cylindrical lens (focal length 150 cm,
(Condenser part width 2mm, length 180mm)
Was configured. The irradiation surface of the substrate (1) is 5
Scan at a speed of 50 cm / min to 50 cm / min.
And the entire surface of the substrate 10cm x 10cm is irradiated with strong light (10).
I did it. Thus, the gate electrode (4) is
Since a large amount of phosphorus is added to the pole (4) side, sufficient light
Absorbed and polycrystallized. The impurity regions (7) and (8) are once melted.
Scanning direction by recrystallization, ie, X
The melting and recrystallization were shifted (moved) in the directions. The result
As a result, compared to simply heating or irradiating the entire surface uniformly,
In addition, it is necessary to increase the crystal grain size because the growth mechanism is added.
did it. The region crystallized by this intense light annealing is:
It is necessary to extend all the regions under the impurity regions (7) and (8).
Absent. In FIG. 1, as indicated by broken lines (11) and (11 ')
Only the upper layer is crystallized at least and the impurity region
It is important to activate (7) and (8). Further, the source region and the drain region
The ends (15) and (15 ') of the region are the ends (16) and (1
6 ') is provided so as to enter the channel region side.
ing. Then, the N-type impurity regions (7), (8),
A chip consisting of a crystalline semiconductor region (2), a junction interface (17), and (17 ')
The channel formation region is a non-single-crystal half in the I-type semiconductor region.
Crystallized semiconductors entering from conductors and impurity regions
It has a hybrid structure composed of This type I
The extent of the crystallized semiconductor in the semiconductor region depends on the optical annealing
It is determined by the scanning speed and intensity (illuminance). After the step of FIG. 1B, the polyimide resin
Is coated on the entire surface to a thickness of 2 μm. And poly
After the electrode holes (13) and (13 ') are formed in the imide resin,
Aluminum ohmic contacts and leads (1)
4) and (14 ') are formed. This second layer leads (14), (1
4 ') may be connected to the gate electrode (4) when forming.
No. The result of this light annealing is that the sheet resistance is
4 × 10^-3(Ohm cm) ^-1From 1 × 10⁺²(Ohm cm)
^-1And improved electrical conductivity characteristics compared to before light annealing.
Was. FIG. 2 shows a drain current according to an embodiment of the present invention.
FIG. 6 is a diagram illustrating characteristics of a gate voltage. Channel formation area
Is 3 μm and 10 μm, the channel width is 1 μm.
2 under the condition of mm.
1), as indicated by (22), V_th= + 2V, V_DD=
1 × 10 at 10V^-FiveA, 2 × 10^-FiveA current was obtained. In addition,
The off current is (V_GG= 0V) 10^-TenOr 10^-11(A)
Of single crystal semiconductor^-610 compared to (A)^-FourIs one part smaller?
Was. In this embodiment, a film is gradually formed from the lower side and added.
Large-scale large-scale collection
It is now possible to perform integration. Therefore, large area example
For example, 500 pieces x 500 pieces in a 30cm x 30cm panel
Even the fabrication of insulated gate field effect semiconductor devices is possible.
Insulated gate type electric field for controlling liquid crystal display elements
It could be applied as an effect semiconductor device. Low temperature of 400 ° C. or less by photo annealing process
Polycrystalline or single-crystal semiconductor due to temperature treatment
Release hydrogen or halogen elements inside
Could be prevented. Also, light annealing is applied to the entire surface of the substrate.
Scan from one end to the other end
I let you. For this reason, light emitted from a cylindrical ultra-high pressure mercury lamp
Is focused linearly by a parabolic mirror and a quartz lens.
Was. The light condensed in this linear shape is orthogonal to
Non-single-crystal semiconductor surface by scanning the substrate in different directions
Was light annealed. This photo annealing is performed by using ultraviolet rays.
Promotes crystallization from the surface of a non-single-crystal semiconductor inward
I let you. For this reason, it was sufficiently polycrystallized or single crystallized.
The impurity region near the surface is a region in the channel formation region.
Control the current flowing very close to the gate insulating film without any problem.
It is now possible. In the light irradiation annealing process, a channel is formed.
Hydrogen or halogen elements added to the region
Unaffected and can maintain the state of non-single-crystal semiconductor
Off-current is 1/10 that of a single-crystal semiconductor.^ThreeOr 1/10^FiveNasu
Can be The source and drain regions are
After the gate electrode is made, the gate is
(G) Stabilize the characteristics without contaminants adhering to the insulator interface. Further, compared to the conventionally known method, the substrate
As a material, not only quartz glass but also any substrate
Douglas, heat-resistant organic film can also be used
You. Non-constituting channel forming regions, which are interfaces between different materials
The formation of the single crystal semiconductor ─ gate insulator ─ gate electrode is the same
Exposure to the atmosphere by a process in one reactor
Feature that there is little generation of interface levels
Having. In this embodiment, the channel forming region
Oxygen, carbon and nitrogen in the non-single crystal semiconductor
Is 5 × 10¹⁸cm^-3It is important that the impurity concentration below
is there. That is, these are conventionally known insulated gate electric fields.
In an effect semiconductor device, 1 to 3 ×
Ten²⁰cm^-3Mixed to a concentration of. In this conventional example
P-channel insulated-gate electric field using non-single-crystal semiconductor
The effect semiconductor device is an insulated gate type electric field in this embodiment.
Current of 1/3 or less of the characteristics of the effect transistor device
Only flows. Then, the non-single-crystal semiconductor in the above conventional example is used.
Of insulated gate field effect semiconductor device using insulator
The cis characteristic is I_DD─V_GG2 × 10 drain electric field⁶V
It was observed when adding more than / cm. Also book
As in the embodiment, oxygen in the non-single-crystal semiconductor is reduced to 5 × 10¹⁸c
m^-3The following is 3 × 10⁶Even at a voltage of V / cm
No presence of steresis was observed. According to this embodiment, the source region and the drain
The in-region has a higher crystallinity than the channel formation region.
ON characteristics of the insulated gate field effect semiconductor device
Can be improved. According to this embodiment, the source region and the
And drain region are non-single-crystal
Since the entire semiconductor layer contains impurities, current flows
Easy, no wobble during switching. According to the present embodiment, the channel formation region
Non-single-crystal semiconductor layer outside the region is linear with a length of 10 cm or more
By strong ultraviolet light consisting of
5 cm / min to 50 from one end to the other in a right angle direction
All crystallized by scanning at a scanning speed of cm / min
Of insulated gate field effect semiconductor devices
Switching characteristics are better at high frequencies
became. According to the present embodiment, the ratio between the channel forming region and the
The crystallinity of the source and drain regions
As a result, sheet resistance is reduced, and large-area large-scale integration
Was able to do. [0041] According to the present invention, oxygen is deposited on the surface of an insulating substrate.
Is 5 × 10¹⁸cm^-3Below, more preferably carbon, or
Nitrogen is also 5 × 10¹⁸cm^-3Very few non-consolidated
Channel formation region in the crystalline semiconductor layer
In addition, a P-type
Alternatively, by adding an N-type impurity,
Because of the high crystallinity, gate voltage-drain voltage
No hysteresis in flow characteristics, good at high frequencies
Switching characteristics. According to the present invention, the non-single-crystal semiconductor layer
The gate insulating film on which the silicon nitride film is formed
Hydrogen or halogen elements in the crystalline semiconductor are not easily degassed, and
It is difficult for moisture to enter.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are longitudinal sectional views of an insulated gate field effect semiconductor device according to one embodiment of the present invention. FIG. 2 is a graph showing characteristics of drain current─gate voltage according to an embodiment of the present invention. [Description of Signs] 1 ... Substrate 2 ... Non-single-crystal semiconductor layer 3 ... Gate insulating film 4 ... Gate electrode 5 ... Area 6 for forming an insulated gate type field effect semiconductor device ... Resist films 7, 8 Impurity region 10 Strong light 11, 11 'Broken line 13, 13' Hole 14, 14 'Lead 15, 15' Source region And end portions 16 and 16 'of the drain region and end portions 17 and 17' of the gate electrode.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-55-50663 (JP, A) JP-A-56-80138 (JP, A) JP-A-56-108231 (JP, A) JP-A 57-80 91517 (JP, A) JP-A-58-2073 (JP, A) JP-A-58-27364 (JP, A) JP-A-58-28867 (JP, A) JP-A-58-93277 (JP, A) JP-A-58-127382 (JP, A) JP-A-58-192379 (JP, A) JP-A-58-197775 (JP, A) JP-A-58-206121 (JP, A) JP-A-59-35423 (JP, A) JP-A-59-75670 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21/20 H01L 21/205 H01L 21 / 265-21/268 G02F 1/1368

Claims (1)

(57) [Claims] Provided on the insulating surface of the substrate and includes the source, drain, and channel formation regions .
A non-single-crystal semiconductor layer , a gate insulating film in contact with the channel formation region, and a gate electrode in contact with the gate insulating film.
Method for driving an insulated gate field effect semiconductor device
The source region and the drain region are
Crystallization was promoted by strong ultraviolet light except for the region where
Is intended, the channel formation region, the oxygen concentration, nitrogen concentration and carbon
Element concentration is 5 × 10 ¹⁸ cm ⁻³ or less and water
A method for driving an insulated gate type field effect semiconductor device, comprising driving at a state containing at least 1 atomic% of element or halogen and no hysteresis is observed in a drain current-gate voltage characteristic. 2. Provided on the insulating surface of the substrate and includes the source, drain, and channel formation regions .
A non-single-crystal semiconductor layer , a gate insulating film made of silicon nitride in contact with the channel forming region, and a gate electrode in contact with the gate insulating film .
A driving method, wherein the source region and the drain region are
Crystallization was promoted by strong ultraviolet light except for the region where
Is intended, the channel formation region, the oxygen concentration, nitrogen concentration and carbon
Element concentration is 5 × 10 ¹⁸ cm ⁻³ or less and water
A method for driving an insulated gate type field effect semiconductor device, comprising driving at a state containing at least 1 atomic% of element or halogen and no hysteresis is observed in a drain current-gate voltage characteristic. 3. Provided on the insulating surface of the substrate and includes the source, drain, and channel formation regions .
For driving an insulated gate field effect semiconductor device having an amorphous silicon layer , a gate insulating film in contact with the channel forming region, and a gate electrode in contact with the gate insulating film
A is, the source region and the drain region, the channel
Crystallization was promoted by strong ultraviolet light except for the region where
Is intended, the channel formation region, the oxygen concentration, nitrogen concentration and carbon
Element concentration is 5 × 10 ¹⁸ cm ⁻³ or less and water
A method for driving an insulated gate type field effect semiconductor device, comprising driving at a state containing at least 1 atomic% of element or halogen and no hysteresis is observed in a drain current-gate voltage characteristic. 4. Provided on the insulating surface of the substrate and includes the source, drain, and channel formation regions .
Insulated gate field effect semiconductor having an amorphous silicon layer , a gate insulating film made of silicon nitride in contact with the channel formation region, and a gate electrode in contact with the gate insulating film
A method of driving the device, wherein the source region and the drain region are
Crystallization was promoted by strong ultraviolet light except for the region where
Is intended, the channel formation region, the oxygen concentration, nitrogen concentration and carbon
Element concentration is 5 × 10 ¹⁸ cm ⁻³ or less and water
A method for driving an insulated gate type field effect semiconductor device, comprising driving at a state containing at least 1 atomic% of element or halogen and no hysteresis is observed in a drain current-gate voltage characteristic.