JP2000323690A - Driving method for insulated-gate field-effect semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a switching characteristic good by a method wherein the channel formation region of a patterned non-single-crystal semiconductor film contains oxygen and hydrogen at a specific value or lower, an electric field between a gate electrode and a drain region is set to a specific value or lower, and an insulated gate field-effect semiconductor device is driven in a state that no hysteresis is generated in a drain current/gate voltage characteristic. SOLUTION: A non-single-crystal semiconductor film 2 which contains an amorphous structure is formed on the surface of a substrate 1. A gate insulating film 3 is laminated on it. After that, a part excluding a region 5 in which a field-effect semiconductor device is formed is removed by a plasma etching method. A pair of impurity regions 7, 8 are formed. The pair of impurity regions 7, 8, the non-single-crystal semiconductor film 2 and junction interfaces 17, 17' constitute a channel formation region. The region contains oxygen at 5×1018 cm-3 or lower and hydrogen. An electric field between a gate electrode and a drain region is set at a range of 3×166 V/cm or lower, and no hysteresis is generated in a drain current/gate voltage characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel used for a display device of a personal computer, a word processor, or an electronic device.

[0002]

2. Description of the Related Art In a field effect transistor described in Japanese Patent Application Laid-Open No. 58-2073, a source region and a drain region are selectively annealed to form a polycrystalline region and a channel forming region to an amorphous region. I have. That is, the field effect transistor disclosed in the publication is
A part of the amorphous region is selectively made into a polycrystalline region by annealing.

[0003]

As described above [0007], the channel forming region in the conventional insulated gate field effect semiconductor device, oxygen, carbon, and about 3 × 10 ²⁰ cm ^-3 it has from 1 to any of the nitrogen It consisted of a non-single-crystal semiconductor layer. When any of oxygen, carbon, and nitrogen is contained at such a high concentration, the insulated gate field-effect semiconductor device is turned on and off when switching.
F "characteristic was bad.

For example, in an insulated gate field effect semiconductor device using a non-single-crystal semiconductor containing oxygen, carbon, and nitrogen at such a high concentration as described above, a good "ON" , "OFF" characteristic was about 1 KHz.

[0005] In order to solve the above problems, an object of the present invention is to provide an insulated gate field effect semiconductor device which has good switching characteristics and can be used at a high frequency.

[0006]

In order to achieve the above object, a liquid crystal display panel according to the present invention comprises a channel forming region, a source region, a drain region, a gate insulating film in contact with the channel forming region, and the gate insulating film. An insulated gate field effect semiconductor device provided on an insulating surface on a substrate, wherein the channel formation region is provided in a patterned non-single-crystal semiconductor film, and oxygen 10 ¹⁸ m ^-3 or less, containing hydrogen or halogen, and an electric field between the gate electrode and the drain region of 3
It is characterized in that no hysteresis is observed in the drain current-gate voltage characteristics in a range of × 10 ⁶ V / cm or less.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The insulated gate field effect semiconductor device according to the present invention is a non-single-crystal semiconductor including a source region, a drain region and a channel forming region on an insulating surface on a substrate made of, for example, quartz, glass or an organic film. A semiconductor is formed, and a gate insulating film in contact with the channel formation region and a gate electrode in contact with the gate insulating film are provided.

According to the present invention, a non-single-crystal semiconductor having no or very little oxygen whose oxygen content is 5 × 10 ¹⁸ cm ⁻³ or less (hereinafter, a non-single-crystal semiconductor to which hydrogen or a halogen element is added is simply referred to as a semiconductor or A gate insulator and a gate electrode thereon were selectively provided. Further, using the gate electrode as a mask, impurities for the source region and the drain region, for example, phosphorus or arsenic for the N-channel type and boron for the P-channel type are added to the inside of the non-single-crystal semiconductor by an ion implantation method or the like.

Thereafter, the region to which the inactive impurities are added is irradiated with strong light at a temperature of 400 ° C. or less, and is subjected to strong light annealing (hereinafter simply referred to as light annealing), so that hydrogen or halogen element is added. Is added and remains, and the semiconductor is transformed into a semiconductor whose crystallinity is promoted more than that of the channel formation region, in particular, a semiconductor having a remarkably polycrystalline or single crystal structure. 10cm to the above substrate
The linear ultraviolet light having the above length is irradiated, and scanning is performed at a scanning speed of 5 cm / min to 50 cm / min from one end to the other end in a direction substantially perpendicular to the longitudinal direction of the line. By the above-described scanning step, the amorphous structure of the non-single-crystal semiconductor is changed to a polycrystalline structure.

In the conventional insulated gate field effect semiconductor device, since the source region and the drain region are selectively annealed, a non-crystallized portion always remains in the non-single-crystal semiconductor layer. As described above, when an uncrystallized region remains in the insulated gate field effect semiconductor device,
When operating as an insulated gate field effect semiconductor device,
Part of the current also flows through this amorphous portion.

Since the amorphous portion has a higher resistance than the crystallized portion, it is difficult for current to flow, and once it flows in, it is stored and flows out slowly. That is, the insulated gate field-effect semiconductor device in the conventional example has a long lifetime in which current flows, and exhibits hysteresis characteristics.

Therefore, the present invention is not to perform laser annealing after ion implantation to a conventionally known single crystal semiconductor to which hydrogen or a halogen element is not added.
A non-single-crystal semiconductor to which hydrogen or a halogen element is added at a concentration of 1 atomic% or more, generally 5 atomic% to 20 atomic%, is ion-implanted, subjected to strong light annealing, and preferably, By scanning light from one end to the other end of the substrate surface, crystal growth is included in the process,
The impurity regions are formed by promoting the crystallinity.

In the insulated gate field effect semiconductor device manufactured by the above method, the source region and the drain region have higher crystallinity than the channel formation region. As a result, the source region and the drain region can have lower electric resistance than the channel formation region, and can improve the ON characteristics of the insulated gate field effect semiconductor device. In addition, the source region and the drain region include impurities in the entire region of the non-single-crystal semiconductor layer except for a channel formation region, have a region with low electric resistance over a wide area, and do not have an amorphous portion where current does not easily flow. Therefore, the current easily flows, and the switching does not flow during switching.

The insulated gate field effect semiconductor device according to the present invention has an oxygen content of 5 × 10 ¹⁸ cm ⁻³ or less, more preferably a carbon or nitrogen content of 5 × 10 ¹⁸ cm ⁻³ or less. P-type or N-type impurities are added to the reduced non-single-crystal semiconductor layer. And
The source region and the drain region are formed by promoting crystallization of only the region to which the impurity is added. The insulated gate field-effect semiconductor device having such a structure is characterized in that the conventional non-single-crystal semiconductor, for example, a non-single-crystal semiconductor containing 1 to 3 × 10 ²⁰ cm ⁻³ of oxygen, carbon, or nitrogen has a frequency of 1 KHz. Although the switching characteristics were such that the switching characteristics could be followed, good switching characteristics were obtained even at a frequency of 1 MHz.

Further, in the insulated gate field effect semiconductor device, oxygen in the non-single-crystal semiconductor layer is 5 × 10 ¹⁸ cm ^−3.
Hereinafter, more preferably, carbon or nitrogen is also 5 × 10 ¹⁸ c
m ⁻³ or less, these impurities are extremely reduced, and all the non-single-crystal semiconductor layers except the channel formation region are formed from a source region and a drain region which promoted crystallization by irradiating strong ultraviolet light. Further, the switching characteristics at higher frequencies are improved. In particular, since the source region and the drain region are not selectively annealed, crystallization can be promoted in all the non-single-crystal semiconductor layers other than the channel formation region.

That is, in the insulated gate field effect semiconductor device of the liquid crystal display panel according to the present invention, since all the regions other than the channel forming region in the non-single-crystal semiconductor layer are the source region and the drain region, No high resistance area is left in the part. As a result, in the insulated gate field effect semiconductor device in the liquid crystal display panel of the present invention, the gate electrode is provided above the non-single-crystal semiconductor layer forming the channel formation region on the substrate.

The optical energy gap (in the case of a silicon semiconductor) of the non-single-crystal semiconductor layer is 1.7 eV to 1.8 eV, whereas the optical energy gap of the source region and the drain region is 1 eV. It has almost the same optical energy gap as 0.6 eV to 1.8 eV. The source region and the drain region are
An active impurity region having the same energy gap as that of the non-single-crystal semiconductor layer was obtained.

Since the source region and the drain region have the same or substantially the same energy gap as the channel forming region, the "ON",
In response to "OFF", the ON current does not flow at the time of rising, and on the other hand, the current does not flow at the time of falling. That is, the insulated gate field effect semiconductor device of the present invention has a small off-state current and can perform "ON" and "OFF" with a high-speed response.

Further, since the crystallinity of the source region and the drain region is higher than that of the channel forming region, the sheet resistance is clearly reduced, and large-area large-scale integration can be performed on one substrate. Was. Since the gate insulating film is formed with a silicon nitride film in contact with the non-single-crystal semiconductor layer, hydrogen or a halogen element in the non-single-crystal semiconductor is not easily degassed, and moisture enters the non-single-crystal semiconductor. hard.

[0020]

1A to 1C are longitudinal sectional views of an insulated gate field effect semiconductor device according to an embodiment of the present invention. In FIG. 1, a substrate (1) is made of, for example, quartz glass and has a thickness of 1.1 m as shown in FIG.
m and the size was 10 cm × 10 cm. This board (1)
The upper surface of the substrate is plasma CVD of silane (SiH ₄ ) (high frequency 13.5
At 6 MHz and a substrate temperature of 210 ° C.), a non-single-crystal semiconductor (2) having an amorphous structure to which hydrogen was added at a concentration of 1 atomic% or more was formed to a thickness of 0.2 μm.

Further, a gate insulating film (3) made of, for example, a silicon nitride film was laminated on the upper surface of the non-single-crystal semiconductor (2) by a photo-CVD method. That is, the gate insulating film
(3) is disilane (Si ₂ H ₆ ) and ammonia (NH ₃ ),
Alternatively, by reaction with hydrazine (N ₂ H ₄ ) (a low-pressure mercury lamp including a wavelength of 2537 °, a substrate temperature of 250 ° C.), Si ₃ N ₄ was formed to a thickness of 1000 mm without using a mercury sensitization method.

Thereafter, the portion excluding the region (5) for forming the insulated gate field effect semiconductor device was removed by a plasma etching method. Plasma etching reaction is CF
₄ + O ₂ (5%) reactive gas was introduced, and a frequency of 13.56 MHz was applied to a parallel plate electrode (not shown).
Performed at room temperature.

On the gate insulating film (3), a microcrystalline or polycrystalline semiconductor of N ⁺ conductivity type was laminated to a thickness of 0.3 μm. Undesired portions of the N ⁺ semiconductor film were removed by a photoetching method using the resist film (6). Thereafter, using the gate portion composed of the resist film (6) and the gate electrode (4) of the N ⁺ semiconductor as a mask, the region serving as the source and drain is implanted at 1 × 10 ²⁰ cm ⁻³ by ion implantation. As shown in FIG. 1 (B), phosphorus was added to this concentration to form a pair of impurity regions (7) and (8).

Further, after the resist film (6) of the gate electrode (4) is removed from the entire substrate (1), the substrate (1) is exposed to intense light (1).
Light annealing of 0) was performed. In other words, for an ultra-high pressure mercury lamp (output 5 KW, wavelength 250 to 600 nm, light diameter 15 mm, length 180 mm), use a parabolic reflector on the back side and use a quartz cylindrical lens (focal length 150 cm,
The light-irradiating portion was constituted by a light-collecting portion having a width of 2 mm and a length of 180 mm).

The irradiation surface of the substrate (1) is 5
Scanning was performed at a speed of 50 cm / min to 50 cm / min, and the entire surface of the substrate 10 cm × 10 cm was irradiated with strong light (10). Thus, the gate electrode (4) absorbed light sufficiently and was polycrystallized because a large amount of phosphorus was added to the gate electrode (4) side.

The impurity regions (7) and (8) are scanned once by melting and recrystallizing, ie, X direction.
The melting and recrystallization were shifted (moved) in the directions. As a result, the crystal grain size could be increased due to the addition of a growth mechanism, compared to simply heating or irradiating the entire surface uniformly. The region crystallized by this intense light annealing is:
It is not necessary to reach all the regions under the impurity regions (7) and (8). In FIG. 1, as shown by broken lines (11) and (11 '), only the upper layer is crystallized at least and the impurity region is removed.
It is important to activate (7) and (8).

Further, the end portions (15) and (15 ') of the source region and the drain region correspond to the end portions (16) and (1) of the gate electrode.
6 ') is provided so as to enter the channel region side. The channel forming region including the N-type impurity regions (7) and (8), the I-type non-single-crystal semiconductor region (2), the junction interface (17) and (17 ') is a non-single-crystal region in the I-type semiconductor region. It has a hybrid structure composed of a semiconductor and a crystallized semiconductor entering from an impurity region. The degree of the crystallized semiconductor in the I-type semiconductor region is determined by the scanning speed and intensity (illuminance) of the optical annealing.

After the step of FIG. 1B, the polyimide resin
Is coated on the entire surface to a thickness of 2 μm. And poly
After the electrode holes (13) and (13 ') are formed in the imide resin,
Aluminum ohmic contacts and their leads (1)
4) and (14 ') are formed. This second layer leads (14), (1
4 ') may be connected to the gate electrode (4) when forming.
No. The result of this light annealing is that the sheet resistance is
4 × 10^-3(Ohm cm) ^-1From 1 × 10⁺²(Ohm cm)
^-1And improved electrical conductivity characteristics compared to before light annealing.
Was.

FIG. 2 is a graph showing the characteristic of drain current / gate voltage according to the embodiment of the present invention. When the length of the channel forming region is 3 μm and 10 μm, the channel width is 1 μm.
2 under the condition of mm.
As shown by 1) and (22), V _th = + 2V, V _DD =
A current of 1 × 10 ⁻⁵ A and 2 × 10 ⁻⁵ A was obtained at 10V. In addition,
The off-state current was (V _GG = 0 V) 10 ^-10 to 10 ^-11 (A), which was smaller by a factor of 10 ^-4 than 10 ^-6 (A) of a single crystal semiconductor.

The present embodiment employs a manufacturing process in which a film is gradually formed and processed from below, so that large-area large-scale integration can be performed. Therefore, it is possible to manufacture even 500 × 500 insulated gate field effect semiconductor devices in a large area, for example, a panel of 30 cm × 30 cm, and as an insulated gate field effect semiconductor device for controlling a liquid crystal display element. Could be applied.

Since the low-temperature treatment is performed at a temperature of 400 ° C. or less by the photo-annealing process, it is possible to prevent a polycrystalline or single-crystal semiconductor from releasing hydrogen or a halogen element therein. The optical annealing was not performed simultaneously on the entire surface of the substrate, but was scanned from one end to the other end. Therefore, light emitted from the cylindrical ultra-high pressure mercury lamp was condensed linearly by a parabolic mirror and a quartz lens. Then, the light condensed in the form of a line could scan the substrate in a direction perpendicular to the linear direction, thereby optically annealing the surface of the non-single-crystal semiconductor.

This photo annealing is performed by using ultraviolet rays.
The crystallization from the surface of the non-single-crystal semiconductor to the inside was promoted. For this reason, in the impurity region near the surface that has been sufficiently polycrystallized or monocrystallized, it is possible to control the current flowing very close to the gate insulating film in the channel formation region without any trouble.

In the light irradiation annealing step, the hydrogen or the halogen element added to the channel formation region is not affected at all and can maintain the state of the non-single-crystal semiconductor, so that the off-state current is reduced to 1 / of that of the single-crystal semiconductor. It can be 10 ³ to 1/10 ⁵ . Since the source region and the drain region are formed by photo annealing after forming the gate electrode, the characteristics are stabilized without contamination adhered to the gate insulator interface.

Further, as compared with a conventionally known method, not only quartz glass as a substrate material but also an arbitrary substrate
Douglas and heat-resistant organic films can also be used. The formation of the non-single-crystal semiconductor, the gate insulator, and the gate electrode that form the channel formation region, which is the interface between dissimilar materials, can be made without exposure to the atmosphere by a process in the same reaction furnace. The feature is that there is little.

In this embodiment, it is important that all of oxygen, carbon and nitrogen of the non-single-crystal semiconductor in the channel formation region have an impurity concentration of 5 × 10 ¹⁸ cm ⁻³ or less. That is, in a conventionally known insulated gate field effect semiconductor device, 1 to 3 ×
It is mixed to a concentration of 10 ²⁰ cm ^-3 . The P-channel insulated-gate field-effect semiconductor device using a non-single-crystal semiconductor according to the conventional example flows only a current of 1/3 or less of the characteristics of the insulated-gate field-effect transistor device according to the present embodiment.

The hysteresis characteristic of the insulated gate field effect semiconductor device using the non-single-crystal semiconductor in the above-mentioned conventional example is such that the drain electric field is 2 × 10 ⁶ V in addition to the I _DD ─V _GG characteristic.
It was observed when adding more than / cm. Further, as in this embodiment, oxygen in the non-single-crystal semiconductor is reduced to 5 × 10 ¹⁸ c
When the value was m ⁻³ or less, no hysteresis was observed even at a voltage of 3 × 10 ⁶ V / cm.

According to the present embodiment, since the source region and the drain region have a higher degree of crystallinity than the channel forming region, the ON characteristics of the insulated gate field effect semiconductor device can be improved.

According to the present embodiment, since the source region and the drain region contain impurities in the entire region of the non-single-crystal semiconductor layer excluding the channel forming region, current flows easily, and the switching occurs during switching. Not flowing.

According to the present embodiment, the non-single-crystal semiconductor layer other than the channel formation region is further exposed to linear intense ultraviolet light having a length of 10 cm or more in one end in a direction substantially perpendicular to the linear longitudinal direction. From 5cm / min to 50 from the other end
Since the crystallization is all promoted by scanning at a scanning speed of cm / min, the switching characteristics of the insulated gate field effect semiconductor device are further improved even at a high frequency.

According to the present embodiment, the crystallinity of the source region and the drain region is made higher than that of the channel forming region, so that the sheet resistance is reduced and a large area and large scale integration can be performed.

[0041]

According to the present invention, oxygen is 5 × 10 ¹⁸ cm ^-3 or less on an insulating substrate surface, very few non-single-crystal semiconductor as more preferably a carbon or nitrogen also 5 × 10 ¹⁸ cm ^-3 or less, Since a channel formation region in the layer is provided, and P-type or N-type impurities are added to the entire region of the source region and the drain region to make the crystallinity higher than that of the channel formation region, the gate voltage − There was no hysteresis in the drain current characteristics, and good switching characteristics at high frequencies were obtained.

According to the present invention, in a gate insulating film in which a silicon nitride film is formed in contact with a non-single-crystal semiconductor layer, hydrogen or a halogen element in the non-single-crystal semiconductor is hardly degassed, and moisture enters. Difficult to do.

[Brief description of the drawings]

FIGS. 1A to 1C are longitudinal sectional views of an insulated gate field effect semiconductor device according to an embodiment of the present invention.

FIG. 2 is a graph showing characteristics of drain current─gate voltage according to an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Non-single-crystal semiconductor layer 3 ... Gate insulating film 4 ... Gate electrode 5 ... Region in which an insulated gate field effect semiconductor device is formed 6 ... Resist film 7, 8 ... impurity region 10 ... strong light 11, 11 '... broken line 13, 13' ... hole 14, 14 '... lead 15, 15' ... end of source region and drain region Portion 16, 16 '... End portion of gate electrode 17, 17' ... Bonding interface

Claims (20)

[Claims] A source region, a drain region, a channel formation region, a gate insulating film in contact with the channel formation region, and a gate electrode in contact with the gate insulation film, wherein the channel formation region is provided on an insulating surface of the substrate. Driving an insulated-gate field-effect semiconductor device made of a non-single-crystal semiconductor in which oxygen is 5 × 10 ¹⁸ cm ⁻³ or less and hydrogen or halogen is 1 atomic% or more in a state where no hysteresis is observed in drain current-gate voltage characteristics A method for driving an insulated gate field effect semiconductor device. 2. A gate insulating film provided on an insulating surface of a substrate and made of silicon nitride in contact with a source region, a drain region, a channel forming region, and the channel forming region;
An insulating gate-type field effect including a gate electrode in contact with the gate insulating film, wherein the channel formation region is a non-single-crystal semiconductor in which oxygen is 5 × 10 ¹⁸ cm ⁻³ or less and hydrogen or halogen is 1 at% or more. A method for driving an insulated gate field effect semiconductor device, wherein the semiconductor device is driven in a state where no hysteresis is observed in drain current-gate voltage characteristics. 3. A semiconductor device, comprising: a source region, a drain region, a channel formation region, a gate insulating film in contact with the channel formation region, and a gate electrode in contact with the gate insulation film, the channel formation region being provided on an insulating surface of the substrate. Driving an insulated-gate field-effect semiconductor device made of amorphous silicon in which oxygen is 5 × 10 ¹⁸ cm ⁻³ or less and hydrogen or halogen is 1 atomic% or more in a state where no hysteresis is observed in drain current-gate voltage characteristics. A method for driving an insulated gate field effect semiconductor device. 4. A gate insulating film provided on an insulating surface of a substrate and made of silicon nitride in contact with a source region, a drain region, a channel forming region, and the channel forming region;
An insulated gate field effect semiconductor device having a gate electrode in contact with the gate insulating film, wherein the channel formation region is made of amorphous silicon in which oxygen is 5 × 10 ¹⁸ cm ⁻³ or less and hydrogen or halogen is 1 atomic% or more. In which no hysteresis is observed in the drain current-gate voltage characteristics. 5. The channel forming region according to claim 1, wherein:
The area is 5 × 10 carbon¹⁸cm ^-3Characterized by the following
An operation method of an insulated gate field effect semiconductor device. 6. The channel forming area according to claim 2, wherein
The area is 5 × 10 carbon¹⁸cm ^-3Characterized by the following
A method for driving an insulated gate field effect semiconductor device. 7. The channel forming region according to claim 3, wherein
The area is 5 × 10 carbon¹⁸cm ^-3Characterized by the following
A method for driving an insulated gate field effect semiconductor device. 8. The channel forming area according to claim 4, wherein
The area is 5 × 10 carbon¹⁸cm ^-3Characterized by the following
A method for driving an insulated gate field effect semiconductor device. 9. The channel forming region according to claim 1, wherein:
The area is 5 × 10 with nitrogen¹⁸cm ^-3Characterized by the following
An operation method of an insulated gate field effect semiconductor device. 10. The method for driving an insulated gate field effect semiconductor device according to claim 2, wherein nitrogen in the channel formation region is 5 × 10 ¹⁸ cm ⁻³ or less. 11. The method for driving an insulated gate field effect semiconductor device according to claim 3, wherein nitrogen in the channel formation region is 5 × 10 ¹⁸ cm ⁻³ or less. 12. The method for driving an insulated gate field effect semiconductor device according to claim 4, wherein nitrogen in the channel formation region is 5 × 10 ¹⁸ cm ⁻³ or less. 13. The method according to claim 1, wherein the substrate is made of quartz, glass, or an organic film. 14. The method according to claim 2, wherein the substrate is made of quartz, glass, or an organic film. 15. The driving method of an insulated gate field effect semiconductor device according to claim 3, wherein the substrate is made of quartz, glass, or an organic film. 16. The method according to claim 4, wherein the substrate is made of quartz, glass, or an organic film. 17. The method for driving an insulated gate field effect semiconductor device according to claim 1, wherein the insulated gate field effect semiconductor device is used for a liquid crystal display panel. 18. The method for driving an insulated gate field effect semiconductor device according to claim 2, wherein the insulated gate field effect semiconductor device is used for a liquid crystal display panel. 19. The method for driving an insulated gate field effect semiconductor device according to claim 3, wherein the insulated gate field effect semiconductor device is used for a liquid crystal display panel. 20. The method for driving an insulated gate field effect semiconductor device according to claim 4, wherein the insulated gate field effect semiconductor device is used for a liquid crystal display panel.