JPH0242419A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To improve working speed by using wiring made of silicide and to improve an element characteristic by a hydrogenization processing on an active matrix substrate by not forming a silicide on the surface of an area which functions as a gate electrode. CONSTITUTION:On the active matrix substrate having a structure in which a scanning wiring is also the gate electrode of a thin-film transistor and the scanning wiring and a signal wiring are made of a silicide, the silicide is not formed in the part of the scanning wiring which functions as a gate electrode 4. That is to say, only a scanning wiring 101 and a signal wiring 102 are made of the silicide and the silicide does not exist in the upper part of the channel area of a thin-film semiconductor element 2. Consequently, even when the hydrogenization or fluorination processing is executed in order to activate the channel area, hydrogen or fluorine ions pass through the gate electrode and reach the channel area. Thus, the channel area is activated sufficiently and the element characteristic can be improved.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a thin film transistor (hereinafter abbreviated as TPT)
The present invention relates to a semiconductor device for a liquid crystal display using a semiconductor device, and particularly to a semiconductor device suitable for an active matrix substrate.

(Prior Art) An active matrix liquid crystal display device using TPT is expected to be suitable for achieving high image quality.

When improving the image quality of a liquid crystal display device, it is important to improve the brightness of the image, and therefore it is necessary to increase the aperture ratio in the active matrix substrate. In particular, as screens become smaller, ensuring a sufficient aperture ratio becomes an important issue.

There are two technical solutions to this problem: miniaturizing the wiring line width and other processing dimensions, and eliminating the need for contact through holes by creating a self-aligned structure as shown in Figure 2. is possible.

In order to achieve finer wiring, it is necessary to reduce the resistance of the wiring. Conventionally, polycrystalline SL doped with impurities has been used as the wiring and gate electrode material, but in order to increase the operating speed with miniaturized wiring, it is necessary to lower the resistance of the wiring, and recently Then, Mo, W, which has lower resistance,
An alloy film of metal such as Ni and Si (hereinafter abbreviated as silicide) has come to be used.

Next, a method for eliminating the need for through holes will be explained using FIG.

FIG. 2(a) shows an example in which the scanning wiring 101 and the gate electrode 4 of the TFT are connected via a contact through hole 20, and in order to provide a margin for mask alignment, a fairly large area of dead space is created. The size of the pixel electrode 10 becomes small.

On the other hand, as shown in FIG. 2(b), the scanning line 101 and T
If the gate electrode 4 of the PT is formed in a self-aligned manner in one photo process, the dead space for forming through holes can be reduced, so that the aperture ratio can be improved.

(Problems to be Solved by the Invention) However, when attempting to apply the above-mentioned silicide wiring technology to a TPT, particularly a TPT using a polycrystalline semiconductor as an active layer material, a serious problem arises. This problem will be explained below.

In general, polycrystalline semiconductors have many structural defects, such as dangling bonds of atoms, in their crystal grain boundaries, and these defects are the main cause of deterioration of device characteristics.

To deal with this, methods are known in which the device characteristics are improved by terminating the dangling bonds with a monocoordinated atom such as H or F, or by alleviating the distortion of the structure.

A common technical means for this is to heat-treat the substrate with a plasma containing H or F. This hydrogenation or fluorination treatment is essential in order to make the polycrystalline abrasive material practical as a device.

During this process, the film thickness and material of the gate electrode are very important factors because they determine the permeability of the TPT gate electrode to H and F and the amount of H and F that reaches the TPT active layer. .

Regarding the relationship between the gate electrode film thickness and the effect of hydrogenation treatment when polycrystalline Si is used as the gate electrode material, for example, as described in Japanese Patent Application No. 62-54044, there is a possibility that the gate electrode film thickness becomes thinner. The hydrogenation effect is significant.

On the other hand, the hydrogenation effect also strongly depends on the gate electrode material.

Figure 3 shows the characteristics of the active layer before hydrogenation treatment (dotted line),
As gate electrode materials, ■ polycrystalline Si film (solid line), ■ platinum-silicide (Pt-3i: double-dashed line) film, ■ AΩ film (
The characteristics of the active layer after hydrogenation using the dot-dashed line) are shown in terms of the relationship between gate voltage and drain current, where the drain voltage is 5V and the channel width/channel length is 1. be.

As is clear from the figure, in the TPT using polycrystalline Si for the gate electrode, the characteristic improvement by hydrogenation treatment is remarkable, but in the AN gate, the characteristic improvement ■ is hardly observed.
Even with the Pt-3t gate, the characteristic improvement (2) is slight.

This difference in hydrogenation effect is clearly due to the difference in hydrogen permeability of the gate electrode material. The reason for this is that in covalent substances such as St, the distance between atoms is relatively large, and H and F can easily diffuse between atoms, whereas Af
This is presumed to be because metals such as i have a close-packed crystal structure and thus have small interatomic distances, making it difficult for H and F to diffuse. In addition, in the case of an alloy of metal and semiconductor such as Pt-3i, its properties are intermediate between that of a metal and a positive conductor, so the ease with which H and F pass through is smaller than that of polycrystalline Si.
It seems to be larger than 8 ohms.

As can be seen from the above, in order to improve the operating speed and the device characteristics at the same time, it is necessary to silicide only the wiring and not to silicide the gate electrode.

On the other hand, if the TPT structure is made into a self-aligned structure in which the scanning line also serves as the gate electrode in order to improve the aperture ratio, the scanning line and the gate electrode are formed at the same time.
When the scanning wiring is silicided, the gate electrode is also silicided at the same time, causing the problem that the active layer is not activated and the device characteristics are not sufficiently improved as described above.

The purpose of the present invention is to solve the above-mentioned problems, and to improve the operating speed by siliciding the wiring and improving the device characteristics by hydrogenation or fluorination treatment in an active matrix substrate that maintains a high aperture ratio through a self-aligned wiring structure. The object of the present invention is to provide an active matrix radix with a structure that can achieve the following.

(Means for Solving the Problems) - In order to solve the problems described above, the present invention provides a structure in which the scanning wiring also serves as the gate electrode of the TPT, and at least one of the scanning wiring and the signal wiring is silicided. The active matrix substrate has a structure in which silicide is not formed on at least a portion of the scanning wiring that functions as a gate electrode.

(Function) According to the above configuration, only the scanning wiring and the signal wiring are silicided, and silicide is not present above the channel region of the thin film semiconductor element.

Therefore, even when hydrogenation or fluorination treatment is performed to activate the channel region in an active matrix substrate that maintains a high aperture ratio due to a self-aligned wiring structure, hydrogen or fluorine ions may pass through the gate electrode. Since it reaches the channel region, the channel region is sufficiently activated and device characteristics can be improved.

Furthermore, since silicide is formed only on a portion of the surface of the gate electrode, the activation of the channel region (M
This makes it possible to further improve the operating speed without causing any problems.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1(a) is a plan view of one cell of an active matrix substrate according to an embodiment of the present invention, and FIG. 1(b) is a sectional view taken along line A-B in FIG. e) is the same figure as (a)
FIG.

In the figure, element regions 2 made of polycrystalline St are formed in a matrix on the main surface of an insulating substrate 1.
A gate electrode 4 is formed on the surface of the element region 2 with a gate insulating film 3 interposed therebetween.

Furthermore, a mask 5iO7 film 7 is formed on the surface and side surfaces of the gate insulating film 3 and the gate electrode 4, and the device region 2 other than the projection region of the mask 5102 film 7, that is, the drain region 6 and the source region 5, is formed. A silicide film 8 is formed on the surface and the surface of the scanning wiring 101 excluding the gate electrode 4.

A signal wiring 102 and a pixel electrode 10 are connected to the silicide film 8 via an interlayer insulating film 9.

FIG. 4 is a cross-sectional view for explaining the manufacturing method of the active matrix substrate shown in FIG. E-F of
A line cross-sectional view is shown. In the same figure, the same 7 membrane numbers as in FIG. 1 or 2 represent the same or equivalent parts.

A polycrystalline silicon film to be an active layer is deposited by 1,500 layers on a glass substrate 1 by low pressure CVD, and then patterned to form an element region 2. Next, the 5102 film was subjected to atmospheric pressure CVD.
Then, a polycrystalline Si film is deposited by 1,500 people using a low pressure CVD method, and then patterned to form a gate insulating film 3, a gate electrode 4, and a scanning wiring 101.

Next, P+ ions are accelerated at a voltage of 20 KV and a dose of 5
After implantation at 1015 cm-2, heat treatment was performed at 600°C for 8 hours to form source electrode 5, drain electrode 6, gate electrode 4,
Lowering the resistance of the scanning wiring 101 [see (a) in the same figure].

Next, 1000 SiO2 films were deposited using the atmospheric CVD method.
Thereafter, the SiO2 film on the portions other than the top and side surfaces of the TPT gate electrode 4 is removed by photo-etching to form a mask 5IO2 film 7.

Next, a Pt film 11 was deposited by 400 people on the entire surface by sputtering [Fig.
, 30 minutes of heat treatment is performed to form a PT silicide layer 8 on the surface of the polycrystalline Si in the area where the mask S t 027 is not present. At this time, the surface of the element region 2 and the scanning wiring 1010 is silicided to approximately the same thickness as the initially deposited PT film 11, and furthermore, the surface of the element region 2 and the scanning wiring 1010 is silicided to a thickness approximately twice that of the PT film 11. A film is formed.

Here, if the entire polycrystalline Si film is silicided, the adhesion and properties with the underlying glass substrate 1 will deteriorate, and the formed silicide film will easily peel off.
The thickness of the PT film 11 needs to be approximately 1/2 or less of that of the polycrystalline Si film.

Next, the remaining PT film 11 that has not been silicided is selectively removed by treatment with hot aqua regia [Figure (C)]
.

Subsequently, phosphosilicate glass (PSG) is deposited by atmospheric pressure CVD to form an interlayer insulating film 9, and then contact through holes are formed.

Next, 6,000 Aρ films are deposited by sputtering, and then patterned to form signal wiring 102.

Next, the substrate is exposed to hydrogen plasma to introduce hydrogen into the element region 2 to reduce defects in the active layer 30 (FIG. 1(d)).
].

Finally, an indium tin oxide (ITO) film is deposited by sputtering, and then patterned to form the pixel drive electrodes 10, completing the active matrix substrate [FIG. 4(e)].

According to this report, since there is no silicide layer above the gate electrode 4 of the TPT, hydrogen enters the active layer (channel region) 30 and improves the device characteristics. Since the wiring 101 is connected without a contact through hole, the aperture ratio can be increased.

In the above embodiment, since the scanning line 101 and part of the source electrode 5 and train electrode 6 of the TFT are silicided at the same time, the thickness of the PT film 11 deposited first is the same as that of the active layer 2 and the gate electrode 6. The upper limit is about 172, which is the thinner of the two. However, when the active layer 2 is made thinner in order to reduce the off-state current of the TPT as much as possible, the thickness of the PT film 11 must be made thinner accordingly.

However, in this case, a problem arises in that a sufficiently thick silicide layer cannot be obtained on the scanning wiring 101, and the resistance of the wiring cannot be made sufficiently low.

A second embodiment will be described below with reference to FIG. 5 as a structure that solves this problem and provides a sufficiently low wiring resistance even when the polycrystalline Si film 2, which is the active layer, becomes thin.

[Example 2 A polycrystalline S1 film was formed on a co-glass substrate 1 using the LPCVD method.
A layer is deposited and then patterned to form an element region 2. Next, 1,000 layers of SIO2 film 51 are deposited, followed by 1,000 layers of polycrystalline Si film 52 [FIG. 4(a)].

Subsequently, 1000 SiO2 films are deposited, and then patterned to form a mask SIO2 film 7. Next, 400 people deposited a PT film 11 by sputtering [Figure (b)]
, Mask S was heat-treated at 480°C for 30 minutes in an oxygen atmosphere.
A portion of the polycrystalline Si film without the iO2 film 7 is selectively made into a silicide layer 8.

Next, the remaining PT was treated with hot aqua regia and was not silicided.
The film is removed and treated with hydrofluoric acid to form a mask SiO2 film 7.
[Figure (C)].

Next, the silicide layer 8, the polycrystalline Si film 52 and the S
The IO 2 film 51 is patterned to form a TPT gate electrode 4, a gate insulating film 3, and a scanning line 101.

Subsequently, As ions were implanted at an acceleration voltage of 30 KV at a dose of m5 x 1015 cm-2, and further at 600°.
The source electrode 5, the train electrode 6, and the gate electrode 4 are heat-treated with C to lower their resistance [FIG. 4(d)].

Thereafter, after depositing the interlayer insulating film 9, the active matrix board is completed in exactly the same manner as in the first embodiment.

In the method of this embodiment, the source electrode 5 and drain electrode 6 of the TPT are not silicided at all, so there is no need to make the PT film 11 particularly thin, and a sufficiently low scanning wiring resistance can be obtained.

[Third Embodiment] If it is necessary to further increase the aperture ratio, the scanning electrode 101 may be connected to the active region (channel region) of the element region 2, as shown in FIGS. 6(a) and 6(b). The scanning electrodes 101 may be arranged so as to be perpendicular to each other, and the scanning electrodes 101 may be used as gate electrodes of the TPT. In this case as well, the above-mentioned 1. As in the second embodiment, the upper part of the TPT active layer is not silicided, but the hydrogenation treatment is performed to sufficiently improve device characteristics.

[Fourth Embodiment] In the above three embodiments, the gate electrode 4 above the active layer of the TFT was explained as being composed only of a semiconductor film, but when higher-speed operation is required, , it is necessary to reduce the resistance of the gate electrode. In such cases,
A silicide film may be formed on a part of the gate electrode above the active layer of the TPT.

FIG. 7(a) is a cross-sectional view of an embodiment in which a silicide film 8 is formed only on a part of the gate electrode 4, and FIG.
There are 14 drawings in which the same reference numerals as above represent the same or equivalent parts.

Even in this structure, hydrogen can pass through between the silicide films 8 and enter the active layer 30, so there is no problem in that the hydrogenation treatment can be prevented.

[Fifth Embodiment] The present invention can also be applied to the case where the drain and drain electrodes 6 of a TFT and the signal wiring 102 are simultaneously formed using one photomask as shown in FIG. This structure can be manufactured by only partially changing the photomask in the manufacturing process shown in FIG.

The manufacturing process of the embodiment shown in FIG. 8 will be described below with reference to FIG. 9. In addition, in FIG. 9, the left half is a sectional view taken along the line CD in FIG. 8, and the right half is a sectional view taken along the line AB.

A polycrystalline Si film is deposited on a glass substrate 1 using the LPCVD method.
After that, the device region 2 and the signal wiring 102 are formed by patterning.

Next, 1000 S102 films are deposited by APCVD, followed by 1500 polycrystalline Si films by LPCVD, and then patterned to form gate insulating film 3 and gate electrode 4.

Next, P+ ions are accelerated at a voltage of 20 KV and a dose of 5
After implantation at 1015 cm-2, heat treatment was performed at 600°C for 8 hours to form source electrode 5, drain electrode 6, gate electrode 4,
The resistance of the signal wiring 102 is reduced [FIG. 2(a)].

Next, 1000 SiO2 films were deposited using the APCVD method, and T
S i of the part other than the -L part and the side surface of the gate electrode 4 of the PT
O2n is removed by photo-etching process and mask 5 is removed.
102 film 7 is formed.

Next, 400 PT films 11 were deposited on the entire surface by sputtering [Figure (b)], and then heated at 480° C. in an oxygen atmosphere.
Heat treatment is performed for 30 minutes to form a pt oxide layer 8 on the surface of the polycrystalline Si2 in the area where the mask S r 02 film 7 is not present.

Next, the remaining PT film 11 that has not been silicided is removed by treatment with hot aqua regia [FIG. 1(C)].

Subsequently, a PSG film is deposited by the APCVD method to form an interlayer insulating film 9.
is formed, and then a contact through hole is opened by an etching process.

Next, 6,000 AΩ films are deposited by sputtering, and then patterned to form scanning wiring 101.

Next, the substrate is exposed to hydrogen plasma to introduce hydrogen ions into the element region 2 to reduce defects in the active layer 30 [see FIG.
d) Ko.

Finally, an ITO film is deposited by sputtering, and then patterned to form pixel drive electrodes 10 to complete the active matrix substrate [FIG. 4(e)].

According to this embodiment, the gate electrode 4 of the TPT is made of polycrystalline S
Since it is an i-film, hydrogen can sufficiently penetrate into the active layer 30, and good device characteristics can be obtained. Furthermore, since the TPT drain electrode 6 and the signal wiring 102 are connected through a contact through hole, the aperture ratio can be further increased.

Although the above embodiments have been described using Pt silicide as an example of the metal silicide film, the method of the present invention is not limited to Pt silicide, but can also be applied to silicides of other metals. For applicable metal materials, it is necessary that the etching solution for the metal does not etch the silicide of the metal.

Specifically, when hot aqua regia is used as the etching solution, Ni and Co5Pd can be used in addition to pt.

Further, in the above embodiments, the silicide layer 8 was described as being formed by heat treatment in an oxygen atmosphere, but in the present invention, the silicide layer 8 may be formed by other methods.

For example, the silicide layer may be formed by heating the bracket by irradiation with laser light, electron beam, halogen lamp light, or the like.

When using a laser beam, for example in the embodiment shown in FIG. 4, after depositing the P film 11, the polycrystalline Si film and the PT film are A silicide layer 8 is formed by reacting with the silicide layer 8.

When irradiating with an electron beam or halogen lamp light, a silicide layer may be formed in exactly the same manner.

(Effects of the Invention) As is clear from the above description, according to the present invention, the following effects are achieved.

(1) Only the scanning wiring and the signal wiring are silicided, and the gate electrode is not silicided. Therefore, silicide (j-) is present above the channel region (active layer) of the thin film F conductor element in order to activate the channel region in the active matrix substrate which maintains a high aperture ratio due to the self-aligned wiring structure. Even when hydrogenation or fluorination treatment is applied to the semiconductor, hydrogen or fluorine ions pass through the gate electrode and reach the channel region, so the channel region is sufficiently activated and the device characteristics can be improved. .

(2> Since silicide is formed only on a portion of the surface of the gate electrode, the operating speed can be further improved without impairing the activation of the channel region.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of one cell of an active matrix dual plate according to an embodiment of the present invention, and FIG. 1(b) is a cross-sectional view taken along line A-B in FIG. Figure 1(e) is the same figure (, t
) (7) Cross-sectional view taken along line C-D, Figures 2 (a) and (b) are plan views of one cell of a conventional active matrix substrate, and Figure 3 shows TPT train currents due to differences in gate electrode materials. FIG. 4 is a sectional view showing the manufacturing process of an embodiment of the present invention, and FIG. 5 is a sectional view showing the manufacturing process of a second embodiment of the invention. , 6th
Figures (a) and (b) show 31a of the third embodiment of the present invention.
Figures 7(a) and 7(b) are a sectional view and a plan view of the fourth practical example of the present invention, respectively, and Figure 8 is a plan view of the fifth embodiment of the present invention, and Figure 9 is a plan view of the fourth practical example of the present invention. The figure is a sectional view taken along lines AB and CD in FIG. 8. Figure 1

Claims (9)

[Claims] (1) A thin film semiconductor element formed in a matrix on the main surface of an insulating substrate, and a thin film semiconductor element formed on the main surface of the insulating substrate in proximity to the thin film semiconductor element and connected to a first electrode of the thin film semiconductor element. a semiconductor thin film formed on the main surface of the insulating substrate in the row direction and serving as a gate electrode of the thin film semiconductor element; a column direction electrode wiring formed in the column direction and connected to the second electrode of the thin film semiconductor element, the row direction electrode wiring, the column direction electrode wiring, the first electrode and the second electrode What is claimed is: 1. A semiconductor device having silicide formed on the surface of at least a portion of the semiconductor device, characterized in that silicide is not formed on the surface of at least a portion of a region functioning as a gate electrode. (2) The semiconductor device according to claim 1, wherein the portion where the silicide is formed is a stack of silicide and a semiconductor thin film. (3) The semiconductor device according to claim 1 or 2, wherein the column direction electrode wiring and the second electrode are formed at the same time. (4) The semiconductor device according to any one of claims 1 to 3, wherein the thin film semiconductor element is a FET. (5) The semiconductor device according to any one of claims 1 to 4, wherein the row direction electrode wiring and the channel region of the thin film semiconductor element are formed so as to be perpendicular to each other. . (6) forming a first semiconductor thin film in a matrix on the main surface of an insulating substrate, and laminating a first insulating film and a second semiconductor thin film on the entire surface of the insulating substrate and the first semiconductor thin film; a step of etching these to form a row-direction electrode wiring that also serves as a gate electrode; a step of forming a protective film on at least the surface and side surfaces of the gate electrode; and a step of forming a metal thin film on the entire surface of the insulating substrate and the semiconductor thin film. a step of applying heat treatment to silicide the metal thin film; a step of removing the metal thin film that has not been silicided; a step of forming a second insulating film on the entire surface of the metal thin film; a step of forming a contact hole with the first semiconductor thin film in the insulating film; a step of forming an electrode metal film on the entire surface thereof; and a step of etching the electrode metal film into a predetermined shape to form an electrode metal. A method for manufacturing a semiconductor device, comprising the steps of: (7) forming a first semiconductor thin film in a matrix on the main surface of an insulating substrate; a first insulating film and a second semiconductor thin film on the entire surface of the insulating substrate and the first semiconductor thin film; and a step of laminating a protective film, a step of etching the protective film leaving the upper part of the second semiconductor thin film that will later become a gate electrode, a step of forming a metal thin film on the entire surface of the second semiconductor thin film, and a step of applying heat treatment to the semiconductor thin film. a step of siliciding the metal thin film; a step of removing the metal thin film that has not been silicided; a step of removing a protective film remaining on the upper part of the second semiconductor thin film; and a step of removing the silicide, the semiconductor thin film, and the second semiconductor thin film. 1 insulating film,
a step of etching the insulating substrate or the semiconductor thin film until it is exposed to form a gate electrode and a row direction electrode wiring; a step of forming a second insulating film on the entire surface of the insulating substrate or the semiconductor thin film; 1. Forming a contact hole with the semiconductor thin film of No. 1; Forming an electrode metal film on the entire surface of these; and Etching the electrode metal film into a predetermined shape to form an electrode metal. A method for manufacturing a semiconductor device, characterized by: (8) The method for manufacturing a semiconductor device according to claim 6 or 7, wherein the silicidation is performed by heat treatment in an oxygen atmosphere. (9) The method for manufacturing a semiconductor device according to claim 6 or 7, wherein the silicidation is performed by irradiation with laser beam, electron beam, or halogen lamp light.