JP3472231B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating substrate (in the present specification, refers to an entire object having an insulating surface, and is not limited to insulating materials such as glass, but also to materials such as semiconductors and metals unless otherwise specified. It also means that an insulator layer is formed on the
The present invention relates to an insulating gate type semiconductor device and a method for forming an integrated circuit having a large number of them formed therein. The semiconductor device according to the present invention is used as a drive circuit such as an active matrix such as a liquid crystal display or an image sensor, or as a thin film transistor in an SOI integrated circuit or a conventional semiconductor integrated circuit (microprocessor, microcontroller, microcomputer, semiconductor memory, etc.). It is what is done.

[0002]

2. Description of the Related Art Recently, much research has been done on forming an insulating gate type semiconductor device (MOSFET) on an insulating substrate. Forming the semiconductor integrated circuit on the insulating substrate in this manner is advantageous for high-speed driving of the circuit. Because
This is because the speed of the conventional semiconductor integrated circuit is limited mainly by the capacitance (stray capacitance) between the wiring and the substrate, but such stray capacitance does not exist on the insulating substrate. A MOSFET having a thin film-like active layer formed on an insulating substrate in this manner is called a thin film transistor (TFT). Also, in order to form an integrated circuit in multiple layers,
TFT is indispensable. Currently, in semiconductor integrated circuits, TFTs are used as load transistors for SRAMs, for example.

Further, recently, a product requiring the formation of a semiconductor integrated circuit on a transparent substrate has appeared. For example, it is a drive circuit for an optical device such as a liquid crystal display or an image sensor. A TFT is also used here. Since these circuits are required to be formed in a large area, it is required to lower the temperature of the TFT manufacturing process. Further, for example, in a device having a large number of terminals on an insulating substrate, even when it is necessary to connect the terminals to the semiconductor integrated circuit, in order to reduce the mounting density, the first stage of the semiconductor integrated circuit, Alternatively, it is considered that the semiconductor integrated circuit itself is monolithically formed on the same insulating substrate.

Conventionally, a TFT is provided with an amorphous, semi-amorphous, or microcrystalline semiconductor film 450.
It has been attempted to improve the crystallinity and improve the quality of the semiconductor film (that is, the mobility is sufficiently high) by annealing at a temperature of ℃ to 1200 ℃. Amorphous TFT using amorphous material for semiconductor film
However, mobility is 5 cm ² / Vs or less, usually 1 cm
^It is as small as ² / Vs, and in terms of operating speed, P
The use of the TFT of the channel type is greatly limited because it cannot be obtained. TF with mobility of 5 cm ² / Vs or more
Annealing at the above temperature was required to obtain T. Moreover, a P-channel TFT (PTFT) could be formed by such annealing.

[0005]

However, such thermal processes have severely constrained the substrate material. That is, in a so-called high temperature process (process with a maximum process temperature of 900 to 1200 ° C.), a high quality thermal oxide film can be used as a gate oxide film, but the substrate is expensive and has a large area like quartz, sapphire, or spinel. Only materials that are difficult to convert could be used.

On the other hand, in the low temperature process (the process in which the maximum process temperature is 450 to 750 ° C.), the range of selection of the substrate material is wider than that in the high temperature process, but long time annealing is required, and it is compared with the high temperature process. Then, the activation of the impurities is not sufficient and the sheet resistance of the source / drain is large. Also, a method of activating the crystallization of the active layer and the activation of the source / drain by irradiation with a laser or the like (hereinafter referred to as a laser process)
However, it was still difficult to reduce the sheet resistance. In particular, the electric field mobility is 150 cm ² / V
If a TFT that exceeds s is not manufactured, 2
A sheet resistance of 00Ω / □ or less was required.

The present invention has been made in view of the above problems and has a maximum process temperature of 750 ° C. or lower.
Without being restricted by the substrate material such as in high temperature process,
It is an object to provide a TFT whose sheet resistance is sufficiently reduced and a method for manufacturing the TFT.

[0008]

In the conventional low temperature process (maximum process temperature of 750 ° C. or lower) or laser process, the activation of the source / drain is particularly insufficient, and the sheet resistance is at least 100 to 1 kΩ / □ at the most. I only got it. For this reason, as a result, the characteristics of the device (particularly the mobility) cannot reach the original characteristics.

That is, since the source / drain parasitic resistance between the source electrode (contact portion) and the drain electrode is large, there is a problem that the ON current and operating speed of the TFT are reduced. However, on the other hand, it is difficult and unwise to bring the source electrode and the drain electrode close to each other because of the pattern formation limit (minimum design rule) and the need to reduce the parasitic capacitance between the gate electrode and other wiring. There wasn't.

According to the present invention, in this respect, a layered silicide, which is an alloy of metal and silicon, is adhered on the source / drain to form the source / drain in substantially the same shape, so that the source / drain is substantially formed. The sheet resistance is reduced to 100Ω / □ or less. Since the silicide is layered, the parasitic capacitance with the gate electrode is almost the same as that of the conventional source / drain. In particular, the present invention is that the gate electrode is covered with its anodic oxide, that the source / drain regions are formed in self-alignment with the gate electrode, and that the source / drain regions are in close contact with each other. Then, thin film silicide is formed.

In the present invention, it is desirable that the metal material forming the silicide is a material that allows the silicide to form ohmic contact with silicon semiconductor or a low-resistance contact close to ohmic contact. In particular,
Molybdenum (Mo), tungsten (W), platinum (platinum, Pt), chromium (Cr), titanium (Ti), cobalt (Co) are suitable. In order to carry out the present invention,
At least one of these metals is reacted with silicon to form a silicide.

Particularly in the present invention, the role played by the insulating anodic oxide is important. This anodic oxide serves to prevent short circuit between the silicide on the source / drain and the gate electrode. That is, the silicide is the source /
Since it is provided on substantially the entire surface of the drain, it eventually comes close to the gate electrode. The source / drain and the gate electrode are separated by the gate insulating film,
Silicide as in the present invention, once due to process requirements,
Since it is formed after removing the gate insulating film on the source / drain, there is a great possibility that the silicide contacts the gate electrode. If the anodic oxide is present on at least the side surface of the gate electrode, it is possible to prevent the contact between the silicide and the gate electrode, and yet to obtain the anodic oxide that is very dense and has good insulating properties. Therefore, the probability of short circuit can be significantly reduced.

Further, if the anodic oxide has an etching characteristic different from that of the gate electrode, the yield can be remarkably improved in the process. If the metal film has a similar etching rate to that of the gate electrode in the step of removing the metal film which has not been silicidized after forming the silicide film in the state where the anodic oxide covering the gate electrode does not exist, When etching the metal film, part or all of the gate electrode is etched. Therefore, from the viewpoint of etching, it is desirable that the anodic oxide be present on the upper surface of the gate electrode.

The method of manufacturing the TFT of the present invention basically comprises a step of anodizing the gate electrode and a step of forming a metal film for forming a silicide on the exposed element surface (including the silicon semiconductor region). The process includes four basic steps: a step of reacting silicon with the metal film by irradiating strong light such as a laser to form a silicide at the interface, and a step of removing an unreacted metal film.

In the present invention, selection of the material of the gate electrode is important because it also determines the type of anodic oxide. In the present invention, the gate electrode may be a pure metal such as aluminum, titanium, tantalum, or silicon, or an alloy obtained by adding a small amount of additive thereto (for example, an alloy obtained by adding 1 to 3% of silicon to aluminum, It is possible to use an alloy obtained by adding phosphorus of 1000 ppm to 5% to silicon), a conductive silicide such as tungsten silicide (WSi ₂ ) or molybdenum silicide (MoSi ₂ ), and a conductive nitride represented by titanium nitride. . In the present specification, unless otherwise specified, for example, aluminum means not only pure aluminum but also 10
% Of additives are included. The same is true for silicon and other materials.

In the present invention, a single-layered gate electrode using these materials alone may be used, or these may be used as the gate electrode.
A multi-layered gate electrode in which more layers are stacked may be used. For example, it has a two-layer structure in which tungsten silicide is stacked on aluminum and a two-layer structure in which aluminum is stacked on titanium nitride. The thickness of each layer may be determined by a practitioner according to the required device characteristics.

Further, in the present invention, the metal film is irradiated with intense light such as a laser and reacted with the underlying silicon semiconductor film to form a silicide, but if a laser is used, a pulsed laser is preferable. . Since the irradiation time of the continuous wave laser is long, there is a risk that the object to be irradiated expands due to the heat and peels off, and also the substrate is thermally damaged.

Regarding the pulsed laser, Nd: YAG
Infrared laser such as laser (preferably Q-switch pulse oscillation) or visible light such as its second harmonic, Kr
Various ultraviolet lasers using excimers such as F, XeCl and ArF can be used, but when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Further, the laser light may be applied from the substrate side. In this case, it is necessary to select the laser light that passes through the underlying silicon semiconductor film.

The thickness of the silicide is selected according to the sheet resistance required for the source / drain regions. If the sheet resistance of 10 to 100 Ω / □ is achieved, the specific resistance of the silicide is 0.1. Since it is ˜1 mΩ · cm, the thickness of the silicide is suitably 10 nm to 1 μm.

[0020]

[Embodiment] [Embodiment 1] FIG. 1 shows the present embodiment. First, the substrate (Corning 7059, 300 mm x 400 m
m or 100 mm × 100 mm) 100, a silicon oxide film having a thickness of 100 to 300 nm was formed as a base oxide film 101. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to further improve mass productivity, a film obtained by decomposing / depositing TEOS by the plasma CVD method may be annealed at 450 to 650 ° C.

After that, an amorphous silicon film of 30 to 500 n is formed by plasma CVD or LPCVD.
m, preferably 100-300 nm, which is 5
It was left to stand in a reducing atmosphere at 50 to 600 ° C. for 24 hours for crystallization. This step may be performed by laser irradiation. Then, the crystallized silicon film was patterned to form the island regions 102.
Further, a thickness of 70 to 150 is further formed on this by sputtering.
A silicon oxide film 103 having a thickness of 10 nm was formed.

After that, an aluminum (Al99% / Si1%) film having a thickness of 200 nm to 5 μm is formed by an electron beam evaporation method, and this is patterned to form a gate electrode 104. Further, an electric current is applied to this to form an anode in the electrolytic solution. It was oxidized to form an anodic oxide 105 having a thickness of 50 to 250 nm. This state is shown in FIG. For conditions of anodic oxidation, etc., see Japanese Patent Application No. 4-30220 (January 2, 1992).
1 day application) was used.

After that, the silicon oxide film 103 was removed except for the portion under the gate electrode and the anodic oxide to expose the surface of the silicon semiconductor 102. To remove the silicon oxide film 103, wet etching using an etching solution containing hydrofluoric acid as a main component or dry etching can be used.

After that, by the ion doping method, impurities are self-alignedly implanted into the island-shaped silicon film of each TFT by using the gate electrode portion (that is, the gate electrode and the anodic oxide film around the gate electrode) as a mask. An impurity region 106 was formed as shown in B). To form an NMOS TFT, phosphine (PH ₃ ) is used as a doping gas, and phosphorus is injected. To form a PMOS TFT, diborane (B ₂ H ₆ ) is used as a doping gas and boron is injected. The acceleration energy was 10 to 60 keV.

After that, as shown in FIG.
A tungsten film 107 having a thickness of up to 50 nm was formed by the sputtering method. Next, as shown in FIG. 1D, a KrF excimer laser (wavelength 248 nm, pulse width 20 ns) is used.
ec) was irradiated to react tungsten with silicon to form a tungsten silicide region 108 on the impurity region (source / drain). The energy density of the laser is 200 to 400 mJ / cm ² , preferably 250 to 3
00 mJ / cm ² was suitable. Much of the laser light was absorbed by the tungsten film and thus was barely utilized to restore the crystallinity of the underlying silicon impurity region, which was significantly damaged by previous ion doping. However, since tungsten silicide has a low resistivity of 30 to 100 μΩ · cm, the sheet resistance of the substantial source and drain regions (region 108 and the impurity region thereunder) was 10 Ω / □ or less. Immediately after the step of introducing impurities, the crystallinity deteriorated by introducing impurities may be restored by laser irradiation, thermal annealing, or the like.

After that, as shown in FIG. 1 (E), the unreacted tungsten film was etched. For example, if reactive etching is performed in a fluorocarbon atmosphere, tungsten becomes tungsten hexafluoride and can be evaporated and removed.

Finally, an interlayer insulator 109 is formed on the entire surface,
A silicon oxide film having a thickness of 300 nm was formed by the CVD method. Contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 110 and 111 were formed. By the above, the TFT was completed. Hydrogen activation may be further performed at 200 to 400 ° C. to activate the impurity regions.

[Second Embodiment] FIG. 2 shows a second embodiment. First, a base oxide film 202, an island-shaped silicon semiconductor region, and a silicon oxide film 204 functioning as a gate oxide film are formed on a substrate (Corning 7059) 201 as in the first embodiment.
A gate electrode 205 was formed from an aluminum film (thickness: 200 nm to 5 μm). Then, as shown in FIG. 2A, impurity implantation was performed by ion doping using the gate electrode as a mask to form an impurity region 203.

After that, the anodic oxide 20 is formed around the gate electrode (side surface and upper surface) by anodic oxidation as in the first embodiment.
6 was formed. In this case, compared to the case of the first embodiment,
It should be noted that the impurity region extends into the inside of the anodic oxide. After that, as shown in FIG. 2B, the region of the silicon oxide film 204 other than the portion existing under the gate electrode was removed to expose the surface of the impurity region.
Before moving to the next step, laser irradiation or thermal annealing may be performed to improve the crystallinity of the impurity region whose crystallinity is deteriorated by ion doping.

Then, as shown in FIG. 2C, the thickness 5
A molybdenum film 207 of ˜50 nm was formed by the sputtering method. Next, as shown in FIG. 2 (D), a KrF excimer laser (wavelength 248 nm, pulse width 20 nse
Irradiation with c) was performed to cause molybdenum to react with silicon to form a molybdenum silicide region 208 on the impurity region (source / drain).

After that, as shown in FIG. 2E, the molybdenum film which has not reacted is etched, and finally, as shown in FIG.
As shown in (F), an interlayer insulator 209 is formed on the entire surface,
A silicon oxide film having a thickness of 300 nm is formed by the CVD method,
Contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 210 and 211 were formed. The TFT was completed by the above steps.

[Third Embodiment] FIG. 3 shows the present embodiment. First, as shown in FIG. 3A, the substrate (Corning 705
9) A base oxide film 301, an island-shaped silicon semiconductor region 302, and a silicon oxide film 303 functioning as a gate oxide film are formed on 300 in the same manner as in Example 1, and a gate electrode 304 made of an aluminum film (thickness 200 nm to 5 μm) is formed. Was formed. Then, as in Example 1, anodic oxide 305 was formed around the gate electrode (side surface and upper surface) by anodic oxidation.

Then, the region of the silicon oxide film 103 other than the portion below the gate electrode portion is removed, and as shown in FIG. 3B, a platinum (Pt) film 306 having a thickness of 5 to 50 nm is formed by the sputtering method. Formed. Further, impurities were introduced by ion doping through this molybdenum film to form impurity regions 307 as shown in FIG. Next, as shown in FIG. 3D, a KrF excimer laser (wavelength 248 nm, pulse width 20 nse
C) is irradiated to react platinum and silicon, and the platinum silicide region 308 is made into an impurity region (source / drain).
Formed on.

After that, as shown in FIG. 3 (E), the unreacted platinum film was etched, and finally, as shown in FIG.
As shown in (F), an interlayer insulator 309 is formed on the entire surface.
A silicon oxide film having a thickness of 300 nm is formed by the CVD method,
Contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 310 and 311 were formed. The TFT was completed by the above steps.

Fourth Embodiment FIG. 4 shows this embodiment. First, as shown in FIG. 4A, the substrate (Corning 705
9) A base oxide film 401, an island-shaped silicon semiconductor region 402, and a silicon oxide film 403 functioning as a gate oxide film are formed on 400 in the same manner as in Example 1, and a gate electrode 404 made of an aluminum film (thickness 200 nm to 5 μm) is formed. Was formed. Then, as in Example 1, anodic oxidation was performed to form anodic oxide 405 around the gate electrode (side surface and upper surface).

Then, the region of the silicon oxide film 403 other than the portion under the gate electrode portion was removed, and as shown in FIG. 4B, a titanium film 406 having a thickness of 5 to 50 nm was formed by the sputtering method. Further, as shown in FIG.
rF excimer laser (wavelength 248 nm, pulse width 2
For 0 nsec) to react titanium with silicon to form a titanium silicide region 407.

After that, as shown in FIG. 4D, the titanium film that has not reacted is etched, and impurities are introduced in a self-aligned manner by the ion doping method using the gate electrode portion as a mask, and the titanium silicide region 407 is formed. Impurity region 408 was formed underneath. Finally, as shown in FIG. 4E, a silicon oxide film having a thickness of 300 nm is formed as an interlayer insulator 409 over the entire surface by a CVD method, contact holes are formed in the source / drain of the TFT, and an aluminum wiring / electrode is formed. 410 and 411 were formed. The TFT was completed by the above steps.

[0038]

According to the present invention, the substantial resistance between the source and the drain can be remarkably reduced. Conventionally, a method of performing thermal annealing for a long time has been used in order to reduce the resistance between the source / drain. However, this method has a low throughput, and the substrate temperature is increased to 550 ° C. or higher, so that the substrate material is restricted. On the other hand, a method using laser irradiation has also been attempted, but it is necessary to optimize the energy density of the laser in order to reduce the sheet resistance, and an appropriate sheet resistance can be obtained regardless of whether the energy density is low or high. There wasn't. Therefore, variations in the characteristics of the obtained TFT are large,
Also, as a result, the obtained sheet resistance is at most 10
It was 0Ω / □.

On the other hand, in the present invention, by forming a very thin silicide film on the surface of the silicon semiconductor (source / drain), the sheet resistance is remarkably reduced, typically to 100 Ω / □ or less. be able to. In the present invention, laser irradiation is required to obtain this silicide film, but the conditions are significantly milder than conventional silicon activation conditions, which contributes to a large improvement in yield.

In the present invention, the impurity region of the silicon semiconductor below the silicide layer may or may not be provided with a step (activation step) for recovering the crystallinity after the ion implantation. For example, when the impurity implantation is performed by the ion doping method, 10 ¹⁵ cm
^When heavy doping of ^-2 or more is performed, a sheet resistance of about 10 kΩ / □ can be obtained without providing an activation process, and a low-resistance silicide layer is formed close to the impurity region as in the present invention. If so, the substantial source or drain sheet resistance is sufficiently low.

However, many defects are present in the silicon semiconductor which has not been subjected to the activation step, and it may not be preferable from the viewpoint of reliability depending on the purpose. For such a purpose, activation of the impurity region should be performed. However, this increases the number of steps. However,
When laser irradiation is used as the activation step in this case, the purpose is not to optimize the sheet resistance of the impurity region, and therefore, a milder condition than in the conventional case can be applied. As described above, the present invention is remarkably beneficial in improving the characteristics of the TFT and improving the yield thereof.

[Brief description of drawings]

FIG. 1 shows a method for manufacturing a TFT according to the present invention.

FIG. 2 shows a method for manufacturing a TFT according to the present invention.

FIG. 3 shows a method for manufacturing a TFT according to the present invention.

FIG. 4 shows a method for manufacturing a TFT according to the present invention.

[Explanation of symbols]

100 insulating substrate 101 Base oxide film (silicon oxide) 102 Silicon semiconductor region 103 Silicon oxide film (becomes a gate oxide film) 104 Gate electrode (aluminum) 105 anodic oxide 106 impurity region 107 Metal film (tungsten) 108 Silicide film (tungsten silicide) 109 Interlayer insulation film (silicon oxide) 110,111 Metal wiring / electrode (aluminum)

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-2-42419 (JP, A) JP-A-61-56460 (JP, A) JP-A-59-110115 (JP, A) JP-A-4- 147629 (JP, A) JP 56-94671 (JP, A) JP 56-83935 (JP, A) JP 60-202931 (JP, A) JP 63-314862 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21/28

Claims (10)

(57) [Claims] 1. A base oxide film formed on a glass substrate, a silicon semiconductor layer formed on the base oxide film, a gate insulating film formed on the silicon semiconductor layer, and a gate insulating film on the gate insulating film. And the gate electrode portion formed on the silicon semiconductor layer are formed in a self-aligned manner by using the gate electrode portion as a mask to ion-dope the silicon semiconductor layer with phosphine or diborane as a doping gas. The source region and the drain region, and the gate insulating film except the portion below the gate electrode portion are removed, and the exposed metal film formed on the source region and the drain region is irradiated with light to form the source region. And silicon in the drain region and the metal film are reacted to form on the source region and the drain region. Wherein a and a Risaido layer. 2. A base oxide film formed on a glass substrate, a silicon semiconductor layer formed on the base oxide film, a gate insulating film formed on the silicon semiconductor layer, and a gate insulating film on the gate insulating film. And the gate electrode portion formed on the silicon semiconductor layer are formed in a self-aligned manner by using the gate electrode portion as a mask to ion-dope the silicon semiconductor layer with phosphine or diborane as a doping gas. The source region and the drain region, and the gate insulating film other than the portion below the gate electrode portion are removed, and the exposed metal film made of cobalt on the exposed source region and drain region is irradiated with light. The source region and the drain are formed by reacting silicon in the source region and the drain region with the metal film. Wherein a and a silicide layer having a cobalt formed on frequency. 3. An underlying oxide film formed on a glass substrate, a silicon semiconductor layer formed on the underlying oxide film, a gate insulating film formed on the silicon semiconductor layer, and on the gate insulating film. The silicon semiconductor layer is damaged by ion-doping the silicon semiconductor layer in a self-aligning manner with phosphine or diborane as a doping gas by using the gate electrode formed as a mask, thereby forming a source region and a drain region. The gate electrode portion including the gate electrode and formed so as to overlap a part of each of the source region and the drain region, and the gate insulating film except the portion below the gate electrode portion are removed to expose the exposed source. The metal film formed on the region and the drain region is irradiated with light so that the source region and the drain region are Wherein a and a silicon and said metal film and a silicide layer formed on the source region and the drain region by the reaction of. 4. A base oxide film formed on a glass substrate, a silicon semiconductor layer formed on the base oxide film, a gate insulating film formed on the silicon semiconductor layer, and a gate insulating film on the gate insulating film. The silicon semiconductor layer is damaged by ion-doping the silicon semiconductor layer in a self-aligning manner with phosphine or diborane as a doping gas by using the gate electrode formed as a mask, thereby forming a source region and a drain region. The gate electrode portion including the gate electrode and formed so as to overlap a part of each of the source region and the drain region, and the gate insulating film except the portion below the gate electrode portion are removed to expose the exposed source. The metal film made of cobalt formed in the region and the drain region is irradiated with light, and the source region and the Wherein a and a silicide layer and silicon in the fine drain region is reacted with the metal film having a cobalt formed on said source region and a drain region. 5. The semiconductor device according to claim 1, wherein the metal film is made of at least one of molybdenum, tungsten, platinum, titanium and chromium. 6. The semiconductor device according to claim 1 or 3, wherein the silicide layer contains at least one of molybdenum, tungsten, platinum, titanium, and chromium. 7. A any one of claims 1 to 6, wherein a said underlying oxide film has a thickness 100 to 300 nm. 8. A any one of claims 1 to 7, wherein a said silicide layer has a thickness 10 nm to 1 m. 9. A any one of claims 1 to 8, wherein a said a gate electrode portion is an anode oxide film covering the periphery of the gate electrode and the gate electrode. 10. A any one of claims 1 to 9, wherein the semiconductor device, liquid crystal displays, image sensors, SOI integrated circuits, microprocessors, microcontrollers, characterized in that it is used in a microcomputer or a semiconductor memory Semiconductor device.