JP2015056459A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having excellent integration.SOLUTION: In a semiconductor device, a gate electrode which is provided to bridge a semiconductor layer from one end face toward the other end face of the semiconductor layer is provided in a manner such that an end face of the gate electrode is brought in line with the end face of the semiconductor layer or arranged on the semiconductor layer. The semiconductor layer included in the semiconductor device is a semiconductor layer having an oxide semiconductor. In this configuration, adjacent gate electrodes can be provided at a distance from each other by the minimal processing dimension and over. In addition, since in the semiconductor layer having the oxide semiconductor, a high-resistant region can be achieved without overlapping the gate electrode in a region which does not overlap the gate electrode, a conduction state of an unnecessary semiconductor device can be inhibited.

Description

The present invention relates to an object, a method, or a manufacturing method. Or this invention relates to a process, a machine, a manufacture, or a composition (composition of matter). In particular, the present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof. In particular, one embodiment of the present invention relates to a semiconductor device, particularly a semiconductor device including an oxide semiconductor.

A transistor using silicon (Si) as a channel formation region (also referred to as an Si transistor) and a transistor using an oxide semiconductor (OS) as a semiconductor layer serving as a channel formation region (also referred to as an OS transistor) ), And a semiconductor device that can hold data is drawing attention (see, for example, FIG. 3 of Patent Document 1).

FIG. 8 of Patent Document 1 discloses an example of a cross-sectional view of a transistor including a semiconductor layer including an oxide semiconductor among transistors included in a semiconductor device that can retain data. The cross-sectional view discloses a configuration in which an end surface of a gate electrode provided so as to cross over a semiconductor layer from one end surface of the semiconductor layer to the other end surface is provided so as to exceed the other end surface of the semiconductor layer. This configuration is also referred to as an end cap.

JP 2011-170340 A

A semiconductor device capable of holding data is required to have a high degree of integration.

However, when designing the layout of a semiconductor device, it is necessary to separate the distance from the distance specified by the design rule, unless the gate electrodes of the transistors are the same node. Therefore, a layout in which the gate electrode of the transistor is an end cap is an obstacle for increasing the degree of integration.

In view of the above, an object of one embodiment of the present invention is to provide a semiconductor device with a novel structure and high integration. Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which the layout area can be reduced. Another object of one embodiment of the present invention is to provide a semiconductor device with a novel structure.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Problems other than those described above will be apparent from the description of the specification, drawings, claims, etc., and problems other than the above can be extracted from the description of the specifications, drawings, claims, etc. It is.

One embodiment of the present invention includes a transistor including a semiconductor layer, a source and drain electrodes, a gate insulating film, and a gate electrode, and the semiconductor layer is a semiconductor layer including an oxide semiconductor and one end surface of the semiconductor layer The semiconductor device is provided so that the end face of the gate electrode provided so as to cross the semiconductor layer from the first end face to the other end face coincides with the other end face.

Another embodiment of the present invention includes a semiconductor layer, a transistor including a source electrode and a drain electrode, a gate insulating film, and a gate electrode. The semiconductor layer is a semiconductor layer including an oxide semiconductor. The end face of the gate electrode provided so as to cross the semiconductor layer from the end face toward the other end face is a semiconductor device provided on the semiconductor layer.

According to one embodiment of the present invention, a first transistor including a first semiconductor layer, a first source electrode, a first drain electrode, a first gate insulating film, and a first gate electrode is provided. A second transistor including a first memory cell, a second semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating film, and a second transistor having a second gate electrode Each of the first semiconductor layer and the second semiconductor layer is a semiconductor layer having an oxide semiconductor, and the first semiconductor layer has a first semiconductor layer extending from one end surface toward the other end surface. The end surface of the first gate electrode provided so as to get over the semiconductor layer of the second semiconductor layer is provided so as to coincide with the other end surface, and the second semiconductor layer is directed from one end surface to the other end surface. Gate electrode provided over the layer The end surface is provided so as to coincide with the other end surface, and the first transistor included in the first memory cell and the second transistor included in the second memory cell are provided adjacent to each other. Device.

According to one embodiment of the present invention, a first transistor including a first semiconductor layer, a first source electrode, a first drain electrode, a first gate insulating film, and a first gate electrode is provided. A second transistor including a first memory cell, a second semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating film, and a second transistor having a second gate electrode Each of the first semiconductor layer and the second semiconductor layer is a semiconductor layer having an oxide semiconductor, and the first semiconductor layer has a first semiconductor layer extending from one end surface toward the other end surface. The end face of the first gate electrode provided so as to get over the semiconductor layer of the second semiconductor layer is provided on the first semiconductor layer, and extends from one end face of the second semiconductor layer toward the other end face of the second semiconductor layer. Second gate electrode provided over the layer The end surface is provided on the second semiconductor layer, and the first transistor included in the first memory cell and the second transistor included in the second memory cell are provided adjacent to each other. Device.

According to one embodiment of the present invention, a semiconductor device with a novel structure with excellent integration can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having a novel structure which can reduce the layout area can be provided. Note that one embodiment of the present invention is not limited to these effects. For example, one embodiment of the present invention may have effects other than these effects depending on circumstances or circumstances. Alternatively, for example, one embodiment of the present invention may not have these effects depending on circumstances or circumstances.

4A and 4B are a top view and a cross-sectional view according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a top view according to one embodiment of the present invention. 1 is a cross-sectional view according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view according to one embodiment of the present invention. 4A and 4B are a circuit diagram and a top view according to one embodiment of the present invention. 1 is a cross-sectional view according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view according to one embodiment of the present invention. 1 is a cross-sectional view according to one embodiment of the present invention. 1 is a cross-sectional view according to one embodiment of the present invention. 1A and 1B are a block diagram and a circuit diagram according to one embodiment of the present invention. 1A and 1B are a block diagram and a circuit diagram according to one embodiment of the present invention. 10A and 10B are a flowchart and a perspective schematic view illustrating a manufacturing process of a semiconductor device. Electronic equipment using semiconductor devices. 1 is a cross-sectional view according to one embodiment of the present invention. 1 is a cross-sectional view according to one embodiment of the present invention. 1 is a cross-sectional view according to one embodiment of the present invention. FIG. 10 is a circuit diagram of a display device according to an embodiment.

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and it is easily understood by those skilled in the art that the modes and details can be variously changed without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments. Note that in the structures of the invention described below, the same portions are denoted by the same reference numerals in different drawings.

In the drawings, the size, the thickness of layers, or regions are exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show an ideal example, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, channel region, and source. It is possible to do.

Here, since the source and the drain vary depending on the structure or operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, a portion functioning as a source and a portion functioning as a drain are not referred to as a source or a drain, one of the source and the drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode. There is a case.

In addition, the ordinal numbers “first”, “second”, and “third” used in this specification and the like are added to avoid confusion between components and are not limited in number. To do.

In this specification and the like, A and B are connected to each other, including A and B being directly connected, as well as those being electrically connected. Here, A and B are electrically connected. When there is an object having some electrical action between A and B, it is possible to send and receive electrical signals between A and B. It says that.

In addition, in this specification and the like, terms indicating arrangement such as “above” and “below” are used for convenience in describing the positional relationship between components with reference to the drawings. Moreover, the positional relationship between components changes suitably according to the direction which draws each structure. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately rephrased depending on the situation.

In addition, in this specification and the like, the arrangement of each circuit block in the drawing specifies the positional relationship for the sake of explanation, and even if it is shown in the drawing to realize different functions in different circuit blocks, actual circuits and regions In some cases, different functions may be realized in the same circuit or in the same region. In addition, the function of each circuit block in the drawing is to specify the function for explanation. Even if the function is shown as one circuit block, in an actual circuit or region, processing performed by one circuit block is performed by a plurality of circuit blocks. In some cases, it is provided.

In this specification and the like, the voltage often indicates a potential difference between a certain potential and a reference potential (for example, a ground potential). Thus, voltage, potential, and potential difference can be referred to as potential, voltage, and voltage difference, respectively. The voltage refers to a potential difference between two points, and the potential refers to electrostatic energy (electric potential energy) possessed by a unit charge in an electrostatic field at a certain point.

In general, the potential and voltage are relative. Therefore, the ground potential is not necessarily limited to 0 volts.

In this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

In this specification and the like, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

(Embodiment 1)
In this embodiment mode, a top view and a cross-sectional view of the semiconductor device, and a circuit diagram and a top view of the semiconductor device which can hold data will be described.

Note that a semiconductor device refers to a device having a semiconductor element. Note that a semiconductor device may include a drive circuit that drives a circuit including a semiconductor element. Note that a semiconductor device may include a driver circuit, a power supply circuit, and the like that are provided over another substrate.

First, FIG. 1A is a top view illustrating an example of a semiconductor device according to one embodiment of the present invention. 1B is a cross-sectional view corresponding to dashed-dotted lines A1-A2 and A3-A4 in FIG. Note that for ease of description, an insulating film or the like functioning as a gate insulating film is not illustrated in FIG.

The top view of the semiconductor device illustrated in FIG. 1A includes a semiconductor layer 11, a source electrode 12 and a drain electrode 13 provided over the semiconductor layer 11, and a gate electrode 15 overlapping with the semiconductor layer 11.

In FIG. 1A, in the region where the semiconductor layer 11 overlaps with the gate electrode 15, the end surface on which the gate electrode 15 rides is defined as one end surface 101, and the end surface on which the gate electrode 15 rides is defined as the other end surface 102. Further, an end face of the gate electrode 15 that goes over the semiconductor layer 11 is shown as an end face 103.

The “end face” refers to the face of the cut surface at the outer periphery when processing according to the mask pattern is performed by etching or the like. When an electrode or a semiconductor layer is processed in accordance with a mask pattern, as shown in end surfaces 101 to 103 in FIG. 1B, the cut surface has an obliquely cut shape or a rounded shape. In this case, as shown in the end surfaces 101 to 103 in FIG. 1B, when the electrode or semiconductor layer processed according to the mask pattern is viewed from the top surface, a surface perpendicular to the outer peripheral portion of the electrode or semiconductor layer is defined as the end surface. To do.

Note that the width of the semiconductor layer 11 is perpendicular to the direction in which the source electrode 12 and the drain electrode 13 are provided (in FIG. 1A, the direction in which the alternate long and short dash line A1-A2 extends) (in FIG. 1A). , The width in the direction in which the alternate long and short dash line A3-A4 extends). The width of the semiconductor layer 11 is preferably a line width having a minimum processing dimension. In FIG. 1A, the width of the semiconductor layer 11 is shown as '1F' which is the line width of the minimum processing dimension.

Further, the width of the semiconductor layer 11 is preferably formed with a minimum processing dimension in the same manner as the width of the semiconductor layer 11. Similarly, it is preferable that the gate electrode 15, the source electrode 12, and the drain electrode 13 are formed with a minimum processing dimension.

Note that the semiconductor layer 11 is preferably a semiconductor layer including an oxide semiconductor. By using the semiconductor layer 11 including an oxide semiconductor, a semiconductor device with extremely low leakage current can be obtained. Here, the small leakage current means that the normalized leakage current per channel width of 1 μm is 10 zA / μm or less at room temperature. Since the leak current is preferably as small as possible, the normalized leak current value is 1 zA / μm or less, more preferably 10 yA / μm or less, and further preferably 1 yA / μm or less. In this case, the voltage between the source and the drain is, for example, about 0.1V, 5V, or 10V.

A cross-sectional view of the semiconductor device illustrated in FIG. 1B includes a semiconductor layer 11 provided over a substrate 10, a source electrode 12 and a drain electrode 13 provided over the semiconductor layer 11, a semiconductor layer 11, and a source electrode. 12 and a gate insulating film 14 provided on the drain electrode 13 and a gate electrode 15 overlapping the semiconductor layer 11 with the gate insulating film 14 interposed therebetween.

Note that various insulating films, conductive films, semiconductor layers, circuit elements, and the like may be provided over the substrate 10. As an example, FIG. 16A illustrates an example in which the insulating film 99 is provided. The insulating film 99 includes, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. One or more materials may be selected from included materials and used in a single layer or a stacked layer.

In FIG. 1B, as in FIG. 1A, in the region where the semiconductor layer 11 overlaps the gate electrode 15, the end surface on the side on which the gate electrode 15 rides is one end surface 101, and the side on which the gate electrode 15 gets over. The end face is the other end face 102. Further, an end face of the gate electrode 15 that goes over the semiconductor layer 11 is shown as an end face 103.

Although there is no major limitation on the substrate 10, it is necessary to have at least heat resistance that can withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 10. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI (Silicon On Insulator) substrate, or the like can be applied, and a semiconductor element is formed on these substrates. A substrate provided with may be used as the substrate 10.

  For example, in this specification and the like, a transistor can be formed using various substrates. The kind of board | substrate is not limited to a specific thing. Examples of the substrate include a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, and a tungsten substrate. , A substrate having a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. As an example of the flexible substrate, there are plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES), or a synthetic resin having flexibility such as acrylic. Examples of the laminated film include polypropylene, polyester, vinyl, polyvinyl fluoride, or vinyl chloride. Examples of the base film include polyester, polyamide, polyimide, an inorganic vapor deposition film, and papers. In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, a transistor with small variation in characteristics, size, or shape, high current capability, and small size can be manufactured. . When a circuit is formed using such transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated.

Note that a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate, and the transistor may be disposed on another substrate. As an example of the substrate on which the transistor is transferred, in addition to the substrate on which the transistor can be formed, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (natural fiber (silk, cotton, hemp), There are synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (including acetate, cupra, rayon, recycled polyester), leather substrates, rubber substrates, and the like. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, reduce weight, or reduce thickness.

  Note that all circuits necessary for realizing a predetermined function can be formed over the same substrate (eg, a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate). Thus, the cost can be reduced by reducing the number of components, or the reliability can be improved by reducing the number of connection points with circuit components.

Note that it is possible not to form all the circuits necessary for realizing a predetermined function on the same substrate. In other words, a part of the circuit necessary for realizing the predetermined function is formed on a certain substrate, and another part of the circuit necessary for realizing the predetermined function is formed on another substrate. It is possible. For example, a part of a circuit necessary for realizing a predetermined function is formed on a glass substrate, and another part of a circuit required for realizing a predetermined function is a single crystal substrate (or an SOI substrate). Can be formed. Then, a single crystal substrate (also referred to as an IC chip) on which another part of a circuit necessary for realizing a predetermined function is formed is connected to the glass substrate by COG (Chip On Glass), and the glass substrate It is possible to arrange the IC chip. Alternatively, the IC chip can be connected to the glass substrate using TAB (Tape Automated Bonding), COF (Chip On Film), SMT (Surface Mount Technology), or a printed circuit board. As described above, part of the circuit is formed over the same substrate as the pixel portion, so that the cost can be reduced by reducing the number of components or the reliability can be improved by reducing the number of connection points with circuit components. . In particular, power consumption is often increased in a circuit having a high driving voltage or a circuit having a high driving frequency. Therefore, such a circuit is formed on a substrate (for example, a single crystal substrate) different from the pixel portion to constitute an IC chip. By using this IC chip, an increase in power consumption can be prevented.

Note that an oxide semiconductor material used for the semiconductor layer 11 may be an In-M-Zn-O-based material, for example. Specifically, the metal element M is Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Ga, Y, Zr, Nb, Mo, Sn, La, Ce, Pr, Nd, Sm, Eu. Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta or W, preferably Al, Ti, Ga, Y, Zr, Ce or Hf. Note that an oxide semiconductor will be described in detail later in an embodiment.

Note that for the source electrode 12 and the drain electrode 13, a conductive layer having a property of extracting oxygen from the semiconductor layer 11 using an oxide semiconductor is preferably used. For example, as a conductive layer having a property of extracting oxygen from the semiconductor layer 11, a simple substance, a nitride, an oxide, or an alloy containing Al, Ti, Cr, Ni, Mo, Ta, W, or the like is formed in a single layer or a stacked layer. Can be used.

Note that the gate insulating film 14 is made of a material containing aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. One or more may be selected and used in a single layer or a stacked layer.

Note that the gate electrode 15 is a single layer, nitride, oxide, or alloy containing one or more of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta, and W, or a single layer, or What is necessary is just to use it by lamination | stacking.

As illustrated in FIGS. 1A and 1B, in one embodiment of the present invention, the semiconductor layer 11 is a semiconductor layer including an oxide semiconductor and is directed from one end surface 101 of the semiconductor layer 11 to the other end surface 102. Thus, the end face 103 of the gate electrode 15 provided so as to get over the semiconductor layer 11 is provided so as to coincide with the other end face 102.

Note that one embodiment of the present invention is not limited to this. In some cases or depending on circumstances, the end surface 103 of the gate electrode 15 may not coincide with the end surface 102 of the semiconductor layer 11.

Note that FIG. 1B illustrates an example in which the gate electrode 15 is provided above the semiconductor layer 11; however, one embodiment of the present invention is not limited to this. A gate electrode 15 </ b> A may be provided below the semiconductor layer 11. An example in that case is shown in FIG. In addition, as illustrated in FIG. 17B, gate electrodes may be provided on both the upper side and the lower side of the semiconductor layer 11. Each gate electrode may be supplied with the same potential, or one of them may be supplied with a normal signal, and the other may be supplied with a constant voltage for controlling the threshold voltage. FIG. 17C shows an example in which the gate electrode 15 and the gate electrode 15A are connected through a contact hole.

A structure example in the case where the structure of the semiconductor device illustrated in FIGS. 1A and 1B is applied to a memory cell which can hold data is described with reference to FIGS.

2A is a circuit diagram in which a memory cell MEM_A (also referred to as a first memory cell) and a memory cell MEM_B (also referred to as a second memory cell) that can hold data are provided adjacent to each other. An example is shown. 2B shows a top view corresponding to the circuit diagram shown in FIG. 3A to 3C are cross-sectional views corresponding to dashed-dotted lines B1-B2, B3-B4, and B5-B6 illustrated in FIG. 2B. Note that for ease of description, an insulating film or the like functioning as a gate insulating film is not illustrated in FIG.

In the circuit diagram of the semiconductor device illustrated in FIG. 2A, the memory cell MEM_A includes a transistor Tr1_A, a transistor Tr2_A, and a capacitor Cp_A. The memory cell MEM_B includes a transistor Tr1_B, a transistor Tr2_B, and a capacitor Cp_B.

Note that the transistor Tr1_A, the transistor Tr2_A, the transistor Tr1_B, and the transistor Tr2_B are transistors in which a semiconductor layer is formed using an oxide semiconductor. In FIG. 2A, the symbol “OS” is attached to the transistor in order to indicate that the transistor includes an oxide semiconductor in a channel formation region.

The transistor Tr1_A has a gate connected to the word line WL_A, one of a source and a drain connected to the bit line BL, and the other of the source and the drain connected to one electrode of the capacitor Cp_A and the gate of the transistor Tr2_A. The other electrode of the capacitor Cp_A is connected to the capacitor line CL_A. In the transistor Tr2_A, one of a source and a drain is connected to the bit line BL, and one of the source and the drain is connected to the source line SL.

The transistor Tr1_B has a gate connected to the word line WL_B, one of a source and a drain connected to the bit line BL, and one of the source and the drain connected to one electrode of the capacitor Cp_B and the gate of the transistor Tr2_B. The other electrode of the capacitor Cp_B is connected to the capacitor line CL_B. In the transistor Tr2_B, one of a source and a drain is connected to the bit line BL, and one of the source and the drain is connected to the source line SL.

The semiconductor layer 11 includes a source electrode 12 and a drain electrode 13 provided on the semiconductor layer 11, and a gate electrode 15 overlapping the semiconductor layer 11.

Note that the data writing operation and the data reading operation with respect to the memory cell MEM_A and the memory cell MEM_B may be referred to Japanese Patent Laid-Open No. 2012-256813.

In the top view of the memory cell MEM_A and the memory cell MEM_B illustrated in FIG. 2B, the transistor Tr1_A, the transistor Tr2_A, and the capacitor Cp_A included in the memory cell MEM_A, and the transistor Tr1_B, the transistor Tr2_B, and the capacitor Cp_B included in the memory cell MEM_B are arranged. An example is shown. 2B illustrates an arrangement example of the word line WL_A, the word line WL_B, the capacitor line CL_A, the capacitor line CL_B, the bit line BL, and the source line SL.

Note that in the top view of the memory cell MEM_A and the memory cell MEM_B illustrated in FIG. 2B, the conductive layer in the same layer as the gate electrode 15 is denoted as “GM”, and the conductive layer in the same layer as the source electrode 12 and the drain electrode 13 is illustrated. It is shown as “S / DM”, and the semiconductor layer 11 is shown as “SEM”.

3A illustrates a semiconductor layer 121 provided over the substrate 10, a semiconductor layer 122, a conductive layer 123, a conductive layer 124, a bit line BL, a source line SL, and gate insulation. The film 14, the conductive layer 125, and the conductive layer 126 are included.

The cross-sectional view shown in FIG. 3B includes a semiconductor layer 121 provided over the substrate 10, a bit line BL, a source line SL, a gate insulating film 14, and a conductive layer 125.

3C illustrates a semiconductor layer 127 provided over the substrate 10, a conductive layer 123, a bit line BL, a gate insulating film 14, a word line WL_A, and a capacitor line CL_A. Have.

3A to 3C, the semiconductor layer 121, the semiconductor layer 122, and the semiconductor layer 127 are semiconductor layers formed in the same layer, and correspond to the semiconductor layer “SEM” illustrated in FIG. It is a semiconductor layer. The conductive layer 123, the conductive layer 124, the bit line BL, and the source line SL are conductive layers formed in the same layer, and are semiconductor layers corresponding to the conductive layer “S / DM” illustrated in FIG. . The conductive layer 125, the conductive layer 126, the word line WL_A, and the capacitor line CL_A are conductive layers formed in the same layer and are semiconductor layers corresponding to the conductive layer “GM” illustrated in FIG.

2B and 3A, in the region where the semiconductor layer 121 and the semiconductor layer 122 overlap with the conductive layer 125 and the conductive layer 126, the end surfaces of the conductive layer 125 and the conductive layer 126 are the semiconductor layer 121 and the semiconductor layer, respectively. It is provided so as to coincide with the end face of the layer 122. Therefore, as illustrated in FIG. 3A, a distance between the conductive layer 125 functioning as a gate electrode and the conductive layer 126 can be provided apart from each other by at least the minimum processing dimension. Therefore, a semiconductor device that is excellent in integration degree or that can reduce the layout area can be obtained.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 2)
In this embodiment, a semiconductor device having a structure different from that of the semiconductor device described in Embodiment 1 is described. In this embodiment, as in Embodiment 1, a top view and a cross-sectional view of a semiconductor device, and a circuit diagram and a top view of a semiconductor device that can hold data are described. In addition, when it becomes repeated description, description is abbreviate | omitted and description of the said Embodiment 1 may be used.

First, FIG. 4A is a top view illustrating an example of a semiconductor device according to one embodiment of the present invention. FIG. 4B is a cross-sectional view corresponding to dashed-dotted lines C1-C2 and C3-C4 in FIG. Note that for ease of description, an insulating film or the like functioning as a gate insulating film is not illustrated in FIG.

The top view of the semiconductor device illustrated in FIG. 4A includes a semiconductor layer 11, a source electrode 12 and a drain electrode 13 provided over the semiconductor layer 11, and a gate electrode 15 overlapping with the semiconductor layer 11.

4B is a cross-sectional view of the semiconductor device, the semiconductor layer 11 provided over the substrate 10, the source electrode 12 and the drain electrode 13 provided over the semiconductor layer 11, the semiconductor layer 11, and the source electrode. 12 and a gate insulating film 14 provided on the drain electrode 13 and a gate electrode 15 overlapping the semiconductor layer 11 with the gate insulating film 14 interposed therebetween.

As shown in FIGS. 4A and 4B, in one embodiment of the present invention, the semiconductor layer 11 is a semiconductor layer including an oxide semiconductor and is directed from one end surface 101 to the other end surface 102 of the semiconductor layer 11. Thus, the end face 103 of the gate electrode 15 provided so as to get over the semiconductor layer 11 is provided on the semiconductor layer 11 so as to be inside the semiconductor layer 11 by a width ΔW from the other end face 102. Is.

In the case where the semiconductor layer 11 is a semiconductor device of silicon, a region where the gate electrode 15 does not overlap becomes a conductor because a process of introducing an impurity element using the gate electrode 15 as a mask is performed. In this case, it becomes difficult to switch between a conductive state and a conductive state of the semiconductor device, which is performed by a voltage applied to the gate electrode 15.

On the other hand, in the semiconductor layer 11 including an oxide semiconductor, the step of introducing an impurity element is not performed using the gate electrode 15 as a mask. As a result, in a region that does not overlap with the gate electrode 15, a high resistance region can be obtained without overlapping the gate electrode 15. Therefore, switching between the conductive state and the conductive state of the semiconductor device can be realized without overlapping the gate electrode 15.

Note that one embodiment of the present invention is not limited to this. In some cases or depending on circumstances, the gate electrode 15 may get over the semiconductor layer 11 and the end face 103 of the gate electrode 15 may be disposed outside the semiconductor layer 11.

17A, 17B, and 17C, the end face of the gate electrode is on the semiconductor layer 11 so as to be inside the semiconductor layer 11 by the width ΔW from the end face 102 of the semiconductor layer 11. It is also possible to provide it. For example, FIG. 18A shows an example of application to FIG. In FIG. 17B, one or both of the gate electrode 15 and the gate electrode 15A have the end surface 102 of the semiconductor layer 11 inside the semiconductor layer 11 by a width ΔW so as to be inside the semiconductor layer 11. It is also possible to provide the upper side. An example in that case is shown in FIGS. Note that there is a case where either one of the gate electrode 15 and the gate electrode 15A goes over the semiconductor layer 11 and the end surface 103 of either the gate electrode 15 or the gate electrode 15A is disposed outside the semiconductor layer 11. is there.

A structure example in the case where the structure of the semiconductor device illustrated in FIGS. 4A and 4B is applied to a memory cell which can hold data is described with reference to FIGS.

In FIG. 5A, a memory cell MEM_A (also referred to as a first memory cell) and a memory cell MEM_B (also referred to as a second memory cell) that can hold data are adjacent to each other as in FIG. 1 shows an example of a circuit diagram provided. 5B shows a top view corresponding to the circuit diagram shown in FIG. 6A to 6C are cross-sectional views corresponding to dashed-dotted lines D1-D2, D3-D4, and D5-D6 illustrated in FIG. 5B. Note that for ease of description, an insulating film or the like functioning as a gate insulating film is not illustrated in FIG.

5B and 6A, in the region where the semiconductor layer 121 and the semiconductor layer 122 overlap with the conductive layer 125 and the conductive layer 126, the end surfaces of the conductive layer 125 and the conductive layer 126 are the semiconductor layer 121 and the semiconductor layer, respectively. It is provided so as to be on the layer 122. Therefore, as illustrated in FIG. 6A, the distance between the conductive layer 125 functioning as a gate electrode and the conductive layer 126 can be larger than the minimum processing dimension and can be separated. Therefore, a semiconductor device that is excellent in integration degree or that can reduce the layout area can be obtained. In addition, in the semiconductor layer including an oxide semiconductor, a high-resistance region can be formed without overlapping the gate electrode in a region that does not overlap with the gate electrode, so that unnecessary conduction of the semiconductor device can be suppressed. .

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 3)
In this embodiment, a modification of the semiconductor device described in Embodiments 1 and 2 is described. In the following, modifications 1 to 3 will be described with reference to FIGS. 7 to 9. In this embodiment, a top view and a cross-sectional view of a semiconductor device will be described as in the description of FIG. 1 of Embodiment 1 and FIG. 4 of Embodiment 2. In addition, when it becomes repeated description, description is abbreviate | omitted and the description of the said Embodiment 1 and Embodiment 2 may be used.

<Modification 1>
FIG. 7A is a top view illustrating an example of a semiconductor device according to one embodiment of the present invention. 7B is a cross-sectional view corresponding to dashed-dotted lines E1-E2 and E3-E4 in FIG. Note that for ease of description, an insulating film or the like functioning as a gate insulating film is not illustrated in FIG.

FIGS. 7A and 7B are structural examples in which the source electrode 12 and the drain electrode 13 are provided apart from the gate electrode 15 by a length ΔL in the semiconductor device described with reference to FIGS. It is the top view and sectional drawing which show.

7A and 7B differ from FIGS. 1A and 1B in that both the source electrode 12 and the drain electrode 13 are provided apart from the gate electrode 15 by a length ΔL. Note that only one of the source electrode 12 and the drain electrode 13 may be provided apart from the gate electrode 15.

The positions of the end surfaces of the source electrode 12 and the drain electrode 13 are preferably formed so as to be aligned with the end portions of the gate electrode 15 described with reference to FIGS. On the other hand, in a process for manufacturing a miniaturized semiconductor device, it is necessary to allow a certain shift due to the process. In a process for manufacturing a miniaturized semiconductor device, the function as a transistor can be maintained even if the source electrode 12 and the drain electrode 13 are separated by a length ΔL.

The semiconductor layer 11 in which the source electrode 12, the drain electrode, and the gate electrode 15 are not overlapped can be a semiconductor layer having a higher resistance than the case where the electrodes are overlapped. Therefore, with the structure illustrated in FIGS. 7A and 7B, a leakage current can be reduced and a semiconductor device having excellent switching characteristics can be obtained.

<Modification 2>
FIG. 8A is a top view illustrating an example of a semiconductor device according to one embodiment of the present invention. 8B is a cross-sectional view corresponding to dashed-dotted lines F1-F2 and F3-F4 in FIG. Note that for ease of description, an insulating film or the like functioning as a gate insulating film is not illustrated in FIG.

8A and 8B illustrate the semiconductor device described with reference to FIGS. 1A and 1B, in which the thickness of the semiconductor layer 11 is increased, and the end surface 103 of the gate electrode 15 is connected to one of the semiconductor layers 11. FIG. 6 is a top view and a cross-sectional view showing a configuration example provided with a distance ΔGI away from the end face 101 of FIG.

8A and 8B differ from FIGS. 1A and 1B in that the end face 103 of the gate electrode 15 is provided apart from one end face 101 of the semiconductor layer 11 by a length ΔGI.

The position of the end surface 103 in the gate electrode 15 is preferably formed so as to be aligned with the other end surface 102 of the semiconductor layer 11 described with reference to FIGS. On the other hand, in a process for manufacturing a miniaturized semiconductor device, it is necessary to allow a certain shift due to the process. In the process for manufacturing a miniaturized semiconductor device, the function as a transistor can be maintained even when the semiconductor device 11 is separated from the one end surface 101 by the length ΔGI.

In the thickened semiconductor layer 11, a voltage applied to the gate electrode 15 is applied through the gate insulating film 14, and a current to be flowed in the thickness direction can be secured. Therefore, with the structure shown in FIGS. 8A and 8B, the minimum processing dimension can be further reduced, and a semiconductor device with excellent integration and a reduced layout area can be obtained.

In addition, the semiconductor layer 11 is not necessarily composed of a single oxide semiconductor, but may be composed of a plurality of stacked oxide semiconductors. For example, FIG. 8C illustrates a configuration example of the semiconductor layer 11 in the case where the semiconductor layer 11 is formed by stacking three layers.

In the cross-sectional view illustrated in FIG. 8C, the semiconductor layers OS1 to OS3 are stacked in this order as the semiconductor layer 11.

The semiconductor layer OS1 and the semiconductor layer OS3 include at least one of metal elements constituting the semiconductor layer OS2 in its constituent elements, and the energy at the lower end of the conduction band is 0.05 eV or more and 0.07 eV than the semiconductor layer OS2. As described above, the semiconductor layer is close to a vacuum level at 0.1 eV or more or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Furthermore, it is preferable that the semiconductor layer OS2 contains at least indium because carrier mobility is increased.

The semiconductor layer OS3 may be provided on the source electrode 12. As an example, an example in which the semiconductor layer 11A is provided over the semiconductor layer 11 and the source electrode 12 is illustrated in FIG.

<Modification 3>
FIG. 9A is a top view illustrating an example of a semiconductor device according to one embodiment of the present invention. 9B is a cross-sectional view corresponding to dashed-dotted lines G1-G2 and G3-G4 in FIG. 9A. Note that for ease of description, an insulating film or the like functioning as a gate insulating film is not illustrated in FIG.

9A and 9B illustrate the base insulating layer 17 between the semiconductor layer 11, the source electrode 12 and the drain electrode 13, and the substrate 10 in the semiconductor device described with reference to FIGS. It is the top view and sectional drawing which show the structural example which provides this.

9A and 9B are different from FIGS. 1A and 1B in that a base insulating layer 17 is provided between the semiconductor layer 11 and the source and drain electrodes 12 and 13 and the substrate 10.

The base insulating layer 17 has a role of preventing diffusion of impurities from the substrate 10 and can also serve to supply oxygen to the semiconductor layer 11. Therefore, the base insulating layer 17 is preferably an insulating layer containing oxygen. For example, an insulating layer containing more oxygen than the stoichiometric composition is more preferable.

Excess oxygen contained in the base insulating layer 17 is oxygen contained exceeding the stoichiometric composition of the material. Accordingly, excess oxygen has a property of releasing when energy such as heat is applied. Excess oxygen is excessively contained with respect to the stoichiometric composition, so that even if it is lost by being released, the film quality is not deteriorated.

By providing the base insulating layer 17, the semiconductor layer 11 can be a high-quality semiconductor layer by mixing impurity elements and supplying oxygen to the semiconductor layer. Therefore, with the structure illustrated in FIGS. 9A and 9B, a semiconductor device having excellent transistor characteristics can be obtained.

As described above, the structure of the semiconductor device described in this embodiment can be implemented by appropriately combining modifications. In that case, in addition to the effects obtained by using the semiconductor device described in Embodiments 1 and 2, the effects described for each modification are added, and a semiconductor device having excellent performance can be obtained.

As described above, the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, a method for manufacturing the semiconductor device described in Embodiments 1 to 3 is described. In this embodiment, as an example, a method for manufacturing the semiconductor device illustrated in FIG. 9 in Embodiment 3 will be described with reference to FIGS. In addition, when it becomes repeated description, description is abbreviate | omitted and the description of the said Embodiment 1 thru | or 3 may be used.

First, the base insulating layer 17 is formed over the substrate 10 (see FIG. 10A).

The base insulating layer 17 may be formed using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, an ALD method, or a pulsed laser deposition (PLD) method.

Next, CMP treatment may be performed to planarize the surface of the base insulating layer 17. By performing the CMP treatment, the average surface roughness (Ra) of the base insulating layer 17 is 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. By setting Ra below the above numerical value, the crystallinity of the semiconductor layer 11 may increase. Ra can be measured with an atomic force microscope (AFM).

Next, an insulating layer containing excess oxygen may be formed by adding oxygen to the base insulating layer 17. Oxygen may be added by plasma treatment or ion implantation. In the case where oxygen is added by an ion implantation method, for example, the acceleration voltage may be 2 kV to 100 kV and the dose may be 5 × 10 ¹⁴ ions / cm ^{2 to} 5 × 10 ¹⁶ ions / cm ² .

Next, the semiconductor layer 11 is formed over the base insulating layer 17 by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method (see FIG. 10B). At this time, the base insulating layer 17 may be appropriately etched. By appropriately etching the base insulating layer 17, the semiconductor layer 11 can be easily covered with the gate electrode layer 410 to be formed later. Note that a hard mask may be used when the semiconductor layer 11 is processed in order to miniaturize the semiconductor device.

Further, in the case where a stacked film including the semiconductor layer OS1, the semiconductor layer OS2, and the semiconductor layer OS3 is formed as the semiconductor layer 11, it is preferable that each layer be continuously formed without being exposed to the air.

In order to reduce impurity contamination and form a semiconductor layer 11 using an oxide semiconductor with high crystallinity, the semiconductor layer 11 has a substrate temperature of 100 ° C. or higher, preferably 150 ° C. or higher, more preferably 200 ° C. or higher. Form a film. The oxygen gas or argon gas used as the film forming gas is a gas that has been highly purified to a dew point of −40 ° C. or lower, preferably −80 ° C. or lower, more preferably −100 ° C. or lower. Note that a low impurity concentration and a low density of defect states (low oxygen vacancies) are referred to as high purity intrinsic or substantially high purity intrinsic.

After the semiconductor layer 11 is formed, first heat treatment may be performed. The first heat treatment may be performed at a temperature of 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or a reduced pressure state. The atmosphere of the first heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement desorbed oxygen after heat treatment in an inert gas atmosphere. By the first heat treatment, the crystallinity of the semiconductor layer 11 can be increased and impurities such as hydrogen and water can be removed from the base insulating layer 17.

Next, a conductive film is formed over the semiconductor layer 11 and etched to divide the conductive film, so that the source electrode 12 and the drain electrode 13 are formed (see FIG. 10C). The conductive film may be formed by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

Note that when the conductive film is etched, the end portions of the source electrode 12 and the drain electrode 13 may be rounded (having a curved surface) in some cases. Further, when the conductive film is etched, the base insulating layer 17 may be appropriately etched.

Next, the gate insulating film 14 is formed over the semiconductor layer 11, the source electrode 12, and the drain electrode 13 (see FIG. 11A). The gate insulating film 14 may be formed using a sputtering method, a CVD method, or an ALD method.

Next, second heat treatment may be performed. The second heat treatment may be performed at a temperature lower than 500 ° C., preferably lower than 400 ° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or a reduced pressure state. The atmosphere for the second heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. By the second heat treatment, impurities such as hydrogen and water can be removed from the gate insulating film 14.

Next, a conductive film is formed over the gate insulating film 14, and the conductive film is etched to form the gate electrode 15 (see FIG. 11B).

Through the above steps, the semiconductor device illustrated in FIG. 9B can be manufactured.

An interlayer insulating layer 16 is formed on the manufactured semiconductor device. In this case, an interlayer insulating layer 16 is formed over the gate insulating film 14 and the gate electrode 15 (see FIG. 11C). The interlayer insulating layer 16 may be formed using a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

Next, third heat treatment may be performed. The third heat treatment can be performed under conditions similar to those of the first heat treatment. In some cases, oxygen vacancies in the semiconductor layer 11 can be reduced by the third heat treatment.

The interlayer insulating layer 16 is made of aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. One or more materials may be selected from included materials and used in a single layer or a stacked layer.

As described above, the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, an oxide semiconductor that can be used for the semiconductor layer 11 described in the above embodiment is described.

An oxide semiconductor used for a semiconductor layer serving as a channel formation region of the transistor preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable to contain In and Zn. In addition to these, it is preferable to have a stabilizer that strongly binds oxygen. The stabilizer may include at least one of gallium (Ga), tin (Sn), zirconium (Zr), hafnium (Hf), and aluminum (Al).

As other stabilizers, lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb) , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu).

Examples of the oxide semiconductor used as a semiconductor layer that serves as a channel formation region of the transistor include indium oxide, tin oxide, zinc oxide, In—Zn-based oxide, Sn—Zn-based oxide, Al—Zn-based oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide (also referred to as IGZO), In-Al-Zn oxide In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-Zr -Zn oxide, In-Ti-Zn oxide, In-Sc-Zn oxide, In-Y-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide In-Pr-Zn-based oxide, In-Nd-Z Oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In -Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga- Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In There are -Hf-Al-Zn-based oxides and the like.

For example, In: Ga: Zn = 1: 1: 1, In: Ga: Zn = 3: 1: 2, or In: Ga: Zn = 2: 1: 3 atomic ratio In—Ga—Zn-based oxidation An oxide in the vicinity of the product or its composition may be used.

When a large amount of hydrogen is contained in the oxide semiconductor film included in the semiconductor layer serving as a channel formation region, a part of the hydrogen becomes a donor and an electron which is a carrier is generated by bonding with the oxide semiconductor. As a result, the threshold voltage of the transistor shifts in the negative direction. Therefore, after the oxide semiconductor film is formed, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film so that impurities are contained as little as possible. preferable.

Note that oxygen may be reduced from the oxide semiconductor film due to dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film. Therefore, it is preferable that oxygen that has been reduced by dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film be added to the oxide semiconductor, or oxygen be supplied to fill oxygen vacancies in the oxide semiconductor film. In this specification and the like, the case where oxygen is supplied to the oxide semiconductor film may be referred to as oxygenation treatment or peroxygenation treatment.

In this manner, the oxide semiconductor film is made i-type (intrinsic) or i-type by removing hydrogen or moisture by dehydration treatment (dehydrogenation treatment) and filling oxygen vacancies by oxygenation treatment. An oxide semiconductor film that is substantially i-type (intrinsic) can be obtained. Note that substantially intrinsic means that the number of carriers derived from a donor in the oxide semiconductor film is extremely small (near zero), and the carrier density is 1 × 10 ¹⁷ / cm ³ or less, 1 × 10 ¹⁶ / cm ³ or less, It means 1 × 10 ¹⁵ / cm ³ or less, 1 × 10 ¹⁴ / cm ³ or less, and 1 × 10 ¹³ / cm ³ or less.

As described above, a transistor including an i-type or substantially i-type oxide semiconductor film can achieve extremely excellent off-state current characteristics. For example, the drain current when the transistor including an oxide semiconductor film is off is 1 × 10 ⁻¹⁸ A or less, preferably 1 × 10 ⁻²¹ A or less, more preferably 1 at room temperature (about 25 ° C.). × 10 ⁻²⁴ A or less, or 1 × 10 ⁻¹⁵ A or less, preferably 1 × 10 ⁻¹⁸ A or less, more preferably 1 × 10 ⁻²¹ A or less at 85 ° C. Note that an off state of a transistor means a state where a gate voltage is sufficiently lower than a threshold voltage in the case of an n-channel transistor. Specifically, when the gate voltage is 1 V or higher, 2 V or higher, or 3 V or lower than the threshold voltage, the transistor is turned off.

Further, the oxide semiconductor to be formed may have a non-single crystal, for example. The non-single crystal includes, for example, CAAC (C Axis Aligned Crystal), polycrystal, microcrystal, and amorphous part.

The oxide semiconductor may include, for example, CAAC. Note that an oxide semiconductor including CAAC is referred to as a CAAC-OS (C Axis Crystallized Oxide Semiconductor).

For example, the CAAC-OS may be able to confirm a crystal part in an observation image obtained by a transmission electron microscope (TEM: Transmission Electron Microscope). In many cases, a crystal part included in the CAAC-OS fits in a cube with a side of 100 nm, for example, as an observation image obtained by a TEM. In addition, in the CAAC-OS, there is a case where the boundary between the crystal part and the crystal part cannot be clearly confirmed in an observation image by TEM. In some cases, the CAAC-OS cannot clearly confirm a grain boundary (also referred to as a grain boundary) in an observation image obtained by a TEM. For example, the CAAC-OS does not have a clear grain boundary; In addition, since the CAAC-OS does not have a clear grain boundary, for example, the density of defect states is rarely increased. In addition, since the CAAC-OS does not have a clear grain boundary, for example, the decrease in electron mobility is small.

For example, the CAAC-OS includes a plurality of crystal parts, and the c-axis is aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface of the plurality of crystal parts. In addition, when the CAAC-OS is analyzed by an out-of-plane method using, for example, an X-ray diffraction (XRD) apparatus, a peak where 2θ indicating orientation is near 31 ° may appear. is there. In the CAAC-OS, for example, spots (bright spots) may be observed in an electron beam diffraction pattern. In particular, an electron beam diffraction pattern obtained using an electron beam having a beam diameter of 10 nmφ or less or 5 nmφ or less is referred to as a micro electron beam diffraction pattern. In the CAAC-OS, for example, the directions of the a-axis and the b-axis may not be uniform between different crystal parts. For example, the CAAC-OS may be c-axis oriented and the a-axis and / or b-axis may not be aligned with the macro.

The crystal part included in the CAAC-OS is aligned, for example, so that the c-axis is in a direction parallel to the normal vector of the formation surface of the CAAC-OS or the normal vector of the surface, and from a direction perpendicular to the ab plane. The metal atoms are arranged in a triangular shape or a hexagonal shape as viewed, and the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers as viewed from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, the term “perpendicular” includes a range of 80 ° to 100 °, preferably 85 ° to 95 °. In addition, a simple term “parallel” includes a range of −10 ° to 10 °, preferably −5 ° to 5 °.

In addition, the CAAC-OS can be formed by reducing the density of defect states, for example. In an oxide semiconductor, for example, oxygen vacancies are defect levels. Oxygen deficiency may become a trap generation level or become a carrier generation source by capturing hydrogen. In order to form the CAAC-OS, for example, it is important to prevent oxygen vacancies from being generated in the oxide semiconductor. Therefore, the CAAC-OS is an oxide semiconductor with a low density of defect states. Alternatively, the CAAC-OS is an oxide semiconductor with few oxygen vacancies.

Low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or substantially high purity intrinsic. An oxide semiconductor that is highly purified intrinsic or substantially highly purified intrinsic has few carrier generation sources, and thus may have a low carrier density. Therefore, a transistor in which the oxide semiconductor is used for a channel formation region may rarely have electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. In addition, an oxide semiconductor that is highly purified intrinsic or substantially highly purified intrinsic has a low defect state density, and thus may have a low trap state density. Therefore, a transistor in which the oxide semiconductor is used for a channel formation region may have a small change in electrical characteristics and be a highly reliable transistor. Note that the charge trapped in the trap level of the oxide semiconductor takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which an oxide semiconductor with a high trap state density is used for a channel formation region may have unstable electric characteristics.

In addition, a transistor using a high-purity intrinsic or substantially high-purity intrinsic CAAC-OS has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

For example, the oxide semiconductor may include polycrystal. Note that an oxide semiconductor including polycrystal is referred to as a polycrystalline oxide semiconductor. A polycrystalline oxide semiconductor includes a plurality of crystal grains.

For example, the oxide semiconductor may include microcrystal. Note that an oxide semiconductor including microcrystal is referred to as a microcrystalline oxide semiconductor.

For a microcrystalline oxide semiconductor, for example, a crystal portion may not be clearly identified in an observation image using a TEM. In many cases, a crystal part included in the microcrystalline oxide semiconductor has a size of 1 nm to 100 nm, or 1 nm to 10 nm, for example. In particular, for example, a microcrystal of 1 nm or more and 10 nm or less is called a nanocrystal (nc: nanocrystal). An oxide semiconductor including nanocrystals is referred to as an nc-OS (nanocrystalline Oxide Semiconductor). In addition, for example, the nc-OS may not be able to clearly confirm the boundary between the crystal part in the observation image by TEM. Further, for example, nc-OS does not have a clear grain boundary in an observation image obtained by a TEM, and thus impurities are hardly segregated. In addition, since the nc-OS does not have a clear grain boundary, for example, the density of defect states is rarely increased. Further, since the nc-OS does not have a clear grain boundary, for example, the decrease in electron mobility is small.

For example, the nc-OS may have periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm). In addition, since the nc-OS has no regularity between crystal parts, for example, there is a case where no periodicity is seen in the atomic arrangement macroscopically or a long-range order is not seen. . Therefore, the nc-OS may not be distinguished from an amorphous oxide semiconductor depending on, for example, an analysis method. For example, when the nc-OS is analyzed by an out-of-plane method with X-rays having a beam diameter larger than that of a crystal part using an XRD apparatus, a peak indicating orientation may not be detected. In nc-OS, for example, a halo pattern may be observed in an electron beam diffraction pattern using an electron beam having a beam diameter larger than that of a crystal part (for example, 20 nmφ or more, or 50 nmφ or more). In nc-OS, for example, a spot may be observed in a micro electron diffraction pattern using an electron beam having a beam diameter (for example, 10 nmφ or less, or 5 nmφ or less) that is the same as or smaller than the crystal part. . In addition, in the nc-OS micro-electron beam diffraction pattern, for example, a region with high luminance may be observed so as to draw a circle. In the micro electron beam diffraction pattern of the nc-OS, for example, a plurality of spots may be observed in the region.

Since the nc-OS may have periodicity in atomic arrangement in a minute region, the density of defect states is lower than that of an amorphous oxide semiconductor. Note that the nc-OS has no regularity between crystal parts, and thus has a higher density of defect states than the CAAC-OS.

Note that the oxide semiconductor may be a mixed film including two or more of a CAAC-OS, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. For example, the mixed film may include two or more of any of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, and a CAAC-OS region. . The mixed film includes, for example, a stacked structure of any two or more of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, a polycrystalline oxide semiconductor region, and a CAAC-OS region. May have.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 6)
In this embodiment, application examples of the semiconductor device described in Embodiments 1 to 3 are described.

FIG. 12 illustrates the case where a semiconductor device that can hold data is used as a memory device. 12A is a block diagram of a memory device, and FIG. 12B is a circuit diagram of a memory cell included in the memory device.

The block diagram of the memory device illustrated in FIG. 12A includes a memory cell array 301, a row driver 302, and a column driver 303 as an example.

The memory cell array 301 includes memory cells MEM arranged in an array.

The row driver 302 is a drive circuit for controlling the capacitor line CL and the word line WL.

The column driver 303 is a drive circuit for controlling the source line SL and the bit line BL.

The circuit diagram of the memory cell MEM illustrated in FIG. 12B includes a transistor Tr1, a transistor Tr2, and a capacitor Cp.

The transistor Tr1 has a gate connected to the word line WL, one of the source and the drain connected to the bit line BL, and the other of the source and the drain connected to one electrode of the capacitor Cp and the gate of the transistor Tr2. The other electrode of the capacitive element Cp is connected to the capacitive line CL. In the transistor Tr2, one of a source and a drain is connected to the bit line BL, and one of the source and the drain is connected to the source line SL.

Note that the transistor Tr1, the transistor Tr2, and the capacitor Cp illustrated in FIG. 12B are elements corresponding to the transistor Tr1_A, the transistor Tr2_A, and the capacitor Cp_A described in FIG. The word line WL and the capacitor line CL are wirings corresponding to the word line WL_A and the capacitor line CL_A described with reference to FIG.

Therefore, by using the semiconductor device according to one embodiment of the present invention, the memory device can be a memory device that is highly integrated or can have a reduced layout area.

Next, FIG. 13 illustrates a case where a semiconductor device that can hold data is used for a switch that can store configuration data included in a programmable logic device (PLD). FIG. 13A shows a block diagram of a PLD, and FIG. 13B shows a circuit diagram of a switch capable of storing configuration data included in the PLD.

The block diagram of the memory device illustrated in FIG. 13A includes a logic array 401, a row driver 402, a column driver 403, a configuration control circuit 404, an input / output circuit 405A, and an input / output circuit 405B as an example.

The logic array 401 includes programmable logic elements PLE arranged in an array and a switch RS capable of storing configuration data.

The row driver 402 and the column driver 403 are drive circuits for controlling configuration data stored in the programmable logic element PLE and the switch RS.

The configuration control circuit 404 is a circuit for controlling switching of configuration data. The input / output circuit 405A and the input / output circuit 405B are circuits whose data input or output functions are switched in accordance with configuration data.

The circuit diagram of the switch RS illustrated in FIG. 13B includes a transistor Tr1 and a transistor Tr2.

The transistor Tr1 has a gate connected to the word line WL, one of the source and the drain connected to the bit line BL, and the other of the source and the drain connected to the gate of the transistor Tr2. The transistor Tr2 has one of a source and a drain connected to the input terminal IN, and one of the source and the drain connected to the output terminal OUT. In FIG. 13B, a node to which the other of the source and the drain of the transistor Tr1 and the gate of the transistor Tr2 are connected is shown as a node FN.

The switch RS illustrated in FIG. 13B takes configuration data given to the bit line BL into the node FN through the transistor Tr1. Since the transistor Tr1 uses an oxide semiconductor for a semiconductor layer, leakage current can be extremely reduced, so that charge corresponding to configuration data can be held in the node FN. The switch RS can control the electrical connection between the input terminal IN and the output terminal OUT according to the configuration data held in the node FN.

The transistors Tr1 and Tr2 are elements corresponding to the transistors Tr1_A and Tr2_A described with reference to FIG. The word line WL is a wiring corresponding to the word line WL_A described with reference to FIG.

Therefore, by applying the semiconductor device according to one embodiment of the present invention, the PLD including the switch RS can be a PLD that has excellent integration or can reduce the layout area.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

(Embodiment 7)
In this embodiment, structural examples of the display panel of one embodiment of the present invention will be described.

[Configuration example]
FIG. 19A is a top view of a display panel of one embodiment of the present invention, and FIG. 19B can be used when a liquid crystal element is applied to a pixel of the display panel of one embodiment of the present invention. It is a circuit diagram for demonstrating a pixel circuit. FIG. 19C is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied to a pixel of the display panel of one embodiment of the present invention.

The transistor provided in the pixel portion can be formed according to the above embodiment mode. In addition, since the transistor can easily be an n-channel transistor, a part of the driver circuit that can be formed using an n-channel transistor is formed over the same substrate as the transistor in the pixel portion. In this manner, a highly reliable display device can be provided by using the transistor described in the above embodiment for the pixel portion and the driver circuit.

An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 801, a first scan line driver circuit 802, a second scan line driver circuit 803, and a signal line driver circuit 804 are provided over a substrate 800 of the display device. In the pixel portion 801, a plurality of signal lines are extended from the signal line driver circuit 804, and a plurality of scanning lines are extended from the first scanning line driver circuit 802 and the second scanning line driver circuit 803. Has been placed. Note that pixels each having a display element are provided in a matrix in the intersection region between the scan line and the signal line. In addition, the substrate 800 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) through a connection unit such as an FPC (Flexible Printed Circuit).

  In FIG. 19A, the first scan line driver circuit 802, the second scan line driver circuit 803, and the signal line driver circuit 804 are formed over the same substrate 800 as the pixel portion 801. For this reason, the number of components such as a drive circuit provided outside is reduced, so that cost can be reduced. Further, when a drive circuit is provided outside the substrate 800, it is necessary to extend the wiring, and the number of connections between the wirings increases. In the case where a driver circuit is provided over the same substrate 800, the number of connections between the wirings can be reduced, and reliability or yield can be improved.

[LCD panel]
An example of a circuit configuration of the pixel is shown in FIG. Here, a pixel circuit which can be applied to a pixel of a VA liquid crystal display panel is shown.

  This pixel circuit can be applied to a configuration having a plurality of pixel electrode layers in one pixel. Each pixel electrode layer is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. Thereby, the signals applied to the individual pixel electrode layers of the multi-domain designed pixels can be controlled independently.

  The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are separated so that different gate signals can be given. On the other hand, the source or drain electrode layer 714 functioning as a data line is used in common for the transistor 716 and the transistor 717. The transistors described in the above embodiments can be used as appropriate as the transistors 716 and 717. Thereby, a highly reliable liquid crystal display panel can be provided.

  The shapes of the first pixel electrode layer electrically connected to the transistor 716 and the second pixel electrode layer electrically connected to the transistor 717 are described. The shapes of the first pixel electrode layer and the second pixel electrode layer are separated by a slit. The first pixel electrode layer has a V-shaped shape, and the second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

  A gate electrode of the transistor 716 is connected to the gate wiring 712, and a gate electrode of the transistor 717 is connected to the gate wiring 713. Different gate signals are given to the gate wiring 712 and the gate wiring 713 so that the operation timings of the transistors 716 and 717 are different, whereby the alignment of the liquid crystal can be controlled.

  Further, a storage capacitor may be formed using the capacitor wiring 710, a gate insulating film functioning as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer.

  The multi-domain structure includes a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 includes a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween, and the second liquid crystal element 719 includes a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. Consists of.

  Note that the pixel circuit illustrated in FIG. 19B is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG.

[Organic EL panel]
FIG. 19C illustrates another example of the circuit configuration of the pixel. Here, a pixel structure of a display panel using an organic EL element is shown.

  In the organic EL element, by applying a voltage to the light-emitting element, electrons are injected from one of the pair of electrodes and holes from the other into the layer containing the light-emitting organic compound, and a current flows. Then, by recombination of electrons and holes, the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

  FIG. 19C illustrates an example of an applicable pixel circuit. Here, an example in which two n-channel transistors are used for one pixel is shown. Note that the metal oxide film of one embodiment of the present invention can be used for a channel formation region of an n-channel transistor. In addition, digital time grayscale driving can be applied to the pixel circuit.

  An applicable pixel circuit configuration and pixel operation when digital time gray scale driving is applied will be described.

  The pixel 720 includes a switching transistor 721, a driving transistor 722, a light-emitting element 724, and a capacitor 723. The switching transistor 721 has a gate electrode layer connected to the scan line 726, a first electrode (one of the source electrode layer and the drain electrode layer) connected to the signal line 725, and a second electrode (the source electrode layer and the drain electrode layer). Is connected to the gate electrode layer of the driving transistor 722. In the driving transistor 722, the gate electrode layer is connected to the power supply line 727 via the capacitor 723, the first electrode is connected to the power supply line 727, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 724. It is connected. The second electrode of the light emitting element 724 corresponds to the common electrode 728. The common electrode 728 is electrically connected to a common potential line formed over the same substrate.

  The transistor described in the above embodiment can be used as appropriate as the switching transistor 721 and the driving transistor 722. Thereby, an organic EL display panel with high reliability can be provided.

  The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. Note that the low power supply potential is lower than the high power supply potential set to the power supply line 727. For example, GND, 0 V, or the like can be set as the low power supply potential. A high power supply potential and a low power supply potential are set so as to be equal to or higher than the threshold voltage in the forward direction of the light emitting element 724, and by applying the potential difference to the light emitting element 724, a current is passed through the light emitting element 724 to emit light. Note that the forward voltage of the light-emitting element 724 refers to a voltage for obtaining desired luminance, and includes at least a forward threshold voltage.

  Note that the capacitor 723 can be omitted by substituting the gate capacitance of the driving transistor 722. With respect to the gate capacitance of the driving transistor 722, a capacitance may be formed between the channel formation region and the gate electrode layer.

  Next, a signal input to the driving transistor 722 will be described. In the case of the voltage input voltage driving method, a video signal that causes the driving transistor 722 to be sufficiently turned on or off is input to the driving transistor 722. Note that a voltage higher than the voltage of the power supply line 727 is applied to the gate electrode layer of the driving transistor 722 in order to operate the driving transistor 722 in a linear region. In addition, a voltage equal to or higher than a value obtained by adding the threshold voltage Vth of the driving transistor 722 to the power supply line voltage is applied to the signal line 725.

  In the case of performing analog gradation driving, a voltage equal to or higher than the value obtained by adding the threshold voltage Vth of the driving transistor 722 to the forward voltage of the light emitting element 724 is applied to the gate electrode layer of the driving transistor 722. Note that a video signal is input so that the driving transistor 722 operates in a saturation region, and a current is supplied to the light-emitting element 724. Further, in order to operate the driving transistor 722 in the saturation region, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By making the video signal analog, current corresponding to the video signal can be passed through the light-emitting element 724 to perform analog gradation driving.

  Note that the structure of the pixel circuit is not limited to the pixel structure illustrated in FIG. For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit illustrated in FIG.

  When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. 19, the source electrode (first electrode) is electrically connected to the low potential side, and the drain electrode (second electrode) is electrically connected to the high potential side. It is assumed that it is connected. Further, the potential of the first gate electrode is controlled by a control circuit or the like, and the potential exemplified above can be input to the second gate electrode, such as a potential lower than the potential applied to the source electrode by a wiring (not shown). do it.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 8)
In this embodiment, an example in which the semiconductor device described in any of the above embodiments is applied to an electronic component and an example in which the semiconductor device is applied to an electronic device including the electronic component will be described with reference to FIGS.

FIG. 14A illustrates an example in which the semiconductor device described in the above embodiment is applied to an electronic component. Note that the electronic component is also referred to as a semiconductor package or an IC package. This electronic component has a plurality of standards and names depending on the terminal take-out direction and the shape of the terminal. Therefore, in this embodiment, an example will be described.

The semiconductor device described in the above embodiment is completed by combining a plurality of parts that can be attached to and detached from the printed circuit board through an assembly process (post-process).

The post-process can be completed through each process shown in FIG. Specifically, after the element substrate obtained in the previous process is completed (step S1), the back surface of the substrate is ground (step S2). This is because by reducing the thickness of the substrate at this stage, it is possible to reduce the warpage of the substrate in the previous process and to reduce the size of the component.

A dicing process is performed in which the back surface of the substrate is ground to separate the substrate into a plurality of chips. Then, a die bonding process is performed in which the separated chips are individually picked up and mounted on the lead frame and bonded (step S3). For the bonding between the chip and the lead frame in this die bonding process, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. The die bonding step may be mounted on the interposer and bonded.

Next, wire bonding is performed in which the lead of the lead frame and the electrode on the chip are electrically connected by a thin metal wire (wire) (step S4). A silver wire or a gold wire can be used as the metal thin wire. For wire bonding, ball bonding or wedge bonding can be used.

The wire-bonded chip is subjected to a molding process that is sealed with an epoxy resin or the like (step S5). By performing the molding process, the inside of the electronic component is filled with resin, the built-in circuit part and wire can be protected by mechanical external force, and the deterioration of characteristics due to moisture and dust can be reduced. .

Next, the lead of the lead frame is plated. Then, the lead is cut and molded (step S6). By this plating treatment, rusting of the lead can be prevented, and soldering when mounting on a printed circuit board can be performed more reliably.

Next, a printing process (marking) is performed on the surface of the package (step S7). An electronic component is completed through a final inspection process (step S8) (step S9).

The electronic component described above can include the semiconductor device described in the above embodiment. Therefore, it is possible to realize an electronic component having a semiconductor device that has a high degree of integration or can reduce the layout area. Since the electronic component includes the semiconductor device described in the above embodiment, it is an electronic component that is reduced in size.

FIG. 14B shows a schematic perspective view of the completed electronic component. FIG. 14B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 700 illustrated in FIG. 14B illustrates a lead 701 and a semiconductor device 703. An electronic component 700 illustrated in FIG. 14B is mounted on a printed circuit board 702, for example. A plurality of such electronic components 700 are combined and each is electrically connected on the printed circuit board 702 to complete a substrate (mounting substrate 704) on which the electronic components are mounted. The completed mounting board 704 is provided inside an electronic device or the like.

Next, electronic devices such as computers, portable information terminals (including mobile phones, portable game machines, sound playback devices, etc.), electronic paper, television devices (also referred to as televisions or television receivers), digital video cameras, etc. A case where the above-described electronic component is applied will be described.

FIG. 15A illustrates a portable information terminal including a housing 901, a housing 902, a first display portion 903a, a second display portion 903b, and the like. At least a part of the housing 901 and the housing 902 is provided with a mounting substrate including the semiconductor device described in the above embodiment. Therefore, a portable information terminal with a reduced size is realized.

Note that the first display portion 903a is a panel having a touch input function. For example, as illustrated in the left diagram of FIG. 15A, a selection button 904 displayed on the first display portion 903a displays “touch input”. "Or" keyboard input "can be selected. Since the selection buttons can be displayed in various sizes, a wide range of people can feel ease of use. Here, for example, when “touch input” is selected, a keyboard 905 is displayed on the first display portion 903a as shown in the right diagram of FIG. As a result, as in the conventional information terminal, quick character input by key input and the like are possible.

In addition, the portable information terminal illustrated in FIG. 15A can remove one of the first display portion 903a and the second display portion 903b as illustrated in the right diagram of FIG. . The first display portion 903a is also a panel having a touch input function, and can be further reduced in weight when carried, and can be operated with the other hand by holding the housing 902 with the other hand. is there.

FIG. 15A illustrates a function for displaying various information (still images, moving images, text images, etc.), a function for displaying a calendar, date, time, or the like on the display unit, and operating or editing the information displayed on the display unit. A function, a function of controlling processing by various software (programs), etc. In addition, an external connection terminal (such as an earphone terminal or a USB terminal), a recording medium insertion portion, or the like may be provided on the rear surface or side surface of the housing.

The portable information terminal illustrated in FIG. 15A may be configured to be able to transmit and receive information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

Further, the housing 902 illustrated in FIG. 15A may have an antenna, a microphone function, or a wireless function, and may be used as a mobile phone.

FIG. 15B illustrates an electronic book mounted with electronic paper, which includes two housings, a housing 911 and a housing 912. A display portion 913 and a display portion 914 are provided in the housing 911 and the housing 912, respectively. The housing 911 and the housing 912 are connected by a shaft portion 915 and can be opened and closed with the shaft portion 915 as an axis. The housing 911 includes a power source 916, operation keys 917, a speaker 918, and the like. At least one of the housing 911 and the housing 912 is provided with a mounting substrate including the semiconductor device described in the above embodiment. Therefore, an electronic book with a reduced size is realized.

FIG. 15C illustrates a television device which includes a housing 921, a display portion 922, a stand 923, and the like. The television device can be operated with a switch included in the housing 921 or a remote controller 924. A mounting substrate including the semiconductor device described in any of the above embodiments is mounted on the housing 921 and the remote controller 924. Therefore, a television device with a reduced size is realized.

FIG. 15D illustrates a smartphone. A main body 930 is provided with a display portion 931, a speaker 932, a microphone 933, an operation button 934, and the like. In the main body 930, a mounting substrate including the semiconductor device described in the above embodiment is provided. Therefore, a smartphone with a reduced size is realized.

FIG. 15E illustrates a digital camera, which includes a main body 941, a display portion 942, operation switches 943, and the like. In the main body 941, a mounting substrate including the semiconductor device described in the above embodiment is provided. Therefore, a digital camera with a reduced size is realized.

As described above, a mounting substrate including the semiconductor device according to any of the above embodiments is mounted on the electronic device described in this embodiment. For this reason, an electronic device with a reduced size is realized.

OS1 semiconductor layer OS2 semiconductor layer OS3 semiconductor layer 11 semiconductor layer 10 substrate 14 gate insulating film 12 source electrode 13 drain electrode 15 gate electrode 16 interlayer insulating layer 17 underlying insulating layer Tr1 transistor Tr1_A transistor Tr1_B transistor Tr2 transistor Tr2_A transistor Tr2_B transistor 101 end face 102 End surface 103 End surface 121 Semiconductor layer 122 Semiconductor layer 123 Conductive layer 124 Conductive layer 125 Conductive layer 126 Conductive layer 127 Semiconductor layer 301 Memory cell array 302 Row driver 303 Column driver 401 Logic array 402 Row driver 403 Column driver 404 Configuration control circuit 405A Input / Output Circuit 405B Input / output circuit 410 Gate electrode layer 700 Electronic component 701 Lead 702 Print G substrate 703 Semiconductor device 704 Mounting substrate 710 Capacitor wiring 712 Gate wiring 713 Gate wiring 714 Drain electrode layer 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 Pixel 721 Switching transistor 722 Driving transistor 723 Capacitance element 724 Light emitting element 725 Signal line 726 Scan line 727 Power line 728 Common electrode 800 Substrate 801 Pixel unit 802 Scan line drive circuit 803 Scan line drive circuit 804 Signal line drive circuit 901 Case 902 Case 903a Display unit 903b Display unit 904 Select button 905 Keyboard 911 Case 912 Housing 913 Display unit 914 Display unit 915 Shaft unit 916 Power source 917 Operation key 918 Speaker 921 Housing 922 Display unit 923 Stand 924 Remote controller 930 Main body 931 Display unit 932 Speaker 933 Microphone 934 Operation button 941 Main body 942 Display unit 943 Operation switch

Claims (6)

A transistor having a semiconductor layer, a source electrode and a drain electrode, a gate insulating film, and a gate electrode;
The semiconductor layer is a semiconductor layer having an oxide semiconductor,
A semiconductor device characterized in that an end face of the gate electrode provided so as to cross over the semiconductor layer from one end face of the semiconductor layer to the other end face is provided so as to coincide with the other end face. . A transistor having a semiconductor layer, a source electrode and a drain electrode, a gate insulating film, and a gate electrode;
The semiconductor layer is a semiconductor layer having an oxide semiconductor,
An end face of the gate electrode provided so as to get over the semiconductor layer from one end face to the other end face of the semiconductor layer is provided on the semiconductor layer. In claim 1 or 2,
The semiconductor device, wherein the semiconductor layer is a semiconductor layer manufactured with a minimum processing dimension. A first memory cell provided with a first transistor having a first semiconductor layer, a first source electrode and a first drain electrode, a first gate insulating film, and a first gate electrode;
A second memory cell provided with a second semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating film, and a second transistor having a second gate electrode. And
The first semiconductor layer and the second semiconductor layer are semiconductor layers having an oxide semiconductor,
An end face of the first gate electrode provided so as to get over the first semiconductor layer from one end face of the first semiconductor layer toward the other end face is provided so as to coincide with the other end face. And
An end surface of the gate electrode provided so as to get over the second semiconductor layer from one end surface to the other end surface of the second semiconductor layer is provided so as to coincide with the other end surface;
The semiconductor device, wherein the first transistor included in the first memory cell and the second transistor included in the second memory cell are provided adjacent to each other. A first memory cell provided with a first transistor having a first semiconductor layer, a first source electrode and a first drain electrode, a first gate insulating film, and a first gate electrode;
A second memory cell provided with a second semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating film, and a second transistor having a second gate electrode. And
The first semiconductor layer and the second semiconductor layer are semiconductor layers having an oxide semiconductor,
An end face of the first gate electrode provided so as to get over the first semiconductor layer from one end face of the first semiconductor layer toward the other end face is provided on the first semiconductor layer. And
An end surface of the second gate electrode provided so as to get over the second semiconductor layer from one end surface to the other end surface of the second semiconductor layer is provided on the second semiconductor layer. And
The semiconductor device, wherein the first transistor included in the first memory cell and the second transistor included in the second memory cell are provided adjacent to each other. In claim 4 or 5,
The semiconductor device, wherein the first semiconductor layer and the second semiconductor layer are semiconductor layers manufactured with a minimum processing dimension.

Images