JPH098312A - Thin film transistor and fabrication thereof - Google Patents

Abstract

PURPOSE: To obtain a thin film transistor in which response and reliability are enhanced while simplifying the fabrication process. CONSTITUTION: The thin film transistor comprises a gate electrode 2, a source electrode 6 and a drain electrode 7 formed on the same plane of an insulating substrate 1, where the source electrode 6 and drain electrode 7 are disposed oppositely each other while spaced apart by a predetermined distance from the side face at the end part of the gate electrode 2. The thin film transistor further comprises a gate insulation film 3 covering the side face at the end part of the gate electrode 2 including at least the side face thereof, and an a-Si film 4 buried between the side face of gate insulation film 3 and the drain electrode 7 and extending to the upper surface thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used in a liquid crystal display, an image sensor, an integrated circuit and the like, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A thin film transistor is used as a switching element for selecting a pixel electrode in an active matrix type liquid crystal display device, a switching element for signal transfer in a contact image sensor, and the like.

In the structure of the thin film transistor, an inverted stagger type,
There is a type called the forward stagger type.

In a forward stagger type or an inverted stagger type thin film transistor, since the gate electrode and the source electrode and the drain electrode are present in different layers with the gate insulating film and the semiconductor film interposed therebetween, alignment in the photolithography process is performed. It is necessary to provide a slight overlap between the gate electrode and the source and drain electrodes in consideration of the shift. Therefore, there are problems that a parasitic capacitance is generated during this period and the response characteristics of the transistor are poor, and that the offset cannot be freely adjusted. Further, there is a problem in that the characteristics of the transistor are varied due to misalignment of the gate electrode with the source electrode and the drain electrode in the photolithography process, resulting in poor reliability.

A thin film transistor called a coplanar type is also known.

FIGS. 6A to 6D are sectional views showing the order of steps for explaining a conventional method of manufacturing a thin film transistor.

First, as shown in FIG. 6A, an amorphous silicon film (hereinafter a-) is formed on an insulating substrate 1 such as glass.
Si film) 21 (or polycrystalline silicon film) is deposited, and then a silicon nitride film and a Cr film are formed on the a-Si film 21.
A film is sequentially deposited and patterned to form a gate insulating film 3 made of a silicon nitride film and a gate electrode 2 made of a Cr film.
Are formed respectively.

Next, as shown in FIG. 6B, phosphorus ions are ion-implanted into the a-Si film 21 using the gate electrode 2 as a mask, and then the a-Si film 21 is patterned to n.
Each of the source region 19 and the drain region 20 made of a ⁺ type silicon layer is formed.

Next, as shown in FIG. 6C, an interlayer insulating film 16 such as a silicon nitride film is deposited on the entire surface including the gate electrode 2 and selectively etched to form a source region 19 and a drain region 20. Form a contact hole on top.

Next, as shown in FIG. 6 (d), a metal film such as a Cr film is deposited on the surface including the contact hole and patterned to connect to the source region 19 and the drain region 20 of the contact hole. The source electrode 6 and the drain electrode 7 are formed.

[0011]

The conventional thin film transistor of the forward stagger type or the inverted stagger type is affected by parasitic capacitance and misalignment due to overlap for allowing an alignment margin between the gate electrode and the source and drain electrodes. Characteristic variations occur, and in the coplanar type,
There is a problem in that the number of steps increases and the productivity is low.

An object of the present invention is to provide a thin film transistor in which misalignment between the gate electrode and the source and drain electrodes is eliminated without increasing the number of steps to reduce parasitic capacitance and improve reliability, and a manufacturing method thereof. Especially.

[0013]

A thin film transistor according to the present invention comprises a gate electrode formed on an insulating substrate and a gate electrode formed on the insulating substrate in the same plane as the gate electrode, and a constant distance from a side surface of an end of the gate electrode. A source electrode and a drain electrode which are spaced apart from each other and face each other; a gate insulating film formed by covering the side surface and the upper surface of the end portion of the gate electrode; and at least the side surface of the gate insulating film and the source and drain. And a semiconductor layer which is embedded between the side surface of the electrode and formed in a region including the source electrode and the drain electrode in common.

The method of manufacturing a thin film transistor according to the present invention comprises:
A step of sequentially depositing and forming a contact layer consisting of a metal film and a semiconductor layer containing impurities on an insulating substrate; and a step of selectively sequentially etching the contact layer and the metal film to form side surfaces of a gate electrode and an end portion of the gate electrode. Forming a source electrode and a drain electrode arranged at a constant distance from each other and facing each other; and depositing and patterning a non-doped amorphous silicon film on the surface including the gate electrode source electrode and drain electrode to form the gate electrode A step of forming a semiconductor layer in a region that commonly includes each end of the source electrode and the drain electrode, and a heat treatment after selectively implanting nitrogen ions into the semiconductor layer in a region including the upper surface and the side surface of the gate electrode And forming a gate insulating film on the upper surface and the side surface of the gate electrode. .

[0015]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1A is a plan view showing a first embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA-A 'of FIG. 1A.

As shown in FIGS. 1A and 1B, the gate electrode 2, the source electrode 6 and the drain electrode 7 are formed on the same plane on the insulating substrate 1, and the side surface of the end portion of the gate electrode 2 is formed. Has a source electrode 6 and a drain electrode 7 which are separated from each other by a constant distance and are arranged to face each other, and the side surface of the gate electrode 2 facing the source electrode 6 and the drain electrode 7. Gate electrode 2 containing at least
A, which is embedded between the gate insulating film 3 covering the end surface of the gate insulating film 3, the side surface of the gate insulating film 3 and the source electrode 6 and the drain electrode 7, and extends to the upper surfaces of the source electrode 6 and the drain electrode 7. An ohmic contact between the source / drain electrodes 6 and 7 and the a-Si film 4 is provided between the -Si film 4 and the upper surfaces of the source electrode 6 and the drain electrode 7 and the a-Si film 4. ^{And a +} type silicon layer 5.

2 (a) to 2 (e) are sectional views showing the order of steps for explaining the manufacturing method of the first embodiment of the present invention. Note that each drawing of FIG. 2 corresponds to the sectional view taken along the line AA-A ′ of FIG.

First, as shown in FIG. 2A, a metal film 8 made of Cr, Al, W or the like is formed on an insulating substrate 1 made of glass or the like.
Is deposited to a thickness of about 500 nm by using a sputtering method, and then an a-Si film is formed on it by plasma CVD.
Is deposited to a thickness of about 50 nm using the method. The plasma CVD condition at this time is, for example, a flow rate of SiH ₄ gas of 30.
0 sccm, H ₂ gas flow rate 200 sccm, temperature 27
0 ° C., RF power 250 W, pressure 100 Pa. Next, in order to form an ohmic contact layer, this a-
N-type impurities such as phosphorus, arsenic and antimony are ion-implanted into the Si film to form an n ⁺ -type silicon layer 5. The ion implantation conditions at this time are, for example, acceleration energy of 70 ke.
V, dose amount 1 × 10 ¹⁵ ions / cm ² .

Next, as shown in FIG. 2B, the n ⁺ type silicon layer 5 and the metal film 8 are selectively and sequentially etched by a photolithography process to form the gate electrode 2, the source electrode 6 and the drain electrode 7. Are patterned into a predetermined shape. At this time, the n ⁺ type silicon layer 5 is patterned into the same shape as the gate electrode 2, the source electrode 6 and the drain electrode 7.

Next, as shown in FIG. 2 (c), a
The -Si film 4 is deposited to a thickness of about 500 nm by the plasma CVD method, and the a-Si film 4 and the n ⁺ -type silicon layer 5 thereunder are continuously etched by a photolithography process to form an island shape. Forming a semiconductor active layer. At this time, this semiconductor active layer is patterned into a shape including the gate insulating film 3 in the a-Si film 4 in FIG.
The n ⁺ type silicon layer 5 outside the semiconductor active layer is removed.

Next, as shown in FIG. 2D, a photoresist film 10 is coated on the insulating substrate 1 and exposed and developed to form a photoresist film on the portion where the gate insulating film 3 is formed. Remove 10. Then, using the photoresist film 10 as a mask, nitrogen is applied to the a-Si film 4, for example, with an acceleration energy of 50 to 100 keV and a dose of 1
Ion implantation is performed under the condition of × 10 ¹⁵ to 1 × 10 ²⁰ ions / cm ² . When forming the photoresist film pattern, the a-Si film 4 is not left on the gate electrode after removing the photoresist film 10 so that the gate electrode 2 is slightly exposed and forming a gate insulating film. To do so.

Next, as shown in FIG. 2E, the photoresist film 10 is removed and heat-treated to form a gate insulating film 3 to form a thin film transistor. Note that the n ⁺ type silicon layer 5 may be formed directly on the metal film 8 by a plasma CVD method or the like instead of forming the n type impurities by ion implantation into the a-Si layer. . The plasma CVD condition at this time is, for example, a flow rate of SiH ₄ gas of 30.
0 sccm, PH ₃ gas flow rate 450 sccm, H ₂ gas flow rate 150 sccm, temperature 270 ° C., RF power 1
It is 50 W and the pressure is 100 Pa.

Further, instead of the a-Si layer 4, a microcrystalline silicon film, a polycrystalline silicon film or the like can be used. Similarly, instead of the n-type silicon layer 5, an n ⁺ -type polycrystalline silicon film or a microcrystalline silicon film can be used.

In this embodiment, since the gate electrode 2, the source electrode 6 and the drain electrode 7 are in the same plane, these electrodes can be formed by a single photolithography process, and the conventional method can be used. It is not necessary to consider misalignment as in a forward stagger type or an inverted stagger type thin film transistor. Therefore, parasitic capacitance generated between the gate electrode and the source and drain electrodes is reduced, and the response characteristics of the transistor can be improved.
Also, the offset can be adjusted freely. Further, variations in transistor characteristics can be reduced.

In this embodiment, the n ⁺ type silicon layer 5 is also used.
When the ion implantation method is used, a semiconductor film is formed twice, a metal film is formed once, a total of three times, similarly, three etching steps are performed, and three times resist coating, exposure, and development are sequentially performed. It can be manufactured by performing the steps and the two ion implantation steps. Therefore, as compared with the conventional coplanar thin film transistor, the number of ion implantation steps is increased by one, but the film formation step is performed twice, the etching step is performed twice, resist coating, exposure and development are sequentially performed. It can be reduced times.

In this embodiment, the thickness of the a-Si film 4 is set to 0.
5 μm, the distance between the source electrode 6 and the drain electrode 7 is 7 μm
m, the distance between the gate electrode 2 and the a-Si film 4 is 0.5 μm
On the other hand, an on-current of 1 × 10 ⁻⁸ A was obtained.

FIG. 3 (a) is a plan view showing an example of an active matrix type liquid crystal display device constructed by using the thin film transistor of the present invention, and FIG. 3 (b) is BB 'of FIG. 3 (a).
It is a line sectional view.

As shown in FIG. 3A, the scanning lines 12 connected to the gate electrodes 2 of the thin film transistors arranged in a matrix and arranged in parallel and the source electrodes 6 of the thin film transistors and the scanning lines 12 are connected. It has the data lines 13 arranged in parallel and intersecting at right angles, and the pixel electrode 14 connected to the drain electrode 7 of the thin film transistor, and the portion where the scanning line 12 and the data line 13 intersect is shown in FIG. b)
As shown in, the scanning line 12 formed on the same surface as the data line 13 on the insulating substrate 1 is divided in front of the data line 13, and the upper surface of the interlayer insulating film 16 covering the surface of the data line 12 at the intersection. The upper layer wiring 17 formed on the
The data lines 12 on both sides are electrically connected to each other and the protective insulating film 15 is formed on the entire surface including the thin film transistor and the pixel electrode 14.

At this intersection, at the intersection of the scanning line 12 and the data line 13 formed at the same time as each electrode of the thin film transistor, the Si layer for selectively forming the active layer of the thin film transistor and the Si layer are selectively deposited and gate insulation is performed. By implanting nitrogen ions into the Si layer at the intersecting portion to form the interlayer insulating film 16 at the same time as implanting the nitrogen ions for forming the film, it is not necessary to additionally add a step of forming the interlayer insulating film 16. Can be simplified.

FIG. 4 (a) is a plan view showing a second embodiment of the present invention, and FIG. 4 (b) is a sectional view taken along the line C--P 'of FIG. 4 (a).

As shown in FIGS. 4A and 4B, the a-Si film 4 is deposited on the surface including the gate electrode 2, the source electrode 6 and the drain electrode 7 in the same process as in the first embodiment. After patterning, the a-Si film 4 is etched so as to have a space spaced apart from the side surface of the gate electrode 2 facing the source electrode 6 and the drain electrode 7 by a constant distance, and an insulating film is formed on the surface including the space. A gate insulating film 3 is formed by depositing and filling the gap, and at the same time, a protective insulating film 15 covering the entire surface including the pixel electrode is formed.

In the second embodiment, the gate insulating film 3 and the protective insulating film 15 can be formed at the same time.
There is an advantage that the process can be shortened as compared with the embodiment.

The gate insulating film 3 may be formed by depositing and patterning a silicon nitride film on the surface including the gate electrode 2 formed on the insulating substrate 1.

FIG. 5 is a plan view showing a third embodiment of the present invention.

As shown in FIG. 5, the gate insulating film 3 formed on the side surface of the portion corresponding to the side oblique side of the gate electrode 2 whose tip is patterned in a trapezoidal shape and a provided on the outer surface thereof.
The structure is the same as that of the first embodiment except that the source electrode 6 and the drain electrode 7 having the side surface facing the gate electrode 2 via the -Si film 4 are provided.
It is possible to reduce the element size of the thin film transistors set to the same channel length, as compared with the above embodiment.

[0037]

As described above, according to the present invention, by providing the gate electrode, the source electrode and the drain electrode on the same plane, the alignment margin for patterning is unnecessary and the gap between the gate electrode and the source electrode and the drain electrode is eliminated. It is possible to reduce the parasitic capacitance generated in the transistor and improve the response characteristics of the transistor. Also, the gate electrode,
Since the source electrode and the drain electrode can be patterned by one photolithography process, variations in transistor characteristics can be reduced, reliability can be improved, and design can be performed without considering misalignment between electrodes. Therefore, the offset can be adjusted freely.

Further, since the gate electrode, the source electrode and the drain electrode are patterned by one photolithography process and the gate insulating film is formed by a method of implanting nitrogen into the semiconductor film, the manufacturing process is simplified. can do.

[Brief description of drawings]

FIG. 1 is a plan view and A- showing a first embodiment of the present invention.
OA 'sectional view taken on the line.

2A to 2D are sectional views showing the manufacturing method according to the first embodiment of the present invention in the order of steps.

3A and 3B are a plan view and a cross-sectional view taken along the line BB ′ showing an example of an active matrix type liquid crystal display device configured by using the thin film transistor of the invention.

FIG. 4 is a plan view and C- showing a second embodiment of the present invention.
Sectional drawing of the PC 'line.

FIG. 5 is a plan view showing a third embodiment of the present invention.

6A to 6C are cross-sectional views showing the order of steps for explaining a conventional method of manufacturing a thin film transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Gate electrode 3 Gate insulating film 4 a-Si film 5 n ⁺ type silicon layer 6 Source electrode 7 Drain electrode 8 Metal film 9 Nitrogen ion implantation layer 10 Photoresist film 12 Scan line 13 Data line 14 Pixel electrode 15 Protection Insulation film 16 Inter-layer insulation film 17 Upper layer wiring

Claims (3)

[Claims] 1. A gate electrode formed on an insulating substrate and a gate electrode formed on the insulating substrate in the same plane as the gate electrode and spaced from the side surface of the end of the gate electrode at a constant distance and facing each other. A source electrode and a drain electrode, a gate insulating film formed by covering the side surface and the upper surface of the end portion of the gate electrode, embedded at least between the side surface of the gate insulating film and the side surface of the source and drain electrode, and A thin film transistor having a semiconductor layer formed in a region including a source electrode and the drain electrode in common. 2. The thin film transistor according to claim 1, further comprising an ohmic contact layer provided between the upper surface of the source electrode and the drain electrode and the semiconductor layer. 3. A step of sequentially depositing and forming a contact layer consisting of a metal film and a semiconductor layer containing impurities on an insulating substrate, and a step of selectively sequentially etching the contact layer and the metal film to form a gate electrode, and Forming a source electrode and a drain electrode that are arranged at a certain distance from the side surface of the end of the gate electrode and opposed to each other, and depositing a non-doped amorphous silicon film on the surface including the gate electrode, the source electrode, and the drain electrode And patterning to form a semiconductor layer in a region including the ends of the gate electrode, the source electrode, and the drain electrode in common, and nitrogen selectively in the semiconductor layer in a region including the upper surface and the side surface of the gate electrode. A step of forming a gate insulating film on the upper surface and the side surface of the gate electrode by performing heat treatment after implanting ions. A method of manufacturing a thin film transistor, comprising: