KR100310707B1 - Thin film transistor liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

The present invention discloses a thin film transistor liquid crystal display device using low temperature polysilicon as a channel layer and preventing short circuits between a gate line and a data line in a thin film transistor liquid crystal display device having a coplanar top gate structure. The thin film transistor liquid crystal display device has a structure in which a buffer layer and a gate line formed between the lower portion of the active layer and the glass substrate are arranged directly on the glass substrate in order to prevent contact failure between the active layer, the source electrode, and the drain electrode. The gate electrode is arranged on top of the first insulating layer formed on the gate line. A second insulating layer for insulating the gate electrode is disposed on the first insulating layer including the gate electrode. The data line is arranged on the second insulating layer so as to be orthogonal to the gate line. The gate lines and gate electrodes insulated from each other form contact holes at their respective ends, and are electrically connected to each other by using a conductive film. In this way, the data line is insulated by the gate line and the first and second insulating layers of two layers, so that a short between them can be substantially prevented.

Description

Thin film transistor liquid crystal display device and manufacturing method thereof

The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor liquid crystal display device using polysilicon as an active layer and a method of manufacturing the same.

The thin film transistors used as switching elements for switching a signal applied to a pixel electrode in a liquid crystal display device include amorphous or polycrystalline silicon as a channel layer and CdSe.

A thin film transistor employing amorphous silicon as a channel layer can be formed at low temperature on a low-cost glass substrate using a chemical vapor deposition method using plasma, so that a large area can be easily increased, and thus it is excellent in mass productivity. In addition, since the energy band gap is about 1.8 eV, the number of free carriers in the film is small, and the OFF current is extremely small. On the other hand, since the mobility is less than 1 cm ² / V · sec, the ON current is small and the integration of the peripheral drive circuit is impossible.

In the thin film transistor liquid crystal display device using polycrystalline silicon as a channel layer, two kinds of substrates, namely, glass substrates and quartz substrates, may be used. The manufacturing process of the thin film transistors varies according to the type of substrate used.

Thin film transistors using quartz substrates instead of glass substrates can be easily used in semiconductor fabrication techniques because of the high temperature thermal oxidation. In this case, the gate thermal oxide film has a physical interface, extremely few defects, and high reliability of the thin film transistor. In addition, the thermal oxidation process can promote the crystal growth rate of polycrystalline silicon and realize high mobility of several 10 cm / Vsec. In addition, since the polycrystalline silicon thin film transistor can be self-aligned by a coplanar structure and an ion implantation method, the parasitic capacitance is extremely low, and the offset voltage can be suppressed, thus enabling integration with the peripheral driving circuit.

Despite these various advantages, the polysilicon thin film transistor using a quartz substrate has a high temperature process of about 1,000 ° C., and the quartz substrate is expensive compared to the glass substrate, and it is difficult to enlarge the quartz substrate. Therefore, methods using glass substrates instead of quartz substrates have been tried. In this case, it is required to lower the process temperature to 600 ° C. or lower for the application of the semiconductor manufacturing process.

Such low-temperature polysilicon thin film transistors are generally manufactured in a coplanar top gate structure. Therefore, only an interlayer insulating film exists between the gate line and the data line, and the thickness of the interlayer insulating film is determined in consideration of the short circuit at the portion where the gate line and the data line cross vertically and the coupling in the driving circuit. In order to secure stability for these two factors, the thickness of the gate insulating film must be increased. However, if the thickness is sufficiently increased considering only the stability, etching for the contact is difficult and the process time is increased. Therefore, an appropriate thickness should be set considering both aspects of insulation and etching process. As such, the low-temperature polysilicon thin film transistor has a problem to solve the short circuit problem between the gate line and the data line while minimizing the thickness of the interlayer insulating layer.

SUMMARY OF THE INVENTION An object of the present invention is to prevent a short between a gate line and a data line in a thin film transistor liquid crystal display device using low temperature polysilicon as a channel layer for a thin film transistor.

1 is a plan view schematically illustrating a portion including a thin film transistor and a peripheral portion of a thin film transistor liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. FIG.

3 is a cross-sectional view taken along line III-III of FIG. 1;

4 is a cross-sectional view taken along the line IV-IV of FIG. 1.

In order to achieve the above object, a thin film transistor liquid crystal display device according to the present invention, the glass substrate and the buffer layer formed between the lower portion of the active layer and the glass substrate in order to prevent contact failure between the active layer, the source electrode and the drain electrode It has a structure arranged just above. The gate electrode is arranged on top of the first insulating layer formed on the gate line. A second insulating layer for insulating the gate electrode is disposed on the first insulating layer including the gate electrode. The data line is arranged on the second insulating layer so as to be orthogonal to the gate line. The gate line and the gate electrode insulated from each other form contact holes at their respective ends, and are electrically connected using a conductive film. In this way, the data line is insulated by the gate line and the first and second insulating layers of two layers, so that a short between them can be substantially prevented.

In addition, according to the manufacturing method of the thin film transistor liquid crystal display device of the present invention, by depositing and patterning a metal layer directly on the glass substrate to form a buffer layer and a gate line separated by a predetermined interval at the same time. Then, a polysilicon layer is formed as an active layer on top of the glass substrate including the pair of buffer layers. The polysilicon layer is converted into a polysilicon layer by depositing an amorphous silicon layer and laser annealing the deposited amorphous silicon layer at low temperature. Next, a first insulating layer is formed on the glass substrate including the buffer layer. A gate electrode is formed on the first insulating layer including the polysilicon layer between the pair of buffer layers. Next, a second insulating layer is formed on the first insulating layer including the gate electrode. Thereafter, a contact hole exposing the polysilicon layer on the pair of buffer layers and a contact hole for connecting the gate line and the gate electrode are formed, and data perpendicular to the gate line through deposition and patterning of a selected metal. A line, a source electrode in contact with the polysilicon layer over the buffer layer adjacent to the data line, a drain electrode in contact with the polysilicon layer over the remaining buffer layer, and a wiring for electrically connecting the gate line and the gate electrode. According to the above method, since the buffer layer and the gate line are formed on the same plane, since two insulating layers are interposed between the gate line and the data line, the short between them can be substantially prevented.

The objects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a plan view schematically illustrating a portion including a thin film transistor and a peripheral portion thereof in a thin film transistor liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the gate line 50 includes a main line 50a arranged in the row direction and a branch line 50b vertically branched from the main line 50a.

The gate electrode 58 is positioned at a position spaced apart from the end of the branch line 50b of the gate line 50 by a predetermined interval. As will be described later, the gate electrode 58 of the present invention does not have a structure integrated with the gate line 50, nor is it located on the same plane as shown in FIG.

Since the gate electrode 58 and the gate line 50 must be electrically connected to each other, a wiring 60 is formed on each of them. The wiring 60 electrically connects the gate electrode 58 and the branch line 50b of the gate line 50 to each other through the lower contact holes 54c and 54d.

The data line 56 is arranged to be orthogonal to the main line 50a of the gate line 50. The data line 56 is a main line 56a orthogonal to the main line 50a of the gate line 50 and a main line 56a of the data line 56 so as to be parallel to the main line 50a of the gate line 50. Branch line 56b branching vertically from the top. Here, the branch line 56b of the data line 56 functions as a source electrode.

In FIG. 1, only one gate line 50 and one data line 56 are shown in relation to only a part of the unit pixels, but the gate line 50 and the data line 56 are substantially spaced apart from each other. A plurality is arranged in parallel with each other. In each of the data line 56 and the gate line 50, branch lines are arranged in parallel with each other at predetermined intervals.

The branch line 56b of the data line 56 is separated from the long side of the gate electrode 58 by a predetermined distance, and is drained to a symmetrical portion of the branch line 56b of the data line 56 with respect to the gate electrode 58. A contact hole 54b is formed to connect a terminal functioning as an electrode (not shown). A contact hole 54a is formed in the lower portion of the branch line 56b of the data line 56 so that the branch line 56b of the data line 56 contacts the lower active layer 46.

The active layer 46 functions as a channel layer for transmitting a signal applied through the data line 56 to a drain electrode (not shown). Under the active layer 46, buffer layers 44a and 44b having a larger area than the contact holes 54a and 54b are disposed.

The buffer layers 44a and 44b are provided to prevent contact defects between the source electrode 56 and the drain electrode (not shown) and the active layer 46 because the thickness of the active layer 46 is too thin. Molybdenum, Made of metal such as tungsten, aluminum, or aluminum alloy.

In the present invention, the buffer layers 44a and 44b and the gate line 50 are made of the same material and are located on the same plane, that is, directly above the glass substrate 42.

FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1, and two buffer layers 44a and 44b are disposed on the glass substrate 42 at predetermined intervals. The active layer 46 is covered on the upper portion of the glass substrate 42 including the two buffer layers 44a and 44b. The gate insulating layer 48, which is the first insulating layer, is formed on the glass substrate 42 including the active layer 46. The gate insulating layer 48 is for insulating the gate electrode 58 to be formed thereon.

The gate electrode 58 is disposed on the gate insulating layer 48 between the two buffer layers 44a and 44b. In order for the gate electrode 58 to function as a gate terminal of the thin film transistor, at least a predetermined portion must overlap at least with the active layer 46 below it. In addition, the two buffer layers 44a and 44b may be spaced apart by the same distance from the gate electrode 58 to form a symmetrical structure with respect to the gate electrode 58.

An interlayer insulating layer 52, which is a second insulating layer, is formed on the gate insulating layer 48 including the gate electrode 58, and a buffer layer is formed on the interlayer insulating layer 52 and the lower gate insulating layer 48. First and second contact holes 54a and 54b are formed to expose the active layer 46 on the upper portions 44a and 44b.

The source electrode 56b, which is a branch line of the data line 56, contacts the lower active layer 46 through the first contact hole 54a formed at one side, that is, at the left side of the gate electrode 58. do.

The active layer 46 is made of polysilicon and has a structure doped with an impurity layer reaching a predetermined depth from its surface, for example, N-type arsenic (As) or phosphorus (P). This impurity layer is arranged in a state where two are separated in one active layer at predetermined intervals. In addition, although not shown in the drawing, the active layer 46 has a lower concentration than that of the impurity layer at portions where the two impurity layers oppose each other in order to reduce the threshold voltage and prevent punch-through. The impurity layer may be configured to have a lightly-doped drain (LDD) structure bonded thereto.

3 is a cross-sectional view taken along line III-III of FIG. 1, wherein the main line 50a of the gate line 50 and the main line 56a of the data line 56 are not only an interlayer insulating film 52 but also a gate insulating film 48. Show the structure arranged with)).

Interposed between the data lines 56 and the gate lines 50 perpendicularly intersecting, two insulating films 48 and 50a are shown in FIG. 4, which is a cross-sectional view taken along the line IV-IV of FIG. 1. As shown, the gate line 50 has a structure separated from the gate electrode 58, and the gate line 50 is coplanar with the buffer layers 44a and 44b.

As such, since two insulating layers of the gate insulating layer 48 and the interlayer insulating layer 52 are interposed between the gate line 50 and the data line 56 of the present invention, a short circuit between these two lines can be substantially prevented. have.

On the other hand, in the above embodiment has been shown and described a case where a glass substrate is used, the same purpose and effect can be achieved even by using a quartz substrate or other transparent insulating substrate.

Hereinafter, a method of manufacturing a thin film transistor liquid crystal display device having the above structure will be described with reference to the accompanying drawings.

1 and 2, a metal layer such as molybdenum, tungsten, or aluminum is deposited and patterned directly on the glass substrate 42 to form a rectangular plate structure, and buffer layers 44a and 44b separated from each other by a predetermined interval. And the gate line 50 are formed at the same time.

Then, the polysilicon pattern layer 46 is formed as an active layer on the glass substrate 42 including the pair of buffer layers 44a and 44b.

The polysilicon pattern layer 46 deposits an amorphous silicon layer, laser anneales the deposited amorphous silicon layer at a low temperature of about 300 ° C., phase-converts the amorphous silicon layer to a polysilicon layer, and is phase-converted. It is formed by patterning a polysilicon layer.

In the polysilicon layer 46, two separate impurity layers containing a predetermined concentration of N-type impurities, for example, arsenic or phosphorus, reaching a predetermined depth from the surface may be selectively formed. It is performed by ion implantation and laser annealing to activate the implanted impurity ions.

In addition, the impurity layer may optionally have a low doping drain (LDD) structure. In this case, as in the general semiconductor manufacturing process, primary ion implantation of low concentration N-type impurities is performed, masking predetermined portions of the low concentration impurity layers facing each other, secondary ion implantation of high concentration of N-type impurities, and finally It can be carried out by laser annealing.

Alternatively, the anodization layer may be further formed by anodizing the buffer layer at the interface between the buffer layers 44a and 44b and the polysilicon pattern layer 46.

Next, a gate insulating layer 48 as a first insulating layer is formed on the glass substrate 42 including the polysilicon pattern layer 46. The gate insulating layer 48 is made of silicon dioxide (SiO ₂ ) having excellent insulating properties. Silicon dioxide used as the gate insulating layer 48 has excellent electrical properties such as insulating properties and interfacial properties, but has a low deposition rate. Therefore, it is preferable to form the silicon dioxide layer as thin as possible in order to shorten the process time as long as the insulating property of the gate is maintained.

Next, the gate electrode 58 is formed on the first insulating layer 48 between the pair of buffer layers 44a and 44b. The gate electrode 58 should at least partially overlap with the polysilicon pattern layer 46 that functions as a channel layer at the bottom thereof. In the case where the gate electrode 58 does not overlap with the polysilicon pattern layer 46, the gate electrode 58 cannot function as the gate electrode of the thin film transistor, so the above conditions must be executed.

Next, an interlayer insulating film 52 serving as a second insulating layer is formed on the gate insulating layer 48 including the gate electrode 58. The interlayer insulating film 52 is for insulating the gate electrode 58 formed below and the source electrode 56a, drain electrode (not shown), and pixel electrode (not shown) to be formed thereon. It is formed thicker than the gate insulating film 48 by using a material having a lower deposition rate than the silicon dioxide (48) but having a high deposition rate.

Thereafter, as shown in FIG. 2, the first and second contact holes 54a and 54b exposing the polysilicon layer 46 over the pair of buffer layers 44a and 44b, and as shown in FIG. 4. The third and fourth contact holes 54c and 54d for electrically connecting the gate line 50 and the gate electrode 58 to each other are formed.

Then, through deposition and patterning of the selected metal, the data line 56 including the source electrode 56b contacting the polysilicon layer 46 on the buffer layer 44a on one side and the buffer layer 44b on the other side. A drain electrode (not shown) in contact with the polysilicon layer 46 and a wiring 60 electrically connecting the gate line 50 and the gate electrode 58 are formed.

Although not shown, following the completion of the above steps, a process of forming a pixel electrode contacting the drain electrode through the second contact hole 54b and a process of forming the alignment layer are followed.

Through the above processes, the thin film transistor substrate is completed, and the color filter substrate facing the thin film transistor substrate is prepared through a conventional method. A liquid crystal display panel is completed through the liquid crystal layer between these two prepared substrates.

According to the above method, by forming the buffer layer and the gate line on the same plane, a gate insulating layer having excellent insulating properties is interposed with the interlayer insulating film between the gate line and the data line, so that a short between the two lines can be substantially prevented. have.

On the other hand, in the above embodiment, although the glass substrate is used to show an example, it has been described, it is also possible to use a transparent insulating substrate such as a quartz substrate. In this case, the process of phase-converting the amorphous silicon layer to polysilicon and the laser annealing process for activating the ion implanted impurities may be replaced by a thermal annealing process.

As described above, the thin film transistor liquid crystal display device using the polysilicon of the present invention as an active layer has a gate line and an interlayer insulating film interposed therebetween by providing a gate insulating layer having an excellent insulating property between the gate line and the data line. It is possible to substantially prevent a short circuit failure at the intersection of the data lines, and to reduce the thickness of the interlayer insulating film in proportion to the thickness of the layered gate insulating layer, thereby ensuring the stability of the etching process for the contact. .

Herein, although specific embodiments of the present invention have been described and illustrated, modifications and improvements may be made by those skilled in the art without departing from the spirit and spirit of the present invention. Accordingly, the claims of the present invention are hereafter considered to include all such modifications and improvements.

Claims (5)

A transparent insulating substrate; A plurality of gate lines arranged in parallel on the insulating substrate at predetermined intervals and including vertically branched branch lines; A pair of buffer layers each formed on the same plane as the gate line in two regions separated by extension lines of the respective branch lines, spaced apart from the extension lines of the respective branch lines by a predetermined distance; An active layer formed on the insulating substrate to cover the pair of buffer layers; A first insulating layer formed on the insulating substrate including the active layer and the gate line; A conductive gate electrode separated from the branch line of the gate line and formed over the first insulating layer so as to overlap at least the active layer between the pair of buffer layers; A second insulating layer formed on the first insulating layer including the gate electrode; First to second layers formed on the second insulating layer and the first insulating layer to expose a predetermined portion of the active layer, an end portion of the gate electrode, and a predetermined portion of the branch line of the gate line, which is positioned above the buffer layer; 4 contact holes; A plurality of source electrodes arranged in parallel with each other at predetermined intervals on the second insulating layer so as to vertically intersect the gate line, and vertically branched from each other, wherein each source electrode is disposed above one buffer layer of the contact hole. A data line in electrical contact with the active layer through a contact hole of the data line; A drain electrode electrically contacting the active layer exposed through the contact hole on the other buffer layer; And And a conductive connection means for electrically connecting the gate electrode and the second line to each other through a contact hole formed at one end of the gate electrode and a contact hole formed at an upper portion of the branch line of the gate line. Transistor liquid crystal display device. The thin film transistor liquid crystal display of claim 1, wherein the gate line and the buffer layer are made of the same material. The thin film transistor liquid crystal display of claim 1, wherein the pair of buffer layers are spaced apart from each other by a predetermined distance from a predetermined position of an extension line of the branch line of the gate line. Each of the plurality of gate lines arranged in parallel with a predetermined distance on the transparent insulating substrate, branch lines vertically branched from the gate lines, and two regions separated by extension lines of the respective branch lines, respectively. Simultaneously forming a pair of buffer layers to be located at a portion spaced apart from the extension line of the branch line by a predetermined distance; Forming an active layer on the insulating substrate to cover the pair of buffer layers; Forming a first insulating layer on the insulating substrate including the active layer and the gate line; Forming a conductive gate electrode on top of the first insulating layer spaced apart from an end of the branch line of the gate line by a predetermined distance and overlapping at least the active layer between the pair of buffer layers; Forming a second insulating layer on top of the first insulating layer including the gate electrode; Forming first to fourth contact holes exposing a predetermined portion of the active layer positioned above the buffer layer, one end of the gate electrode, and a predetermined portion of the branch line of the gate line; A source electrode vertically branching from the data line, the source electrode perpendicular to the gate line, and a source electrode electrically contacting the active layer through a contact hole in an upper portion of the buffer layer adjacent thereto among the first to fourth contact holes; And simultaneously forming a drain electrode electrically contacting the active layer exposed through the contact hole above the remaining buffer layer, and conductive connecting means electrically connecting the gate electrode and the second line of the gate line. A method of manufacturing a thin film transistor liquid crystal display device. 5. The method of claim 4, wherein the data line, the source and drain electrodes, and the conductive connecting means are simultaneously formed by deposition and patterning of the same material.