JP2000216387A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a construction and a manufacturing method, wherein an etching margin is assured when a connection hole is formed in an active layer of a thin-film transistor, the controllability of ion implantation is improved in the depth direction, and further the crystal defects and distortion are eliminated in a channel region. SOLUTION: In a semiconductor device, having a thin-film transistor 1 wherein an active layer is formed in a silicon film, a source region 12S and a drain region 12D of the thin-film transistor 1 formed in a first silicon film 12 are formed thicker than the thickness of a second silicon film 13 constructing a channel region CH formed between them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a characteristic in an active region of a thin film transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Generally, an active layer of a thin film transistor used for a liquid crystal display device or the like is formed of a silicon thin film (for example, an amorphous silicon thin film or a polycrystalline silicon thin film). Since these silicon thin films contain many crystal defects and distortions, an increase in leakage current and a decrease in on-current are likely to occur. As a countermeasure, crystal defects and distortions are eliminated by high-temperature annealing, long-time low-temperature annealing, laser annealing, or the like.

[0003]

However, it is difficult to completely eliminate crystal defects and distortion in the amorphous silicon thin film and the polycrystalline silicon thin film by the above-mentioned annealing. Further, since the thin film transistor has a thin active layer, an etching margin is small when a connection hole (for example, a contact hole) is formed in an interlayer insulating film formed on the active layer by etching. Therefore, the active layer may be excessively etched by the etching of the connection hole. Further, when a silicon thin film is used for a layer other than the channel layer of a transistor, the electrical resistance increases due to the thin film. Further, when the impurity diffusion layer is formed by ion implantation, it is difficult to control the ion implantation depth because the margin in the depth direction of ion implantation is small.

[0004]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of manufacturing the same to solve the above-mentioned problems.

A semiconductor device according to the present invention comprises a thin film transistor having an active layer formed on a silicon thin film. In the semiconductor device, a source region and a drain region of the thin film transistor formed on the active layer are thin film transistors formed on the active layer. Is formed to be thicker than the channel region.

In the above semiconductor device, the source region and the drain region of the thin film transistor are formed thicker than the channel region of the thin film transistor. In other words, the channel region is formed thinner than the source region and the drain region. Crystal defects per unit area of the channel region can be made smaller than those of the source region and the drain region. Further, since the source region and the drain region have a sufficient thickness, the source region and the drain region remain sufficiently even if excessive etching is performed when forming a connection hole (for example, a contact hole). In addition, a connection hole can be formed on the drain region.

In a first method of manufacturing a semiconductor device, a first silicon thin film for forming a source region and a drain region is formed on a substrate, and the first silicon thin film is formed on the source region and the drain region. Processing, forming a second silicon thin film to be a channel region between at least a source region and a drain region made of the first silicon thin film, and forming a gate on the channel formation region of the second silicon thin film Forming an insulating film; and forming a gate electrode on a region of the second silicon thin film to be a channel region via a gate insulating film.

In the first method of manufacturing a semiconductor device, a first silicon thin film for forming a source region and a drain region is formed on a substrate and processed, and a source region made of the first silicon thin film is formed. Forming a second silicon thin film to be a channel region between the first silicon thin film and the second silicon thin film. Therefore, it is possible to form the first silicon thin film thickly and the second silicon thin film thinly. Therefore, when forming a connection hole (for example, a contact hole) on the source region and the drain region, even if the silicon thin film in the source region and the drain region is excessively etched, the silicon thin film has a sufficient thickness. So it remains enough. Therefore, it becomes possible to form a connection hole on the source region and the drain region. Further, in the case where the impurity diffusion layers such as the source region and the drain region are formed by ion implantation, the first silicon thin film can be formed thick, so that the margin in the depth direction of ion implantation becomes large. Therefore, control of the ion implantation depth becomes easy.

A second method for manufacturing a semiconductor device includes a step of forming a silicon thin film on a substrate, and a step of selectively oxidizing an upper layer of the silicon thin film to be a region where a channel is formed, to form an oxide film. Forming a thin film region and a thick film region on the silicon thin film by selectively removing the oxide film, and forming a gate insulating film on the thin film region of the silicon thin film; A step of forming a gate electrode on a thin region of the silicon thin film via a gate insulating film, forming a source region on the silicon thin film on one side of the gate electrode, and forming a drain region on the other side of the gate electrode; Forming a step.

In the second method of manufacturing a semiconductor device, an upper layer of the silicon thin film is selectively oxidized to form an oxide film, and then the oxide film is selectively removed to form a thin film region on the silicon thin film. And the formation of a thick region,
The region where the thickness of the silicon thin film is small is used as the channel region, and the source region and the drain region can be formed in the region where the thickness of the silicon thin film is large. Therefore, when forming a connection hole (for example, a contact hole) on the source region and the drain region, even if the silicon thin film in the source region and the drain region is excessively etched, the silicon thin film has a sufficient thickness. So it remains enough. Therefore, it becomes possible to form a connection hole on the source region and the drain region. Further, when an impurity diffusion layer such as a source region and a drain region is formed by ion implantation, a thick silicon thin film can be formed, so that a margin in the depth direction of ion implantation is increased.
Therefore, control of the ion implantation depth becomes easy.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the semiconductor device according to the present invention will be described with reference to the schematic sectional view of FIG. FIG. 1 shows a semiconductor device in which an MIS thin film transistor and a capacitor are mounted on a silicon thin film formed on a glass substrate.

As shown in FIG. 1, a first silicon thin film 12 serving as a source region 12S and a drain region 12D of a MIS type thin film transistor and a lower electrode 12C of a capacitor is formed on a substrate (for example, a glass substrate) 11, for example.
It is formed of a conductive type (here, N ⁺ type) polycrystalline silicon thin film. Therefore, the first silicon thin film 12 is not formed between the source region 12S and the drain region 12D, that is, in a portion to be a channel region described later, and the source region 12S and the drain region 12D are separated. . On the other hand, the source region 12S and the lower electrode 12C are formed in a continuous state.

Between the source region 12S and the drain region 12D, a second thinner than the first silicon thin film 12 is formed.
Of the second conductivity type (here, P
^- is formed of a polycrystalline silicon thin film of a mold), constitutes a channel region CH. Note that a part of the second silicon thin film 13 forming the channel region CH is formed by each channel region CH of the source region 12S and the drain region 12D.
The side is also formed to overlap. Further, the second silicon thin film 13 is formed on the lower electrode 12 of the capacitor.
It is also formed on C.

On the second silicon thin film 13, a gate insulating film 14 and a capacitor insulating film 15 of the thin film transistor are formed by, for example, a silicon oxide film of the same layer. These insulating films may be formed in a three-layer structure including a silicon oxide film / a silicon nitride film / a silicon oxide film.

The gate electrode 1 is formed on the gate insulating film 14.
6 is formed of, for example, a polycrystalline silicon film. On the capacitor insulating film 15, an upper electrode 17 of the capacitor is formed of, for example, a polycrystalline silicon film. These polycrystalline silicon films are formed, for example, of the same layer.

Therefore, the MIS type thin film transistor 1 is constituted by the gate electrode 16, the gate insulating film 14, the second silicon thin film 13 forming the channel region CH, the source region 12S and the drain region 12D, and the upper electrode 17 and the capacitor insulation The capacitor 2 is formed by the film 15 and the lower electrode 12C.

Further, a first interlayer insulating film 2 is formed so as to cover the MIS type thin film transistor 1 and the capacitor 2.
1 is formed. A connection hole 22 is formed in the first interlayer insulating film 21 so as to communicate with the drain region 12D.
Is formed. A second interlayer insulating film 24 covering the wiring 23 is formed on the first interlayer insulating film 21.
Are formed. The second interlayer insulating film 24 and the first interlayer insulating film 21 are formed with a connection hole 25 communicating with the source region 12S. On the second interlayer insulating film 21, a transparent hole connected to the source region 12D is formed. An electrode 26 is formed.

The configuration as described above can be adopted for the configuration of a TFT (Thin Film Toransistor) and a capacitor of a liquid crystal display device.

In the semiconductor device composed of the MIS type thin film transistor 1 and the capacitor 2, the source region 12S and the drain region 12D of the thin film transistor 1
Is formed thicker than the channel region CH of the thin film transistor 1, in other words, since the channel region CH is formed thinner than the source region 12S and the drain region 12D, crystal defects per unit area of the channel region CH Can be made smaller than the source region 12D and the drain region 12D. In addition, since the source region 12S and the drain region 12D have a sufficient thickness, the source region 12S and the drain region 12D are sufficiently formed even when excessive etching is performed when forming the contact holes (contact holes) 22 and 25. Since the connection holes 22 and 25 remain, the connection holes 22 and 25 can be formed on the source region 12S and the drain region 12D. In addition, since the first silicon thin film made of polycrystalline silicon on the substrate (glass substrate) 11 can be formed as a thick film, the transmittance of light from the substrate side can be reduced.

Next, when the LDD structure is formed, the MOS
An example of a transistor will be described with reference to a schematic cross-sectional view of FIG. 2, the same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 2, a first silicon thin film 12 serving as a source region 12S and a drain region 12D of an MIS thin film transistor is formed on a substrate (eg, a glass substrate) 11 by, for example, an N ⁺ type polycrystalline silicon thin film. It is formed with. Therefore, the first silicon thin film 12 is not formed between the source region 12S and the drain region 12D, that is, in the channel region CH.
And the drain region 12D are separated from each other.

In the channel region CH, a second silicon thin film 13 is formed of, for example, a P ^- type polycrystalline silicon film. Note that a part of the second silicon thin film 13 formed in the channel region CH is formed so as to overlap also on the channel region CH side of the source region 12S and the drain region 12D. And, for example, the second
Of the portion where the silicon thin film 13 overlaps
Of the first silicon thin film 1
It is formed in an N ⁻ type having a concentration lower than 2, and has a so-called LDD (Lightly Doped Drain) structure.

The MIS is formed on the second silicon thin film 13.
The gate insulating film 14 of the type thin film transistor is formed of, for example, a silicon oxide film. The gate insulating film 14 may be formed in a three-layer structure including a silicon oxide film / a silicon nitride film / a silicon oxide film. On the gate insulating film 14, a gate electrode 16 is formed of, for example, a polycrystalline silicon film.

Therefore, the gate electrode 16, the gate insulating film 14, the second silicon thin film 13 forming the channel region CH, the source region 12S and the drain region 12D constitute the MIS type thin film transistor 3 having the LDD structure.

As described above, by adopting the LDD structure, in the thin film transistor 3, the electric field in the vicinity of the drain is reduced, so that the characteristic deterioration of the MOS transistor due to hot carriers is reduced.

In the MIS type thin film transistor 1 described with reference to FIG. 1, as shown in the layout diagram of FIG. 3A, the gate width w of the gate electrode 16 is limited to the width of the source region 12S or the drain region 12D. The configuration is longer than W. As shown in the layout diagram of FIG. 3B, the leakage current can be reduced by making the gate width w of the gate electrode 16 shorter than the width W of the source region 12S or the drain region 12D. Becomes possible.

Next, a second embodiment of the semiconductor device according to the present invention will be described with reference to the schematic sectional view of FIG. The same components as those described with reference to FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 4, a silicon thin film 41 is formed on a substrate (eg, a glass substrate) 11 by, for example, a polycrystalline silicon film. The silicon thin film 41 is made of MI
The source region 41S, the channel region 41CH, the drain region 41D, and the lower electrode 41C of the capacitor of the S-type thin film transistor are provided. The source region 41S, the drain region 41D, and the lower electrode 41C of the capacitor are of the first conductivity type (here, N ⁺ And the channel region 41CH is formed of the second conductivity type (here, P ⁻ type), and only the channel region 41CH is formed thinner than the other portions.

The gate insulating film 14 of the MIS type thin film transistor is formed on the channel region 41CH, and the capacitor insulating film 15 is formed on the lower electrode 41C of the capacitor. These insulating films are formed, for example, of a silicon oxide film having the same layer. Alternatively, a three-layer structure including a silicon oxide film / a silicon nitride film / a silicon oxide film may be used.

The gate electrode 1 is formed on the gate insulating film 14.
6 is formed of, for example, a polycrystalline silicon film. On the capacitor insulating film 15, an upper electrode 17 of the capacitor is formed of, for example, a polycrystalline silicon film. These polycrystalline silicon films are formed, for example, of the same layer.

Therefore, the MIS type thin film transistor 5 is composed of the gate electrode 16, the gate insulating film 14, the silicon thin film 41 formed in the channel region 41CH, the source region 41S and the drain region 41D, and the upper electrode 17, the capacitor insulating film 15 And the lower electrode 41C constitute the capacitor 6.

Further, the first interlayer insulating film 2 is formed so as to cover the MIS type thin film transistor 5 and the capacitor 6.
1 is formed. A connection hole 22 is formed in the first interlayer insulating film 21 so as to communicate with the drain region 41D, and the drain region 41D is formed in the first interlayer insulating film 21.
Is formed. A second interlayer insulating film 24 covering the wiring 23 is formed on the first interlayer insulating film 21.
Are formed. The second interlayer insulating film 24 and the first interlayer insulating film 21 are formed with a connection hole 25 communicating with the source region 41S. On the second interlayer insulating film 21, a transparent hole connected to the source region 41D is formed. An electrode 26 is formed.

In the semiconductor device composed of the MIS type thin film transistor 5 and the capacitor 6, the source region 41S and the drain region 41D of the thin film transistor 5
Are formed thicker than the channel region 41CH of the thin film transistor 5, in other words, the channel region 41CH is formed.
Since CH is formed thinner than the source region 41S and the drain region 41D, the channel region 41CH is formed.
Can be smaller than the source region 41D and the drain region 41D. Further, the source region 41S and the drain region 41D
Has a sufficient thickness, so that the source region 41S and the drain region 41 are sufficiently formed even when excessive etching is performed when forming the contact holes (contact holes) 22 and 25.
Since D remains, connection holes 22 and 25 can be formed on source region 41S and drain region 41D. In addition, since the first silicon thin film made of polycrystalline silicon on the substrate (glass substrate) 11 can be formed as a thick film, the transmittance of light from the substrate side can be reduced.

Next, a layout example of the semiconductor device having the above-described configuration will be described with reference to FIG. FIG. 5 shows a layout example of the semiconductor device shown in FIG. 1 as an example, and the same components as those shown in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 5, on a substrate 11 composed of a glass substrate, a drain region 12D composed of a first silicon thin film 12, and a source region 12S composed of the first silicon thin film 12 at a predetermined position separated therefrom. And a lower electrode 12C of the capacitor which is continuous therewith.
A channel region CH made of a second silicon thin film 13 thinner than the first silicon thin film 12 is formed between the source region 12S and the drain region 12D. A part of the second silicon thin film 13 forming the channel region CH is formed so as to overlap also on the respective channel region CH sides of the source region 12S and the drain region 12D. The second silicon thin film 13
Are also formed on the lower electrode 12C of the capacitor.

The gate electrode 1 is formed on the channel region CH of the second silicon thin film 13 with a gate insulating film 14 interposed therebetween.
6 is formed on the lower electrode 12C of the capacitor.
The upper electrode 17 of the capacitor is formed via the silicon thin film 13 and the capacitor insulating film 15. Thus, the gate electrode 16, the gate insulating film 14, the second silicon thin film 13 forming the channel region CH, and the source region 1
The MIS type thin film transistor 1 is constituted by the 2S and the drain region 12D, and the capacitor 2 is constituted by the upper electrode 17, the capacitor insulating film 15, and the lower electrode 12C.

Further, a first interlayer insulating film (not shown) is formed so as to cover the MIS type thin film transistor 1 and the capacitor 2. A connection hole 22 communicating with the drain region 12D is formed in the first interlayer insulating film, and the drain region 12D is formed in the first interlayer insulating film.
The wiring 23 connected to the first silicon thin film 12 is formed in a transparent state. A connection hole 27 communicating with the gate electrode 16 is formed in the first interlayer insulating film.
A wiring 28 connected to the gate electrode 16 and connected to another gate electrode 16 is formed in the first interlayer insulating film.

In the above configuration, the polycrystalline silicon layer serving as the gate electrode 16 and the second silicon thin film 13 serving as the channel region CH are patterned in the same shape.
Each gate electrode 14 is characterized by being connected by a wiring 28. In addition, also in the capacitor 2,
Since the polycrystalline silicon layer serving as the upper electrode 17 of the capacitor and the second silicon thin film 13 are patterned in the same shape, the upper electrode 17 of each capacitor is connected through the connection hole 29 formed in the first interlayer insulating film. 30 are connected.

Next, an embodiment of the first method of manufacturing a semiconductor device will be described with reference to FIGS. 6 and 7. 6 and 7 show, as an example, a method of manufacturing a semiconductor device including the thin film transistor and the capacitor described with reference to FIG. 1, and the same components as those described with reference to FIG.

As shown in FIG. 6A, a first silicon thin film 12 is formed to a thickness of, for example, 200 nm on a substrate 11 by, for example, a chemical vapor deposition method. The substrate 11 is made of, for example, a glass substrate, and the first silicon thin film 12 is made of, for example, a polycrystalline silicon thin film. After that, a resist film (not shown) used as a mask is formed by, for example, application, and the resist film is patterned into a shape of a drain, source and capacitor formation region of the MOS transistor by a lithography technique. Next, using the resist film as an etching mask, the first silicon thin film 12 is patterned. After that, the resist film is removed.

Further, the first silicon thin film 12 is doped with, for example, arsenic (As ⁺ ) or phosphorus (P ⁺ ) as an N-type impurity by an ion implantation technique. For example, in the case of arsenic ions, for example, the implantation energy is set to 200 keV, and the dose is set to 1.0 × 10 ¹⁶ /
cm ² . In the case of phosphorus ions, for example, the implantation energy was set to 70 keV, and the dose was set to 8.0 × 10 ¹⁵ / cm ² . This allows
A lower electrode 12C, a source region 12S, and a drain region 12D of the capacitor are formed. Note that the lower electrode 12C and the source region 12S are formed in a continuous state.

Next, as shown in FIG. 6 (2), the first substrate is formed on the substrate 11 by, for example, a chemical vapor deposition method.
The second silicon thin film 13 is formed to a thickness of, for example, 50 nm so as to cover the silicon thin film 12. The second silicon thin film 13 is made of, for example, a polycrystalline silicon thin film.

Next, annealing (for example, low-temperature annealing: 550 ° C. to 700 ° C.) is performed to reduce crystal defects and distortion of the first silicon thin film 12 and the second silicon thin film 13. Next, boron (B) as a P-type impurity is
⁺ ) To a predetermined concentration. As an example, the implantation energy at this time was set to 30 keV, and the dose was set to 2.0 × 10 ¹² / cm ² . After that, the resist film used as a mask for ion implantation is removed. As a result, a channel region 13C is formed in the second silicon thin film 13.

Next, as shown in (3) of FIG.
A gate insulating film 14 and a capacitor insulating film 15 are formed on the silicon thin film 13 of FIG. The gate insulating film 14 and the capacitor insulating film 15 are formed of, for example, the same insulating film, and are formed of, for example, one layer of a silicon oxide film or a silicon oxide film / silicon nitride film / silicon oxide film. It may be formed in three layers.

Next, an electrode forming film is formed of, for example, a polycrystalline silicon film. Subsequently, a resist film (not shown) used as a mask is formed, for example, by coating, and then the resist film in the transistor formation region is patterned into the shape of the gate electrode by ordinary lithography, and the resist on the capacitor formation region is formed. The film is patterned into the shape of the capacitor electrode. Next, the electrode forming film is patterned using the patterned resist film as an etching mask to form a gate electrode (including, for example, a gate wiring) 16 and an upper electrode 17 of the capacitor. After that, the resist film is removed.

As described above, the gate electrode 16, the gate insulating film 14, the second silicon thin film 13 forming the channel region CH, the source region 12S and the drain region 12
D forms the MIS transistor 1 and the upper electrode 1
7. The capacitor 2 is formed by the capacitor insulating film 15 and the lower electrode 12C.

Thereafter, as shown in FIG. 7D, the thin film transistor 1 and the capacitor 2 are
A first interlayer insulating film 21 is formed. Thereafter, a resist film (not shown) used as a mask is formed, for example, by coating, and then an opening is formed in the resist film on a region where the connection hole 22 is to be formed by a normal lithography technique. Using the resist film as an etching mask, the first interlayer insulating film 21 is etched to form a connection hole 22. After that, the resist film is removed.

Next, the film is formed on the first interlayer insulating film 21 and in a state in which the connection holes 22 are buried by a usual film forming technique for forming a wiring (for example, sputtering, chemical vapor deposition or vapor deposition). A conductive film for forming a wiring is formed. Next, after a resist film (not shown) used as a mask is formed by, for example, application, the resist film is patterned into a predetermined wiring shape by a normal lithography technique. Next, the conductive film is patterned using the patterned resist film as an etching mask to form the wiring 23. After that, the resist film is removed.

Thereafter, as shown in FIG. 7 (5), a second interlayer insulating film 24 is formed so as to cover the wiring 23. After that, a resist film (not shown) used as a mask is formed, for example, by coating, and then an opening is formed in a region of the resist film where a predetermined connection hole is formed by ordinary lithography. Using the patterned resist film as an etching mask, the first and second interlayer insulating films 21 and
A connection hole 25 is formed in 24. After that, the resist film is removed.

Next, a transparent electrode film is formed on the second interlayer insulating film 24 and on the inner wall of the connection hole 25 by a normal film forming technique (for example, sputtering, chemical vapor deposition or vapor method). I do. Next, after forming a resist film (not shown) used for the mask by, for example, coating,
The resist film is patterned into a predetermined shape by a usual lithography technique. Next, the transparent electrode film is patterned using the patterned resist film as an etching mask to form a transparent electrode 26. After that, the resist film is removed.

In the first method of manufacturing a semiconductor device, a step of forming and processing a first silicon thin film 12 for forming a source region 12S and a drain region 12D on a substrate 11; Forming a second silicon thin film 13 to be a channel region CH between the source region 1S and the drain region 12D made of the thin film 12, so that the first silicon thin film 12 and the second silicon thin film are formed. 13 is formed separately. Therefore,
It is possible to form the first silicon thin film 12 thick and the second silicon thin film 13 thin. for that reason,
Due to the annealing, the number of crystal defects and strains per unit area of the channel region 13C becomes smaller than those of the source region 12S and the drain region 12D.

Therefore, when forming the connection holes 22 and 25 on the source region 12S and the drain region 12D,
Even if the first silicon thin film 12 forming the source region 12S and the drain region 12D is excessively etched,
The first silicon thin film 12 has a sufficient thickness and remains sufficiently. Therefore, it is possible to form the connection holes 22 and 25 on the source region 12S and the drain region 12D.

Further, when the impurity diffusion layers such as the source region 12S and the drain region 12D are formed by ion implantation, the first silicon thin film 12 can be formed thick, so that the margin in the depth direction of ion implantation is large. Become. Therefore, control of the ion implantation depth becomes easy. Further, since the first silicon thin film 12 is doped with arsenic or phosphorus at a high concentration, the resistance of the lower electrode 12C of the capacitor 2 can be prevented from becoming high.

The case where the thin film transistor 1 is formed in the LDD structure in the above manufacturing method will be described below.

In FIG. 6A, after patterning the first silicon thin film 12 using a technique such as etching, first, ion implantation for forming an LDD structure is performed on the entire surface of the first silicon thin film 12. Do. As an example of the ion implantation conditions at this time, phosphine (PH ₃ ) was used as a dopant, the implantation energy was set to 90 keV, and the dose was set to 3.0 × 10 ¹³ / cm ² . Further, after forming and covering a resist mask in a region where the thin film transistor is to be formed, ion implantation for forming a lower electrode of the capacitor is performed. As an example of ion implantation conditions at this time, arsenic (As) is used as a dopant, the implantation energy is set to 50 keV, and the dose is 6.0.
× 10 ¹³ / cm ² was set. After that, the resist mask is removed.

Further, as described with reference to FIG. 6C, after the gate electrode 14 is formed, ion implantation for forming a source region and a drain region is performed. As an example of the ion implantation conditions, arsenic (As) is used as a dopant, the implantation energy is set to 220 keV, and the dose is set to 1.0 × 10 ¹⁶ / cm ² . Thus, the thin film transistor is formed in an LDD structure.

Next, an embodiment relating to a second method of manufacturing a semiconductor device will be described with reference to FIGS. 8 and 9 show, by way of example, the method of manufacturing the semiconductor device described with reference to FIG. 3, and the same components as those described with reference to FIG.

As shown in FIG. 8A, a silicon thin film 41 is formed on the substrate 11 by, for example, a chemical vapor deposition method. The substrate 11 is made of, for example, a glass substrate, and the silicon thin film 41 is made of, for example, a polycrystalline silicon thin film. Further, after the pad oxide film 51 is formed of, for example, a thermal oxide film to a thickness of 10 to 50 nm, a silicon nitride film 52 serving as an oxidation mask is formed to a thickness of about 100 nm or more. Thereafter, a resist film (not shown) used as a mask is formed by, for example, coating, and then the resist film on the channel formation region of the MOS transistor and the region where the silicon thin film 41 is removed is removed by a normal lithography technique. Next, using the remaining resist film as an etching mask, the silicon nitride film 52 is used.
Is patterned. By performing ion implantation in this state, the silicon nitride film 52 can be used as an ion implantation mask and the channel formation region can be doped with a P-type impurity such as boron at a predetermined concentration. As an ion implantation condition at that time, for example,
The implantation energy was set to 60 keV and the dose was 1.
Set to 0 × 10 ¹² / cm ² .

Then, as shown in FIG. 8 (2), the upper layer of the silicon thin film 41 is oxidized by a thermal oxidation method using the silicon nitride film 52 (see FIG. 8 (1)) as a mask.
A silicon oxide film 53 is formed. The silicon oxide film 5
Since the silicon thin film 41 is supplied with silicon to the silicon oxide film 53 at the time of formation of the silicon oxide film 3, the thickness of the oxidized portion of the silicon thin film 41 is reduced. Thereafter, the silicon nitride film 42 is selectively removed using an etching solution such as hot phosphoric acid. In this state, for example, arsenic can be doped to a predetermined concentration as an N-type impurity by ion implantation using the silicon oxide film 53 as a mask.
As an example of the ion implantation conditions at this time, the implantation energy is set to 220 keV, and the dose is set to 6.0 ×
Set to 10 ¹⁵ / cm ² . As a result, the silicon thin film 4
1, a lower electrode 41C of the capacitor, a part of the source region 41S, and a part of the drain region 41D are formed.

Next, as shown in FIG. 8 (3), the silicon oxide film 53 (see FIG. 8 (2)) is selectively removed by etching. As a result, the silicon thin film 41
The channel formation region is formed thin. Here, silicon ions are implanted to make the silicon thin film amorphous. As an example of the ion implantation conditions, as an example, silane tetrafluoride (SiF ₄ ) is used as a dopant, the implantation energy is set to 60 keV, and the dose is 3.0 × 10 ^13.
/ Cm ² . If channel ion implantation has not been performed first, boron is doped into the channel formation region at a predetermined concentration, for example, as a P-type impurity. As an example of the ion implantation conditions, boron difluoride (BF ₂ ) is used as a dopant, the implantation energy is set to 60 keV, and the dose is 1.0 × 10 ¹² /
cm ² .

Next, annealing (for example, low-temperature annealing) is performed to reduce crystal defects and distortion of the silicon thin film 41.

Next, as shown in FIG. 8D, after a resist film (not shown) used as a mask is formed by, for example, application, the resist film is formed by a normal lithography technique to form a transistor formation region and a capacitor. Pattern in the shape of the region. Next, using the patterned resist film as an etching mask, the silicon thin film 41 is etched to form a lower electrode region of the capacitor, and an active layer which becomes a source region, a channel region, and a drain region of the transistor in a continuous state. Form an area. After that, the resist film is removed.

The ion implantation for forming the channel region and the ion implantation for amorphization may be performed after patterning the silicon thin film 41.
In that case, the above-mentioned annealing is performed after performing these ion implantations.

Next, as shown in FIG. 9 (5), a gate insulating film 14 and a capacitor insulating film 15 are formed on the silicon thin film 41. The gate insulating film 14 and the capacitor insulating film 15 are formed of, for example, the same insulating film.
The material is formed of, for example, one layer of a silicon oxide film.
Alternatively, a three-layer structure of a silicon oxide film / a silicon nitride film / a silicon oxide film may be used.

Next, an electrode forming film is formed of, for example, a polycrystalline silicon film. Subsequently, a resist film (not shown) used as a mask is formed, for example, by coating, and then the resist film in the transistor formation region is patterned into the shape of the gate electrode by ordinary lithography, and the resist on the capacitor formation region is formed. The film is patterned into the shape of the capacitor electrode. Next, the electrode forming film is patterned using the patterned resist film as an etching mask to form a gate electrode (including, for example, a gate wiring) 16 and an upper electrode 17 of the capacitor. At this time, unnecessary portions of the insulating film on which the gate insulating film 14 and the capacitor insulating film 15 are formed are also removed by this etching. After that, the resist film is removed.

Next, after a resist film (not shown) used as a mask is formed by, for example, application, an opening is formed in a predetermined region of the resist film by ordinary lithography. Then, arsenic, an N-type impurity, is ion-implanted into the silicon thin film 41 on both sides of the gate electrode 16 to a predetermined concentration by ion implantation to form N ⁺ -type source and drain regions 41S and 41D. After that, the resist mask used in the ion implantation is removed. Thus, the MOS transistor 5 and the capacitor 6 are formed on the silicon thin film 41.

Thereafter, as shown in FIG. 9 (6), a first interlayer insulating film 21 is formed so as to cover the MOS transistor 5 and the capacitor 6. Thereafter, a resist film (not shown) used as a mask is formed by, for example, coating, and then an opening is formed in the resist film on a region where a connection hole is to be formed by ordinary lithography. By using the resist film as an etching mask, the first interlayer insulating film 21 is etched to form a connection hole 22 communicating with the drain region 41D. After that, the resist film is removed.

Next, a film forming technique for forming a normal wiring (eg, sputtering, chemical vapor deposition, or vapor method)
Accordingly, a conductive film for forming a wiring is formed on the first interlayer insulating film 21 and in a state where the connection hole 22 is buried. Next, after a resist film (not shown) used as a mask is formed by, for example, application, the resist film is patterned into a predetermined wiring shape by a normal lithography technique. Next, the conductive film is patterned using the patterned resist film as an etching mask to form the wiring 23. After that, the resist film is removed.

Thereafter, the second wiring 23 is covered with the second wiring.
Is formed. Next, after a resist film (not shown) used as a mask is formed by, for example, coating, an opening is formed in the resist film on a region where a connection hole is to be formed by ordinary lithography. Using the resist film as an etching mask, the first and second interlayer insulating films 21 and 24 are provided with connection holes 2 communicating with the source region 41S.
5 is formed. After that, the resist film is removed.

Next, a transparent electrode film is formed on the second interlayer insulating film 24 and on the inner wall of the connection hole 25 by a normal film forming technique (for example, sputtering, chemical vapor deposition or vapor method). I do. Next, after forming a resist film (not shown) used for the mask by, for example, coating,
The resist film is patterned into a predetermined shape by a usual lithography technique. Next, the transparent electrode film is patterned using the patterned resist film as an etching mask to form a transparent electrode 26. After that, the resist film is removed.

In the second method of manufacturing a semiconductor device, the silicon oxide film 53 is formed by selectively oxidizing the upper layer of the silicon thin film 41 and then selectively removing the silicon oxide film 53. Since a thin film region and a thick film region are formed in the silicon thin film 41, the thin film region of the silicon thin film 41 is defined as a channel region 41CH, and the source region 41S and the drain region 41D are formed in the thick silicon thin film region. Can be formed. for that reason,
Due to the annealing, the number of crystal defects and the number of strains per unit area of the channel region 41CH are smaller than those of the source region 41S and the drain region 41D.

Therefore, when forming the connection holes 22 and 25 on the source region 41S and the drain region 41D,
Even if the silicon thin film 41 forming the source region 41S and the drain region 41D is excessively etched, the silicon thin film 41 has a sufficient thickness and remains sufficiently. Therefore, the source region 41S and the drain region 4
It becomes possible to form the connection holes 22 and 25 on 1D.

Further, when the impurity diffusion layers such as the source region 41S and the drain region 41D are formed by ion implantation, the silicon thin film 41 can be formed to be thick, so that the margin in the depth direction of ion implantation becomes large. Therefore, control of the ion implantation depth becomes easy. Since the silicon thin film 41 is doped with arsenic or phosphorus at a high concentration, the resistance of the lower electrode 41C of the capacitor 6 can be prevented from becoming high.

[0074]

As described above, according to the semiconductor device of the present invention, the source region and the drain region of the thin film transistor are formed thicker than the channel region of the thin film transistor. Since the channel region is formed thinner than the drain region, the number of crystal defects and the number of strains per unit area of the channel region can be made smaller than those of the source region and the drain region, so that transistor characteristics and reliability can be improved. . Further, since the source region and the drain region have a sufficient thickness, the source region and the drain region sufficiently remain even if excessive etching is performed when forming the connection hole. That is, an etching margin is secured. Therefore, even if the connection holes are formed on the source region and the drain region, the reliability is not impaired.

According to the first method of manufacturing a semiconductor device of the present invention, a step of forming and processing a first silicon thin film for forming a source region and a drain region on a substrate; Forming a second silicon thin film serving as a channel region between the source region and the drain region comprising the first silicon thin film and the second silicon thin film.
Can be formed separately from the silicon thin film. Therefore, the first silicon thin film can be formed to be thick and the second silicon thin film can be formed to be thin. Therefore, when the connection holes are formed on the source region and the drain region, the thickness of the source region and the drain region is reduced. Even if the silicon thin film is excessively etched, the silicon thin film has a sufficient thickness and can be sufficiently left. That is, an etching margin can be secured. Further, when the impurity diffusion layers such as the source region and the drain region are formed by ion implantation, the first silicon thin film can be formed thick, so that the margin in the depth direction of ion implantation is increased, and the ion implantation depth is increased. Can be easily controlled. That is, it is possible to improve the controllability in the depth direction in the ion implantation. Therefore, a thin film transistor having excellent reliability can be formed.

According to the second method of manufacturing a semiconductor device of the present invention, an oxide film is formed by selectively oxidizing an upper layer of a silicon thin film, and then the oxide film is selectively removed to form a film on the silicon thin film. Since the thin region and the thick region are formed, the thin region of the silicon thin film can be used as the channel region, and the source region and the drain region can be formed in the thick region of the silicon thin film. Therefore, when the connection holes are formed on the source region and the drain region, even if the silicon thin film in the source region and the drain region is excessively etched, the silicon thin film has a sufficient thickness. Can be left. That is, an etching margin can be secured. Further, when impurity diffusion layers such as a source region and a drain region are formed by ion implantation, a thick silicon thin film can be formed, so that a margin in the depth direction of ion implantation is increased, and the ion implantation depth can be controlled. It can be done easily. That is, it is possible to improve the controllability in the depth direction in the ion implantation. Therefore, a thin film transistor having excellent reliability can be formed.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of a semiconductor device according to the present invention.
It is a schematic structure sectional view showing an example.

FIG. 2 is a schematic configuration sectional view showing an example of a MOS transistor when an LDD structure is formed.

FIG. 3 is a layout diagram illustrating a gate width of a thin film transistor.

FIG. 4 shows a second embodiment of the semiconductor device according to the present invention.
It is a schematic structure sectional view showing an example.

FIG. 5 is a layout diagram illustrating a layout example of a semiconductor device.

FIG. 6 is a manufacturing process diagram showing an embodiment according to a first manufacturing method of the present invention.

FIG. 7 is a manufacturing step diagram (continued) showing an embodiment according to the first manufacturing method of the present invention.

FIG. 8 is a manufacturing process diagram showing an embodiment according to a second manufacturing method of the present invention.

FIG. 9 is a manufacturing step diagram (continued) showing an embodiment according to the second manufacturing method of the present invention.

[Explanation of symbols]

1: thin film transistor, 12: first silicon thin film, 1
2S: source region, 12D: drain region, 13: second
Silicon thin film, CH ... channel region

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F110 BB01 CC02 CC05 DD02 EE09 EE25 FF02 FF03 FF10 GG02 GG13 GG19 GG22 GG24 GG25 GG26 GG32 GG42 GG44 GG52 HJ01 HJ04 HJ13 HJ23 HK09 HK14 HK24 HK24 HK24 HM15 NN02 NN03 NN72 PP10 PP33 QQ08

Claims (8)

[Claims] 1. A semiconductor device comprising a thin film transistor having an active layer formed on a silicon thin film, wherein a source region and a drain region of the thin film transistor formed on the active layer are channel regions of the thin film transistor formed on the active layer. A semiconductor device characterized by being formed thicker than a semiconductor device. 2. The semiconductor device according to claim 1, wherein said channel region, said source region and said drain region are formed of different layers of silicon thin film. 3. The semiconductor device according to claim 1, wherein said channel region, said source region and said drain region are formed of the same layer of silicon thin film. 4. A step of forming a first silicon thin film for forming a source region and a drain region on a substrate, and processing the first silicon thin film into a source region and a drain region; Forming a second silicon thin film serving as a channel region between the source region and the drain region made of the first silicon thin film; and forming a gate insulating film on the channel formation region of the second silicon thin film And a step of forming a gate electrode on a region of the second silicon thin film to be a channel region via the gate insulating film. 5. A step of forming a silicon thin film on a substrate, a step of selectively oxidizing an upper layer of the silicon thin film to be a region where a channel is formed, to form an oxide film, and selectively forming the oxide film. Forming a thin film region and a thick film region in the silicon thin film by removing the silicon thin film; forming a gate insulating film on the thin film region of the silicon thin film; Forming a gate electrode on the thin film region via the gate insulating film; and forming a source region on the silicon thin film on one side of the gate electrode and forming the source region on the silicon thin film on the other side of the gate electrode. Forming a drain region. 6. The method according to claim 1, wherein an oxide mask is formed on the silicon thin film to oxidize the silicon thin film when an oxide film is formed by selectively oxidizing an upper layer of the silicon thin film. Item 6. The method for manufacturing a semiconductor device according to Item 5. 7. The method according to claim 5, wherein the silicon thin film is doped with impurities using the oxide film as a mask. 8. The silicon thin film is doped with impurities using the oxidation mask.
The manufacturing method of the semiconductor device described in the above.