KR20060117635A - Multilayered thin films, thin film transistor including the same, and manufacturing method thereof - Google Patents

Abstract

A multilayer thin film, a TFT with the same, and a method for manufacturing a TFT display panel are provided to reduce the contact resistance and to enhance the adhesiveness between a semiconductor layer and a metal film by using an auxiliary contact layer. A semiconductor layer is formed on a substrate(110). A gate insulating layer(140) with a first contact hole for exposing partially the semiconductor layer to the outside is formed on the semiconductor layer. A gate electrode(124a) is formed on the gate insulating layer. An interlayer dielectric with a second contact hole corresponding to the first contact hole is formed on the resultant structure. An auxiliary contact layer for contacting the semiconductor layer through the first and the second contact hole is formed on the interlayer dielectric. A metal film is formed on the auxiliary contact layer. A data line and a drain electrode are formed by etching selectively the metal film. A contact member is formed by removing partially the auxiliary contact layer.

Description

MULTILAYERED THIN FILMS, THIN FILM TRANSISTOR INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a cross-sectional view of a contact structure between a polycrystalline structure and a signal line according to an exemplary embodiment of the present invention.

4 and 6 are layout views of a thin film transistor array panel according to an exemplary embodiment of the present invention.

5 and 7 are cross-sectional views taken along the lines V-V ′ and VII-VII ′ of the thin film transistor array panels of FIGS. 4 and 6, respectively.

8 and 9 are layout views in an intermediate step of manufacturing the thin film transistor array panel illustrated in FIGS. 4 to 7 according to an embodiment of the present invention.

FIG. 10 is a cross-sectional view of the thin film transistor array panel of FIGS. 8 and 9 taken along lines X-X 'and X'-X' ', and

11 and 12 are layout views of a thin film transistor array panel in the next step of FIGS. 8 and 9;

FIG. 13 is a cross-sectional view of the thin film transistor array panel of FIGS. 11 and 12 taken along lines XIII-XIII 'and XIII'-XIII' ', and

14 and 15 are layout views of a thin film transistor array panel in the next step of FIGS. 10 and 11.

FIG. 16 is a cross-sectional view of the thin film transistor array panel of FIGS. 14 and 15 cut along the lines XVI-XVI ', XVI'-XVI' ', and

FIG. 17 is a cross-sectional view of the thin film transistor array panel of FIG. 16 taken along the lines XVI-XVI ', XVI'-XVI' ', and

FIG. 18 is a cross-sectional view of the thin film transistor array panel of FIG. 17 taken along the lines XVI-XVI ', XVI'-XVI' ', and

19 and 20 are layout views of a thin film transistor array panel in the next step of FIGS. 14 and 15.

FIG. 21 is a cross-sectional view of the thin film transistor array panel of FIGS. 19 and 20 taken along lines XXI-XXI ′ and XXI′-XXI ″.

 ※ Explanation of main parts of drawing ※

110: insulating substrate 121: gate line

124a: gate electrode 131: sustain electrode line

137: sustain electrode 140: gate insulating film

153a: source region 154a: channel region

155a: drain region 171: data line

173a: source electrode 175a: drain electrode

191: pixel electrode

The present invention relates to a multilayer thin film, a thin film transistor including the same, and a method of manufacturing a thin film transistor array panel, and more particularly, to a multilayer thin film including a semiconductor and a metal layer.

In general, a thin film transistor (TFT) is used as a switching element for driving each pixel independently in a flat panel display such as a liquid crystal display or an organic light emitting display. The thin film transistor array panel including the thin film transistor includes a scan signal line (or gate line) for transmitting a scan signal to the thin film transistor and a data line for transmitting a data signal, in addition to the thin film transistor and the pixel electrode connected thereto.

The thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a semiconductor layer positioned on the gate electrode. The data signal from the data line is transferred to the pixel electrode. In this case, the semiconductor layer of the thin film transistor is made of polycrystalline silicon (polysilicon) or amorphous silicon (amorphous silicon).

Since polycrystalline silicon has a large electron mobility used for amorphous silicon, the use of a polycrystalline silicon thin film transistor enables high-speed driving. In addition, a driving circuit for driving the thin film transistor array panel may be formed as a separate integrated circuit chip and integrated on the substrate in the form of a thin film transistor without being attached to the substrate.

The electrical properties of the thin film using such polycrystalline silicon are greatly influenced by grain size and uniformity. That is, the field effect mobility increases as the size and uniformity of the particles increase. Accordingly, there is increasing interest in a method of forming uniform polycrystalline silicon while enlarging the particles.

Methods of forming polycrystalline silicon include ELA (eximer laser anneal), furnace annealing (chamber annal), etc. Recently, a sequential lateral solidification (SLS) technique for producing polycrystalline silicon by inducing lateral growth of silicon crystals with a laser has been proposed. .

The SLS crystallization method has better field effect mobility than the ELA method due to its larger grain size. However, protrusions may be formed on the surface of the polycrystalline silicon grown through the SLS crystallization method, and the protrusions may increase the contact resistance between the polycrystalline silicon and the metal wiring thereon.

To improve this, many companies are developing to suppress the formation of protrusions, but the contact resistance of polycrystalline silicon and the metal wiring thereon is 10 ?? The polycrystalline silicon thin film transistor having the above values and formed by the SLS crystallization method has not significantly improved the distribution of the threshold voltage value compared with the polycrystalline silicon thin film transistor formed by the ELA method. This may lower the characteristics of the thin film transistor, thereby lowering the reliability of the product.

Therefore, the technical problem of the present invention is to improve the characteristics of the thin film transistor array panel.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention includes forming a semiconductor layer on a substrate, and forming a gate insulating layer formed on the semiconductor layer and having a first contact hole exposing at least a portion of the semiconductor layer. Forming a gate electrode on the gate insulating film; forming an interlayer insulating film having a second contact hole connected to the first contact hole on the gate electrode and the gate insulating film; Stacking a contact auxiliary layer in contact with the semiconductor layer through a second contact hole, stacking a metal layer on the contact auxiliary layer, forming a data line and a drain electrode by etching the metal layer, and the data Removing the portion of the contact auxiliary layer not covered with a line and the drain electrode. Forming a contact member to be removed.

The semiconductor layer may include polycrystalline silicon, the contact auxiliary layer may include amorphous silicon, and the amorphous silicon may include conductive impurities.

The metal layer may include aluminum, and the metal layer may be a single layer.

The method may further include heat treating the substrate after the lamination of the metal layer.

The heat treatment may be carried out at 200 ℃ to 300 ℃.

The interlayer insulating layer may include an organic material having a deformation temperature of 200 ° C. to 300 ° C.

The contact auxiliary layer may have a thickness of 500 kPa to 1,000 kPa.

The method may further include forming a passivation layer on the interlayer insulating layer, the data line, and the drain electrode, and forming a pixel electrode connected to the drain electrode on the passivation layer.

A polycrystalline silicon film formed on a substrate, an amorphous silicon film in contact with the polycrystalline silicon film, and an aluminum-based metal thin film formed on the amorphous silicon film.

The metal thin film may include only aluminum, and the metal thin film may be a single layer.

The amorphous silicon film may include conductive impurities, and the amorphous silicon film may have the same planar shape as the metal thin film.

And a semiconductor layer formed on the substrate, an interlayer insulating film formed on the semiconductor layer, a contact member made of amorphous silicon formed on the interlayer insulating film, and a conductor formed on the contact member.

The semiconductor layer may include polycrystalline silicon.

The conductor may comprise aluminum, and the conductor may be a single layer.

The amorphous silicon may include conductive impurities.

The contact member may have the same shape as the plane of the conductor.

An interlayer insulating film formed over a substrate, a gate insulating film formed over the semiconductor layer, a gate electrode formed over the gate insulating film, an interlayer insulating film formed over the gate electrode, the contact hole exposing a portion of the semiconductor layer, And a contact member formed on the interlayer insulating layer and connected to the semiconductor layer through the contact hole, and a source electrode and a drain electrode formed on the contact member.

The semiconductor layer may include polycrystalline silicon.

The source electrode and the drain electrode may include aluminum, and the source electrode and the drain electrode may have a single layer structure.

The semiconductor layer may have protrusions formed on a surface thereof.

The contact member may include amorphous silicon, and the amorphous silicon may include conductive impurities.

The contact member may have the same planar shape as the source electrode and the drain electrode.

The display device may further include a passivation layer formed on the source electrode and the drain electrode, and a pixel electrode connected to the drain electrode on the passivation layer.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "above" another part, this includes not only the case where it is "above" another part but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display, which is an example of the display device according to an exemplary embodiment.

As illustrated in FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display panel unit 300, a gate driver 400 and a data driver 500 connected thereto. ), A gray voltage generator 800 connected to the data driver 500, and a signal controller 600 for controlling the gray voltage generator 800.

Referring to FIG. 1, the display panel unit 300 is connected to a plurality of display panel lines G1 -Gn and D1 -Dm and arranged in a substantially matrix form when viewed in an equivalent circuit. and a plurality of pixels PX constituting a display area DA.

Referring to FIG. 2, the display panel 300 of the liquid crystal display includes lower and upper display panels 100 and 200 and a liquid crystal layer 3 therebetween. In the case of an organic light emitting diode display, the display panel 300 may include only one display panel.

The display signal lines G1 -Gn and D1 -Dm are a plurality of gate lines G1 -Gn for transmitting a gate signal (also called a "scan signal") and a data line for transmitting a data signal. (D1-Dm). The gate lines G1 -Gn extend substantially in the row direction and are substantially parallel to each other, and the data lines D1 -Dm extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes at least one active element (not shown) such as a transistor and at least one capacitor (not shown).

Referring to FIG. 2, each pixel PX of the liquid crystal display device is, for example, a pixel defined by an i-th gate line Gi and a j-th data line Dj, and is connected to display signal lines Gi and Dj. Device Q includes a liquid crystal capacitor (CLC) and a storage capacitor (CST) connected thereto. The display signal lines Gi and Dj are disposed on the lower display panel 100, and the storage capacitor CST may be omitted as necessary.

The switching element Q, such as a polysilicon thin film transistor, is provided in the lower panel 100, and a control terminal connected to the gate line Gi, an input terminal connected to the data line Dj, and a liquid crystal capacitor, respectively. It is a three-terminal device with an output terminal connected to the CLC and the holding capacitor CST.

The liquid crystal capacitor CLC has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor CST is a capacitor that assists the liquid crystal capacitor CLC. The storage capacitor CST is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100, and common to the separate signal lines. A predetermined voltage such as voltage Vcom is applied. However, the storage capacitor CST may be formed by the pixel electrode 191 overlapping the front gate line directly above the insulator.

In order to implement color display, each pixel PX uniquely displays one of a plurality of primary colors (spatial division) or alternately displays a plurality of primary colors (time division), so that the spatial In time, the desired color is indicated. Examples of the primary colors include three primary colors including red, green, and blue. FIG. 2 shows an example of spatial division in which each pixel PX includes a color filter 230 representing one color of the primary colors in a corresponding region facing the pixel electrode 191 in the upper panel 200. have. Alternatively, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the display panel unit 300.

Each pixel PX of the organic light emitting diode display includes a switching transistor (not shown) connected to the display signal lines G1 -Gn and D1 -Dm, a driving transistor (not shown), and a storage capacitor (not shown) connected thereto. Not shown), and an organic light emitting diode (OLED) (not shown). The light emitting diode includes an anode electrode (not shown) and a cathode electrode (not shown) and an organic light emitting member (not shown) therebetween.

Referring back to FIG. 1, the gray signal generator 800 generates a plurality of gray signals related to the transmittance of the pixel PX. The gray level signal generator 800 for the liquid crystal display generates two gray level voltages each having a positive value and a negative value with respect to the common voltage Vcom.

The gate driver 400 is connected to the gate lines G1 -Gn of the display panel unit 300 so that the gate signals G2 have the same two values as the gate on voltage Von and the gate off voltage Voff, respectively. -Gn). The gate driver 400 is integrated in the display panel 300 and includes a plurality of driving circuits (not shown). Each driving circuit of the gate driver 400 is connected to one gate line G1 -Gn and includes a plurality of N-type, P-type, and complementary polysilicon thin film transistors. The data driver 500 includes a display panel. It is connected to the data lines D1-Dm of the unit 300 and selects a gray voltage from the gray signal generator 800 and applies it to the data lines D1-Dm as data voltages. Like the gate driver 400, the data driver 500 is integrated in the display panel 300 and includes a plurality of driving circuits (not shown). Each driving circuit of the data driver 500 is connected to one data line D1 -Dm and includes a plurality of N-type, P-type, and complementary polysilicon thin film transistors.

However, the gate driver 400 or the data driver 500 may be mounted on the display panel 300 in the form of one or more integrated circuit (IC) chips or mounted on the flexible printed circuit film attached to the display panel 300. Can be.

The driving units 400 and 500 are positioned in the peripheral area positioned outside the display area DA in the display panel 300.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like, and may be mounted on a printed circuit board (PCB).

As described above, a polycrystalline silicon thin film transistor is used in such a display device, and in the polycrystalline silicon thin film transistor, the contact structure of the polycrystalline silicon and the signal line is important. An example of such a contact structure will be described in detail with reference to FIG. 3.

3 is a cross-sectional view of a multilayer thin film according to an exemplary embodiment of the present invention, illustrating a contact structure between a polycrystalline semiconductor film and a wiring. Herein, the multilayer thin film means a plurality of thin films in different layers, which may be made of a conductor, a semiconductor, or an insulator.

A polycrystalline silicon film 42 is formed on a substrate 41 made of transparent glass or plastic. The surface of the polycrystalline silicon film 42 may have protrusions generated during the conversion from amorphous silicon to polycrystalline silicon, and impurity ions may be implanted into the polycrystalline silicon film 42.

On the polycrystalline semiconductor 42, an insulating film 43 having a contact hole 44 exposing the surface of the polycrystalline silicon film 42 is formed.

On the insulating film 43, a wiring having a double film structure of the amorphous silicon film 45 and the conductive film 46 is formed.

The amorphous silicon film 45 is in contact with the exposed polycrystalline silicon film 42 through the contact hole 44. The amorphous silicon film 45 has a good adhesive force with the polycrystalline silicon film 42, and the contact area of the amorphous silicon film 42 is large even if there is a projection. As a result, the contact resistance between the amorphous silicon film 45 and the polycrystalline silicon film 42 is small. In addition, the upper surface of the amorphous silicon film 45 is smoother than the rough surface of the polycrystalline silicon film 42 having projections.

The conductive film 46 is preferably positioned on the amorphous silicon film 45 and has a single film structure made of aluminum-based metal. The conductive film 46 has substantially the same planar shape as the amorphous silicon film 45.

As described above, since the surface of the amorphous silicon film 45 is smoother than the surface of the polycrystalline silicon film 42, contact with the amorphous silicon film 45 is smaller than the contact with the polysilicon film 42. .

In addition, metal atoms of the conductive film 46 may penetrate into the vicinity of the upper surface of the amorphous silicon film 45 through heat treatment, so that the contact resistance between the amorphous silicon film 45 and the conductive film 46 is increased. Can be smaller.

As described above, since the contact resistance between the amorphous silicon film 45 and the semiconductor 42 is small, and the contact resistance between the conductive film 46 and the amorphous silicon film 45 is also small, the polycrystalline silicon film 42 and the conductive film 46 The contact resistance between the can also be small. Therefore, the contact resistance between the polycrystalline silicon film 42 and the wirings 45 and 46 is very small.

Therefore, the contact resistance between the polycrystalline silicon film and the metal wiring can be greatly reduced by placing the amorphous silicon film as described above between the polycrystalline silicon film forming the channel such as the thin film transistor and the metal wiring that receives a signal from or transmits a signal to the thin film transistor. Can be. In addition, the amorphous silicon film itself can sufficiently serve as a wiring for transmitting signals along with the metal wiring.

Next, an example of the thin film transistor array panel illustrated in FIG. 3 will be described in detail with reference to FIGS. 4 to 7.

Here, it is assumed that the thin film transistor of the pixel PX is N type and the thin film transistor of the gate driver 400 is P type.

4 and 6 are layout views of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 5 and 7 illustrate the thin film transistor array panels of FIGS. 4 and 6 along the lines V-V ′ and VII-VII ′, respectively. It is a cut section.

A blocking film 111 made of silicon nitride (SiNx) or silicon oxide (SiO 2) is formed on an insulating substrate 110 made of transparent glass or plastic. The blocking film 111 may have a multilayer structure.

On the blocking film 111, a plurality of pixel portion island semiconductors 151a and driver unit island semiconductors 151b made of polycrystalline silicon are formed. Surfaces of the pixel island semiconductor 151a and the driver island semiconductor 151b may have protrusions generated during the conversion from amorphous silicon to polycrystalline silicon.

Each of the semiconductors 151a and 151b includes an extrinsic region containing conductive impurities and an intrinsic region containing little conductive impurities, and a heavily doped region having a high impurity concentration in the impurity region. region and lightly doped region with low impurity concentration.

The intrinsic region of the pixel portion semiconductor 151a includes a channel region 154a, and the high concentration impurity region is sequentially separated from the source region 153a, which is sequentially separated around the channel region 154a. And a region 156a and a drain region 155a. The low concentration impurity region 152 is located between the intrinsic region 154a and the high concentration impurity regions 153a, 155a, and 156a and is narrow in width. In particular, the low concentration impurity region 152 located between the source region 153a and the channel region 154a and between the drain region 155a and the channel region 154a is referred to as a lightly doped drain region (LDD region). do. This lightly doped drain region may be omitted.

The intrinsic region of the driver semiconductor 151b includes a channel region 154b, and the high concentration impurity region includes a source region 153b and a drain region 155b.

Examples of the P-type conductive impurity include boron (B) and gallium (Ga), and examples of the N-type impurity include phosphorus (P) and arsenic (As).

A gate insulating layer 140 made of silicon nitride or silicon oxide is formed on the semiconductors 151a and 151b and the blocking layer 111.

A gate conductor including a plurality of gate lines 121 including a gate electrode 124a and a plurality of control electrodes 124b and a plurality of storage electrode lines on the gate insulating layer 140. An electrode line 131 is formed.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. The gate electrode 124a extends upward from the gate line 121 to cross the pixel portion semiconductor 151b, and overlaps the channel region 154a. Each gate line 121 may include a wide end portion for connection with another layer or an external driving circuit. When a gate driving circuit (not shown) generating a gate signal is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The control electrode 124b is separated from the gate line 121, and overlaps the channel region 154b of the driver semiconductor 151b and is connected to another signal line (not shown) to which a control signal is applied.

The storage electrode line 131 receives a predetermined voltage such as a common voltage applied to a common electrode (not shown), and is extended upward to extend the wider portion 137 and the vertical portion 133 extending upward. It includes.

The gate conductors 121 and 124b and the storage electrode line 131 may be made of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based copper such as copper (Cu) or copper alloy The metal, molybdenum (Mo) or molybdenum alloy such as molybdenum-based metal, it may be made of chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W). However, the gate line 121, the storage electrode line 131, and the control electrode 124b may have a multilayer film structure including two conductive films (not shown) having different physical properties. One of these conductive films is a low resistivity metal such as aluminum-based metal or silver so as to reduce the signal delay or voltage drop of the gate line 121, the sustain electrode line 131, and the control electrode 124b. It may be made of a metal of a series, a metal of a copper series. The other conductive layer may be formed of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metal, chromium, tantalum, titanium, or the like. A good example of such a combination is a chromium bottom film, an aluminum (alloy) top film, an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate line 121 may be made of various other metals and conductors.

Side surfaces of the gate conductors 121 and 124b and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle thereof is preferably about 30 to 80 degrees.

An interlayer insulating film 160 is formed on the gate conductors 121 and 124b and the storage electrode line 131. The interlayer insulating layer 160 is made of an inorganic insulator such as silicon nitride or silicon oxide, an organic insulator, or a low dielectric insulator. The dielectric constant of the organic insulator and the low dielectric insulator is preferably 4.0 or less. Examples of the low dielectric insulator include a-Si: C: O and a-Si: O formed by plasma enhanced chemical vapor deposition (PECVD). : F, etc. can be mentioned. The interlayer insulating layer 160 may be formed by having photosensitivity among the organic insulators, and the surface of the interlayer insulating layer 160 may be flat.

A plurality of contact holes 163, 165, 166, and 167 exposing the source and drain regions 153a, 153b, 155a, and 155b are formed in the interlayer insulating layer 160 and the gate insulating layer 140.

Contact members 170a, 170b, 172a, and 172b made of amorphous silicon (a-Si) are formed on the interlayer insulating layer 160. Here, the amorphous silicon may be doped in high concentration with n-type impurities such as phosphorus. Here, it is preferable that the thickness of the contact members 170a, 170b, 172a, and 172b is 500 kPa-1,000 kPa.

The contact members 170a, 170b, 172a, and 172b contact the source regions 153a and 153b and the drain regions 155a and 155b through the contact holes 163, 165, 166, and 167, and the surfaces thereof are flat.

The contact members 170a, 170b, 172a, and 172b have good adhesive strength with the semiconductors 151a and 151b, even if the semiconductors 153a, 155a, 153b, and 155b have protrusions. Accordingly, the resistance between the semiconductors 153a, 155a, 153b, and 155b in contact with the contact members 170a, 170b, 172a, and 172b is small. In addition, the surfaces of the contact members 170a, 170b, 172a, and 172b are smoother than the rough surfaces of the projected semiconductors 153a, 155a, 153b, and 155b.

A plurality of data lines 171, a plurality of drain electrodes 175a, a plurality of input electrodes 173b, and a plurality of output electrodes 175b are disposed on the contact members 170a, 170b, 172a, and 172b. A plurality of data conductors including) are formed.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 includes a source electrode 173a connected to the source region 153a through the contact hole 163, and includes a wide end portion for connecting to another layer or an external driving circuit. can do. When a data driving circuit (not shown) generating a data signal is integrated on the substrate 110, the data line 171 may be directly connected to the data driving circuit.

The drain electrode 175a is spaced apart from the source electrode 173a and connected to the drain region 155a through the contact hole 165. The drain electrode 175a is connected to the extension portion 137 and the vertical portion 133 of the storage electrode line 131, respectively. An overlapping extension 177 and a vertical portion 176 are included. The vertical portion 133 of the storage electrode line 131 is positioned between the vertical portion 176 of the drain electrode 175 and the boundary line facing the data line 171 to prevent signal interference therebetween. The input electrode 173b and the output electrode 175b are separated from each other with respect to the control electrode 124b and may be connected to another signal line (not shown).

These data conductors 171, 173b, 175a, and 175b are substantially the same as the planar shape of the contact members 170a, 170b, 172a, and 172b.

The data conductors 171, 173b, 175a, and 175b are made of an aluminum based metal such as aluminum-niodymium (AlNd).

As described above, since the surfaces of the contact members 170a, 170b, 172a, and 172b are smoother than the surfaces of the semiconductors 153a, 155a, 153b, and 155b, they are in contact with the semiconductors 153a, 155a, 153b, and 155b. The contact resistance is small in contact with the members 170a, 170b, 172a, and 172b.

As such, the contact resistance between the contact members 170a, 170b, 172a, and 172b and the semiconductors 153a, 155a, 153b, and 155b is small, and the data conductors 171, 173b, 175a, and 175b and the contact members 170a, Since the contact resistances of the 170b, 172a, and 172b are also small, the contact resistance between the contact members 170a, 170b, 172a, and 172b and the data conductors 171, 173b, 175a, and 175b may also be reduced.

Meanwhile, aluminum particles of the data conductors 171, 173b, 175a, and 175b may be diffused in the contact members 170a, 170b, 172a, and 172b, and the aluminum particles may be contact members 170a, 170b, 172a, and 172b. Lower the resistance of).

Like the gate conductors 121 and 121b, the data conductors 171, 172, 175a, and 175b also preferably have their side surfaces inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

A passivation layer 180 including a lower passivation layer 180p and an upper passivation layer 180q is formed on the data conductors 171, 173b, 175a, and 175b and the interlayer insulating layer 160. The lower passivation layer 180p is made of an inorganic insulator such as silicon nitride or silicon oxide, and the upper passivation layer 180q is made of an organic material having excellent planarization characteristics. The upper passivation layer 180q may have photosensitivity and have a dielectric constant of 4.0 or less, such as a-Si: C: O and a-Si: O: F, which are formed by plasma enhanced chemical vapor deposition (PECVD). It may be made of a low dielectric constant insulating material.

The passivation layer 180 is provided with a plurality of contact holes 185 exposing the extension 177 of the drain electrode 175a. A plurality of contact holes (not shown) may also be formed in the passivation layer 180 to expose an end portion of the data line 171, and an end portion of the gate line 121 may be formed in the passivation layer 180 and the interlayer insulating layer 160. A plurality of contact holes (not shown) may be formed to reveal the gaps. The passivation layer 180 may be omitted in the driver.

A plurality of pixel electrodes 191 are formed on the passivation layer 180. The pixel electrode 191 is physically and electrically connected to the drain electrode 175a through the contact hole 185 and may be made of a transparent conductive material such as ITO or IZO, or a reflective metal such as aluminum, silver, or an alloy thereof. have.

The pixel electrode 191 is connected to the drain electrode 175a in contact with the contact member 172a connected to the drain region 155a through the contact hole 185, thereby providing a data voltage from the drain region 155a and the drain electrode 175a. Is authorized. The pixel electrode 191 to which the data voltage is applied generates an electric field together with the common electrode 270 to which the common voltage is applied, thereby determining the direction of the liquid crystal molecules of the liquid crystal layer 3 between the two electrodes 191 and 270 or An electric current is made to flow through a light emitting layer (not shown) between electrodes, and light is emitted.

Referring to FIG. 2, the pixel electrode 191 and the common electrode 270 form a liquid crystal capacitor CLC to maintain an applied voltage even after the thin film transistor Q is turned off, and the storage capacitor CST is a pixel electrode ( A portion of the drain electrode 175a and the storage electrode line 131 including the vertical portion 133 and the expansion portion 137 are made to overlap.

When the passivation layer 180 is formed of an organic material having a low dielectric constant, the pixel electrode 191 may be overlapped with the data line 171 and the gate line 121 to improve the aperture ratio.

Next, a method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 7 according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 8 to 21.

8 and 9 are layout views in an intermediate step of manufacturing the thin film transistor array panel illustrated in FIGS. 4 to 7 according to an embodiment of the present invention, and FIG. 10 is an X-X view of the thin film transistor array panel of FIGS. 8 and 9. 11 and 12 are layout views of a thin film transistor array panel in the next steps of FIGS. 8 and 9, and FIG. 13 is a thin film of FIGS. 11 and 12. A cross-sectional view of the transistor display panel taken along the lines XIII-XIII 'and XIII'-XIII' ', and FIGS. 14 and 15 are layout views of the thin film transistor array panel in the next steps of FIGS. 10 and 11, and FIG. 14 and 15 are cross-sectional views taken along the XVI-XVI 'and XVI'-XVI' lines of the thin film transistor array panel, and FIG. 17 is a XVI-XVI 'and XVI' section of the thin film transistor array panel in the next step of FIG. A cross-sectional view taken along the line XVI '', and FIG. 19. FIG. 19 and FIG. 20 are layout views of the thin film transistor array panel in the next step of FIGS. 14 and 15. The thin film transistor array panel in the step is cut and pasted along the lines XVI-XVI 'and XVI'-XVI' '. FIG. 21 is a cross-sectional view of the thin film transistor array panel of FIGS. 19 and 20 taken along lines XXI-XXI ′ and XXI′-XXI ″.

First, as shown in FIGS. 8 to 10, the blocking film 111 is formed on the transparent insulating substrate 110, and then, as amorphous silicon by chemical vapor deposition (CVD), sputtering, or the like. The formed semiconductor film is formed. The semiconductor film is then crystallized by laser annealing, furnace annealing or sequential lateral solidification (SLS). In this case, protrusions may be formed on the surface of the semiconductor film.

Then, the semiconductor film is patterned to form a plurality of pixel portion and driver island type semiconductors 151a and 151b.

11 to 13, the gate insulating layer 140 is formed on the semiconductors 151a and 151b by a chemical vapor deposition method, and the plurality of gate lines 121 including the gate electrode 124a thereon. And a plurality of sustain electrode lines 131 and control electrodes 124b including the extension 137. Impurity ions are implanted into the semiconductor layers 151a and 151b to form the N-type high concentration impurity regions 153a, 153b, 155a, 155b, and 156a, the intrinsic region 154a, and the low concentration impurity region 152.

Next, as shown in FIGS. 14 to 18, a plurality of contact holes exposing the source and drain regions 153a, 155a, 153b, and 153b by stacking and photolithography the interlayer insulating layer 160 on the entire surface of the substrate 110. (163, 165, 166, 167). Here, the interlayer insulating layer 160 may be made of an organic film material having a deformation temperature of 200 ° C. to 300 ° C. and having a high transmittance.

Thereafter, impurities on the surfaces of the semiconductors 153a, 155a, 153b, and 155b exposed through the contact holes 163, 165, 166, and 167 and the interlayer insulating layer 160 are removed using plasma.

Next, a contact auxiliary layer 174 made of amorphous silicon (a-Si) and an aluminum-based metal layer 178 such as aluminum-niodymium (AlNd) are sequentially stacked. Here, the amorphous silicon may have a sheet resistance value of 10 ⁹ Ω / □ or more, and n-type impurities such as phosphorus may be doped at a high concentration.

Since the contact auxiliary layer 174 has good adhesion with the semiconductors 151a and 151b, even if the semiconductors 153a, 155a, 153b, and 155b have a large contact area, the contact auxiliary layer 174 and the semiconductors 151a and 151b have a large contact area. The contact resistance of is small. In addition, since the exposed surface of the contact auxiliary layer 174 is flat, the contact resistance between the contact auxiliary layer 174 and the metal layer 178 is reduced. At this time, the thickness of the contact auxiliary layer 174 is preferably 500 kPa to 1,000 kPa.

Thereafter, a heat treatment process of 200 ° C to 300 ° C is performed. This process causes the aluminum atoms of the metal layer 178 to diffuse into the contact auxiliary layer 174, thereby increasing the contact force between the semiconductors 153a, 155a, 153b, and 155b and the metal layer 178, thereby increasing the contact resistance. Lowers. As a result, the contact resistance between the semiconductors 153a, 155a, 153b, and 155b and the metal layer 178 further decreases.

[Table 1] shows contact surface resistance (Ω / □) after heat treatment of amorphous silicon (a-Si) having a different thickness or amorphous silicon (n + a-Si) implanted with a high concentration of n-type impurities and the metal layer 178. It shows the value measured several times by changing the position.

Subsequently, the photoresist layers 71, 72, 73, and 74 are formed on the metal layer 178, and the metal layers 178 are wet or dry etched using the mask to form a plurality of data lines 173a having the source electrode 173a, A drain electrode 175a, an input electrode 173b, and an output electrode 175b are formed.

Next, as shown in FIG. 21, the contact auxiliary layers 174 are etched using the photosensitive films 71, 72, 73, and 74 as masks to form the contact members 170a, 170b, 172a, and 172b. At this time, the photoresist films 71, 72, 73, and 74 may be removed, and the data line 171, the drain electrode 175a, the input electrode 173b, and the output electrode 175b may be used as a mask. Accordingly, the contact members 170a, 170b, 172a, and 172b have the same planar shape as the data conductors 171, 173a, 175a, and 175b.

The etching of the contact auxiliary layer 174 is preferably dry etching.

As shown in FIGS. 19 to 21, a lower passivation layer 180p made of an inorganic material is laminated by chemical vapor deposition, and an upper passivation layer 180q made of a photosensitive organic material is applied. Subsequently, the upper passivation layer 180q is irradiated with light through a photo mask (not shown), and then developed to expose the lower passivation layer 180p, and then the exposed portion of the lower passivation layer 180p and the gate below it by a dry etching method. A portion of the insulating layer 140 is removed to form a plurality of contact holes 185 exposing the drain electrode 175a of the pixel portion.

Finally, as shown in FIGS. 3 and 4, the drain electrode 175a is formed on the passivation layer 180 through the contact hole 185 with a transparent conductive material such as indium zinc oxide (IZO), indium tin oxide (ITO), or the like. A plurality of pixel electrodes 191 connected to each other are formed.

In the method of manufacturing the thin film transistor and the thin film transistor array panel according to the present invention, a contact auxiliary layer having good adhesion between the interlayer insulating film and the metal layer is reduced to reduce the contact resistance between the semiconductor and the contact auxiliary layer, and then the substrate is heat treated to heat the metal layer and the contact auxiliary layer. Increasing the adhesion between the two can further reduce the contact resistance. As a result, contact resistance between the semiconductor and the metal layer may be reduced, and adhesion may be improved, thereby improving characteristics of the thin film transistor.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (31)

Forming a semiconductor layer on the substrate, Forming a gate insulating layer formed on the semiconductor layer and having a first contact hole exposing at least a portion of the semiconductor layer, Forming a gate electrode on the gate insulating film, Forming an interlayer insulating film having a second contact hole connected to the first contact hole on the gate electrode and the gate insulating film, Stacking a contact auxiliary layer in contact with the semiconductor layer through the first and second contact holes on the interlayer insulating film, Stacking a metal layer on the contact auxiliary layer; Forming a data line and a drain electrode by etching the metal layer, and Removing a portion of the contact auxiliary layer that is not covered by the data line and the drain electrode to form a contact member Method of manufacturing a thin film transistor array panel comprising a. In claim 1, And the semiconductor layer comprises polycrystalline silicon. The method of claim 1 or 2, And the contact auxiliary layer comprises amorphous silicon. In claim 3, And the amorphous silicon comprises a conductive impurity. In claim 3, The metal layer may include aluminum. In claim 1, The metal layer is a single layer thin film transistor array panel manufacturing method. In claim 1, And heat treating the substrate after the metal layer stacking step. In claim 7, The heat treatment is a method of manufacturing a thin film transistor array panel performed at 200 ℃ to 300 ℃. In claim 8, The interlayer insulating layer may include an organic material having a deformation temperature of 200 ° C. to 300 ° C. 10. In claim 1, The thickness of the contact auxiliary layer is 500 Å to 1,000 Å. In claim 1, Forming a passivation layer on the interlayer insulating layer, the data line, and the drain electrode; and forming a pixel electrode connected to the drain electrode on the passivation layer. A polycrystalline silicon film formed on the substrate, An amorphous silicon film in contact with the polycrystalline silicon film, and An aluminum-based metal film formed on the amorphous silicon film Multilayer thin film comprising a. In claim 12, The metal film is a multilayer thin film containing only aluminum. In claim 12, The metal film is a multilayer thin film. In claim 12, The amorphous silicon film is a multilayer thin film containing conductive impurities. In claim 12, The amorphous silicon film is a multilayer thin film having the same planar shape as the metal film. A semiconductor layer formed on the substrate, An interlayer insulating film formed on the semiconductor layer, A contact member made of amorphous silicon formed on the interlayer insulating film, and A conductor formed on the contact member Multilayer thin film comprising a. The method of claim 17, The semiconductor layer is a multilayer thin film containing polycrystalline silicon. The method of claim 17, The conductor is a multilayer thin film comprising aluminum. The method of claim 17, The conductor is a multilayer thin film of a single layer. The method of claim 17, The amorphous silicon is a multilayer thin film containing a conductive impurity. The method of claim 17, The contact member is a multilayer thin film that is the same as the planar shape of the conductor. A semiconductor layer formed on the substrate, A gate insulating film formed on the semiconductor layer, A gate electrode formed on the gate insulating film, An interlayer insulating film formed on the gate electrode and having a contact hole exposing a portion of the semiconductor layer; A contact member formed on the interlayer insulating film and connected to the semiconductor layer through the contact hole, and A source electrode and a drain electrode formed on the contact member Thin film transistor array panel comprising a. The method of claim 23, The semiconductor layer is a thin film transistor array panel including polycrystalline silicon. The method of claim 23, The thin film transistor array panel of which the source electrode and the drain electrode include aluminum. The method of claim 23, The thin film transistor array panel of which the source electrode and the drain electrode have a single layer structure. The method of claim 23, The thin film transistor array panel having protrusions formed on a surface of the semiconductor layer. The method of claim 23, The contact member includes amorphous silicon. The method of claim 28, The amorphous silicon includes a conductive impurity. The method of claim 23, The contact member is a thin film transistor array panel having the same planar shape as the source electrode and the drain electrode. The method of claim 23, A protective film formed on the source electrode and the drain electrode, and A pixel electrode connected to the drain electrode on the passivation layer Thin film transistor display panel further comprising.

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