KR20080003985A - Thin film transistor array panel and method for manufacturing the same - Google Patents

Abstract

A thin film transistor display panel and a method for manufacturing the same is provided to reduce a leakage current of a thin film transistor made of an amorphous silicon by doping conductive type impurities. A gate line(121) is formed on a substrate. A gate dielectric is formed on the gate line. A semiconductor(154a) is formed on the gate dielectric. The semiconductor is comprised of an amorphous silicon that is doped with conductive impurities. A data line(171) is partially overlapped with the semiconductor. A drain electrode(175a) is separated from the data line. The drain electrode is partially overlapped with the semiconductor. A protective layer covers the semiconductor. A pixel electrode(191) is formed on the protective layer. The pixel electrode is connected to the drain electrode through contact holes(183,185). A resistive contact member is formed between the drain electrode and the semiconductor and between the data line and the semiconductor. Further, phosphorus is doped in the resistive contact member.

Description

Thin film transistor array panel and manufacturing method therefor {THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME}

1 is a block diagram of a display device according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display, which is an example of a display device according to an exemplary embodiment of the present invention.

3 is a layout view illustrating a pixel portion of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 4 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 3 taken along the line IV-IV.

5 is a layout view schematically illustrating a thin film transistor for a gate driver of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view of the thin film transistor illustrated in FIG. 5 taken along the line VI-VI.

7 and 9 are layout views at intermediate stages in a method of manufacturing a display panel according to an exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view taken along the line VIII-VIII of FIG. 7.

10 is a cross-sectional view taken along the line X-X of FIG. 9,

11 and 13 are layout views at the next stage of FIGS. 7 and 9.

12 is a cross-sectional view taken along the line XII-XII of FIG. 11.

14 is a cross-sectional view taken along the line XIV-XIV of FIG. 13.

15 and 17 are layout views at the next stage of FIGS. 11 and 13.

FIG. 16 is a cross-sectional view taken along the line XV-XV of FIG. 15.

FIG. 18 is a cross-sectional view taken along the line XVIII-XVIII of FIG. 17.

19 and 21 are layout views at the next stage of FIGS. 15 and 17.

20 is a cross-sectional view taken along the line XX-XX of FIG. 19.

FIG. 22 is a cross-sectional view taken along the line XXII-XII of FIG. 21.

* Description of the major symbols in the drawings *

83: connecting bridge

110: insulating substrate 121: gate line

124a: gate electrode 124b: control electrode

131: sustain electrode lines 133a and 133b: sustain electrode

140: gate insulating film 151, 154a, 154b: semiconductor

161, 163a, 163b, 165a, 165b: resistive contact member

171: data line 173a: source electrode

171b: input electrode 175a: drain electrode

175b: output electrode 180: protective film

183, 184, and 185: contact hole 191: pixel electrode

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

The thin film transistor array panel is used as a substrate of a flat panel display device such as a liquid crystal display or an organic light display (OLED) having a plurality of pixels driven by the thin film transistor.

The thin film transistor included in the pixels of these display devices includes a semiconductor made of silicon. Generally, silicon may be divided into amorphous silicon and crystalline silicon according to the crystal state.

Crystalline silicon is more expensive due to the complexity of the process compared to its high drive capability. In addition, amorphous silicon can be deposited at a low temperature to form a thin film, and thus is mainly used in semiconductors of active devices of display devices using glass having a low melting point as a substrate.

At present, in order to reduce the manufacturing cost in spite of low electrical characteristics, a gate driving circuit is formed together with the thin film transistor of the display unit using amorphous silicon.

However, amorphous silicon is sensitive to light or heat, and changes in electrical characteristics such as an increase in Ioff current at an initial voltage (0 volt) require much effort to obtain stable display characteristics.

Accordingly, a technical problem of the present invention is to maintain a stable Ioff value at an initial voltage even when a transistor made of amorphous silicon is exposed to heat or light.

According to another aspect of the present invention, a thin film transistor array panel includes a substrate, a gate line formed on the substrate, a gate insulating film formed on the gate line, and an amorphous silicon formed on the gate insulating film and doped with conductive impurities. The semiconductor device includes a semiconductor, a data line partially overlapping the semiconductor, a drain electrode partially separated from the data line, a passivation layer covering the semiconductor, and a pixel electrode formed on the passivation layer and connected to the drain electrode through a contact hole.

The conductive impurity may be boron.

Conductive impurities may be doped at a concentration of 5 × 10 ¹¹ to 1 × 10 ¹³ holes / cm ³ .

The semiconductor device may further include an ohmic contact member formed between the drain electrode and the semiconductor and between the data line and the semiconductor.

The ohmic contact may be doped with phosphorus (P).

Another thin film transistor array panel for achieving the above object is a first thin film transistor formed on a substrate, a plurality of intersecting gate lines and a plurality of data lines, gate lines and data lines, respectively, each first thin film A gate driver comprising a pixel electrode connected to the transistor and a circuit comprising a plurality of second thin film transistors for inputting a scan signal to each gate line, wherein the first thin film transistor or the second thin film transistor includes a source electrode; A drain electrode and an amorphous semiconductor doped with conductive impurities.

The conductive impurity may be boron.

Conductive impurities may be doped at a concentration of 5 × 10 ¹¹ to 1 × 10 ¹³ holes / cm ³ .

The semiconductor device may further include an ohmic contact member formed between the drain electrode and the semiconductor and between the source electrode and the semiconductor.

The ohmic contact member may be made of amorphous silicon doped with phosphorus (P).

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, the method including forming a gate electrode on a substrate, forming a gate insulating film covering the gate electrode, and forming an intrinsic semiconductor and resistive silicon on the gate insulating film. Forming a contact member, doping a conductive semiconductor impurity in the intrinsic semiconductor, forming a data line and a drain electrode on the resistive contact member and the gate insulating film, and having a contact hole exposing the drain electrode on the data line and the drain electrode. Forming a passivation layer; and forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer.

Or forming a gate electrode on the substrate, forming a gate insulating film covering the gate electrode, forming an amorphous silicon film for intrinsic semiconductor and an amorphous silicon film doped with impurities on the gate insulating film, and forming an amorphous silicon film for intrinsic semiconductor. Doping a conductive impurity, patterning an amorphous silicon film doped with an impurity and an amorphous silicon film for intrinsic semiconductor to form an impurity semiconductor pattern and a semiconductor, and forming a data line and a drain electrode on the impurity semiconductor pattern and the gate insulating film Forming an ohmic contact by etching the impurity semiconductor pattern using the data line and the drain electrode as a mask; forming a protective film having contact holes exposing the drain electrode on the data line and the drain electrode; Pixel former connected to the drain electrode A includes forming.

The conductive impurity may be boron.

Conductive impurities may be doped at a concentration of 5 × 10 ¹¹ to 1 × 10 ¹³ holes / cm ³ .

The amorphous silicon film doped with impurities may be formed of amorphous silicon containing phosphorus (P).

A protective film can be formed at the temperature of 300-380 degreeC.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A display panel and a manufacturing method thereof according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a display device according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of a liquid crystal display, which is an example of the display device according to an exemplary embodiment.

According to an exemplary embodiment, a display device includes a display panel unit 300, a gate driver 400 connected thereto, a data driver 500, and a gray level signal generator 800 connected to the data driver 500. And a signal controller 600 for controlling them.

Referring to FIG. 1, the display panel unit 300 is connected to a plurality of display panel lines G1 -Gn and D1 -Dm and arranged in a substantially matrix form when viewed in an equivalent circuit. and a plurality of pixels PX constituting a display area DA. Referring to FIG. 2, the display panel 300 of the liquid crystal display includes lower and upper display panels 100 and 200 and a liquid crystal layer 3 therebetween.

The display signal lines G ₁ -G _n and D ₁ -D _m transmit a data signal and a plurality of gate lines G ₁ -G _n that transmit a gate signal (also called a “scan signal”). It includes a data line (D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes at least one switching element (not shown) such as a thin film transistor and at least one capacitor (not shown).

Referring to FIG. 2, each pixel PX of the liquid crystal display device includes a switching element Q connected to the display signal lines G ₁ -G _n and D ₁ -D _m and a liquid crystal capacitor C connected thereto. _LC ) and a storage capacitor (C _ST ). The display signal lines G ₁ -G _n and D ₁ -D _m are disposed on the lower display panel 100, and the storage capacitor C _ST may be omitted as necessary.

The switching element Q such as the thin film transistor is provided in the lower panel 100, and is connected to the control terminal and the data line D ₁ -D _m connected to the gate lines G ₁ -G _n , respectively. It is a three-terminal device with an input terminal and an output terminal connected to a liquid crystal capacitor (C _LC ) and a holding capacitor (C _ST ).

The liquid crystal capacitor C _LC has two terminals, a pixel electrode 191 of the lower panel 100 and a common electrode 270 of the upper panel 200, and a liquid crystal layer 3 between the two electrodes 191 and 270. It functions as a dielectric. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor C _ST is a capacitor that assists the liquid crystal capacitor C _LC . A separate signal line (not shown) and a pixel electrode 191 provided on the lower panel 100 overlap each other, and the separate signal line A predetermined voltage such as the common voltage Vcom is applied to the. However, the storage capacitor C _ST may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

In order to implement color display, each pixel PX uniquely displays one of a plurality of primary colors (spatial division) or alternately displays a plurality of primary colors (time division) so that the spatial and temporal sum of the primary colors can be achieved. Indicates the desired color. Examples of primary colors include red, green and blue. FIG. 2 illustrates an example of spatial division in which each pixel PX includes a color filter 230 representing one color of primary colors in a corresponding region of the upper panel 200 facing the pixel electrode 191. . Alternatively, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the display panel unit 300.

Each pixel PX of the organic light emitting diode display includes a switching transistor (not shown) connected to the display signal lines G ₁ -G _n , D ₁ -D _m , a driving transistor (not shown) connected thereto, Sustain capacitors (not shown), and light emitting diodes (not shown). The light emitting diode includes a pixel electrode (not shown), a common electrode (not shown), and a light emitting member (not shown) therebetween.

Referring back to FIG. 1, the gray signal generator 800 generates a plurality of gray signals related to the transmittance of the pixel PX. The gray level signal generator 800 for the liquid crystal display generates two gray level voltages each having a positive value and a negative value with respect to the common voltage Vcom.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the display panel 300 to receive a gate signal having two values equal to the gate on voltage Von and the gate off voltage Voff, respectively. G ₁ -G _n ). The gate driver 400 is integrated in the display panel 300 and includes a plurality of driving circuits (not shown). Each driving circuit of the gate driver 400 is connected to one gate line G ₁ -G _n and includes a plurality of thin film transistors. However, the gate driver 400 may be mounted on the display panel 300 in the form of an integrated circuit (IC) chip or on a flexible printed circuit (FPC) film. In the latter case, a flexible printed circuit film is attached onto the display panel unit 300.

The data driver 500 is connected to the data lines D ₁ -D _m of the display panel 300 and selects a gray voltage from the gray signal generator 800 to select the gray voltage as the data voltage D ₁ -D _m. ) Is applied. The data driver 500 may also be a flexible printed circuit (FPC) integrated into the display panel unit 300, mounted on the display panel unit 300 in the form of one or more integrated circuit chips, or attached to the display panel unit 300. ) Can be mounted on the film.

The driving units 400 and 500 or the flexible printed circuit film on which they are mounted are positioned in a peripheral area positioned outside the display area DA in the display panel 300.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like, and may be mounted on a printed circuit board (PCB).

Next, an example of the lower panel for the liquid crystal display device, that is, the thin film transistor array panel shown in FIGS. 1 and 2 will be described in detail with reference to FIGS. 3 to 6.

3 is a layout view illustrating a pixel portion of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment. FIG. 4 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 3 taken along line IV-IV. 5 is a layout view schematically illustrating a thin film transistor for a gate driver of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view of the thin film transistor illustrated in FIG. 5 taken along a line VI-VI. It's a shave.

3 to 6, a plurality of gate lines 121 including a gate electrode 124a and a plurality of storage electrode lines on an insulating substrate 110 made of transparent glass or plastic. 131 and a plurality of control electrodes 124b are formed.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction and has a gate electrode 124a protruding below the gate line 121. One end of the gate line 121 is directly connected to the gate driving circuit.

The gate electrode 124b is connected to another signal line (not shown) that applies a control signal.

The storage electrode line 131 receives a predetermined voltage, and includes a stem line extending substantially in parallel with the gate line 121 and a plurality of pairs of storage electrodes 133a and 133b separated therefrom. Each of the storage electrode lines 131 is positioned between two adjacent gate lines 121, and the stem line is closer to the lower side of the two gate lines 121. Each of the sustain electrodes 133a and 133b has a fixed end connected to the stem line and a free end opposite thereto. The fixed end of one sustain electrode 133b has a large area, and its free end is divided into two parts, a straight part and a bent part. However, the shape and arrangement of the storage electrode line 131 may be modified in various ways.

The gate line 121, the control electrode 124b, and the storage electrode line 131 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper (Cu), copper alloy, or the like. It may be made of a molybdenum-based metal such as copper-based metal, molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop. In contrast, other conductive films are made of other materials, particularly materials having excellent physical, chemical, and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, tantalum, and titanium. Good examples of such a combination include a chromium bottom film, an aluminum (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate line 121 and the storage electrode line 131 may be made of various other metals or conductors.

Side surfaces of the gate line 121, the control electrode 124b, and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate line 121, the control electrode 124b, and the storage electrode line 131.

A pixel unit linear semiconductor 151 and a driver island semiconductor 154b formed of hydrogenated chlorinated amorphous silicon (a-Si) on the gate insulating layer 140 and including a plurality of projections 154a may be formed. Formed. The linear semiconductor 151 mainly extends in the longitudinal direction. The island-like semiconductor 154b overlaps the control electrode 124b.

Conductive impurities are doped on the semiconductors 151 and 154b. The conductive impurity may be boron (B), and may have a concentration of 5 × 10 ¹¹ to 1 × 10 ¹³ particles / cm ³ .

A plurality of linear and island ohmic contacts 161, 163a, 163b, 165a and 165b are formed on the semiconductors 151 and 154b. The ohmic contacts 161, 163a, 163b, 165a, and 165b may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus (P) are heavily doped, or made of silicide. The linear ohmic contact 161 has a plurality of protrusions 163a, and the protrusions 163a and the island-like ohmic contact 165a are arranged in pairs and disposed on the protrusions 154a of the semiconductor 151. The island-like ohmic contacts 163b and 165b are also disposed on the island-like semiconductor 151b to face each other.

Side surfaces of the semiconductors 151 and 154b and the ohmic contacts 161, 163a, 163b, 165a, and 165b are also inclined with respect to the substrate 110, and the inclination angle is about 30 ° to 80 °.

A plurality of data lines 171, a plurality of drain electrodes 175a, and a plurality of input electrodes are formed on the ohmic contacts 161, 163a, 163b, 165a, and 165b and the gate insulating layer 140. 173b and a plurality of output electrodes 175b are formed.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 also crosses the storage electrode line 131 and is formed between adjacent sets of storage electrodes 133a and 133b. Each data line 171 includes a plurality of source electrodes 173a extending toward the gate electrode 124a.

The drain electrode 175a is separated from the data line 171 and faces the source electrode 173a around the gate electrode 124a. Each drain electrode 175a has one wide end portion and the other end portion having a rod shape. The wide end portion overlaps the storage electrode line 131, and the rod-shaped end portion is partially surrounded by the source electrode 173a bent in a C shape.

A portion of the input electrode 173b and the output electrode 175b protrude from each other and form a pair to face the semiconductor 154b.

In the pixel portion, one gate electrode 124a, one source electrode 173a, and one drain electrode 175a, together with the protrusion 154a of the semiconductor 151, have one pixel portion thin film transistor (TFT). A channel of the pixel portion thin film transistor is formed in the protrusion 154a between the source electrode 173a and the drain electrode 175a. In the driver, the control electrode 124a, the input electrode 173b, and the output electrode 175b together with the semiconductor 154b form one driver thin film transistor, and the channels of the driver thin film transistor are the input electrode 173b and the output electrode 175b. Formed between).

In an exemplary embodiment of the present invention, an increase in Ioff may be reduced by heat or light at an initial voltage by doping a conductive impurity on top of the semiconductors 151 and 154b.

The data line 171, the drain electrode 175a, the input electrode 173b, and the output electrode 175b may be made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof. It may have a multilayer structure including a metal film (not shown) and a low resistance conductive film (not shown). Examples of the multilayer structure include a double layer of chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, and a triple layer of molybdenum (alloy) lower layer and aluminum (alloy) interlayer and molybdenum (alloy) upper layer. However, the data line 171, the drain electrode 175a, the input electrode 173b, and the output electrode 175b may be made of various other metals or conductors.

The data line 171, the drain electrode 175a, the input electrode 173b, and the output electrode 175b may also be inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161, 163a, 163b, 165a, and 165b include the semiconductors 151 and 154b below and the data lines 171, the drain electrode 175a, the input electrode 173b, and the output electrode 175b thereon. It exists only between) and lowers the contact resistance between them. In most places, the width of the linear semiconductor 151 is smaller than the width of the data line 171.

A passivation layer 180 is formed on the data line 171, the drain electrode 175a, the output electrode 175b, the input electrode 173b, and the exposed semiconductor 154a and 154b. The passivation layer 180 is made of an inorganic insulator such as silicon nitride or silicon oxide, an organic insulator, or a low dielectric insulator. The dielectric constant of the organic insulator and the low dielectric insulator is preferably 4.0 or less. Examples of the low dielectric insulator include a-Si: C: O, a-Si: formed by plasma enhanced chemical vapor deposition (PECVD). O: F, etc. are mentioned. The passivation layer 180 may be formed by having photosensitivity among the organic insulators, and the surface of the passivation layer 180 may be flat. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portions of the semiconductors 154a and 154b while maintaining excellent insulating properties of the organic layer.

A plurality of contact holes 185 are formed in the passivation layer 180, and a plurality of contact holes 185 are formed in the passivation layer 180. In the passivation layer 180 and the gate insulating layer 140, a storage electrode line near the fixed end of the sustain electrode 133b is formed. A plurality of contact holes 183 and 184 exposing a portion of the free end of the 131 is formed.

A plurality of pixel electrodes 191 and a plurality of overpasses 83 are formed on the passivation layer 180. These may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives a data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied has a liquid crystal between the two electrodes by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. The direction of the liquid crystal molecules in the layer (not shown) is determined. The pixel electrode 191 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 overlaps the storage electrode line 131 including the storage electrodes 133a and 133b. A capacitor formed by the pixel electrode 191 and the drain electrode 175 electrically connected to the pixel electrode 191 overlapping the storage electrode line 131 is called a storage capacitor, and the storage capacitor enhances the voltage holding capability of the liquid crystal capacitor.

The connecting leg 83 crosses the gate line 121 and exposes the exposed portion of the storage electrode line 131 and the storage electrode through contact holes 183 and 184 positioned opposite to each other with the gate line 121 interposed therebetween. 133b) is connected to the exposed end of the free end. The storage electrode lines 131 including the storage electrodes 133a and 133b may be used together with the connecting legs 83 to repair defects in the gate line 121, the data line 171, or the thin film transistor.

Next, a method of manufacturing the thin film transistor array panel shown in FIGS. 3 to 6 will be described in detail with reference to FIGS. 7 to 22.

7 and 9 are layout views at an intermediate stage of a method of manufacturing a display panel according to an exemplary embodiment of the present invention. FIG. 8 is a cross-sectional view taken along the line VIII-VIII of FIG. 7, and FIG. 10 is a view of FIG. 9. 11 and 13 are layout views at the next stage of FIGS. 7 and 9, FIG. 12 is a cross-sectional view taken along the line XII-XII of FIG. 11, and FIG. 14 is a cross-sectional view taken along line XII-XII. 13 is a cross-sectional view taken along the line XIV-XIV of FIG. 13, and FIGS. 15 and 17 are layout views at the next stage of FIGS. 11 and 13, and FIG. 16 is a cross-sectional view taken along the line XV-XV of FIG. 15. 18 is a cross-sectional view taken along the line XVIII-XVIII of FIG. 17, and FIGS. 19 and 21 are layout views at the next stage of FIGS. 15 and 17, and FIG. 20 is a XX-XX line of FIG. 19. It is sectional drawing cut along the figure, and FIG. 22 is sectional drawing cut along the XXII-XII line of FIG.

First, as illustrated in FIGS. 7 to 10, a plurality of gate lines 121 including the gate electrode 124a are maintained by stacking and patterning a metal film on an insulating substrate 110 made of transparent glass or plastic. A plurality of sustain electrode lines 131 and control electrodes 124b including electrodes 133a and 133b are formed.

And a gate insulating layer 140 made of silicon nitride (SiNx) on the gate line 121, the control electrode 124b and the storage electrode line 131, an intrinsic amorphous silicon (a-Si) film 150 which is not doped with impurities, and An impurity doped amorphous silicon (n + a-Si) film 160 is formed by plasma chemical vapor deposition (PECVD).

Next, as shown in FIGS. 11 to 14, the linear intrinsic semiconductor 151 including the gate insulating layer 140 and the plurality of protrusions 154a by photo etching the doped amorphous silicon film and the intrinsic amorphous silicon. The island-like intrinsic semiconductor 154b and the plurality of impurity semiconductor patterns 164 are formed.

Thereafter, the conductive semiconductors 151 and 154b are doped with conductive impurities. The conductive impurity doping may be doped prior to patterning the intrinsic semiconductors 151 and 154b and the semiconductor pattern 164.

Next, as shown in FIGS. 15 to 18, a data metal layer is formed on the impurity semiconductor pattern 164 by a sputtering method.

Thereafter, the metal layer is patterned to form a data line 171 including the source electrode 173a, a drain electrode 175a, an input electrode 173b, and an output electrode 175b.

And a plurality of linears including a plurality of protrusions 163a by removing the exposed impurity semiconductor 164 without being covered by the source electrode 173a, the drain electrode 175a, the input electrode 173b, and the drain electrode 175b. The ohmic contact layer 161 and the plurality of islands of ohmic contact 163b, 165a, and 165b are completed while exposing portions of the intrinsic semiconductors 154a and 154b beneath it.

Next, as shown in FIGS. 19 to 22, the passivation layer 180 is formed by depositing an organic material having excellent planarization characteristics and photosensitive properties. In this case, the passivation layer 180 is formed at a temperature of about 300 to 380 ° C., and the conductive dopants doped in the semiconductors 151 and 154b are activated by the heat. Therefore, simply adding a doping process can easily reduce the leakage current.

Thereafter, a plurality of contact holes 183, 184, and 185 are formed in the passivation layer 180 by a photo process.

3 to 6, a transparent conductive layer such as ITO is deposited on the passivation layer 180 by sputtering and then patterned to form the pixel electrode 191 and the connection bridge 83.

As described above, the doping of the conductive impurities may reduce the leakage current of the thin film transistor made of amorphous silicon, thereby providing a liquid crystal display having stable display characteristics.

Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

Claims (16)

Board, A gate line formed on the substrate, A gate insulating film formed on the gate line, A semiconductor formed of the amorphous silicon formed on the gate insulating layer and doped with a conductive impurity, A data line partially overlapping the semiconductor, A drain electrode separated from the data line and partially overlapping the semiconductor; A protective film covering the semiconductor, and And a pixel electrode formed on the passivation layer and connected to the drain electrode through a contact hole. In claim 1, The conductive impurity is boron. In claim 1, The conductive type dopant is doped at a concentration of 5 × 10 ¹¹ to 1 × 10 ¹³ holes / cm ³ . In claim 1, And a resistive contact member formed between the drain electrode and the semiconductor and between the data line and the semiconductor. In claim 4, The thin film transistor array panel on which the ohmic contact is doped with phosphorus (P). Board, A plurality of gate lines and a plurality of data lines formed on the substrate and crossing each other; A first thin film transistor connected to the gate line and the data line, respectively; A pixel electrode connected to each of the first thin film transistors, and A gate driver including a circuit comprising a plurality of second thin film transistors for inputting a scan signal to each of the gate lines; Including, The thin film transistor array panel of claim 1, wherein the first thin film transistor or the second thin film transistor comprises a source electrode, a drain electrode, and an amorphous semiconductor doped with conductive impurities. In claim 6, The conductive impurity is boron. In claim 6, The conductive dopant is doped at a concentration of 5 × 10 ¹¹ to 1 × 10 ¹³ holes / cm ³ . In claim 6, And a resistive contact member formed between the drain electrode and the semiconductor and between the source electrode and the semiconductor. In claim 9, The resistive contact member is a thin film transistor array panel made of amorphous silicon doped with phosphorus (P). Forming a gate electrode on the substrate, Forming a gate insulating film covering the gate electrode; Forming an intrinsic semiconductor made of amorphous silicon and a resistive contact member on the gate insulating film, Doping a conductive impurity into the intrinsic semiconductor, Forming a data line and a drain electrode on the ohmic contact and the gate insulating layer; Forming a protective film having a contact hole exposing the drain electrode on the data line and the drain electrode; and Forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer Method of manufacturing a thin film transistor array panel comprising a. Forming a gate electrode on the substrate, Forming a gate insulating film covering the gate electrode; Forming an amorphous silicon film for intrinsic semiconductor and an amorphous silicon film doped with impurities on the gate insulating film, Doping a conductive impurity into the amorphous silicon film for the intrinsic semiconductor, Patterning the amorphous silicon film doped with the impurity and the amorphous silicon film for the intrinsic semiconductor to form an impurity semiconductor pattern and a semiconductor, Forming a data line and a drain electrode on the impurity semiconductor pattern and the gate insulating layer; Etching the impurity semiconductor pattern using the data line and the drain electrode as a mask to form an ohmic contact; Forming a protective film having a contact hole exposing the drain electrode on the data line and the drain electrode; and Forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer Method of manufacturing a thin film transistor array panel comprising a. The method of claim 11 or 12, And the conductive impurity is boron. The method of claim 11 or 12, The conductive impurity is doped in a concentration of 5 × 10 ¹¹ ~ 1 × 10 ¹³ / cm ³ A manufacturing method of a thin film transistor array panel. The method of claim 11 or 12, And the amorphous silicon film doped with impurities is made of amorphous silicon containing phosphorus (P). The method of claim 11 or 12, The protective film is a method of manufacturing a thin film transistor array panel formed at a temperature of 300 ~ 380 ℃.

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