KR20060084488A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The thin film transistor array panel according to the present invention is formed on a substrate, a blocking film having first and second portions having different thicknesses, a semiconductor formed on the first portion of the blocking film, a gate insulating film formed on the semiconductor, and a gate insulating film. A gate line formed, a data line formed over the gate insulating film, and a pixel electrode formed over the gate insulating film, wherein the first portion is formed thicker than the second portion.

Crystallization, SLS, size, heat conduction

Description

Thin film transistor array panel and method for manufacturing same {THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF}

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II'-II ".

3 is a cross-sectional view at a first stage of a method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 of the present invention according to one embodiment of the present invention.

4A is a layout view of a thin film transistor array panel in the next step of FIG. 3.

4B is a cross-sectional view taken along the line IVb-IVb′-IVb ″ of FIG. 4A.

FIG. 5A is a layout view of a thin film transistor array panel in the next step of FIG. 4A.

FIG. 5B is a cross-sectional view taken along the line Vb-Vb′-Vb ″ of FIG. 5A.

FIG. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5B taken along the line Vb-Vb′-Vb ″ of FIG. 5A.

FIG. 7A is a layout view of a thin film transistor array panel in the next step of FIG. 6.

FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb′-VIIb ″ of FIG. 7A.

8A is a layout view of a thin film transistor array panel in the next step of FIG. 7A.                 

FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb'-VIIIb ″ of FIG. 8A.

9 is a layout view illustrating a structure of a thin film transistor array panel for an organic light emitting diode display according to another exemplary embodiment of the present invention.

10 and 11 are cross-sectional views of the thin film transistor array panel of FIG. 9 taken along lines X-X 'and XI-XI'.

* Description of symbols on the main parts of the drawings *

70: light emitting layer

110: substrate

121: gate line

133: sustain electrode

151, 151a, 151b: semiconductor

171: data line

190: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistor array panels, and more particularly, to a thin film transistor array panel having a semiconductor made of polycrystalline silicon and a method of manufacturing the same.

The thin film transistor array panel is used as a substrate of a flat panel display such as a liquid crystal display or an organic light display (OLED) having a plurality of pixels driven by the thin film transistor.

The liquid crystal display includes a field generating electrode for generating an electric field and a liquid crystal layer therebetween. In such a liquid crystal display, an electric field is formed on the liquid crystal layer by applying a voltage to two field generating electrodes to determine the alignment of liquid crystal molecules and to adjust the polarization of incident light to display an image. In this case, the thin film transistor is used to control the signal applied to the electrode.

The organic light emitting diode display is a self-emission display device that displays an image by exciting an emission of a light emitting organic material. The organic light emitting diode display includes a hole injection electrode (anode), an electron injection electrode (cathode), and an organic light emitting layer interposed therebetween, and when holes and electrons are injected into the organic light emitting layer, they are paired up and extinguished to emit light. .

Each pixel of the OLED display includes two thin film transistors, that is, a driving thin film transistor and a switching transistor. The amount of current of the driving thin film transistor that supplies a current for light emission is controlled by a data signal applied through the switching transistor. Widely used thin film transistors are made of amorphous silicon, polycrystalline silicon, or the like. Amorphous silicon can be deposited at a low temperature to form a thin film, and thus is mainly used in display devices using glass having a low melting point as a substrate.

However, the amorphous silicon thin film has difficulty in large area of the display device due to problems such as low field effect mobility. Therefore, there is a demand for the application of polycrystalline silicon having high field effect mobility, high frequency operating characteristics, and low leakage current electrical characteristics.

The electrical properties of the thin film using such polycrystalline silicon are greatly influenced by the size and uniformity of the grains. That is, as the size and uniformity of the particles increase, the field effect mobility also increases. Therefore, there is increasing interest in a method of forming uniform polycrystalline silicon while increasing the particle size.

SUMMARY OF THE INVENTION An aspect of the present invention is to provide a thin film transistor array panel and a method of manufacturing the same that can maximize the size of crystal grains of polycrystalline silicon to improve electron mobility.

In order to achieve the above object, the thin film transistor array panel according to the present invention is formed on a substrate, a substrate having a first and second portions having different thicknesses, a semiconductor formed on the first portion of the circuit, and a semiconductor formed on the semiconductor. A gate insulating film, a gate line formed over the gate insulating film, a data line formed over the gate insulating film, and a pixel electrode formed over the gate insulating film, the first portion is formed thicker than the second portion.

And the first portion is about 5,000 mm 3, and the second portion is about 2,000 mm 3.                     

The display device may further include a storage electrode line parallel to the gate line.

In addition, the insulating film may further include a blocking film formed between the semiconductor.

The semiconductor device may further include a passivation layer formed between the gate line and the data line and the pixel electrode.

The display device may further include a partition formed on the pixel electrode and a light emitting layer surrounded by the partition.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, the method including forming a blocking film having first and second portions having different thicknesses on a substrate, forming a semiconductor film formed of amorphous silicon on the blocking film, and a semiconductor. Crystallizing the film by a sequential lateral solidification technique, patterning the semiconductor film to form a semiconductor on the first portion, forming a gate insulating film on the semiconductor, forming a gate line on the gate insulating film, semiconductor using the gate line as a mask Doping the conductive impurity ions into the semiconductor substrate, forming a data line crossing the gate line, and forming a pixel electrode connected to the data line, wherein the first portion is formed thicker than the second portion.

In the crystallization step, it is preferable that the grains of the first portion are formed larger than the second portion.

In addition, the forming of the blocking film may include forming an insulating film by depositing an insulating material on a substrate, forming a photosensitive film pattern having a different thickness on the insulating film, and etching the insulating film using a photosensitive film pattern as a mask.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First, a polysilicon thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along a line II-II'-II ".

A blocking film 111 made of silicon oxide (SiO ₂ ), silicon nitride (SiNx), or the like is formed on the transparent insulating substrate 110. The blocking film 111 includes a first portion A that is relatively thicker than other portions and a second portion B that is thinner than the first portion A. FIG. The 1st part A is formed in thickness of 5,000 kPa, and the 2nd part B is formed in thickness of 2,000 kPa.

On the first portion A of the blocking layer 111, a plurality of island-like semiconductors 151 made of polycrystalline silicon are formed. The width of the island-like semiconductor 151 may be wider or narrower than the width of the first portion A. Unlike shown, the width of the island 151 may be narrower than that of the first portion A. In the case where it is wide like this, it is preferable to form the sloping angle of the side of the first portion A more smoothly than in the case of narrowing.

The island-like semiconductor 151 is long horizontally, and both ends thereof have a large area for connection with other layers.

Each semiconductor 151 includes an impurity region containing conductive impurities and an intrinsic region containing little conductive impurities, and a heavily doped region having a high impurity concentration in the impurity region. There is a lightly doped region with low concentrations of impurities.

The intrinsic region includes two channel regions 154a and 154b that are spaced apart from each other. The high concentration impurity region includes a plurality of source / drain regions 153, 155, and 157 separated from each other with respect to the channel regions 154a and 154b. The source / drain regions may be formed in fewer or more than the embodiments of the present invention, and thus the number of channel regions may be formed in fewer or more.

The low concentration impurity regions 152a and 152b located between the source / drain regions 153, 155 and 157 and the channel regions 154a and 154b are called lightly doped drain regions (LDD regions) and have a width. Narrower than other areas

Examples of the conductive impurity include P-type impurities such as boron (B) and gallium (Ga) and N-type impurities such as phosphorus (P) and arsenic (As). The lightly doped regions 152a and 152b prevent leakage current or punch through from the thin film transistor, and the lightly doped regions 152a and 152b are free of impurities. ) Can be replaced with an area.

On the semiconductor 151 and the blocking layer 111, a gate insulating layer 140 having a thickness of several hundred micrometers of silicon nitride or silicon oxide is formed.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 extending in the horizontal direction are formed on the gate insulating layer 140.

The gate line 121 transmits a gate signal, and a portion of the semiconductor 151 protrudes upward and includes a plurality of protrusions overlapping the channel regions 154a and 154b of the semiconductor 151. As such, a portion of the gate line 121 overlapping the channel regions 154a and 154b is used as the gate electrodes 124a and 124b of the thin film transistor. The gate electrodes 124a and 124b may also overlap the lightly doped regions 152a and 152b.

One end portion of the gate line 121 may have a large area for connecting with another layer or an external driving circuit, and when a gate driving circuit (not shown) generating a gate signal is integrated on the substrate 110. The gate line 121 may be directly connected to the gate driving circuit.

The storage electrode line 131 is positioned between the two gate lines 121 and is adjacent to the lower side of the two gate lines 121. The storage electrode line 131 includes the storage electrode 133 extending in the vertical direction to the vicinity of the upper gate line 121, and applies a predetermined voltage such as a common voltage applied to a common electrode (not shown). Receive.

The gate line 121 and the storage electrode line 131 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, Molybdenum-based metals such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta) and titanium (Ti) and the like. However, the gate line 121 may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of the conductive layers is made of a low resistivity metal, for example, an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce a signal delay or voltage drop of the gate line 121. The other conductive layer may be made of another material, particularly a material having excellent physical, chemical and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metal, chromium, tantalum, or titanium. . A good example of such a combination is a chromium bottom film and an aluminum top film, and an aluminum bottom film and a molybdenum top film.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110 so that the upper thin film can be smoothly connected.

An interlayer insulating film 160 is formed on the gate line 121, the storage electrode line 131, and the gate insulating layer 140. The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and photosensitivity, a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or the like formed by plasma chemical vapor deposition, or It may be formed of an inorganic material such as silicon nitride. A plurality of contact holes 163 and 165 exposing the outermost source / drain regions 153 and 155 are formed in the interlayer insulating layer 160 and the gate insulating layer 140, respectively.

A plurality of date lines 171 and a plurality of output electrodes 175 are formed on the interlayer insulating layer 160 to intersect the gate line 121.

Each data line 171 includes an input electrode 173 connected to the source / drain region 153 through the contact hole 163. One end of the data line 171 may have a large area in order to connect with another layer or an external driving circuit, and when a data driving circuit (not shown) generating a data signal is integrated on the substrate 110 Line 171 may be directly connected to the data driving circuit. The storage electrode 133 is positioned between two adjacent data lines 171.

The output electrode 175 is separated from the input electrode 173 and connected to the source / drain region 155 through the contact hole 165.

The data line 171 and the output electrode 175 are preferably made of a refractory metal such as molybdenum, chromium, tantalum, titanium, or an alloy thereof. However, they may also have a multilayer structure including a conductive film having a low resistance and a conductive film having good contact characteristics, such as the gate line 121. Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

Side surfaces of the data line 171 and the output electrode 175 may also be inclined with respect to the substrate 110 surface.

A passivation 180 made of an organic material having excellent planarization characteristics is formed on the data line 171, the output electrode 175, and the interlayer insulating layer 160. The passivation layer 180 may be made of only a photo process using a material having photosensitivity. The passivation layer 180 may also be formed of plasma enhanced chemical vapor deposition (PECVD), such as a-Si: C: O, a-Si: O: F, or a dielectric constant of 4.0 or less, such as dielectric constant or silicon nitride The protective layer 180 may include a lower layer of an inorganic material and an upper layer of an organic material. The protective layer 180 may include a plurality of contact holes 185 and a data line 171 exposing the output electrode 175. It has a plurality of contact holes 182 exposing one end of the.

On the passivation layer 180b, a pixel electrode 190 and a contact auxiliary member 82 made of a transparent conductive material such as IZO (indium zinc oxide) or ITO (indium tin oxide), or an opaque reflective conductive material such as aluminum or silver ) Is formed.

The pixel electrode 190 is connected to the output electrode 175 connected to the source / drain region 155 through the contact hole 185 to receive a data voltage from the source / drain region 155 and the output electrode 175.

The contact assistant 82 serves to protect the adhesiveness between the end portion of the data line 171 and the external device. The pixel electrode 190 to which the data voltage is applied generates an electric field together with the common electrode to which the data voltage is applied to determine the direction of liquid crystal molecules of a liquid crystal layer (not shown) between the two electrodes.

In the case of the liquid crystal display, the pixel electrode 190 and the common electrode form a capacitor (hereinafter, referred to as a 'liquid crystal capacitor') to maintain an applied voltage even after the thin film transistor is turned off. To do this, another capacitor connected in parallel with the liquid crystal capacitor is provided, which is called a storage capacitor. The storage capacitor is made by overlapping the storage electrode line 131 including the pixel electrode 190 and the storage electrode 133. The storage electrode 133 may not be formed depending on the amount of storage power required.

The pixel electrode 190 may overlap the data line 171 to improve the aperture ratio.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 2 will be described in detail with reference to FIGS. 1 and 2, together with FIGS. 3 to 8B.

3 is a cross-sectional view at a first stage of a method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 of the present invention according to an embodiment of the present invention, and FIG. 4A is a thin film transistor at the next stage of FIG. 4B is a cross-sectional view taken along line IVb-IVb′-IVb ″ of FIG. 4A, FIG. 5A is a layout view of a thin film transistor array panel in the next step of FIG. 4A, and FIG. 5B is a view of FIG. 5A. FIG. 6 is a cross-sectional view taken along the line Vb-Vb'-Vb ', and FIG. 6 is a cross-sectional view taken along the line Vb-Vb'-Vb' of FIG. FIG. 7A is a layout view of a thin film transistor array panel in the next step of FIG. 6, and FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb′-VIIb ″ of FIG. 7A, and FIG. 8A is a cross sectional view of the next step of FIG. 7A. 8B is a layout view of a thin film transistor array panel, and FIG. 8B is a VI of FIG. 8A It is sectional drawing cut along the IIb-VIIIb'-VIIIb "line.

First, as shown in FIG. 3, the blocking layer 111 is formed on the transparent insulating substrate 110. Thereafter, the upper portion of the blocking layer 111 is partially removed by a photolithography process to form first and second portions A and B having different thicknesses. In the photolithography process, a photoresist layer is formed on the blocking layer 111, and the photoresist layer is exposed and developed using the photomask MP having the slit S to form a photoresist pattern PR having a different thickness. The barrier layer 111 is etched using the photoresist pattern PR as a mask.

Next, as shown in FIGS. 4A and 4B, a semiconductor film made of amorphous silicon is formed by a method such as chemical vapor deposition (CVD), sputtering, or the like.

Next, the semiconductor film 150 is crystallized in a sequential side solidification method. At this time, the size of the crystal grains is changed due to the difference in thickness of the blocking film 111. That is, the first portion A of the blocking layer 111 is thicker than the second portion B, and heat is slowly released from the second portion B relatively. Thus, the grain size of the first portion A is larger than that of the second portion B.

Then, the semiconductor film is patterned to form a semiconductor 151.

As shown in FIGS. 5A and 5B, the gate insulating layer 140 is formed on the substrate by chemical vapor deposition. In addition, a metal film is stacked on the gate insulating layer 140 by sputtering to form a photoresist pattern PR. The metal film is etched using the photoresist pattern PR as an etch mask to form a plurality of gate lines 121 including the gate electrode 124 and a plurality of storage electrode lines 131 including the storage electrode 133.

In this case, the etching time is sufficiently long so that the boundary line between the gate line 121 and the storage electrode line 131 is positioned inside the photoresist pattern PR.

Subsequently, a high concentration of N-type or P-type impurity ions are implanted into the island-type semiconductor 151 using the photoresist pattern PR as an ion implantation mask to form a plurality of high-concentration impurity regions including the source / drain regions 153, 155, and 157. Form.

Next, as shown in FIG. 6, after removing the photoresist pattern PR, the island-type semiconductor 151 is doped with low concentration of N-type or P-type impurity ions using the gate line 121 and the storage electrode line 131 with an ion implantation mask. Thus, a plurality of low concentration impurity regions 152a and 152b are formed. In this way, the region under the gate electrode 124 positioned between the source / drain regions 153, 155, and 157 becomes the channel regions 154a and 154b.

The low concentration impurity regions 152a and 152b may be formed by using metal films having different etching ratios in addition to the photoresist pattern described above, or by forming spacers on sidewalls of the gate line 121 and the storage electrode line 131. have.

7A and 7B, the plurality of contact holes 163 exposing the source / drain regions 153 and 155 at both ends, respectively, by stacking and photographing the interlayer insulating layer 160 on the entire surface of the substrate 110. 165).

Next, a plurality of data lines 171 and a plurality of output electrodes 175 having an input electrode 173 connected to the source / drain regions 153 through contact holes 163 and 165, respectively, are formed on the interlayer insulating layer 160. Form.

As shown in FIGS. 8A and 8B, the passivation layer 180 is stacked and photo-etched to form a plurality of contact holes 185 exposing the output electrode 175.

1 and 2, contact holes 185 and 182 exposing portions of the passivation layer 180 by the photolithography process to expose the ends of the output electrode 175 and the data line 171, respectively. To form.

Next, a thin film transistor array panel according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 9 to 11.

FIG. 9 is a layout view illustrating a structure of a thin film transistor array panel for an organic light emitting diode display according to another exemplary embodiment. FIGS. 10 and 11 illustrate X-X ′ and XI-XI ′ lines of the thin film transistor array panel of FIG. 9. It is a cross-sectional view cut along.

9 to 11, a blocking film 111 made of silicon oxide, silicon nitride, or the like is formed on the insulating substrate 110. The blocking film 111 includes a first portion A that is relatively thicker than other portions and a second portion B that is thinner than the first portion A. FIG. The 1st part A is formed in thickness of 5,000 kPa, and the 2nd part B is formed in thickness of 2,000 kPa.

On the first portion A of the blocking layer 111, a plurality of island-like semiconductors 151 made of polycrystalline silicon are formed. The width of the island-like semiconductor 151 may be wider or narrower than the width of the first portion A. Unlike shown, the width of the island 151 may be narrower than that of the first portion A. In the case where it is wide like this, it is preferable to form the sloping angle of the side of the first portion A more smoothly than in the case of narrowing.

First and second semiconductors 151a and 151b including polycrystalline silicon formed by a sequential lateral solidification technique are formed on the blocking layer 111, and a capacitor semiconductor 157 is connected to the second semiconductor 151b. have. The first semiconductor 151a includes a first source / drain region and a channel region 153a, 154a, and 155a, and the second semiconductor 151b includes a second source / drain region and channel region 153b, 154b, and 155b. ).

The first source / drain regions 153a and 155a of the first semiconductors 153a, 154a, and 155a are doped with n-type impurities, and the second source / drain regions 153b of the second semiconductors 153b, 154b, and 155b. , 155b) is doped with a p-type impurity. Depending on the driving conditions, the first source / drain regions 153a and 155a may be doped with p-type impurities, and the second source / drain regions 153b and 155b may be doped with n-type impurities.

Here, the first semiconductors 153a, 154a, and 155a are semiconductors of the switching thin film transistor, and the second semiconductors 153b, 154b and 155b are semiconductors of the driving thin film transistor.

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the semiconductors 151a, 151b, and 157. The gate line 121 and the storage electrode 133 are formed on the gate insulating layer 140. The first gate electrode 124a is connected to the gate line 121 to have a branch shape, and overlaps the channel region 154a of the first semiconductor. The second gate electrode 124b is connected to the gate line 121. Are separated and overlap with the channel region (second channel portion 154b) of the second semiconductor 151b. The storage electrode 133 is connected to the second gate electrode 124b and overlaps the storage electrode portion 157 of the semiconductor.

The gate line 121 and the storage electrode line 133 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, Molybdenum-based metals such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta) and titanium (Ti) and the like. However, the gate line 121 may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of the conductive layers is made of a low resistivity metal, for example, an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce a signal delay or voltage drop of the gate line 121. The other conductive layer may be made of another material, particularly a material having excellent physical, chemical and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metal, chromium, tantalum, or titanium. . A good example of such a combination is a chromium bottom film and an aluminum top film, and an aluminum bottom film and a molybdenum top film.

A first interlayer insulating layer 801 is formed on the gate line 121, the first and second gate electrodes 124a and 124b, and the storage electrode 133, and transmits a data signal on the first interlayer insulating layer 801. A data line 171, a linear power supply voltage electrode 172 for supplying a power supply voltage, first and second input electrodes 173a and 173b, and first and second output electrodes 175a and 175b are formed. have.

The first input electrode 173a is a part of the data line 171 and has a branch shape, and the first source / through the contact hole 181 penetrating the first interlayer insulating film 801 and the gate insulating film 140. It is connected to the drain region 153a, and the second source / drain region 173b has a branch shape as part of the electrode for the power voltage 172, and penetrates through the first interlayer insulating film 801 and the gate insulating film 140. It is connected with the 2nd source / drain area | region 153b through the contact hole 184 which is made.

The first source / drain region 175a is provided with the first source / drain region 155a and the second gate electrode through the contact holes 182 and 183 penetrating the first interlayer insulating layer 801 and the gate insulating layer 140. 124b is contacted and they are electrically connected to each other. The second output electrode 175b is connected to the second source / drain region 155b through the contact hole 186 penetrating the first interlayer insulating layer 801 and the gate insulating layer 140, and the data line 171. It is made of the same material as).

A second interlayer insulating film 802 made of silicon nitride, silicon oxide, or an organic insulating material is formed on the data line 171, the power voltage electrode 172, and the first and second output electrodes 175a and 175b. , The second interlayer insulating film 802 is formed as the second substrate. It has a contact hole 185 exposing the electrode 175b.                     

The pixel electrode 190 connected to the second output electrode 175b is formed on the second interlayer insulating layer 802 through the contact hole 185. The pixel electrode 190 is preferably formed of a material having excellent reflectivity such as aluminum or silver alloy.

However, if necessary, the pixel electrode 190 may be formed of a transparent insulating material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 190 made of a transparent conductive material is applied to a bottom emission organic light emitting diode that displays an image in a downward direction of the display panel. The pixel electrode 190 made of an opaque conductive material is applied to top emission organic light emitting diodes that display an image in an upper direction of the display panel.

An organic insulating material is formed on the second interlayer insulating layer 802, and a partition 803 is formed to separate the organic light emitting cells. The partition 803 surrounds the pixel electrode 190 to define a region in which the organic emission layer 70 is to be filled. The partition wall 803 serves as a light shielding film by exposing and developing a photosensitive agent including a black pigment, and at the same time, the forming process can be simplified. An organic emission layer 70 is formed in an area on the pixel electrode 190 surrounded by the partition 803. The organic light emitting layer 70 is formed of an organic material emitting one of red, green, and blue light, and the red, green, and blue organic light emitting layers 70 are repeatedly arranged in sequence.

The buffer layer 804 is formed on the organic light emitting layer 70 and the partition 803. The buffer layer 804 may be omitted as necessary.

The common electrode 270 is formed on the buffer layer 804. The common electrode 270 is made of a transparent conductive material such as ITO or IZO. If the pixel electrode 190 is made of a transparent conductive material such as ITO or IZO, the common electrode 270 may be made of a metal having good reflectivity such as aluminum.

Although not shown, an auxiliary electrode may be formed of a metal having low resistance to compensate for the conductivity of the common electrode 270. The auxiliary electrode may be formed between the common electrode 270 and the buffer layer 804 or on the common electrode 270. The auxiliary electrode may be formed in a matrix shape along the partition wall 803 so as not to overlap the organic light emitting layer 70. .

As described above, according to the present invention, the grain size of the polycrystalline silicon is increased by varying the thickness of the blocking film to improve the current mobility of the semiconductor, thereby providing a high quality thin film transistor array panel.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (9)

Board, A barrier film formed on the substrate and having first and second portions having different thicknesses; A semiconductor formed on the first portion of the blocking film, A gate insulating film formed on the semiconductor, A gate line formed on the gate insulating film, A data line formed on the gate insulating film, and A pixel electrode formed on the gate insulating film, The thin film transistor array panel of which the first portion is formed thicker than the second portion. In claim 1, The thin film transistor array panel of which the first portion is about 5,000 mV and the second portion is about 2,000 mV. In claim 1, The thin film transistor array panel further includes a storage electrode line parallel to the gate line. In claim 1, The thin film transistor array panel of claim 1, further comprising a blocking layer formed between the insulating substrate and the semiconductor. In claim 1, And a passivation layer formed between the gate line and the data line and the pixel electrode. In claim 1, Barrier ribs formed on the pixel electrodes; And a light emitting layer surrounded by the partition wall. Forming a blocking film having first and second portions having different thicknesses on the substrate, Forming a semiconductor film made of amorphous silicon on the blocking film, Crystallizing the semiconductor film by a sequential lateral solidification technique; Patterning the semiconductor film to form a semiconductor on the first portion, Forming a gate insulating film on the semiconductor, Forming a gate line on the gate insulating layer; Doping the semiconductor with conductive impurity ions using the gate line as a mask; Forming a data line crossing the gate line; Forming a pixel electrode connected to the data line; And forming the first portion thicker than the second portion. In claim 7, In the crystallization step, A method of manufacturing a thin film transistor array panel in which the crystal grains of the first portion are larger than the second portion. In claim 7, Forming the blocking film, Depositing an insulating material on the substrate to form an insulating film, Forming a photoresist pattern having a different thickness on the insulating layer; And manufacturing the thin film transistor array panel by etching the insulating layer using the photoresist pattern as a mask.

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