KR20050063015A - Method for manufacturing a thin film transistor - Google Patents

Abstract

First, amorphous silicon is laminated on the insulating substrate, and then the amorphous silicon is patterned to pattern the edge portion to have a thickness thinner than the center portion to form an amorphous silicon pattern. Subsequently, the amorphous silicon pattern is crystallized to form a semiconductor layer of polycrystalline silicon, a gate insulating film covering the semiconductor layer is formed, a gate electrode is formed on the gate insulating film of the semiconductor layer, and impurities are formed on the semiconductor layer. By implantation, source and drain regions are formed on both sides of the gate electrode. Subsequently, a first interlayer insulating layer covering the gate electrode is formed, and then source and drain electrodes electrically connected to the source and drain regions are respectively formed.

Description

METHODS FOR MANUFACTURING A THIN FILM TRANSISTOR

The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a thin film transistor using polycrystalline silicon as a semiconductor.

In general, the thin film transistor array panel is used as a substrate such as a liquid crystal display device or an organic EL display device having pixels having a matrix array. At this time, each pixel is provided with a thin film transistor as a switching element to selectively drive the R, G, B pixels, it is possible to implement a screen of various colors.

A liquid crystal display is an apparatus that displays an image by applying an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two display panels by using an electrode, and controlling the amount of light transmitted through the substrate by adjusting the intensity of the electric field. . In this case, a thin film transistor is used as the switching element to control the image signal transmitted to the electrode.

Organic electro-luminescence is a display device that displays an image by electrically exciting and emitting a fluorescent organic material, and includes a hole injection electrode (anode), an electron injection electrode (cathode), and an organic light emitting layer formed therebetween. When charge is injected into the organic light emitting layer, electrons and holes are paired and extinguished to emit light. Each pixel includes a driving thin film transistor and a switching transistor. In this case, the amount of current of the driving thin film transistor that supplies the current for light emission is controlled by the data voltage applied through the switching transistor, and the gate and source of the switching transistor and the gate signal line (or scan line) are disposed to cross each other. It is connected to the data signal line.

The most common thin film transistor used in such a display device uses amorphous silicon as a semiconductor layer.

Such amorphous silicon thin film transistors are approximately 0.5 占 ??. It has a mobility of about 1 cm 2 / Vsec, so that it can be used as a switching element of a liquid crystal display device, but the mobility is small and a direct drive circuit in a display device such as a liquid crystal panel or an organic electroluminescence (EL). There is an inadequate disadvantage of forming it.

Therefore, to overcome this problem, the current mobility is approximately 20 ??. A liquid crystal display device or an organic EL (electro luminescence) using a polycrystalline silicon thin film transistor using a polycrystalline silicon of about 150 cm 2 / Vsec as a semiconductor layer as a switching element or a driving element has been developed. Because of the current mobility, it is possible to implement a chip in glass in which a driving circuit is embedded in a panel for a display device.

In this case, in order to use polycrystalline silicon as a semiconductor layer, an amorphous silicon layer should be stacked on top of the substrate and then subjected to a crystallization process. Currently, a method of crystallizing and forming a thin film of polycrystalline silicon on a glass substrate having a low melting point is the most. Popular methods include excimer laser annealing and sequential lateral solidification.

However, since these methods deposit an amorphous silicon layer on top of a substrate and then perform a crystallization process over the entire substrate area, the yield per unit time is lowered, which is disadvantageous in terms of productivity. The problem arises because the process is added. In order to solve this problem, a method of stacking an amorphous silicon layer and patterning the photolithography process using a mask has been developed. However, in this process, there is a problem in that the crystallization rate is partially different from the thermal conductivity of the center portion and the edge portion of the patterned amorphous silicon layer. In particular, in the case of forming a fine pattern, this phenomenon occurs more severely, and after crystallization, the polycrystalline silicon cools down, and the edge portion is condensed to form a spherical strain, which causes a problem in that a channel of the thin film transistor cannot be formed.

It is an object of the present invention to provide a method for manufacturing a thin film transistor capable of uniformly proceeding the crystallization of patterned amorphous silicon.

In order to solve the above problems, in the present invention, the thickness of the amorphous silicon layer is partially differently patterned, and then crystallization is performed. At this time, it is preferable to form to a thickness thinner than the center of the edge portion.

More specifically, in the method of manufacturing a thin film transistor according to an embodiment of the present invention, first, amorphous silicon is laminated on an insulating substrate, and then amorphous silicon is patterned to form an amorphous silicon pattern having a partially different thickness. Subsequently, the amorphous silicon pattern is crystallized to form a semiconductor layer of polycrystalline silicon, a gate insulating film covering the semiconductor layer is formed, a gate electrode is formed on the gate insulating film of the semiconductor layer, and impurities are formed on the semiconductor layer. By implantation, source and drain regions are formed on both sides of the gate electrode. Subsequently, a first interlayer insulating layer covering the gate electrode is formed, and then source and drain electrodes electrically connected to the source and drain regions are respectively formed.

In the manufacturing method, the method may further include forming a second interlayer insulating layer covering the source and drain electrodes, and forming a pixel electrode connected to the drain electrode.

In this case, the edge portion of the amorphous silicon is preferably formed to have a thickness thinner than the center portion, the amorphous silicon pattern is formed by a photolithography process using a photoresist pattern, the photoresist pattern has a partially different thickness, the photoresist pattern is partially It is preferable to form using a mask having a different transmittance.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

In the method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention, a description will be given of a method of manufacturing a display panel used as a substrate of a display device including a thin film transistor.

First, the structure of the thin film transistor array panel for an organic light emitting display device will be described with reference to FIGS. 1 to 3.

A blocking layer 111 made of silicon oxide, silicon nitride, or the like is formed on the insulating substrate 110, and first and second polycrystalline silicon layers 150a and 150b are formed on the blocking layer 111, and a second layer is formed on the insulating substrate 110. The polycrystalline silicon layer 157 for capacitors is connected to the polycrystalline silicon layer 150b. The first polycrystalline silicon layer 150a includes first transistor portions 153a, 154a, and 155a, and the second polycrystalline silicon layer 150b includes second transistor portions 153b, 154b, and 155b. The source region (first source region 153a) and the drain region (first drain region, 155a) of the first transistor portions 153a, 154a, and 155a are doped with n-type impurities, and the second transistor portions 153b and 154b. The source region (second source region 153b) and the drain region (second drain region 155b) of 155b are doped with p-type impurities. At this time, depending on the driving conditions, the first source region 153a and the drain region 155a may be doped with p-type impurities, and the second source region 153b and the drain region 155b may be back-doped with n-type impurities. . Here, the first transistor portions 153a, 154a, and 155a are semiconductors of the switching thin film transistor, and the second transistor portions 153b, 154b, and 155b are semiconductors of the driving thin film transistor. At this time, the edge portions of the polycrystalline silicon layers 150a, 150b, and 157 have inclined profiles made of a tapered structure.

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the polycrystalline silicon layers 150a, 150b, and 157. On the gate insulating layer 140, a gate line 121 including a conductive film made of a low resistance conductive material such as aluminum or an aluminum alloy, first and second gate electrodes 124a and 124b, and a storage electrode 133 are formed. have. The first gate electrode 124a is connected to the gate line 121 to have a branch shape, and overlaps the channel portion (first channel portion 154a) of the first transistor, and the second gate electrode 124b is a gate. It is separated from the line 121 and overlaps with the channel portion (second channel portion 154b) of the second transistor. The storage electrode 133 is connected to the second gate electrode 124b and overlaps the storage electrode portion 157 of the polysilicon layer.

A first interlayer insulating layer 801 is formed on the gate line 121, the first and second gate electrodes 124a and 124b, and the storage electrode 133, and transmits a data signal on the first interlayer insulating layer 801. A data line 171, a linear power supply voltage electrode 172 for supplying a power supply voltage, first and second source electrodes 173a and 173b, and first and second drain electrodes 175a and 175b are formed. have. The first source electrode 173a is a part of the data line 171 and has a branch shape, and the first source region is formed through the contact hole 181 penetrating the first interlayer insulating layer 801 and the gate insulating layer 140. The contact hole 153a is connected to the second source electrode 173b and has a branch shape as part of the electrode 172 for the power supply voltage and penetrates the first interlayer insulating film 801 and the gate insulating film 140. It is connected to the second source region 153b through 184. The first drain electrode 175a is connected to the first drain region 155a and the second gate electrode 124b through the contact holes 182 and 183 penetrating the first interlayer insulating layer 801 and the gate insulating layer 140. They are in electrical contact with each other by contact. The second drain electrode 175b is connected to the second drain region 155b through a contact hole 186 penetrating through the first interlayer insulating layer 801 and the gate insulating layer 140, and the data line 171. It is made of the same material.

A second interlayer insulating layer 802 made of silicon nitride, silicon oxide, or an organic insulating material is formed on the data line 171, the power voltage electrode 172, and the first and second drain electrodes 175a and 175b. The second interlayer insulating film 802 has a contact hole 185 exposing the second drain electrode 175b.

The pixel electrode 190 connected to the second drain electrode 175b is formed on the second interlayer insulating layer 802 through the contact hole 185. The pixel electrode 190 is preferably formed of a material having excellent reflectivity such as aluminum or silver alloy. However, if necessary, the pixel electrode 190 may be formed of a transparent insulating material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 190 made of a transparent conductive material is applied to a bottom emission organic light emitting diode that displays an image in a downward direction of the display panel. The pixel electrode 190 made of an opaque conductive material is applied to top emission organic light emitting diodes that display an image in an upper direction of the display panel.

An organic insulating material is formed on the second interlayer insulating layer 802, and a partition 803 is formed to separate the organic light emitting cells. The partition 803 surrounds the pixel electrode 190 to define a region in which the organic emission layer 70 is to be filled. The partition wall 803 serves as a light shielding film by exposing and developing a photosensitive agent including a black pigment, and at the same time, the forming process can be simplified. An organic emission layer 70 is formed in an area on the pixel electrode 190 surrounded by the partition 803. The organic light emitting layer 70 is formed of an organic material emitting one of red, green, and blue light, and the red, green, and blue organic light emitting layers 70 are repeatedly arranged in sequence.

The buffer layer 804 is formed on the organic light emitting layer 70 and the partition 803. The buffer layer 804 may be omitted as necessary.

The common electrode 270 is formed on the buffer layer 804. The common electrode 270 is made of a transparent conductive material such as ITO or IZO. If the pixel electrode 190 is made of a transparent conductive material such as ITO or IZO, the common electrode 270 may be made of a metal having good reflectivity such as aluminum.

Although not shown, an auxiliary electrode may be formed of a metal having low resistance to compensate for the conductivity of the common electrode 270. The auxiliary electrode may be formed between the common electrode 270 and the buffer layer 804 or on the common electrode 270. The auxiliary electrode may be formed in a matrix shape along the partition wall 803 so as not to overlap the organic light emitting layer 70. .

The driving of such an organic light emitting panel will be briefly described.

When an on pulse is applied to the gate line 121, the first transistor is turned on, and an image signal voltage or data voltage applied through the data line 171 is transferred to the second gate electrode 124b. When the image signal voltage is applied to the second gate electrode 124b, the second transistor is turned on so that a current caused by the data voltage flows to the pixel electrode 190 and the organic light emitting layer 70, and the organic light emitting layer 70 has a specific wavelength band. Emits light. In this case, the amount of light emitted from the organic light emitting layer 70 varies according to the amount of current flowing through the second thin film transistor, thereby changing the luminance. At this time, the amount of current that the second transistor can flow is determined by the magnitude of the difference between the image signal voltage transmitted through the first transistor and the power supply voltage transmitted through the power supply voltage electrode 172.

Next, a method of manufacturing the thin film transistor array panel for the OLED display will be described with reference to FIGS. 4 to 19B and FIGS. 1 to 3.

First, as shown in FIGS. 4 to 5B, a silicon oxide or the like is deposited on the substrate 110 to form a blocking layer 111, and an amorphous silicon layer is deposited on the blocking layer 111. Subsequently, the amorphous silicon layer is patterned by a photolithography process using a photoresist pattern, and then irradiated with a laser beam through an excimer laser or a mask in which a slit is formed in a transmissive region, thereby forming the first and second thin film transistor units 150a, 150b) and crystallization to polycrystalline silicon including the sustain electrode portion 157. In this case, as described above, the crystallization process is performed after the amorphous silicon layer is patterned, and when the amorphous silicon layer is patterned, it is formed to have a partly different thickness, and in particular, the edge portion is formed to have a thickness thinner than the center part. It demonstrates concretely with reference to drawings.

6A and 6B, an amorphous silicon layer 150 is first stacked on the blocking layer on the substrate 110. Deposition of the amorphous silicon layer may be performed by low temperature chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVE), or sputtering. Subsequently, a photoresist film is applied on the amorphous silicon layer 150 to a thickness of 1 μm to 2 μm, and then irradiated with light through a photomask (not shown) to develop the photoresist pattern 52. 54).

At this time, the thickness of the developed photoresist film is different depending on the position, the photoresist film is composed of the first to third portions of which the thickness becomes smaller. The first part located in the center area A and the second part located in the edge area C are denoted by reference numerals 52 and 54, respectively, and reference numerals are not given to the third part located in the other area B. This is because the third portion has a thickness of zero, and the amorphous silicon layer 150 below is exposed. The ratio of the thickness of the first portion 52 and the second portion 54 can be adjusted according to the process conditions in the subsequent process.

As described above, there may be various methods of varying the thickness of the photoresist film according to the position, and the transparent mask and the light blocking area as well as the translucent area may be provided in the exposure mask. Yes. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness.

When the amorphous silicon layer 150 is etched using the photoresist patterns 52 and 54 as an etching mask, the edge portion is thinner than the center portion as shown in FIGS. 7A and 7B to correspond to the thickness of the photoresist patterns 52 and 54. Amorphous silicon patterns 150a ', 150b', and 157 'having a thickness may be formed.

5A and 5B, the crystallization process is performed by irradiating a laser or applying heat to crystallize the amorphous silicon patterns 150a ', 150b' and 157 'into the polycrystalline silicon patterns 150a, 150b and 157. do. At this time, the edges of the amorphous silicon patterns 150a ', 150b', and 157 'are patterned to a thin thickness and then crystallized, so that the edges of the polysilicon patterns 150a, 150b and 157 have a tapered structure having a gentle profile. The crystallization may be uniformly performed at the center and the edge, and thus the characteristics of the thin film transistor may be uniformly obtained.

Next, as shown in FIGS. 8 to 9B, the gate insulating layer 140 is deposited on the polycrystalline silicon layers 150a, 150b, and 157. Subsequently, the gate metal layer 120 is deposited, the photosensitive film is coated, exposed, and developed to form the first photoresist film pattern PR1. By etching the gate metal layer 120 using the first photoresist pattern PR1 as a mask, the second gate electrode 124b and the sustain electrode 133 are formed, and the second transistor portion 150b is exposed to the polycrystalline silicon layer. The p-type impurity ions are implanted to define the channel region 154b and form the second source region 153b and the second drain region 155b. In this case, the polycrystalline silicon layer of the second transistor unit 150a is covered and protected by the first photoresist pattern PR1 and the gate metal layer 120.

Next, as shown in FIGS. 10 to 11B, the first photoresist pattern PR1 is removed, the photoresist is newly applied, exposed and developed to form a second photoresist pattern PR2. The gate metal layer 120 is etched using the second photoresist pattern PR2 as a mask to form the first gate electrode 124a and the gate line 121, and to the exposed first polycrystalline silicon layer 150a. The n-type impurity ions are implanted to define the channel region 154a and form the first source region 153a and the first drain region 155a. At this time, the second transistor unit 150a and the storage electrode unit 157 are covered and protected by the second photosensitive film pattern PR2.

Next, as shown in FIGS. 12 to 13B, a first interlayer insulating film 801 is stacked on the gate lines 121 and 124b, the second gate electrode 124b, and the storage electrode 133, and the gate insulating film 140 and Photo-etched together, the contact holes 181, 182, 184, and 186 exposing the first source region 173a, the first drain region 175a, the second source region 173b, and the second drain region 175b, respectively. And a contact hole 183 exposing one end of the second gate electrode 124b.

Next, as shown in FIGS. 14 to 15B, the data metal layer is stacked and photo-etched to form a data line 171, a power voltage electrode 172, and first and second drain electrodes 175a and 175b. In this case, the pixel electrode 190 to be formed later may be formed together. When the pixel electrode 190 is formed of a transparent conductive material such as ITO or IZO, the pixel electrode 190 is formed through a separate photolithography process.

Next, as shown in FIGS. 16 to 17B, the second interlayer insulating layer 802 is stacked and patterned by a photolithography process using a mask to form a contact hole 185 exposing the second drain electrode 175b.

18 to 19B, the pixel electrode 190 is formed by stacking and patterning a transparent conductive material or a conductive material having a low resistance.

Next, as shown in FIGS. 1 to 3, an organic film including a black pigment is coated on the second interlayer insulating film 802 on which the pixel electrode 190 is formed, exposed, and developed to form a partition 803. The organic emission layer 70 is formed in each pixel area. At this time, the organic light emitting layer 70 usually has a multilayer structure. The organic light emitting layer 70 is formed by masking, deposition, and inkjet printing.

Next, a conductive organic material is coated on the organic emission layer 70 to form a buffer layer 804, and ITO or IZO is deposited on the buffer layer 804 to form a common electrode 270.

At this time, although not shown, the auxiliary electrode may be formed of a low resistance material such as aluminum before or after the common electrode 270 is formed. When the pixel electrode 190 is formed of a transparent conductive material, the common electrode 270 is formed of a metal having excellent reflectivity.

In the organic light emitting diode display panel according to the exemplary embodiment of the present invention and a method of manufacturing the same, the pixel electrode 190 is formed of an opaque conductive film, and the common electrode 270 is formed of a transparent conductive material to form an image. The top emission method of displaying in the upper direction of the display panel has been described.

On the other hand, in the crystallization method according to the embodiment of the present invention, when the pixel electrode 190 is formed of a transparent conductive material and the common electrode 270 is formed of an opaque conductive material, the bottom emission of displaying an image below the display is shown. The same may be applied to the thin film transistor array panel and the method of manufacturing the same. The same may be applied to the thin film transistor array panel and the manufacturing method of the liquid crystal display, and one embodiment will be described with reference to the drawings.

20 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display device including a polysilicon layer through a crystallization method according to an exemplary embodiment of the present invention, and FIG. 21 is a line XXI-XXI ′ of the thin film transistor array panel of FIG. 20. A cross-sectional view taken along the line.

20 and 21, a blocking layer 111 made of silicon oxide or silicon nitride is formed on the transparent insulating substrate 110, and n-type impurities are heavily doped on the blocking layer 111. The polysilicon layer 150 of the thin film transistor including the source region 153 and the drain region 155 and a channel region 154 disposed between them and having no impurities doped therein is formed.

Gate gates 121 elongated in one direction are formed on the gate insulation 140, and a portion of the gate lines 121 extend to overlap the channel region 154 of the polysilicon layer 150. A portion of the gate line 121 to be used is used as the gate electrode 124 of the thin film transistor. A low concentration doped region 152 is formed between the source region 153 and the channel region 154 and between the drain region 155 and the channel region 154 in which n-type impurities are lightly doped.

In addition, a storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and formed on the same layer on the gate insulating layer 140. A portion of the storage electrode line 131 overlapping the polycrystalline silicon layer 150 becomes the storage electrode 133, and the polycrystalline silicon layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157. Low concentration doped regions 152 are formed on both sides of the sustain electrode region 157, and a high concentration doped region 158 is positioned on one side of the sustain electrode region 157. One end portion of the gate line 121 may be formed wider than the width of the gate line 121 to be connected to an external circuit, and may be directly connected to an output terminal of the gate driving circuit.

The first interlayer insulating layer 801 is formed on the gate insulating layer 140 and the semiconductor layer 150 on which the gate line 121 and the storage electrode line 131 are formed. The first interlayer insulating layer 801 includes first and second contact holes 141 and 142 exposing the source region 153 and the drain region 155, respectively.

A data line 171 is formed to intersect the gate line 121 on the first interlayer insulating layer 801 to define a pixel region. A portion or the branched portion of the data line 171 is connected to the source region 153 through the first contact hole 141 and the portion connected to the source region 153 is the source electrode 173d of the thin film transistor. Used. One end of the data line 171 may be formed wider than the width of the data line 171 to be connected to an external circuit (not shown), and may be directly connected to an output terminal of the data driving circuit.

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 142.

The second interlayer insulating layer 802 is formed on the first interlayer insulating layer 801 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 143 exposing the drain electrode 175.

The pixel electrode 190 connected to the drain electrode 175d through the third contact hole 143 is formed in each pixel area on the second interlayer insulating layer 802.

 In the method of manufacturing a thin film transistor array panel for a liquid crystal display device according to an exemplary embodiment of the present invention, the polysilicon layer 150 is patterned to have a thickness smaller than the center portion as described above, and then crystallized to secure the characteristics of the thin film transistor. can do.

Meanwhile, the method of manufacturing the thin film transistor according to the exemplary embodiment of the present invention is more useful when forming a gate driving integrated circuit and a data driving integrated circuit for outputting an image signal or a scanning signal than a thin film transistor for driving a pixel. .

As described above, in the present invention, the edge portion is patterned to a thickness thinner than other portions, and then the amorphous silicon layer is crystallized, thereby stably securing the characteristics of the thin film transistor, thereby improving display characteristics of the display device.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

1 is a layout view illustrating a structure of a thin film transistor array panel for an organic light emitting display device completed through a manufacturing process according to an exemplary embodiment of the present invention.

2 and 3 are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines II-II 'and III-III',

4, 8, 10, 12, 14, 16, and 18 are layout views illustrating intermediate steps in the method of manufacturing the thin film transistor array panel of FIGS. 1 to 3.

5A and 5B are cross-sectional views taken along the line Vb-Vb 'of FIG. 4;

6A and 6B are cross-sectional views taken along the line Vb-Vb ′ in FIG. 4, illustrating a step of patterning an amorphous silicon layer before performing a crystallization process.

7A and 7B are cross-sectional views taken along the line Vb-Vb 'of FIG. 5, illustrating the next steps of FIGS. 6A and 6B.

9A and 9B are cross-sectional views taken along the line IXb-IXb 'of FIG. 8;

11A and 11B are cross-sectional views taken along the line XIb-XIb ′ of FIG. 10.

13A and 13B are cross-sectional views taken along the line XIIIb-XIIIb 'of FIG. 12;

15A and 15B are cross-sectional views taken along the line XVb-XVb 'of FIG. 14;

17A and 17B are cross-sectional views taken along the line XVIIb-XVIIb ′ in FIG. 16,

19A and 19B are cross-sectional views taken along the line XIXb-XIXb 'of FIG. 18;

20 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display device completed through a manufacturing method according to an exemplary embodiment of the present invention.

FIG. 21 is a cross-sectional view of the thin film transistor array panel of FIG. 20 taken along a line XX-XX '.

Claims (5)

Depositing amorphous silicon on top of the insulating substrate, Patterning the amorphous silicon to form an amorphous silicon pattern having a partially different thickness; Crystallizing the amorphous silicon pattern to form a semiconductor layer of polycrystalline silicon; Forming a gate insulating film covering the semiconductor layer; Forming a gate electrode on the gate insulating layer of the semiconductor layer; Implanting impurities into the semiconductor layer to form source and drain regions on both sides of the gate electrode; Forming a first interlayer insulating film covering the gate electrode; Forming source and drain electrodes electrically connected to the source and drain regions, respectively; Method of manufacturing a thin film transistor comprising a. In claim 1, Forming a second interlayer insulating film covering the source and drain electrodes; Forming a pixel electrode connected to the drain electrode Method of manufacturing a thin film transistor further comprising. In claim 1, The edge portion of the amorphous silicon is a thin film transistor manufacturing method of forming a thickness thinner than the central portion. In claim 3, The amorphous silicon pattern is formed by a photolithography process using a photoresist pattern, wherein the photoresist pattern has a partially different thickness. In claim 4, And the photosensitive film pattern is formed using a mask having a partially different transmittance.