KR101032944B1 - Mask for solidification, and method for manufacturing a thin film transistor array panel using the method - Google Patents

Abstract

In the method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, first, an amorphous silicon thin film is formed on an insulating substrate, and then crystallized by irradiating a laser beam through a chevron-shaped transmission portion disposed in the first region of the mask. Next, the amorphous silicon thin film is crystallized by irradiating a laser beam through a rhombus light shield disposed in the second region and performing recrystallization. Subsequently, the crystallized silicon thin film is patterned to form a semiconductor layer, a gate insulating film covering the semiconductor layer is formed, and then a gate electrode is formed on the gate insulating film of the semiconductor layer. Subsequently, impurities are injected into the semiconductor layer to form source and drain regions on both sides of the gate electrode, and a first interlayer insulating layer covering the gate electrode is formed, and then source and drain electrically connected to the source and drain regions, respectively. Each electrode is formed. Subsequently, a second interlayer insulating layer covering the source and drain electrodes is formed, and a pixel electrode connected to the drain electrode is formed.

Amorphous, Solid State Crystal, Grain, Rhombus, Chevron

Description

Crystallization mask and manufacturing method of thin film transistor array panel using same {MASK FOR SOLIDIFICATION, AND METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR ARRAY PANEL USING THE METHOD}

1 is a plan view showing the structure of a mask according to an embodiment of the present invention,

FIG. 2 is a view showing a grain structure of polycrystalline silicon grown in a sequential solid crystal process using a chevron mask.

3 to 4 are views illustrating a process of growing grains when performing a sequential solid crystallization process using a chevron-shaped transmission portion and a rhombus shading portion,

5 is a view showing the grain shape of the single crystal silicon completed through the sequential solid phase crystallization process using a mask according to an embodiment of the present invention,

6 is a layout view illustrating a structure of a thin film transistor array panel for an organic light emitting display device manufactured using a crystallization mask according to an exemplary embodiment of the present invention.

7 and 8 are cross-sectional views illustrating the thin film transistor array panel of FIG. 6 taken along lines VII-VII 'and VIII-VIII',

9, 11, 13, 15, 17, 19, and 21 are layout views illustrating intermediate steps in the method of manufacturing the thin film transistor array panel of FIGS. 6 to 8.

10A and 10B are cross-sectional views taken along the lines Xa-Xa 'and Xb-Xb' in FIG. 9,

12A and 12B are cross-sectional views taken along the lines XIIa-XIIa 'and XIIb-XIIb' in FIG. 11,

14A and 14B are cross-sectional views taken along lines XIVa-XIVa 'and XIVb-XIVb' in FIG. 13,

16A and 16B are cross-sectional views taken along the lines XVIa-XVIa 'and XVIb-XVIb' of FIG. 15;

18A and 18B are cross-sectional views taken along the lines XVIIIa-XVIIIa 'and XVIIIb-XVIIIb' in FIG. 17,

20A and 20B are cross-sectional views taken along the lines XXa-XXa 'and XXb-XXb' of FIG. 19.

22A and 22B are cross-sectional views taken along the lines XXIIa-XXIIa 'and XXIIb-XXIIb' of FIG. 21.

FIG. 23 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display device manufactured using a mask for crystallization according to an exemplary embodiment of the present invention.

FIG. 24 is a cross-sectional view of the thin film transistor array panel of FIG. 23 taken along a line XXIV-XXIV '.

The present invention relates to a mask for crystallization and a method for manufacturing a thin film transistor array panel using the same.

In general, the thin film transistor array panel is used as a substrate such as a liquid crystal display device or an organic EL display device having pixels having a matrix array. At this time, each pixel is provided with a thin film transistor as a switching element to selectively drive the R, G, B pixels, it is possible to implement a screen of various colors.

A liquid crystal display is an apparatus that displays an image by applying an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two display panels by using an electrode, and controlling the amount of light transmitted through the substrate by adjusting the intensity of the electric field. . In this case, a thin film transistor is used as the switching element to control the image signal transmitted to the electrode.

Organic electro-luminescence is a display device that displays an image by electrically exciting and emitting a fluorescent organic material, and includes a hole injection electrode (anode), an electron injection electrode (cathode), and an organic light emitting layer formed therebetween. When charge is injected into the organic light emitting layer, electrons and holes are paired and extinguished to emit light. Each pixel includes a driving thin film transistor and a switching transistor. In this case, the amount of current of the driving thin film transistor that supplies the current for light emission is controlled by the data voltage applied through the switching transistor, and the gate and source of the switching transistor and the gate signal line (or scan line) are disposed to cross each other. It is connected to the data signal line.

The most common thin film transistor used in such a display device uses amorphous silicon as a semiconductor layer.

Such amorphous silicon thin film transistors are approximately 0.5 占 ??. It has a mobility of about 1 cm 2 / Vsec, so that it can be used as a switching element of a liquid crystal display device, but the mobility is small and a direct drive circuit in a display device such as a liquid crystal panel or an organic electroluminescence (EL). There is an inadequate disadvantage of forming it.

Therefore, to overcome this problem, the current mobility is approximately 20 ??. A liquid crystal display device or an organic EL (electro luminescence) using a polycrystalline silicon thin film transistor using a polycrystalline silicon of about 150 cm 2 / Vsec as a semiconductor layer as a switching element or a driving element has been developed. Because of the current mobility, it is possible to implement a chip in glass in which a driving circuit is embedded in a panel for a display device.

Currently, the most widely used method of crystallizing polycrystalline silicon thin film formed on the glass substrate having low melting point is excimer laser annealing, which irradiates an excimer laser in the wavelength band absorbed directly by amorphous silicon. The amorphous silicon is melted to a temperature of about 1400 ° C. to crystallize into polycrystal. At this time, the size of the crystal grains is formed to a relatively uniform particle size of about 3,000-5,000Å, hardening time is only 30-200 ns does not damage the organic substrate. However, due to non-uniform grain boundaries, the uniformity of the electrical characteristics between the thin film transistors may be reduced or the microstructure of the particles may not be controlled.

To solve this problem, a sequential lateral solidification process has been developed that can artificially control the distribution of grain boundaries. This technique takes advantage of the fact that the grains of polycrystalline silicon grow in a direction perpendicular to the interface at the boundary between the liquid region to which the laser is irradiated and the solid region to which the laser is not irradiated. At this time, when the laser beam is passed through the transmission region (slit) of the mask to completely dissolve the amorphous silicon to form a slit-shaped liquid region, the liquid amorphous silicon is cooled and crystallized, and the crystal is a solid region without laser irradiation. From the boundary of, grows in a direction perpendicular to the interface and the growth of grains stops when they meet at the center of the liquid region. This sequential lateral solid crystal has the advantage of growing the grain size by the width of the slit.

However, in the polycrystalline silicon layer crystallized through this sequential side solid phase crystallization process, grains grow in only one direction, resulting in uneven characteristics of the thin film transistor along the channel direction. In order to solve this problem, a method of crystallizing by irradiating a laser beam several times has been developed, but there is a problem in that mass productivity is poor.

Disclosure of Invention An object of the present invention is to provide a crystallization mask capable of uniformly improving the characteristics of a thin film transistor and ensuring mass productivity, and a method of manufacturing the thin film transistor array panel using the same.

In order to solve the above problems, the present invention crystallizes the amorphous silicon layer by performing sequential lateral solid crystals using a mask having both a chevron-shaped transmission portion having a concave portion including a vertex and a circular or polygonal light shielding portion.

The mask according to an embodiment of the present invention is a crystallization mask for locally transmitting a laser beam in a crystallization process, and includes a first region and a second region, and the first region defines a liquid region of amorphous silicon and the laser beam. A transmission portion for locally transmitting the light is arranged, and a light shielding portion for locally blocking the laser beam is arranged in the second region.

In this case, it is preferable that the transmission part of the first area is formed of a polygon having a concave part including a vertex, and the light blocking part of the second area is formed of a circular or polygonal shape. The transmission part may have a chevron shape, and the light blocking part may have a rhombus shape.

In the method for manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention using such a mask, after forming an amorphous silicon thin film on an insulating substrate, a part includes a mask having a light transmitting portion and a light transmitting portion that locally transmits a laser beam. The laser beam is locally irradiated to crystallize the amorphous silicon thin film. Subsequently, the crystallized silicon thin film is patterned to form a semiconductor layer, a gate insulating film covering the semiconductor layer is formed, and a gate electrode is formed on the gate insulating film of the semiconductor layer. Next, impurities are injected into the semiconductor layer to form source and drain regions on both sides of the gate electrode, and a first interlayer insulating layer covering the gate electrode is formed. Subsequently, source and drain electrodes electrically connected to the source and drain regions are respectively formed, and then a second interlayer insulating layer covering the source and drain electrodes is formed, and a pixel electrode connected to the drain electrode is formed.

In this case, the thin film transistor array panel may use one substrate of a liquid crystal display or an organic light emitting display.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Now, a crystal mask and a method of manufacturing a thin film transistor array panel using the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the sequential lateral solidification process, a laser beam is passed through a transmission region using a mask defining a transmission region as a slit, thereby locally dissolving the amorphous silicon completely to form a liquid region in the amorphous silicon layer, and then the solid region. The grain is grown perpendicular to the interface of to crystallize the amorphous silicon into polycrystalline silicon. In the embodiment of the present invention, instead of having a slit shape defining the shape of the liquid region, the mask is formed with a chevron-shaped transmission portion having a recess including a vertex and a circular or polygonal light shielding portion. In the crystallization method using such a mask, crystallization is initially performed using a chevron-shaped transmission part, and then the mask is moved to perform crystallization using a circular or polygonal transmission part. This will be described in detail with reference to the drawings.

1 is a plan view showing the structure of a mask according to an embodiment of the present invention, Figure 2 is a view showing a grain structure of polycrystalline silicon grown in a sequential solid-phase crystallization process using a chevron-shaped mask, 3 to 4 are views illustrating a process of growing grains when performing a sequential solid crystallization process using a chevron-shaped transmission portion and a rhombus shading portion, and FIG. 5 is a sequential solid crystallization using a mask according to an embodiment of the present invention. It is a figure which shows the grain shape of the single crystal silicon completed through the process.

The crystallization mask 400 according to an embodiment of the present invention includes first and second regions 410 and 420 in which transmission parts having different shapes are arranged regularly. In this case, the transmission portion 411 is formed in a chevron shape in which the laser beam is transmitted to define the liquid phase region of the amorphous silicon, and is alternately disposed in the column direction and the row direction. In the second region 420, the light blocking portion 422 for blocking the laser beam is formed in a rhombus shape. The light blocking portions 422 of the second region 420 are alternately arranged in the column direction and the row direction. . In this case, the light blocking portion 422 of the second region 420 is disposed corresponding to the vertexes of the chevron shape among the transmission portions 411 of the first region 410.

When sequential solid phase crystallization is performed using the crystal mask 400 according to the embodiment of the present invention, the laser beam is irradiated twice to an arbitrary region. Initially, the laser beam is irradiated through the light-transmitting region 411 of the first region 410. In this case, as shown in FIG. 2, the liquid-crystalline region is formed in amorphous silicon corresponding to the transmissive portion 411. Grains grow perpendicular to the interface. At this time, one grain (a) larger than the other portion grows at the chevron-shaped recessed vertex. Subsequently, the mask 400 is moved by the widths of the first and second regions 410 and 420 so that the light blocking portion 422 of the second region 420 is crystal grains of the first region 410 as shown in FIG. 3. (a) Aligned to the center and irradiated with laser beam to recrystallize. Then, as shown in FIG. 4, one grain (a) grown from the vertex of the penetrating portion 411 of the first region 410 grows again, and in the molten liquid region through the penetrating portion 421 of the second region 420. The boundary (c) of the growing grains grows gradually, and the listing of the grains stops when they meet with neighboring grains so that the crystal grains of the crystallized silicon are formed in a rhombus shape as shown in FIG. 5.

In the sequential solid-state crystallization process using the crystallization mask according to the embodiment of the present invention can be formed of a single crystal silicon having a rhombus crystal grain, through which the characteristics of the thin film transistor can be uniformly secured even if the channel direction is different. Can be. In addition, the crystallization process of forming silicon having uniform crystal grains may be performed through two laser beam irradiations, thereby ensuring mass productivity.                     

Next, a method of manufacturing the polycrystalline silicon thin film transistor array panel including the crystallization mask and the crystallization method using the same according to the embodiment of the present invention will be described in detail.

First, a structure of a thin film transistor array panel for an organic light emitting display device will be described with reference to FIGS. 7 to 8.

A blocking layer 111 made of silicon oxide, silicon nitride, or the like is formed on the insulating substrate 110, and first and second polycrystalline silicon layers 150a and 150b are formed on the blocking layer 111, and a second layer is formed on the insulating substrate 110. The polycrystalline silicon layer 157 for capacitors is connected to the polycrystalline silicon layer 150b. The first polycrystalline silicon layer 150a includes first transistor portions 153a, 154a, and 155a, and the second polycrystalline silicon layer 150b includes second transistor portions 153b, 154b, and 155b. The source region (first source region 153a) and the drain region (first drain region, 155a) of the first transistor portions 153a, 154a, and 155a are doped with n-type impurities, and the second transistor portions 153b and 154b. The source region (second source region 153b) and the drain region (second drain region 155b) of 155b are doped with p-type impurities. At this time, depending on the driving conditions, the first source region 153a and the drain region 155a may be doped with p-type impurities, and the second source region 153b and the drain region 155b may be back-doped with n-type impurities. . Here, the first transistor portions 153a, 154a, and 155a are semiconductors of the switching thin film transistor, and the second transistor portions 153b, 154b, and 155b are semiconductors of the driving thin film transistor.

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the polycrystalline silicon layers 150a, 150b, and 157. On the gate insulating layer 140, a gate line 121 including a conductive film made of a low resistance conductive material such as aluminum or an aluminum alloy, first and second gate electrodes 124a and 124b, and a storage electrode 133 are formed. have. The first gate electrode 124a is connected to the gate line 121 to have a branch shape, and overlaps the channel portion (first channel portion 154a) of the first transistor, and the second gate electrode 124b is a gate. It is separated from the line 121 and overlaps with the channel portion (second channel portion 154b) of the second transistor. The storage electrode 133 is connected to the second gate electrode 124b and overlaps the storage electrode portion 157 of the polysilicon layer.

A first interlayer insulating layer 801 is formed on the gate line 121, the first and second gate electrodes 124a and 124b, and the storage electrode 133, and transmits a data signal on the first interlayer insulating layer 801. A data line 171, a linear power supply voltage electrode 172 for supplying a power supply voltage, first and second source electrodes 173a and 173b, and first and second drain electrodes 175a and 175b are formed. have. The first source electrode 173a is a part of the data line 171 and has a branch shape, and the first source region is formed through the contact hole 181 penetrating the first interlayer insulating layer 801 and the gate insulating layer 140. The contact hole 153a is connected to the second source electrode 173b and has a branch shape as part of the electrode 172 for the power supply voltage and penetrates the first interlayer insulating film 801 and the gate insulating film 140. It is connected to the second source region 153b through 184. The first drain electrode 175a is connected to the first drain region 155a and the second gate electrode 124b through the contact holes 182 and 183 penetrating the first interlayer insulating layer 801 and the gate insulating layer 140. They are in electrical contact with each other by contact. The second drain electrode 175b is connected to the second drain region 155b through a contact hole 186 penetrating through the first interlayer insulating layer 801 and the gate insulating layer 140, and the data line 171. It is made of the same material.

A second interlayer insulating layer 802 made of silicon nitride, silicon oxide, or an organic insulating material is formed on the data line 171, the power voltage electrode 172, and the first and second drain electrodes 175a and 175b. The second interlayer insulating film 802 has a contact hole 185 exposing the second drain electrode 175b.

The pixel electrode 190 connected to the second drain electrode 175b is formed on the second interlayer insulating layer 802 through the contact hole 185. The pixel electrode 190 is preferably formed of a material having excellent reflectivity such as aluminum or silver alloy. However, if necessary, the pixel electrode 190 may be formed of a transparent insulating material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 190 made of a transparent conductive material is applied to a bottom emission organic light emitting diode that displays an image in a downward direction of the display panel. The pixel electrode 190 made of an opaque conductive material is applied to top emission organic light emitting diodes that display an image in an upper direction of the display panel.

An organic insulating material is formed on the second interlayer insulating layer 802, and a partition 803 is formed to separate the organic light emitting cells. The partition 803 surrounds the pixel electrode 190 to define a region in which the organic emission layer 70 is to be filled. The partition wall 803 is formed by exposing and developing a photosensitive agent including a black pigment to serve as a light shielding film, and at the same time, the forming process can be simplified. An organic emission layer 70 is formed in an area on the pixel electrode 190 surrounded by the partition 803. The organic light emitting layer 70 is formed of an organic material emitting one of red, green, and blue light, and the red, green, and blue organic light emitting layers 70 are repeatedly arranged in sequence.

The buffer layer 804 is formed on the organic light emitting layer 70 and the partition 803. The buffer layer 804 may be omitted as necessary.

The common electrode 270 is formed on the buffer layer 804. The common electrode 270 is made of a transparent conductive material such as ITO or IZO. If the pixel electrode 190 is made of a transparent conductive material such as ITO or IZO, the common electrode 270 may be made of a metal having good reflectivity such as aluminum.

Although not shown, an auxiliary electrode may be formed of a metal having low resistance to compensate for the conductivity of the common electrode 270. The auxiliary electrode may be formed between the common electrode 270 and the buffer layer 804 or on the common electrode 270. The auxiliary electrode may be formed in a matrix shape along the partition wall 803 so as not to overlap the organic light emitting layer 70. .

The driving of such an organic light emitting panel will be briefly described.

When an on pulse is applied to the gate line 121, the first transistor is turned on, and an image signal voltage or data voltage applied through the data line 171 is transferred to the second gate electrode 124b. When an image signal voltage is applied to the second gate electrode 124b, the second transistor is turned on so that a current caused by the data voltage flows into the pixel electrode 190 and the organic light emitting layer 70, and the organic light emitting layer 70 has a specific wavelength band. Emits light. In this case, the amount of light emitted from the organic light emitting layer 70 varies according to the amount of current flowing through the second thin film transistor, thereby changing the luminance. At this time, the amount of current that the second transistor can flow is determined by the magnitude of the difference between the image signal voltage transmitted through the first transistor and the power supply voltage transmitted through the power supply voltage electrode 172.

Next, a method of manufacturing the thin film transistor array panel for the OLED display will be described with reference to FIGS. 9 to 22B and FIGS. 6 to 8.

First, as shown in FIGS. 9 to 10B, a silicon oxide or the like is deposited on the substrate 110 to form a blocking layer 111, and an amorphous silicon layer is deposited on the blocking layer 111. Deposition of the amorphous silicon layer may be performed by low temperature chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVE), or sputtering. Then, the amorphous silicon layer is irradiated with a laser beam to crystallize into single crystal or polycrystalline silicon. In this case, as described above, the sequential solid phase crystallization is performed using the mask of FIG. 1 to form a silicon layer having a rhombus crystal grain as shown in FIGS. 3 to 5. Therefore, the characteristics of the thin film transistor can be secured uniformly and stably, thereby improving display characteristics of the display device. In addition, single crystal silicon having uniform grains can be formed through two laser beam irradiations, thereby ensuring mass productivity.

Next, the silicon layer is photo-etched by a photolithography process using a mask to form the first and second transistor parts 150a and 150b and the storage electrode part 157.                     

Next, as shown in FIGS. 11 through 12B, the gate insulating layer 140 is deposited on the polycrystalline silicon layers 150a, 150b, and 157. Subsequently, the gate metal layer 120 is deposited, the photosensitive film is coated, exposed, and developed to form the first photoresist film pattern PR1. By etching the gate metal layer 120 using the first photoresist pattern PR1 as a mask, the second gate electrode 124b and the sustain electrode 133 are formed, and the second transistor portion 150b is exposed to the polycrystalline silicon layer. The p-type impurity ions are implanted to define the channel region 154b and form the second source region 153b and the second drain region 155b. In this case, the polycrystalline silicon layer of the second transistor unit 150a is covered and protected by the first photoresist pattern PR1 and the gate metal layer 120.

Next, as shown in FIGS. 13 to 14B, the first photoresist pattern PR1 is removed, the photoresist is newly applied, exposed to light, and developed to form a second photoresist pattern PR2. The gate metal layer 120 is etched using the second photoresist pattern PR2 as a mask to form the first gate electrode 124a and the gate line 121, and to the exposed first polycrystalline silicon layer 150a. The n-type impurity ions are implanted to define the channel region 154a and form the first source region 153a and the first drain region 155a. At this time, the second transistor unit 150a and the storage electrode unit 157 are covered and protected by the second photosensitive film pattern PR2.

Next, as shown in FIGS. 15 to 16B, a first interlayer insulating film 801 is stacked on the gate lines 121 and 124b, the second gate electrode 124b, and the storage electrode 133, and the gate insulating film 140 is formed. Photo-etched together, the contact holes 181, 182, 184, and 186 exposing the first source region 173a, the first drain region 175a, the second source region 173b, and the second drain region 175b, respectively. And a contact hole 183 exposing one end of the second gate electrode 124b.

Next, as illustrated in FIGS. 17 to 18B, the data metal layer is stacked and photo-etched to form the data line 171, the power voltage electrode 172, and the first and second drain electrodes 175a and 175b. In this case, the pixel electrode 190 to be formed later may be formed together. When the pixel electrode 190 is formed of a transparent conductive material such as ITO or IZO, the pixel electrode 190 is formed through a separate photolithography process.

Next, as shown in FIGS. 19 to 20B, the second interlayer insulating layer 802 is stacked and patterned by a photolithography process using a mask to form a contact hole 185 exposing the second drain electrode 175b.

Next, as illustrated in FIGS. 21 to 22B, the pixel electrode 190 is formed by stacking and patterning a transparent conductive material or a conductive material having a low resistance.

Next, as shown in FIGS. 6 to 8, an organic film including a black pigment is coated on the second interlayer insulating film 802 on which the pixel electrode 190 is formed, exposed, and developed to form a partition 803. The organic emission layer 70 is formed in each pixel area. At this time, the organic light emitting layer 70 usually has a multilayer structure. The organic light emitting layer 70 is formed by masking, deposition, and inkjet printing.

Next, a conductive organic material is coated on the organic emission layer 70 to form a buffer layer 804, and ITO or IZO is deposited on the buffer layer 804 to form a common electrode 270.

At this time, although not shown, the auxiliary electrode may be formed of a low resistance material such as aluminum before or after the common electrode 270 is formed. When the pixel electrode 190 is formed of a transparent conductive material, the common electrode 270 is formed of a metal having excellent reflectivity.

In the organic light emitting diode display panel according to the exemplary embodiment of the present invention and a method of manufacturing the same, the pixel electrode 190 is formed of an opaque conductive film, and the common electrode 270 is formed of a transparent conductive material to form an image. The top emission method of displaying in the upper direction of the display panel has been described.

On the other hand, in the crystallization method according to the embodiment of the present invention, when the pixel electrode 190 is formed of a transparent conductive material and the common electrode 270 is formed of an opaque conductive material, the bottom emission of displaying an image below the display is shown. The same may be applied to the thin film transistor array panel of the type and a method of manufacturing the same. The same may also be applied to the method of manufacturing a thin film transistor array panel for a liquid crystal display. One embodiment will be described with reference to the accompanying drawings.

FIG. 23 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display including a semiconductor layer of silicon formed through a crystallization method according to an exemplary embodiment of the present invention, and FIG. 24 is a cross-sectional view of the thin film transistor array panel of FIG. 23. Is a cross-sectional view taken along a line.

23 and 24, a blocking layer 111 made of silicon oxide or silicon nitride is formed on the transparent insulating substrate 110, and a high concentration of n-type impurities is doped on the blocking layer 111. The polycrystalline silicon layer 150 of the thin film transistor including the source region 153 and the drain region 155 and the channel region 154 which is not doped with impurities is formed.

Gate gates 121 elongated in one direction are formed on the gate insulation 140, and a portion of the gate lines 121 extend to overlap the channel region 154 of the polysilicon layer 150. A portion of the gate line 121 to be used is used as the gate electrode 124 of the thin film transistor. A low concentration doped region 152 is formed between the source region 153 and the channel region 154 and between the drain region 155 and the channel region 154 in which n-type impurities are lightly doped.

In addition, a storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and formed on the same layer on the gate insulating layer 140. A portion of the storage electrode line 131 overlapping the polycrystalline silicon layer 150 becomes the storage electrode 133, and the polycrystalline silicon layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157. Low concentration doped regions 152 are formed on both sides of the sustain electrode region 157, and a high concentration doped region 158 is positioned on one side of the sustain electrode region 157. One end portion of the gate line 121 may be formed wider than the width of the gate line 121 to be connected to an external circuit, and may be directly connected to an output terminal of the gate driving circuit.

The first interlayer insulating layer 801 is formed on the gate insulating layer 140 and the semiconductor layer 150 on which the gate line 121 and the storage electrode line 131 are formed. The first interlayer insulating layer 801 includes first and second contact holes 141 and 142 exposing the source region 153 and the drain region 155, respectively.                     

A data line 171 is formed to intersect the gate line 121 on the first interlayer insulating layer 801 to define a pixel region. A portion or the branched portion of the data line 171 is connected to the source region 153 through the first contact hole 141 and the portion connected to the source region 153 is the source electrode 173d of the thin film transistor. Used. One end of the data line 171 may be formed wider than the width of the data line 171 to be connected to an external circuit (not shown), and may be directly connected to an output terminal of the data driving circuit.

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 142.

The second interlayer insulating layer 802 is formed on the first interlayer insulating layer 801 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 143 exposing the drain electrode 175.

The pixel electrode 190 connected to the drain electrode 175d through the third contact hole 143 is formed in each pixel area on the second interlayer insulating layer 802.

 In the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, the polysilicon layer 150 may be crystallized as described above to secure the characteristics of the thin film transistor.

As described above, in the present invention, a thin film transistor having uniform characteristics is obtained by crystallizing amorphous silicon with silicon having rhombus crystal grains by irradiating a laser beam twice using a mask having a chevron transmission portion and a circular or polygonal difference end portion. Can be formed, and a crystallization process can be performed to ensure mass productivity. In addition, the display characteristics of the display device may be stably obtained through this.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (12)

As a crystallization mask for locally transmitting a laser beam in a crystallization process, The crystallization mask includes a first region and a second region, wherein the first region defines a liquid region of amorphous silicon and has a transmission portion for locally transmitting a laser beam, and in the second region, a laser beam. The light shield is arranged to block the The light shielding portion of the second region is positioned in the transmission portion of the first region when the first region and the second region overlap. In claim 1, The transmissive portion of the first region is formed of a polygon having a concave portion including a vertex, and the light shielding portion of the second region is a crystal mask of a circular or polygonal shape. 3. The method of claim 2, The transmissive portion of the first region is a crystal mask having a chevron shape. 3. The method of claim 2, The light shielding portion of the second region is a crystallization mask having a rhombus shape. Forming an amorphous silicon thin film on the insulating substrate, Disposing a crystallization mask including a first region and a second region on the amorphous silicon thin film; Irradiating the amorphous silicon thin film through a first region and a second region of the crystallization mask to form a polycrystalline silicon film having a first irradiation region and a second irradiation region, respectively, Moving the crystallization mask and disposing the second region of the crystallization mask on the first irradiation area; Recrystallizing the polycrystalline silicon film through the crystallization mask Including, The first region and the second region each have a transmission portion and a light shielding portion, And the crystallization mask is moved such that the light shielding portion of the second region is located in a region corresponding to the transmission portion of the first region. delete In claim 5, The transmission portion of the first region is composed of a polygon including a concave portion having a vertex, The light blocking portion of the second region is a method of manufacturing a thin film transistor array panel of circular or polygonal shape. In claim 7, The transmission part has a chevron shape manufacturing method of a thin film transistor array panel. In claim 7, The light blocking part has a rhombus shape. In claim 7, The transmissive portion of the first region comprises a single crystal sharing a vertex of the recessed portion, The light blocking portion of the second region is disposed to overlap the single crystal. In claim 5, The area of the light blocking portion of the second region is smaller than the area of the light transmitting portion of the first region. delete

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