KR100992124B1 - Panel for a display device and method for manufacturing thereof - Google Patents

Abstract

A display panel for a display device of the present invention includes an insulating substrate in which a plurality of pixel regions are defined in a matrix form, a plurality of semiconductor layers having channel portions formed in each pixel region, a gate insulating film formed on the semiconductor layer, and a gate insulating film. A plurality of gate lines each having a gate electrode overlapping the channel portion of the semiconductor layer, a first interlayer insulating layer formed on the gate line, and a source electrode formed on the first interlayer insulating layer and connected to each semiconductor layer A plurality of data lines connected to the semiconductor layer and having a drain electrode facing the source electrode around the channel portion, a second interlayer insulating layer formed on the data line, and a drain electrode formed on the second interlayer insulating layer. A pixel electrode connected to the plurality of pixel regions; The located channel portion is not located in a straight line.

Polycrystalline, ELA, Uniform

Description

Display panel for display device and manufacturing method thereof

1 is a circuit diagram schematically illustrating a structure of a display area of an organic light emitting diode display according to an exemplary embodiment of the present invention.

2 is a layout view of one pixel of a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention.

3 and 4 are cross-sectional views taken along lines III-III 'and IV-IV' of FIG. 2, respectively.

5A, 6A, 7A, 8A, and 9A are layout views at each step of manufacturing a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention.

5B and 5C are cross-sectional views taken along lines Vb-Vb 'and Vc-Vc' of FIG. 5A, respectively.

6B and 6C are cross-sectional views at the next stage of FIGS. 5B and 5C;

7B and 7C are cross-sectional views at the next stage of FIGS. 6B and 6C,

8B and 8C are cross-sectional views at the next stage of FIGS. 7B and 7C;

9B and 9C are cross-sectional views at the next stage of FIGS. 8B and 8C;

10 is a diagram schematically illustrating a correlation between a pixel pitch, a shift pitch, and a channel according to an embodiment of the present invention.

11A and 11B schematically illustrate distributions of channels in a display panel for a display device according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

70 organic light emitting layer 121, 124a, 124b: gate line

133: sustain electrode 150a, 150b: polycrystalline silicon layer

171a, 171b, 173a, 173b, 175a, 175b: data line

181, 182, 183, 184, 185, 186: contact hole

190: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel for a display device and a manufacturing method thereof, and more particularly to a display panel for a display device having a thin film transistor array using a polysilicon film as a semiconductor layer and a method for manufacturing the same.

Generally, silicon may be divided into amorphous silicon and crystalline silicon according to the crystal state. Amorphous silicon can be deposited at a low temperature to form a thin film, and is mainly used in semiconductor layers of switching elements of display devices that use glass having a low melting point as a substrate.

However, the amorphous silicon thin film has difficulty in large area of the display device due to problems such as low field effect mobility. Therefore, there is a demand for the application of polycrystalline silicon having high field effect mobility, high frequency operating characteristics, and low leakage current electrical characteristics.

The electrical properties of thin films using polycrystalline silicon are greatly influenced by the size and uniformity of the grains. That is, as the size and uniformity of the particles increase, the field effect mobility also increases. Methods of forming such polycrystalline silicon include ELA (eximer laser anneal, ELA), furnace annealing (chamber annal), and recently, sequential lateral which produces polycrystalline silicon by inducing lateral growth of silicon crystals with a laser. solidification, hereinafter referred to as SLS) technology.

The SLS technology takes advantage of the fact that silicon particles grow at the interface between liquid silicon and solid silicon in a direction perpendicular to the interface, and shift the size of the laser beam energy and the range of irradiation of the laser beam to the optical system and the mask. It is to crystallize the amorphous silicon by lateral growth of the silicon particles by a predetermined length by appropriately adjusting by using.

The ELA technique uses an excimer laser as a light source to irradiate an amorphous silicon film with laser light to polycrystallize the polysilicon while moving the irradiation area of the laser light little by little.

That is, the laser beam is aligned and irradiated so that a part of the irradiation area is overlapped with several irradiations, and the crystallization process is performed while irradiating an arbitrary portion several times.

However, when the width and the moving pitch of the excimer laser beam cannot be controlled accurately, there is a portion where the laser beam has not been irradiated the same number of times, and in most cases, the portion where the laser beam has been irradiated once more is crystallized. Depending on the stripes form.

At this time, if some of the channels of the thin film transistor are located at the once irradiated portion and the other part is located at the other portion, the characteristics of the thin film transistor are different depending on the position of the channel because the degree of crystallization of the two portions is different. In a display device using a thin film transistor as a switching element, there is a problem in that display characteristics of the display device are deteriorated.

In particular, the organic light emitting display using an organic material emitting light by a flowing current (hereinafter referred to as EL) display device is sensitive to the flow of the current in accordance with the uniformity of the polycrystal, this phenomenon is more severe.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a display panel for a display device and a method of manufacturing the same, which can ensure uniform display characteristics.

A display panel for a display device of the present invention for achieving the above object is formed on an insulating substrate in which a plurality of pixel regions are defined in a matrix form, a plurality of semiconductor layers having a channel portion formed in each pixel region, a semiconductor layer And a plurality of gate lines each having a gate electrode overlapping the channel portion of the semiconductor layer, a first interlayer insulating film formed on the gate line, and a first interlayer insulating film formed on the gate insulating film. A plurality of data lines having a source electrode connected to the semiconductor layer, a drain electrode connected to the semiconductor layer and facing the source electrode around the channel portion, a second interlayer insulating layer formed on the data line, and a second interlayer insulating layer formed on the data line And the pixel electrode connected to the drain electrode around the channel portion. And channel portions positioned in the plurality of pixel regions are not positioned in a straight line.

The organic EL layer may further include an organic EL layer formed in a predetermined region on the pixel electrode, a partition formed on the data line and the pixel electrode, and defining a region of the organic EL layer, and a common electrode formed on the organic EL layer and the partition wall. It is preferable.

In this case, the channel portions of the three pixel regions consecutively adjacent to each other may be positioned on a straight line. In addition, it is preferable that red, green, and blue organic EL be formed in each of the three pixel regions.

According to another aspect of the present invention, there is provided a method of manufacturing a display panel for a display device, the method including: forming an amorphous silicon film on a substrate, irradiating a laser beam to a predetermined region of the amorphous silicon film once, a laser beam or a substrate Repeating the irradiation step while moving to a predetermined pitch to crystallize the amorphous silicon film into the polycrystalline silicon film, patterning the polycrystalline silicon film to form a semiconductor layer, forming a gate line overlapping a portion with the semiconductor layer, and semiconductor Forming a channel, a doped source region and a drain region in the layer, forming a first interlayer insulating film covering the gate line and the semiconductor layer, defining a pixel region having a source electrode connected to the source region and intersecting the gate line A step of forming a data line and a drain electrode connected to the drain region; Forming a second interlayer insulating film covering the drain electrode, and forming a pixel electrode connected to the drain electrode, wherein the moving pitch of the laser beam or the substrate in crystallization is an integral multiple of the pitch of the pixel region or the length of the channel. Has

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a circuit diagram illustrating a structure of a display panel for an organic light emitting diode display according to an exemplary embodiment of the present invention.

As illustrated in FIG. 1, a display panel for display devices includes a plurality of gate lines G ₁ to G _{m that} are long in one direction, and are insulated from and cross the gate lines G ₁ to G _m to define a pixel area. A plurality of data lines D _1a to D _nb are formed. Transistors are connected to the gate lines G ₁ to G _m and the data lines D _1a to D _{nb of} each pixel region P, and each transistor is connected to a pixel electrode (not shown). .

The driving of the organic light emitting panel will be briefly described. When an on (on) pulse is applied to the gate line 121, the first transistor TFT1 is turned on, and thus the first data line D _1a to D _na. Is applied to the second gate electrode (not shown, see FIG. 2). When the image signal voltage is applied to the second gate electrode, the second transistor TFT2 is turned on so that a current transmitted through the second data lines D _1b to D _nb is induced with the pixel electrode (not shown in FIG. 2). It flows to the common electrode (not shown) of the opposing display panel through the light emitting layer EL. Here, the second data lines D _1b to D _nb are connected to a constant voltage power supply.

The organic light emitting layer EL emits light in a specific wavelength band when current flows. The amount of light emitted by the organic light emitting layer EL varies according to the amount of current flowing, thereby changing the luminance. In this case, the amount of current through which the second transistor TFT2 can flow is determined by the magnitude of the image signal voltage transmitted through the first transistor TFT1.

A pixel of the display panel for an organic light emitting diode display including the polysilicon thin film transistor described above will be described in more detail with reference to the accompanying drawings.

FIG. 2 is a layout view of one pixel of a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention, and FIGS. 3 and 4 are cross-sectional views taken along lines III-III 'and IV-IV' of FIG. 2, respectively. to be.

2 to 4, a blocking film 111 made of silicon oxide or the like is formed on the transparent insulating substrate 110, and the polycrystalline silicon layers 153a 154a, 155a, 153b, 154b, 155b and 157 are formed.                     

The polysilicon layers 153a, 154a, 155a, 153b, 154b, 155b, and 157 may include the first transistor portions 153a, 154a, 155a, the second transistor portions 153b, 154b, 155b, and the storage electrode portion 157. Include. The source region (first source region 153a) and the drain region (first drain region, 155a) of the first transistor portions 153a, 154a, and 155a are doped with n-type impurities, and the second transistor portions 153b and 154b. The source region (second source region 153b) and the drain region (second drain region 155b) of 155b are doped with p-type impurities. In this case, depending on the driving conditions, the first source region 153a and the drain region 155a may be doped with p-type impurities, and the second source region 153b and the drain region 155b may be doped with n-type impurities. .

In addition, channel regions 154a and 154b which are not doped with impurities are positioned between the source regions 153a and 153b and the drain regions 155a and 155b, and channels are formed between the driving regions 153a, 153b, 155a, and 155b during driving. do.

In this case, the plurality of channel regions 154a and 154b positioned in the plurality of pixels constituting the display region are not disposed in a straight line. In the crystallization process to be described later, the pixel width in the moving direction of the laser beam is an integer multiple of the moving pitch Pm of the laser beam or the substrate, and the channel region 154a is positioned at an integer multiple of the moving pitch Pm. 154b) are arranged at regular intervals. This will be described in detail with the manufacturing method described later.

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the polycrystalline silicon layers 153a, 154a, 155a, 153b, 154b, 155b, and 157. On the gate insulating layer 140, a gate line 121 made of metal such as aluminum, chromium, molybdenum, or an alloy thereof, first and second gate electrodes 124a and 124b, and a storage electrode 133 are formed.

The first gate electrode 124a is formed in the shape of a branch of the gate line 121 and overlaps the channel region (first channel region 154a) of the first transistor, and the second gate electrode 124b is a gate line ( 121 and overlap with the channel region (second channel region 154b) of the second transistor. The storage electrode 133 is connected to the second gate electrode 124b and overlaps the storage electrode portion 157 of the polysilicon layer. One end of the gate line 121 may be formed wider than the width of the gate line 121 to receive a signal transmitted from an external driving circuit (not shown).

An interlayer insulating film 801 is formed on the gate line 121, the first and second gate electrodes 124a and 124b, and the storage electrode 133, and on the interlayer insulating film 801, the first and second data lines ( 171a and 171b, first and second source electrodes 173a and 173b, and first and second drain electrodes 175a and 175b are formed.

The first source electrode 173a is connected to the first source region 153a as a branch of the first data line 171a through a contact hole 181 penetrating through the interlayer insulating film 801 and the gate insulating film 140. The second source electrode 173b is a branch of the second data line 171b and a second source region 153b through a contact hole 184 penetrating through the interlayer insulating film 801 and the gate insulating film 140. It is connected. The first drain electrode 175a is in contact with the first drain region 155a and the second gate electrode 124b through the contact holes 182 and 183 penetrating the interlayer insulating layer 801 and the gate insulating layer 140. The second drain electrode 175b is connected to the second drain region 155b through a contact hole 185 penetrating through the gate insulating layer 140 and the interlayer insulating layer 801. On the other hand, the second data line 171b overlaps the sustain electrode 133.

An interlayer insulating film 802 having a contact hole 186 exposing the second drain electrode 175b is formed on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b.

The pixel electrode 190 connected to the second drain electrode 175b is formed on the interlayer insulating layer 802 through the contact hole 186. The pixel electrode 190 is preferably formed of a material having excellent reflectivity such as aluminum. However, if necessary, the pixel electrode 190 may be formed of a transparent insulating material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A partition wall 803 made of an organic insulating material is formed on the pixel electrode 190. The partition 803 surrounds the pixel electrode 190 to define a region in which the organic emission layer 70 is to be filled.

The partition wall 803 is formed by exposing and developing a photosensitive agent including a black pigment to serve as a light shielding film, and at the same time, the forming process may be simplified. An organic emission layer 70 is formed in an area on the pixel electrode 190 surrounded by the partition 803. The organic light emitting layer 70 is formed of an organic material emitting one of red, green, and blue light, and the red, green, and blue organic light emitting layers 70 are repeatedly arranged in sequence.                     

The buffer layer 804 is formed on the organic light emitting layer 70 and the partition 803. The buffer layer 804 may be omitted as necessary.

The common electrode 270 is formed on the buffer layer 804. The common electrode 270 is made of a transparent conductive material such as ITO or IZO. If the pixel electrode 190 is made of a transparent conductive material such as ITO or IZO, the common electrode 270 is formed of a metal having good reflectivity such as aluminum.

Although not shown, an auxiliary electrode may be formed of a metal having low resistance to compensate for the conductivity of the common electrode 270. The auxiliary electrode may be formed between the common electrode 270 and the buffer layer 804 or on the common electrode 270. The auxiliary electrode may be formed in a matrix shape along the partition wall 803 so as not to overlap the organic light emitting layer 70. .

A method of manufacturing the thin film transistor array panel for the organic light emitting display device described above will be described in detail with reference to FIGS. 5A to 9C and FIGS. 2 to 4.

5A, 6A, 7A, 8A, and 9A are layout views at each stage of manufacturing a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention, and FIGS. 5B and 5C are respectively shown in FIG. 5A. Sectional views taken along lines Vb-Vb 'and Vc-Vc', FIGS. 6B and 6C are cross-sectional views at the next stage of FIGS. 5B and 5C, and FIGS. 7B and 7C are the next stages of FIGS. 6B and 6C. 8B and 8C are cross-sectional views at the next steps of FIGS. 7B and 7C, and FIGS. 9B and 9C are cross-sectional views at the next steps of FIGS. 8B and 8C.

First, as shown in FIGS. 5A to 5C, a silicon oxide or the like is deposited on the insulating substrate 110 to form a blocking film 111, and an amorphous silicon film 150 (see FIG. 10) is deposited on the blocking film 111. do. The deposition of the amorphous silicon film 150 may be performed by low temperature chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVE), or sputtering.

Subsequently, the amorphous silicon film 150 is crystallized by ELA (Excimer laser anneal: ELA) method, and then patterned by a photolithography process using a mask to form polycrystalline silicon layers 153a, 154a, 155a, 153b, 154b, and 155b. 157 (hereinafter referred to as semiconductor layer) are formed.

At this time, in order to pattern the polycrystalline silicon layers 153a, 154a, 155a, 153b, 154b, 155b, and 157 having a uniform crystal state in each of the pixels disposed on the entire surface, the pitch of the pixels or later is disposed. The channel length of the thin film transistor is such that it becomes an integral multiple with respect to the moving pitch of the laser beam or the substrate during crystallization. This will be described in detail with reference to the accompanying drawings.

FIG. 10 is a view illustrating a positional relationship between a pitch of a pixel and a pitch of a moving pitch of a substrate of a laser beam or a substrate in a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention.

In order to crystallize the amorphous silicon film 150 in the ELA process, first, a linear laser beam is irradiated once linearly to a predetermined region of the amorphous silicon film 150 along the irradiation direction. . Thereafter, the laser beam or the substrate is moved by a predetermined distance in the moving direction, and then irradiated again, and the laser beam or the substrate is repeatedly irradiated to the entire substrate to polycrystalline the amorphous silicon film.

At this time, the irradiated regions of neighboring laser beams proceed while moving the laser beam or the substrate so as to overlap each other. If the moving pitch is constant, the portions irradiated repeatedly at different irradiation times appear regularly in the polysilicon film.

The part where the number of survey changes is divided by hatching. In addition, the channel is simplified for ease of explanation. Here, Pm is a moving pitch of the substrate or laser beam, C is a channel of the thin film transistor, P is a pitch of the pixel, the horizontal direction is the moving direction of the laser beam or the substrate during repeated irradiation, and the vertical direction is the irradiation progress direction.

As shown in Fig. 10, when patterning the polycrystalline silicon film crystallized by laser beam irradiation, the pixel pitch P is determined to be an integer multiple of the moving pitch Pm, and the channel is also an integer multiple of the moving pitch Pm. Position it in the area.

In general, a plurality of pixel regions having the same size are defined on a substrate, and the shape and size of the channel of the thin film transistor formed in each pixel region are the same, and the position of the channel in each pixel region is also formed in the same manner.

Therefore, when the pixel pitch P is made to be an integer multiple of the moving pitch Pm, the polycrystalline silicon film patterned in all pixels has the same crystal state, and thus, the channel of the thin film transistor that is completed later has the same electrical characteristics.

Therefore, since characteristics such as luminance of neighboring pixels are uniform, display characteristics of the display device can be ensured uniformly.                     

Next, the case where the moving pitch Pm and the pixel pitch P are not integer multiples will be described.

11A and 11B schematically show the distribution of channel C throughout the substrate. Reference numeral S denotes a reference point for explaining the positional relationship of the channels.

First, as shown in FIG. 11A, the reference points S1 and S2 of the channels C of the first and second transistor units are not disposed on a straight line.

Looking at the distribution of the channel with respect to the hatched portion, the reference points (S1, S2) of the channel (C) located in the hatched portion is patterned so as not to be located in a straight line. That is, the reference points S1 and S2 of the channel C are randomly located in the hatched portion and the area beyond the hatched portion.

Alternatively, as shown in FIG. 11B, each channel C located in at least three pixel areas may be formed in one group and positioned on the same straight line. In this case, each pixel corresponding to three pixel areas in which the red, green, and blue organic emission layers are formed may be determined as a group.

Such irregular arrangement of channels prevents the channel C formed on the polycrystalline silicon film having the same electrical and physical properties from being arranged in a uniform manner so that streaks and the like do not appear in the pixel areas located in the same row or column. do.

Next, as shown in FIGS. 6A to 6C, the gate insulating layer 140 is deposited on the semiconductor layers 150a, 150b, and 157. Subsequently, metal is deposited to form a gate metal film 120. Thereafter, a photoresist film is coated on the gate metal film 120, followed by exposure and development to form a first photoresist film pattern PR1.                     

Next, the gate metal film 120 is etched using the first photoresist film pattern PR1 as a mask to form the second gate electrode 124b and the sustain electrode 133, and the exposed second transistor unit 150b. The p-type impurity ions are implanted into the semiconductor layer to form the second source region 153b, the second drain region 155b, and the second channel region 154b that is not doped with impurities. In this case, the semiconductor layer of the first transistor unit 150a is covered and protected by the first photoresist film pattern PR1 and the gate metal film 120. At this time, since the sustain electrode part 157 overlaps with the data line 171b formed later, the sustain electrode part 157 is protected by the photosensitive film so that impurities are not doped.

Next, as shown in FIGS. 7A to 7C, the first photoresist pattern PR1 is removed, the photoresist is newly coated, exposed and developed to form a second photoresist pattern PR2. The gate metal film 120 is etched using the second photoresist pattern PR2 as a mask to form the first gate electrode 124a and the gate line 121, and the exposed first transistor portion 150a semiconductor layer. The n-type impurity ions are implanted into the first source region 153a, the first drain region 155a, and the first channel region 154a which is not doped with impurities. At this time, the second transistor units 153b, 154b, and 155b and the storage electrode unit 157 are covered and protected by the second photosensitive film pattern PR2.

Next, as shown in FIGS. 8A to 8C, the interlayer insulating layer 801 is stacked on the gate lines 121, 124a, 124b, and 133, and the interlayer insulating layer 801 and the gate insulating layer 140 are formed by a photolithography process. The interlayer and the contact holes 181, 182, 184, and 185 exposing the first source region 173a, the first drain region 175a, the second source region 173b, and the second drain region 175b, respectively, by etching. The insulating layer 801 is etched to form a contact hole 183 exposing one end of the second gate electrode 124b.

Next, the data metal film is stacked and the data lines 171a, 171b, 173a and 173b and the drain electrodes 175a and 175b are formed by a photolithography process.

9A to 9C, an interlayer insulating film 802 is formed on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b, and then the interlayer insulating film 802 is formed by a photolithography process. By etching, the contact hole 186 exposing the second drain electrode 175b is formed.

Subsequently, a metal having excellent reflectivity such as aluminum is deposited on the interlayer insulating layer 802 and patterned by a photolithography process to form a pixel electrode 190 connected to the second drain electrode 175b through the contact hole 186.

Next, as shown in FIGS. 2 to 4, an organic film including a black pigment is coated on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b, and exposed and developed to partition the barrier rib 803. The organic light emitting layer 70 is formed in each pixel area. At this time, the organic light emitting layer 70 usually has a multilayer structure. The organic light emitting layer 70 is deposited after masking, or formed by inkjet printing or the like.

Next, a conductive organic material is coated on the organic emission layer 70 to form a buffer layer 804, and ITO or IZO is deposited on the buffer layer 804 to form a common electrode 270.

At this time, although not shown, the auxiliary electrode may be formed of a low resistance material such as aluminum before or after the common electrode 270 is formed. In addition, when the pixel electrode 190 is formed of a transparent conductive material, the common electrode 270 is formed using a metal having excellent reflectivity.

As described above, a display panel having uniform display characteristics can be formed by irregularly arranging a plurality of channels or arranging them to be an integer multiple of a moving distance of a laser beam or a substrate.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary and can be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. There will be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

As described above, when the amorphous silicon film is polycrystallized, the pixel pitch is designed to be an integer multiple of the moving direction of the laser beam or the substrate, and the channels having the same electrical characteristics can be formed by arranging the channels so that they are integral multiples. .

In addition, a display panel for a display device capable of securing high-quality display characteristics without streaks or the like by arranging channels irregularly in a polycrystalline silicon film having a different number of overlapping irradiations can be obtained.

Claims (6)

In a display panel for a display device including a plurality of pixels, Each pixel includes a thin film transistor and a pixel electrode connected to the thin film transistor, respectively. The pixels are formed in groups of three, The channels of the thin film transistors included in the groups are located in a straight line. A display panel for a display device, wherein channels of the thin film transistors of neighboring groups are not disposed in a straight line. Insulation board, A plurality of gate lines formed on the insulating substrate, A plurality of data lines intersecting the gate lines, A plurality of thin film transistors connected to the gate lines and the data lines, respectively; A plurality of pixel electrodes connected to the thin film transistors, respectively Including, The semiconductor layer of the thin film transistor is crystallized by laser annealing, And the semiconductor layer is disposed at a position that is an integer multiple of a moving interval of the laser beam during the laser annealing. Insulation board, A plurality of gate lines formed on the insulating substrate, A plurality of data lines intersecting the gate lines, A plurality of thin film transistors connected to the gate lines and the data lines, respectively; A plurality of pixel electrodes connected to the thin film transistors, respectively Including, The semiconductor layer of the thin film transistor is crystallized by laser annealing, And the semiconductor layer is randomly distributed on the insulating substrate. In claim 1, The pixel further includes an organic EL layer formed on the pixel electrode, a common electrode formed on the organic EL layer, And each of the groups comprises red, green, and blue organic EL layers. Forming an amorphous silicon film on the substrate, Irradiating a laser beam linearly on a predetermined region of the amorphous silicon film once, Repeating the irradiation step while moving the laser beam or the substrate at a predetermined pitch to crystallize the amorphous silicon film into a polycrystalline silicon film, Patterning the polycrystalline silicon film to form a semiconductor layer, Forming a gate line partially overlapping the semiconductor layer;  Forming a channel, a doped source region and a drain region in the semiconductor layer, Forming a first interlayer insulating layer covering the gate line and the semiconductor layer; Forming a data line having a source electrode connected to the source region and crossing the gate line to define a pixel region, and a drain electrode connected to the drain region; Forming a second interlayer insulating film covering the data line and the drain electrode; Forming a pixel electrode connected to the drain electrode; And a moving pitch of the laser beam or the substrate in the crystallization has an integral multiple with respect to the pitch of the pixel region or the length of the channel. In claim 1, The channel is formed in a semiconductor crystallized using a laser beam, The straight line is a display panel for a display device, the irradiation direction of the laser beam.

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