CN117238928A - Low-temperature polysilicon thin film transistor, manufacturing method thereof and liquid crystal display - Google Patents
Low-temperature polysilicon thin film transistor, manufacturing method thereof and liquid crystal display Download PDFInfo
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- CN117238928A CN117238928A CN202311326968.9A CN202311326968A CN117238928A CN 117238928 A CN117238928 A CN 117238928A CN 202311326968 A CN202311326968 A CN 202311326968A CN 117238928 A CN117238928 A CN 117238928A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 43
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 40
- 239000010409 thin film Substances 0.000 title claims abstract description 30
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000009194 climbing Effects 0.000 claims abstract description 14
- 239000010408 film Substances 0.000 claims description 72
- 238000005530 etching Methods 0.000 claims description 50
- 238000000034 method Methods 0.000 claims description 16
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000007788 liquid Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 208000010392 Bone Fractures Diseases 0.000 description 2
- 206010017076 Fracture Diseases 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Abstract
The invention discloses a manufacturing method of a low-temperature polysilicon thin film transistor, which comprises the following steps: step 100: forming a shading pattern on a substrate, wherein the outer edge of the shading pattern is provided with a step slope structure; step 200: forming a bottom insulating layer on the light shielding pattern and the substrate; step 300: and forming an active layer on the bottom insulating layer, wherein the active layer is provided with a step climbing structure corresponding to the step slope structure. The manufacturing method can reduce the risk of breakage of the climbing structure of the active layer while meeting the thickness of the shading pattern. The invention also discloses a low-temperature polysilicon thin film transistor and a liquid crystal display.
Description
Technical Field
The invention relates to the technical field of display, in particular to a low-temperature polysilicon thin film transistor, a manufacturing method thereof and a liquid crystal display.
Background
Low temperature polysilicon (Low Temperature Poly-silicon, LTPS for short) is a new generation of thin film transistor liquid crystal display (TFT-LCD) manufacturing process. The amorphous silicon is processed by high-energy laser to change the internal structure from amorphous to polycrystal at low temperature below 600 deg.C. After such treatment, the conductivity of one glass is improved by several hundred times, and then a display panel is manufactured using it as a substrate. Because the conductivity of the material is greatly improved, the gaps (lines) between the pixels can be greatly reduced and narrowed, thereby directly bringing the advantages of increased screen resolution (increased pixel density) and increased screen brightness. The LTPS has the advantages of high response speed, high brightness, high resolution, low power consumption and the like, and can be widely used in display equipment because the carrier mobility of the transistor is over one hundred times higher than that of the amorphous silicon technology.
The low-temperature polysilicon active layer is easy to generate carriers after being irradiated by light, so that the light leakage is formed. In order to solve the technical problem, a light shielding layer is manufactured below the low-temperature polysilicon active layer in the prior art to shield backlight of the liquid crystal display, so that carriers generated by the irradiation of the low-temperature polysilicon active layer by the backlight are avoided. The chinese patent CN201610272425.7 discloses a method for manufacturing a semiconductor device, which comprises: providing a semiconductor substrate, wherein the semiconductor substrate corresponds to an active region, a drain region and a channel region between the source region and the drain region; forming a light shielding layer on the semiconductor substrate corresponding to the source region, the drain region and the channel region; forming an insulating layer on the light shielding layer; an amorphous silicon layer is formed on the insulating layer, and the amorphous silicon layer is crystallized to be converted into polycrystalline silicon.
However, since the outer edge of the light shielding layer will form a slope structure after etching, the low-temperature polysilicon active layer needs to be routed to the light shielding layer from the outside of the light shielding layer through the climbing structure, the climbing structure of the low-temperature polysilicon active layer is easy to break, and the larger the thickness of the light shielding pattern is, the larger the risk of breakage of the low-temperature polysilicon active layer in the climbing structure is, and as the requirement of the liquid crystal display on high-brightness backlight is increased, the thickness of the light shielding layer has to be increased, so as to meet the light shielding requirement under the high-brightness backlight, and further improve the risk of breakage of the low-temperature polysilicon active layer in the climbing structure.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides a manufacturing method of a low-temperature polysilicon thin film transistor, which can reduce the risk of breakage of a climbing structure of an active layer while meeting the thickness of a shading pattern.
The invention also provides a low-temperature polysilicon thin film transistor and a liquid crystal display.
The technical problems to be solved by the invention are realized by the following technical scheme:
the manufacturing method of the low-temperature polysilicon thin film transistor comprises the following steps:
step 100: forming a shading pattern on a substrate, wherein the outer edge of the shading pattern is provided with a step slope structure;
step 200: forming a bottom insulating layer on the light shielding pattern and the substrate;
step 300: and forming an active layer on the bottom insulating layer, wherein the active layer is provided with a step climbing structure corresponding to the step slope structure.
Further, in step 100, the step of forming a light shielding pattern on a substrate is as follows:
step 110: sequentially forming n shading film layers on the substrate, wherein n is more than or equal to 2;
step 120: etching the shading film layers to different degrees so that the shading film layers form layers with different sizes, and the nth layer of layer is smaller than the (n-1) th layer of layer.
Further, each layer of the image layer comprises a bottom surface and a top surface which are opposite, and the bottom surface of the nth layer of the image layer is smaller than the top surface of the n-1 layer of the image layer.
Further, the top surface of the n-1 layer comprises a central area and a peripheral area, the peripheral area surrounds the outer edge of the central area, the n-1 layer is stacked on the central area of the top surface of the n-1 layer, and the peripheral area of the top surface of the n-1 layer is exposed from the outer edge of the n-1 layer.
Further, each light shielding film layer has different etching rates for the same etching solution, and the etching rate of the n-th light shielding film layer is greater than the etching rate of the n-1-th light shielding film layer, and in step 120, the n-th light shielding film layer is etched simultaneously by using the same etching solution.
Further, each shading film layer is a metal film layer with different film qualities.
Further, the active layer is polysilicon.
Further, the manufacturing method further comprises the following steps:
step 400: ion implantation is carried out on the active layer so as to form a gate doping region and a source-drain doping region on the active layer;
step 500: forming a gate insulating layer on the active layer;
step 600: forming a gate electrode corresponding to the gate doping region on the gate insulating layer;
step 700: forming a top insulating layer on the grid electrode and the grid insulating layer, and forming source and drain conducting holes on the grid insulating layer and the positions of the top insulating layer corresponding to the source and drain doped regions;
step 800: and forming a source drain electrode corresponding to the source drain doping region on the top insulating layer, wherein the source drain electrode is conducted with the source drain doping region through the source drain conducting hole.
A low-temperature polysilicon thin film transistor is manufactured by the method.
A liquid crystal display comprises a backlight module and a liquid crystal panel, wherein the liquid crystal panel is arranged on the light emitting side of the backlight module; the liquid crystal panel comprises the low-temperature polysilicon thin film transistor.
The invention has the following beneficial effects: this patent is through will the light shading pattern's outer edge preparation becomes ladder slope structure, ladder slope structure refers to the layering appears in the outer edge of light shading pattern, and the area of last layer is less than the area of next layer for the outer edge of last layer is compared the outer edge of next layer and is inwards contracted to form the ladder, and the top surface of each layer is less than the bottom surface simultaneously, makes the outer edge side of each layer form the slope, the active layer passes through ladder climbing structure follow the bottom insulation layer warp ladder slope structure department walks the line to when on the light shading pattern, can pass through slope inclined plane and the ladder plane of each layer in proper order at intervals, can all turn into the level after every climbs the slope of one layer and walk the line, then climb the slope of next layer again under the equal circumstances of thickness and slope angle of light shading pattern, the active layer can have lower fracture risk owing to need not to keep at all the time in climbing state.
Drawings
Fig. 1 is a block diagram of steps of a method for fabricating a low temperature polysilicon thin film transistor according to the present invention.
Fig. 2 is a schematic stacking diagram of a low-temperature polysilicon thin film transistor according to the present invention.
Fig. 3 is a schematic stacking diagram of a light shielding pattern in a low temperature polysilicon thin film transistor according to the present invention.
Fig. 4 is a schematic diagram of stacking a low-temperature polysilicon thin film transistor before etching.
Fig. 5 is a block diagram illustrating steps of another method for fabricating a low temperature polysilicon thin film transistor according to the present invention.
Fig. 6 is a schematic stacking diagram of another low-temperature polysilicon thin film transistor according to the present invention.
Description of the embodiments
The present invention is described in detail below with reference to the drawings and the embodiments, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
In the description of the present invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate describing the present invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", or a third "may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," "disposed," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, or can be communicated between two elements or the interaction relationship between the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Example 1
As shown in fig. 1 and 2, a method for manufacturing a low-temperature polysilicon thin film transistor includes the following steps:
step 100: forming a light shielding pattern 2 on a substrate 1, the outer edge of the light shielding pattern 2 having a stepped slope structure 21;
step 200: forming a bottom insulating layer 3 on the light shielding pattern 2 and the substrate 1;
step 300: an active layer 4 is formed on the bottom insulating layer 3, the active layer 4 having a stepped ramp structure 41 corresponding to the stepped ramp structure 21.
This patent is through will the outer edge preparation of shading pattern 2 becomes ladder slope structure 21, as shown in fig. 3, ladder slope structure 21 refers to the layering appears in the outer edge of shading pattern 2, and the area of last layer is less than the area of next layer, make the outer edge of last layer contract in the outer edge of next layer and form the ladder, the top surface of each layer is less than the bottom surface simultaneously, make the outer edge side of each layer form the slope, active layer 4 passes through ladder climbing structure 41 follow bottom insulating layer 3 through ladder slope structure 21 department walk the line to on the shading pattern 2, can pass through slope inclined plane 23 and the ladder plane 24 of each layer in proper order at intervals, all can turn to the level after the slope of every last layer and walk the line, then climb the slope of next layer again, under the thickness and the slope angle of shading pattern 2 are the same the circumstances all need not to keep all the time in the climbing state, active layer 4 can have lower fracture risk.
The top and bottom surfaces of each layer of the stepped slope structure 21 formed on the outer edge of the light shielding pattern 2 are parallel to the substrate 1, at least to the surface of the substrate 1 facing the bottom insulating layer 3.
The thickness of the bottom insulating layer 3 is the same throughout so that the stepped slope structure 21 of the light shielding pattern 2 may be embodied on the bottom insulating layer 3.
Preferably, in step 100, the step of forming the light shielding pattern 2 on the substrate 1 is as follows:
step 110: as shown in FIG. 4, n light shielding film layers 22', n.gtoreq.2 are sequentially formed on the substrate 1;
step 120: the light shielding film layers 22 'are etched to different degrees, so that the light shielding film layers 22' form different layers 22, and the nth layer 22 is smaller than the (n-1) th layer 22.
The etched light shielding film layers 22 'in the light shielding film layers 22 are formed into the layers 22, because the areas of the upper layer 22 are smaller than the areas of the lower layer 22, the outer edge of the upper layer 22 is shrunk inwards to form a step compared with the outer edge of the lower layer 22, and because the top surface of each light shielding film layer 22' is etched firstly and then etched when being etched, the etching time of the top surface of each light shielding film layer is longer than the etching time of the ground, the sizes of the etched top surface and the etched bottom surface are different, the area of the top surface of each layer 22 is smaller than the area of the bottom surface of each layer, and the side surface of the outer edge of each layer 22 forms a slope with a narrower upper part and a wider lower part, so that the step slope structure 21 is finally formed.
In this embodiment, the number of the light shielding layers 22' is three, and in a specific implementation, the actual number of the light shielding layers 22' may be determined according to the thickness of the light shielding pattern 2 and the thickness of each light shielding layer 22 '.
Each layer 22 includes a bottom surface and a top surface opposite to each other, and the bottom surface of the n layer 22 is smaller than the top surface of the n-1 layer 22, so that the outer edge of the bottom surface of the n layer 22 is retracted compared with the outer edge of the top surface of the n-1 layer 22, and the peripheral area of the top surface of the n-1 layer 22 is exposed, thereby forming the step plane 24.
The top surface of the n-1 layer 22 includes a central region and a peripheral region, the peripheral region surrounding the outer edge of the central region, the n-1 layer 22 overlies the central region of the top surface of the n-1 layer 22, and the peripheral region of the top surface of the n-1 layer 22 is exposed from the outer edge of the n-1 layer 22 to form a stepped plane 24.
Preferably, each light shielding film layer 22 'has different etching rates for the same etching solution, and the etching rate of the n-th light shielding film layer 22' is greater than the etching rate of the n-1-th light shielding film layer 22', and in step 120, the steps of etching each light shielding film layer 22' to different degrees are as follows:
step 121: forming a photoresist layer on the n-th light shielding film layer 22';
step 122: exposing and developing the photoresist layer to form the photoresist layer on the photoresist pattern 5 corresponding to the shading pattern 2;
step 123: etching the n light shielding film layers 22' simultaneously by using the same etching liquid to penetrate the photoresist patterns 5;
step 124: and stripping the remaining photoresist pattern 5.
In the etching process of step 123, the n-th light-shielding film layer 22 'is contacted with the etching solution, in the etching process of the n-th light-shielding film layer 22', the top surface of the n-th light-shielding film layer 22 'is contacted with the etching solution, and the bottom surface of the n-th light-shielding film layer 22' is contacted with the etching solution, the etching time of the top surface of the n-th light-shielding film layer 22 'is longer than the etching time of the bottom surface of the n-th light-shielding film layer, so that the outer edge side surface of the n-th light-shielding film layer 22' is etched into a slope of the n-th image layer 22; when the n-1-th light shielding film layer 22 'is etched to a certain extent, the n-1-th light shielding film layer 22' is exposed from the n-th light shielding film layer 22 'and then contacts with the etching liquid, and in the same way, in the etching process of the n-1-th light shielding film layer 22', the top surface of the n-1-th light shielding film layer 22 'contacts with the etching liquid first, the bottom surface of the n-1-th light shielding film layer 22' contacts with the etching liquid later, and the etching time of the top surface of the n-1-th light shielding film layer 22 'is longer than the etching time of the bottom surface, so that the outer edge side surface of the n-1-th light shielding film layer 22' can be etched to form a slope of the n-1-th image layer 22; in the etching process of the n-1-th light-shielding film layer 22', the n-th light-shielding film layer 22' is still corroded by the etching solution, and the etching rate of the etching solution on the n-th light-shielding film layer 22 'is greater than that of the etching solution on the n-1-th light-shielding film layer 22', so that discontinuous etching marks appear on the outer edge side surface between the n-th light-shielding film layer 22 'and the n-1-th light-shielding film layer 22', specifically, the newly exposed peripheral area of the n-1-th light-shielding film layer 22 is not corroded by the etching solution, but remains to form on the step plane 24, and finally the step slope structure 21 is formed.
Each light shielding film layer 22' is a metal film layer with different film qualities, and the same etching liquid is used for etching by utilizing the metal film layers with different etching rates of different film qualities, so that the etching efficiency is improved, and the step slope structure 21 is finally formed.
The metal film layers are made of the same metal, and can be, but not limited to, molybdenum film layers, aluminum film layers, titanium film layers and the like, and the film quality difference means that the metal film layers have different compactness and porosity degree by adjusting process parameters when forming films, and the etching rate can be influenced.
In the present embodiment, the thickness of each light shielding film layer 22' is the same to better grasp the overall etching time, but in a specific implementation, the actual thickness of each light shielding film layer 22' may be determined according to the thickness of the light shielding pattern 2 and the number of layers of the light shielding film layer 22 '.
In step 300, the active layer 4 is polysilicon, and the active layer 4 is formed on the bottom insulating layer 3, and the step of forming the active layer 4 with the step climbing structure 41 corresponding to the step slope structure is as follows:
step 310: forming an amorphous silicon thin film on the bottom insulating layer 3;
step 320: using excimer laser as heat source, the laser beam generates laser beam with energy evenly distributed after passing through projection system, and projects the laser beam onto the amorphous silicon film of the bottom insulating layer 3, so that the amorphous silicon film is converted into polysilicon film after absorbing the energy of excimer laser;
step 330: and etching the polycrystalline silicon film to form the active layer 4 with the shape of a silicon island.
When the amorphous silicon thin film is uniformly formed on the bottom insulating layer 3 by means of magnetron sputtering or vapor deposition, etc., the amorphous silicon thin film naturally forms the stepped ramp structure 41 at a position corresponding to the stepped ramp structure 21. Of course, the bottom insulating layer 3 is also required to be uniformly formed on the light shielding pattern 2 and the substrate 1 by magnetron sputtering or vapor deposition, etc. to conduct the stepped ramp structure 21 of the light shielding pattern 2 onto the surface thereof.
The excimer laser process in step 320 is performed at a temperature below 600 c, and thus the formed polysilicon film is referred to as a low temperature polysilicon film.
Example two
As an optimization scheme of the first embodiment, in this embodiment, as shown in fig. 5 and 6, the manufacturing method further includes the following steps:
step 400: ion implantation is carried out on the active layer 4 so as to form a gate doping region and a source-drain doping region on the active layer 4;
step 500: forming a gate insulating layer 6 on the active layer 4;
step 600: forming a gate electrode 7 corresponding to the gate doping region on the gate insulating layer 6;
step 700: forming a top insulating layer 8 on the grid electrode 7 and the grid insulating layer 6, and forming source and drain conducting holes on positions of the grid insulating layer 6 and the top insulating layer 8 corresponding to the source and drain doping regions;
step 800: source and drain electrodes 10a and 10b corresponding to the source and drain doped regions are formed on the top insulating layer 8, and the source and drain electrodes 10a and 10b are conducted with the source and drain doped regions through the source and drain conducting holes.
Example III
A low temperature polysilicon thin film transistor fabricated by the method of embodiment one or embodiment two.
Example IV
A liquid crystal display comprises a backlight module and a liquid crystal panel, wherein the liquid crystal panel is arranged on the light emitting side of the backlight module; the liquid crystal panel comprises the low-temperature polysilicon thin film transistor according to the third embodiment.
Finally, it should be noted that the foregoing embodiments are merely for illustrating the technical solution of the embodiments of the present invention and are not intended to limit the embodiments of the present invention, and although the embodiments of the present invention have been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the embodiments of the present invention may be modified or replaced with the same, and the modified or replaced technical solution may not deviate from the scope of the technical solution of the embodiments of the present invention.
Claims (10)
1. The manufacturing method of the low-temperature polysilicon thin film transistor is characterized by comprising the following steps:
step 100: forming a shading pattern on a substrate, wherein the outer edge of the shading pattern is provided with a step slope structure;
step 200: forming a bottom insulating layer on the light shielding pattern and the substrate;
step 300: and forming an active layer on the bottom insulating layer, wherein the active layer is provided with a step climbing structure corresponding to the step slope structure.
2. The method of manufacturing a low temperature polysilicon thin film transistor according to claim 1, wherein in step 100, the step of forming a light shielding pattern on the substrate is as follows:
step 110: sequentially forming n shading film layers on the substrate, wherein n is more than or equal to 2;
step 120: etching the shading film layers to different degrees so that the shading film layers form layers with different sizes, and the nth layer of layer is smaller than the (n-1) th layer of layer.
3. The method of claim 2, wherein each of the layers includes opposite bottom and top surfaces, and the bottom surface of the n-th layer is smaller than the top surface of the n-1-th layer.
4. The method of fabricating a low temperature polysilicon thin film transistor according to claim 2, wherein the top surface of the n-1 layer comprises a central region and a peripheral region, the peripheral region surrounds an outer edge of the central region, the n-1 layer is stacked on the central region of the top surface of the n-1 layer, and the peripheral region of the top surface of the n-1 layer is exposed from the outer edge of the n-1 layer.
5. The method according to claim 2, wherein each of the light shielding layers has different etching rates for the same etching solution, and the etching rate of the n-th light shielding layer is greater than the etching rate of the n-1-th light shielding layer, and in step 120, the n-th light shielding layers are etched simultaneously using the same etching solution.
6. The method of manufacturing a low temperature polysilicon thin film transistor according to claim 2, wherein each light shielding film layer is a metal film layer with different film qualities.
7. The method of claim 1, wherein the active layer is polysilicon.
8. The method of fabricating a low temperature polysilicon thin film transistor according to claim 1, further comprising the steps of:
step 400: ion implantation is carried out on the active layer so as to form a gate doping region and a source-drain doping region on the active layer;
step 500: forming a gate insulating layer on the active layer;
step 600: forming a gate electrode corresponding to the gate doping region on the gate insulating layer;
step 700: forming a top insulating layer on the grid electrode and the grid insulating layer, and forming source and drain conducting holes on the grid insulating layer and the positions of the top insulating layer corresponding to the source and drain doped regions;
step 800: and forming a source drain electrode corresponding to the source drain doping region on the top insulating layer, wherein the source drain electrode is conducted with the source drain doping region through the source drain conducting hole.
9. A low temperature polysilicon thin film transistor fabricated by the method of any of claims 1-8.
10. The liquid crystal display is characterized by comprising a backlight module and a liquid crystal panel, wherein the liquid crystal panel is arranged on the light emitting side of the backlight module; the liquid crystal panel comprising the low temperature polysilicon thin film transistor of claim 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311326968.9A CN117238928A (en) | 2023-10-13 | 2023-10-13 | Low-temperature polysilicon thin film transistor, manufacturing method thereof and liquid crystal display |
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| CN202311326968.9A CN117238928A (en) | 2023-10-13 | 2023-10-13 | Low-temperature polysilicon thin film transistor, manufacturing method thereof and liquid crystal display |
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