KR101018749B1 - Mask for solidification, and method for manufacturing a thin film transistor array panel using the mask - Google Patents

Abstract

In the method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, first, an amorphous silicon thin film is formed on an insulating substrate, and then a laser beam is locally irradiated using a mask having a light shielding part of a different shape to form an amorphous silicon thin film. Crystallize. Subsequently, the crystallized silicon thin film is patterned to form a semiconductor layer, a gate insulating film covering the semiconductor layer is formed, and then a gate electrode is formed on the gate insulating film of the semiconductor layer. Subsequently, impurities are injected into the semiconductor layer to form source and drain regions on both sides of the gate electrode, and a first interlayer insulating layer covering the gate electrode is formed, and then source and drain electrically connected to the source and drain regions, respectively. Each electrode is formed. Subsequently, a second interlayer insulating layer covering the source and drain electrodes is formed, and a pixel electrode connected to the drain electrode is formed.

Amorphous, solid crystal, mask, laser, dot

Description

Crystallization mask, manufacturing method of thin film transistor array panel {MASK FOR SOLIDIFICATION, AND METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR ARRAY PANEL USING THE MASK}

1 and 2 are diagrams showing the grain structure of polycrystalline silicon grown in a sequential solid-state crystal process using a mask having a triangular and circular light shielding portion,

3 is a plan view showing a structure of a mask for crystallization according to an embodiment of the present invention;

4 to 6 are views showing in detail the process of growing grains in the sequential solid phase crystallization process according to an embodiment of the present invention,

FIG. 7 is a layout view illustrating a structure of a thin film transistor array panel for an organic light emitting display device manufactured using a crystallization mask according to an exemplary embodiment of the present invention.

8 and 9 are cross-sectional views of the thin film transistor array panel of FIG. 7 taken along lines VIII-VIII 'and IX-IX',

10, 12, 14, 16, 18, 20, and 22 are layout views illustrating intermediate steps in the method of manufacturing the thin film transistor array panel of FIGS. 7 to 9.

11A and 11B are cross-sectional views taken along the lines XIa-XIa 'and XIb-XIb' of FIG. 10.                 

13A and 13B are cross-sectional views taken along the lines XIIIa-XIIIa 'and XIIIb-XIIIb' in FIG. 12,

15A and 15B are cross-sectional views taken along lines XVa-XVa 'and XVb-XVb' in FIG. 14,

17A and 17B are cross-sectional views taken along the lines XVIIa-XVIIa 'and XVIIb-XVIIb' in FIG. 16,

19A and 19B are cross-sectional views taken along the lines XIXa-XIXa 'and XIXb-XIXb' in FIG. 18,

21A and 21B are cross-sectional views taken along the lines XXIa-XXIa 'and XXIb-XXIb' in FIG. 20,

23A and 23B are cross-sectional views taken along the lines XXIIIa-XXIIIa 'and XXIIIb-XXIIIb' of FIG. 22.

24 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display device manufactured using a crystallization mask according to an embodiment of the present invention.

FIG. 25 is a cross-sectional view of the thin film transistor array panel of FIG. 24 taken along a line XXV-XXV '.

The present invention relates to a crystallization mask, a crystallization method using the same, and a method of manufacturing a thin film transistor array panel including the same.

In general, the thin film transistor array panel is used as a substrate such as a liquid crystal display device or an organic EL display device having pixels having a matrix array. At this time, each pixel is provided with a thin film transistor as a switching element to selectively drive the R, G, B pixels, it is possible to implement a screen of various colors.

A liquid crystal display is an apparatus that displays an image by applying an electric field to a liquid crystal material having an anisotropic dielectric constant injected between two display panels by using an electrode, and controlling the amount of light transmitted through the substrate by adjusting the intensity of the electric field. . In this case, a thin film transistor is used as the switching element to control the image signal transmitted to the electrode.

Organic electro-luminescence is a display device that displays an image by electrically exciting and emitting a fluorescent organic material, and includes a hole injection electrode (anode), an electron injection electrode (cathode), and an organic light emitting layer formed therebetween. When charge is injected into the organic light emitting layer, electrons and holes are paired and extinguished to emit light. Each pixel includes a driving thin film transistor and a switching transistor. In this case, the amount of current of the driving thin film transistor that supplies the current for light emission is controlled by the data voltage applied through the switching transistor, and the gate and source of the switching transistor and the gate signal line (or scan line) are disposed to cross each other. It is connected to the data signal line.

The most common thin film transistor used in such a display device uses amorphous silicon as a semiconductor layer.                         

Such amorphous silicon thin film transistors are approximately 0.5 占 ??. It has a mobility of about 1 cm 2 / Vsec, so that it can be used as a switching element of a liquid crystal display device, but the mobility is small and a direct drive circuit in a display device such as a liquid crystal panel or an organic electroluminescence (EL). There is an inadequate disadvantage of forming it.

Therefore, to overcome this problem, the current mobility is approximately 20 ??. A liquid crystal display device or an organic EL (electro luminescence) using a polycrystalline silicon thin film transistor using a polycrystalline silicon of about 150 cm 2 / Vsec as a semiconductor layer as a switching element or a driving element has been developed. Because of the current mobility, it is possible to implement a chip in glass in which a driving circuit is embedded in a panel for a display device.

Currently, the most widely used method of crystallizing polycrystalline silicon thin film formed on the glass substrate having low melting point is excimer laser annealing, which irradiates an excimer laser in the wavelength band absorbed directly by amorphous silicon. The amorphous silicon is melted to a temperature of about 1400 ° C. to crystallize into polycrystal. At this time, the size of the crystal grains is formed to a relatively uniform particle size of about 3,000-5,000Å, hardening time is only 30-200 ns does not damage the organic substrate. However, due to non-uniform grain boundaries, the uniformity of the electrical characteristics between the thin film transistors may be reduced or the microstructure of the particles may not be controlled.

To solve this problem, a sequential lateral solidification process has been developed that can artificially control the distribution of grain boundaries. This technique takes advantage of the fact that the grains of polycrystalline silicon grow in a direction perpendicular to the interface at the boundary between the liquid region to which the laser is irradiated and the solid region to which the laser is not irradiated. At this time, when the laser beam is passed through the transmission region (slit) of the mask to completely dissolve the amorphous silicon to form a slit-shaped liquid region, the liquid amorphous silicon is cooled and crystallized, and the crystal is a solid region without laser irradiation. From the boundary of, grows in a direction perpendicular to the interface and the growth of grains stops when they meet at the center of the liquid region. This sequential lateral solid crystal has the advantage of growing the grain size by the width of the slit.

However, in the polycrystalline silicon layer crystallized through such a sequential side solid phase crystallization process, grains grow in only one direction, and thus the characteristics of the thin film transistor appear uneven along the channel direction of the thin film transistor. In order to solve this problem, a method of crystallizing by irradiating a laser beam several times has been developed, but there is a problem in that mass productivity is poor.

Disclosure of Invention An object of the present invention is to provide a crystallization mask capable of uniformly improving the characteristics of a thin film transistor and ensuring mass productivity, and a method of manufacturing the thin film transistor array panel using the same.

In order to solve the above problems, the present invention crystallizes the amorphous silicon layer by performing sequential side solid phase crystals using a mask having circular and polygonal light shields.

The crystallization mask according to an embodiment of the present invention is a crystallization mask having a light shielding portion that locally transmits a laser beam in a crystallization process, and includes a first region and a second region, and shields the first and second regions. Wealth consists of different shapes.

In this case, the light blocking portion of the first region is formed of a polygon having a vertex, the light blocking portion of the second region is preferably formed of a circular shape, the light blocking portion of the second region is disposed corresponding to the vertex of the light blocking portion of the first region, It is preferable that the light shielding part of 1 area | region is triangular shape.

In the method for manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention using such a crystallization mask, first, an amorphous silicon thin film is formed on an insulating substrate, and then a laser beam is locally formed using a mask having a different light shielding portion. Irradiation crystallizes the amorphous silicon thin film. Subsequently, the crystallized silicon thin film is patterned to form a semiconductor layer, a gate insulating film covering the semiconductor layer is formed, and then a gate electrode is formed on the gate insulating film of the semiconductor layer. Subsequently, impurities are injected into the semiconductor layer to form source and drain regions on both sides of the gate electrode, and a first interlayer insulating layer covering the gate electrode is formed, and then source and drain electrically connected to the source and drain regions, respectively. Each electrode is formed. Subsequently, a second interlayer insulating layer covering the source and drain electrodes is formed, and a pixel electrode connected to the drain electrode is formed.                     

The thin film transistor array panel may be used as a substrate of a liquid crystal display or a substrate of an organic light emitting diode display. In the crystallization step, a laser beam is irradiated through a light blocking part of a first region to an arbitrary region of an amorphous silicon thin film to perform crystallization. Next, recrystallization is performed by irradiating a laser beam through the light shielding portion of the second region.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Now, a crystal mask and a method of manufacturing a thin film transistor array panel using the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In the sequential lateral solidification process, a laser beam is passed through a transmission region using a mask defining a transmission region as a slit, thereby locally dissolving the amorphous silicon completely to form a liquid region in the amorphous silicon layer, and then the solid region. The grain is grown perpendicular to the interface of to crystallize the amorphous silicon into polycrystalline silicon. In the embodiment of the present invention, instead of defining the shape of the liquid region in a slit shape, the shape of the solid region is defined along the shape of the light shielding portion formed in the mask, and the crystal grains of the polycrystalline silicon are grown perpendicular to the interface of the solid region. . In this case, initially, crystallization is performed by using a polygonal light shield, and then, the mask is moved to perform crystallization by using a circular light shield. This will be described in detail with reference to the drawings.

1 and 2 illustrate a grain structure of polycrystalline silicon grown in a sequential solid-state crystal process using a mask having a triangular and circular light shield, and FIG. 3 shows a structure of a crystal mask according to an embodiment of the present invention. 4 to 6 are views illustrating a process of growing grains in a sequential solid phase crystallization process according to an embodiment of the present invention.

In the sequential lateral solid-state determination process according to the embodiment of the present invention, the laser beam is locally irradiated using a mask having polygonal, for example, triangular or circular light shielding portions to form a solid region on an amorphous silicon layer corresponding to the light shielding portion. It forms and forms the liquid phase area | region except solid state area | region. At this time, as shown in FIGS. 1 and 2, grains of polycrystalline silicon grow in a direction perpendicular to the interface at the boundary between the liquid region to which the laser is irradiated and the solid state region to which the laser is not irradiated, and the amorphous silicon layer is the polycrystalline silicon layer. Crystallize. Thus, as shown in FIGS. 1 and 2, the crystal grains grow radially around the light shielding portion, where one grain grows at a portion corresponding to a vertex, and grains grow larger than another portion. In an embodiment of the present invention, the amorphous silicon is crystallized using such a point, and the crystallization mask according to the embodiment of the present invention includes two regions in which light blocking parts are regularly arranged, and one region of the polygon has a vertex. The light shielding portions are arranged regularly, and the circular light shielding portions are regularly arranged in the other regions.

As an example, as shown in FIG. 3, the crystal mask 400 according to the embodiment of the present invention includes first and second regions 410 and 420 in which light blocking portions having different shapes are arranged. At this time, a triangular light shielding portion 411 is regularly arranged in the transmission region 412 through which the laser beam is transmitted, and the right triangle and the inverted triangle are alternately arranged in the column direction. . A circular light blocking portion 421 is regularly arranged in the transmission region 422 through which the laser beam is transmitted. The light blocking portion 421 of the second region 421 is formed of a first light. It is disposed corresponding to a triangle vertex of the light blocking portion 411 of the region 410. Here, the light blocking portions 411 of the two rows of the first regions 410 facing each other are alternately arranged by an interval of 2a, and the light blocking portions 411 of the two rows of the first regions 410 facing each other are arranged. ) Are alternately arranged by a interval, and the light blocking portions 411 of the first region 410 are arranged at intervals b in the column direction, and are spaced apart by intervals b in units of two columns.

When sequential solid phase crystallization is performed using the crystal mask 400 according to the embodiment of the present invention, the laser beam is irradiated twice to an arbitrary region. Initially, the laser beam is irradiated through the first region 410, and at this time, as shown in FIG. 4, grains grow vertically with respect to the light blocking portion 411 and correspond to a vertex of the light blocking portion 411. There is one grain growing larger than the other part. Subsequently, the mask 400 is moved by the width of the first and second regions 410 and 420 so that the light blocking portion 421 of the second region 420 is different from the first region 410 as shown in FIG. 5. Recrystallization is performed by irradiating a laser beam aligned so as to correspond to crystal grains grown from vertices of the light portion 411. Then, as shown in FIG. 6, one grain grown from the vertex of the light blocking portion 411 of the first region 410 grows again, and the crystal grain growing through the light blocking portion 421 of the second region 420 is grown. Stopped at the center of the light blocking portion 421 of the second region 420 adjacent to each other, the crystal grains of the crystallized silicon are formed in a hexagonal shape.

Therefore, in the sequential solid-state crystallization process using the crystallization mask according to the embodiment of the present invention, it is possible to form a hexagonal silicon, through which the characteristics of the thin film transistor can be uniformly secured even if the channel direction is different. In addition, through two laser beam irradiation, the crystallization process of forming silicon having uniform grains in all directions can be performed, thereby ensuring mass productivity.

Next, a method of manufacturing the polycrystalline silicon thin film transistor array panel including the crystallization mask and the crystallization method using the same according to the embodiment of the present invention will be described in detail.

First, the structure of the thin film transistor array panel for an organic light emitting display device will be described with reference to FIGS. 7 to 9.

A blocking layer 111 made of silicon oxide, silicon nitride, or the like is formed on the insulating substrate 110, and first and second polycrystalline silicon layers 150a and 150b are formed on the blocking layer 111, and a second layer is formed on the insulating substrate 110. The polycrystalline silicon layer 157 for capacitors is connected to the polycrystalline silicon layer 150b. The first polycrystalline silicon layer 150a includes first transistor portions 153a, 154a, and 155a, and the second polycrystalline silicon layer 150b includes second transistor portions 153b, 154b, and 155b. The source region (first source region 153a) and the drain region (first drain region, 155a) of the first transistor portions 153a, 154a, and 155a are doped with n-type impurities, and the second transistor portions 153b and 154b. The source region (second source region 153b) and the drain region (second drain region 155b) of 155b are doped with p-type impurities. At this time, depending on the driving conditions, the first source region 153a and the drain region 155a may be doped with p-type impurities, and the second source region 153b and the drain region 155b may be back-doped with n-type impurities. . Here, the first transistor portions 153a, 154a, and 155a are semiconductors of the switching thin film transistor, and the second transistor portions 153b, 154b, and 155b are semiconductors of the driving thin film transistor.

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the polycrystalline silicon layers 150a, 150b, and 157. On the gate insulating layer 140, a gate line 121 including a conductive film made of a low resistance conductive material such as aluminum or an aluminum alloy, first and second gate electrodes 124a and 124b, and a storage electrode 133 are formed. have. The first gate electrode 124a is connected to the gate line 121 to have a branch shape, and overlaps the channel portion (first channel portion 154a) of the first transistor, and the second gate electrode 124b is a gate. It is separated from the line 121 and overlaps with the channel portion (second channel portion 154b) of the second transistor. The storage electrode 133 is connected to the second gate electrode 124b and overlaps the storage electrode portion 157 of the polysilicon layer.

A first interlayer insulating layer 801 is formed on the gate line 121, the first and second gate electrodes 124a and 124b, and the storage electrode 133, and transmits a data signal on the first interlayer insulating layer 801. A data line 171, a linear power supply voltage electrode 172 for supplying a power supply voltage, first and second source electrodes 173a and 173b, and first and second drain electrodes 175a and 175b are formed. have. The first source electrode 173a is a part of the data line 171 and has a branch shape, and the first source region is formed through the contact hole 181 penetrating the first interlayer insulating layer 801 and the gate insulating layer 140. The contact hole 153a is connected to the second source electrode 173b and has a branch shape as part of the electrode 172 for the power supply voltage and penetrates the first interlayer insulating film 801 and the gate insulating film 140. It is connected to the second source region 153b through 184. The first drain electrode 175a is connected to the first drain region 155a and the second gate electrode 124b through the contact holes 182 and 183 penetrating the first interlayer insulating layer 801 and the gate insulating layer 140. They are in electrical contact with each other by contact. The second drain electrode 175b is connected to the second drain region 155b through a contact hole 186 penetrating through the first interlayer insulating layer 801 and the gate insulating layer 140, and the data line 171. It is made of the same material.

A second interlayer insulating layer 802 made of silicon nitride, silicon oxide, or an organic insulating material is formed on the data line 171, the power voltage electrode 172, and the first and second drain electrodes 175a and 175b. The second interlayer insulating film 802 has a contact hole 185 exposing the second drain electrode 175b.

The pixel electrode 190 connected to the second drain electrode 175b is formed on the second interlayer insulating layer 802 through the contact hole 185. The pixel electrode 190 is preferably formed of a material having excellent reflectivity such as aluminum or silver alloy. However, if necessary, the pixel electrode 190 may be formed of a transparent insulating material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 190 made of a transparent conductive material is applied to a bottom emission organic light emitting diode that displays an image in a downward direction of the display panel. The pixel electrode 190 made of an opaque conductive material is applied to top emission organic light emitting diodes that display an image in an upper direction of the display panel.

An organic insulating material is formed on the second interlayer insulating layer 802, and a partition 803 is formed to separate the organic light emitting cells. The partition 803 surrounds the pixel electrode 190 to define a region in which the organic emission layer 70 is to be filled. The partition wall 803 serves as a light shielding film by exposing and developing a photosensitive agent including a black pigment, and at the same time, the forming process can be simplified. An organic emission layer 70 is formed in an area on the pixel electrode 190 surrounded by the partition 803. The organic light emitting layer 70 is formed of an organic material emitting one of red, green, and blue light, and the red, green, and blue organic light emitting layers 70 are repeatedly arranged in sequence.

The buffer layer 804 is formed on the organic light emitting layer 70 and the partition 803. The buffer layer 804 may be omitted as necessary.

The common electrode 270 is formed on the buffer layer 804. The common electrode 270 is made of a transparent conductive material such as ITO or IZO. If the pixel electrode 190 is made of a transparent conductive material such as ITO or IZO, the common electrode 270 may be made of a metal having good reflectivity such as aluminum.

Although not shown, an auxiliary electrode may be formed of a metal having low resistance to compensate for the conductivity of the common electrode 270. The auxiliary electrode may be formed between the common electrode 270 and the buffer layer 804 or on the common electrode 270. The auxiliary electrode may be formed in a matrix shape along the partition wall 803 so as not to overlap the organic light emitting layer 70. .

The driving of such an organic light emitting panel will be briefly described.

When an on pulse is applied to the gate line 121, the first transistor is turned on, and an image signal voltage or data voltage applied through the data line 171 is transferred to the second gate electrode 124b. When the image signal voltage is applied to the second gate electrode 124b, the second transistor is turned on so that a current caused by the data voltage flows to the pixel electrode 190 and the organic light emitting layer 70, and the organic light emitting layer 70 has a specific wavelength band. Emits light. In this case, the amount of light emitted from the organic light emitting layer 70 varies according to the amount of current flowing through the second thin film transistor, thereby changing the luminance. At this time, the amount of current that the second transistor can flow is determined by the magnitude of the difference between the image signal voltage transmitted through the first transistor and the power supply voltage transmitted through the power supply voltage electrode 172.

Next, a method of manufacturing the thin film transistor array panel for the OLED display will be described with reference to FIGS. 10 to 23B and FIGS. 7 to 9.

First, as shown in FIGS. 10 to 11B, a silicon oxide or the like is deposited on the substrate 110 to form a blocking layer 111, and an amorphous silicon layer is deposited on the blocking layer 111. Deposition of the amorphous silicon layer may be performed by low temperature chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVE), or sputtering. Then, the amorphous silicon layer is irradiated with a laser beam to crystallize into single crystal or polycrystalline silicon. At this time, as described above, the sequential solid phase crystallization is performed using the mask of FIG. 3 to form a silicon layer having hexagonal crystal grains as shown in FIGS. 4 to 6. Therefore, the characteristics of the thin film transistors can be secured uniformly and stably in all directions, thereby improving display characteristics of the display device. In addition, silicon having a uniform crystal grain can be formed through two laser beam irradiations, thereby ensuring mass productivity.

Next, the silicon layer is photo-etched by a photolithography process using a mask to form the first and second transistor parts 150a and 150b and the storage electrode part 157.

Next, as shown in FIGS. 12 to 13B, the gate insulating layer 140 is deposited on the polycrystalline silicon layers 150a, 150b, and 157. Subsequently, the gate metal layer 120 is deposited, the photosensitive film is coated, exposed, and developed to form the first photoresist film pattern PR1. By etching the gate metal layer 120 using the first photoresist pattern PR1 as a mask, the second gate electrode 124b and the sustain electrode 133 are formed, and the second transistor portion 150b is exposed to the polycrystalline silicon layer. The p-type impurity ions are implanted to define the channel region 154b and form the second source region 153b and the second drain region 155b. In this case, the polycrystalline silicon layer of the second transistor unit 150a is covered and protected by the first photoresist pattern PR1 and the gate metal layer 120.

Next, as shown in FIGS. 14 to 15B, the first photoresist pattern PR1 is removed, the photoresist is newly applied, exposed to light, and developed to form a second photoresist pattern PR2. The gate metal layer 120 is etched using the second photoresist pattern PR2 as a mask to form the first gate electrode 124a and the gate line 121, and to the exposed first polycrystalline silicon layer 150a. The n-type impurity ions are implanted to define the channel region 154a and form the first source region 153a and the first drain region 155a. At this time, the second transistor unit 150a and the storage electrode unit 157 are covered and protected by the second photosensitive film pattern PR2.

Next, as shown in FIGS. 16 to 17B, a first interlayer insulating film 801 is stacked on the gate lines 121 and 124b, the second gate electrode 124b, and the storage electrode 133, and the gate insulating film 140 is formed. Photo-etched together, the contact holes 181, 182, 184, and 186 exposing the first source region 173a, the first drain region 175a, the second source region 173b, and the second drain region 175b, respectively. And a contact hole 183 exposing one end of the second gate electrode 124b.

Next, as shown in FIGS. 18 through 19B, the data metal layer is stacked and photo-etched to form the data line 171, the power voltage electrode 172, and the first and second drain electrodes 175a and 175b. In this case, the pixel electrode 190 to be formed later may be formed together. When the pixel electrode 190 is formed of a transparent conductive material such as ITO or IZO, the pixel electrode 190 is formed through a separate photolithography process.

Next, as shown in FIGS. 20 to 21B, the second interlayer insulating layer 802 is stacked and patterned by a photolithography process using a mask to form a contact hole 185 exposing the second drain electrode 175b.

Subsequently, as shown in FIGS. 22 to 23B, the pixel electrode 190 is formed by stacking and patterning a transparent conductive material or a conductive material having low resistance.                     

Next, as shown in FIGS. 7 to 9, an organic film including a black pigment is coated on the second interlayer insulating film 802 on which the pixel electrode 190 is formed, and exposed and developed to form a partition 803. The organic emission layer 70 is formed in each pixel area. At this time, the organic light emitting layer 70 usually has a multilayer structure. The organic light emitting layer 70 is formed by masking, deposition, and inkjet printing.

Next, a conductive organic material is coated on the organic emission layer 70 to form a buffer layer 804, and ITO or IZO is deposited on the buffer layer 804 to form a common electrode 270.

At this time, although not shown, the auxiliary electrode may be formed of a low resistance material such as aluminum before or after the common electrode 270 is formed. When the pixel electrode 190 is formed of a transparent conductive material, the common electrode 270 is formed of a metal having excellent reflectivity.

In the organic light emitting diode display panel according to the exemplary embodiment of the present invention and a method of manufacturing the same, the pixel electrode 190 is formed of an opaque conductive film, and the common electrode 270 is formed of a transparent conductive material to form an image. The top emission method of displaying in the upper direction of the display panel has been described.

On the other hand, in the crystallization method according to the embodiment of the present invention, when the pixel electrode 190 is formed of a transparent conductive material and the common electrode 270 is formed of an opaque conductive material, the bottom emission of displaying an image below the display is shown. The same may be applied to the thin film transistor array panel of the type and a method of manufacturing the same. The same may also be applied to the method of manufacturing a thin film transistor array panel for a liquid crystal display. One embodiment will be described with reference to the accompanying drawings.                     

FIG. 24 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display including a semiconductor layer of silicon formed through a crystallization method according to an exemplary embodiment of the present invention, and FIG. 25 is a cross-sectional view of the thin film transistor array panel of FIG. 24. Is a cross-sectional view taken along a line.

As shown in FIGS. 24 and 25, a blocking layer 111 made of silicon oxide or silicon nitride is formed on the transparent insulating substrate 110, and n-type impurities are heavily doped on the blocking layer 111. The polysilicon layer 150 of the thin film transistor including the source region 153 and the drain region 155 and a channel region 154 disposed between them and having no impurities doped therein is formed.

Gate gates 121 elongated in one direction are formed on the gate insulation 140, and a portion of the gate lines 121 extend to overlap the channel region 154 of the polysilicon layer 150. A portion of the gate line 121 to be used is used as the gate electrode 124 of the thin film transistor. A low concentration doped region 152 is formed between the source region 153 and the channel region 154 and between the drain region 155 and the channel region 154 in which n-type impurities are lightly doped.

In addition, a storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and formed on the same layer on the gate insulating layer 140. A portion of the storage electrode line 131 overlapping the polycrystalline silicon layer 150 becomes the storage electrode 133, and the polycrystalline silicon layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157. Low concentration doped regions 152 are formed on both sides of the sustain electrode region 157, and a high concentration doped region 158 is positioned on one side of the sustain electrode region 157. One end portion of the gate line 121 may be formed wider than the width of the gate line 121 to be connected to an external circuit, and may be directly connected to an output terminal of the gate driving circuit.

The first interlayer insulating layer 801 is formed on the gate insulating layer 140 and the semiconductor layer 150 on which the gate line 121 and the storage electrode line 131 are formed. The first interlayer insulating layer 801 includes first and second contact holes 141 and 142 exposing the source region 153 and the drain region 155, respectively.

A data line 171 is formed to intersect the gate line 121 on the first interlayer insulating layer 801 to define a pixel region. A portion or the branched portion of the data line 171 is connected to the source region 153 through the first contact hole 141 and the portion connected to the source region 153 is the source electrode 173d of the thin film transistor. Used. One end of the data line 171 may be formed wider than the width of the data line 171 to be connected to an external circuit (not shown), and may be directly connected to an output terminal of the data driving circuit.

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 142.

The second interlayer insulating layer 802 is formed on the first interlayer insulating layer 801 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 143 exposing the drain electrode 175.

A pixel electrode 190 connected to the drain electrode 175d through the third contact hole 143 is formed in each pixel area on the second interlayer insulating layer 802.

 In the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, the polysilicon layer 150 may be crystallized as described above to secure the characteristics of the thin film transistor.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, in the present invention, a thin film transistor having uniform characteristics in all directions is obtained by crystallizing amorphous silicon with silicon having hexagonal crystal grains by irradiating a laser beam using a mask having a polygonal block and a circular block. It can form and the crystallization process which can ensure mass productivity can be performed. In addition, the display characteristics of the display device may be stably obtained through this.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (11)

A crystallization mask for performing crystallization using a laser beam, The crystallization mask includes a first region and a second region each having a plurality of light blocking portions having different shapes to locally block the laser beam, The light blocking portion of the first region is formed of a polygon having a vertex, and when the light blocking portion of the second region is connected in a straight line, the crystal mask having the same shape as the polygon. In claim 1, The light shielding portion of the second region is disposed to correspond to the vertex of the polygon. In claim 2, The light shielding portion of the second region has a circular crystallization mask. 4. The method of claim 3, The light shielding portion of the first region is a crystallization mask. Forming an amorphous silicon thin film on the insulating substrate, Crystallizing the amorphous silicon thin film by locally irradiating a laser beam using a mask including a first region and a second region each having a different light blocking portion; Including, The crystallizing may include first crystallizing an amorphous silicon thin film using the first region of the mask, Secondary crystallizing the amorphous silicon thin film using the second region of the mask, The first region is composed of a polygon having a vertex, and the second crystallization is crystallization method after arranging to correspond to the light-shielding portion of the second region corresponding to the vertex of the polygon. In claim 5, And the light blocking portion of the second region is circular. delete In claim 6, The light blocking portion of the first region is a crystallization method. In claim 8, The thin film crystallized by the mask has a honeycomb pattern formed by stacking a plurality of hexagons. delete delete

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