WO2001082275A1

WO2001082275A1 - Display panel substrate, method for producing the same, thin-film forming apparatus used therefor

Info

Publication number: WO2001082275A1
Application number: PCT/JP2001/003485
Authority: WO
Inventors: Munehiro Shibuya; Masaharu Terauchi; Yukihiro Morita; Masashi Goto; Mikihiko Nishitani
Original assignee: Matsushita Electric Industrial Co., Ltd.
Priority date: 2000-04-21
Filing date: 2001-04-23
Publication date: 2001-11-01
Also published as: TW501279B

Abstract

A method for producing a substrate for a display panel at low cost with good productivity by using a few masks. The method for producing a substrate for a display panel including an insulating substrate and elements fabricated by processing conductive layers, insulating layers, and semiconductor layers the three formed on the insulating substrate, wherein the lowermost conductive layer out of the conductive layers is processed into a wiring element, the other conductive layers are electrically connected to the lowermost conductive layer, the conductive layers, insulating layers, or semiconductor layers are selectively formed in predetermined regions by using, e.g., a shield selectively covering the periphery of the insulating substrate.

Description

Description Display panel substrate, method of manufacturing the same, and thin film forming apparatus used for the same

The present invention relates to a display panel substrate, and more particularly, to an active matrix using a thin film transistor (TFT) as a switching element. The present invention relates to an improvement in a method for stably manufacturing a liquid crystal display panel at a lower cost. Background technology

Liquid crystal display panel; Active matrix that controls the dimming or light emission of each pixel in a display panel such as an organic light emitting display panel. It is expected that a display panel of a rectangular type will be excellent in the vividness of a displayed image and the like. Thin film transistors (TFTs) with excellent response speed are widely used as switching elements for controlling pixels.

A TFT can be obtained by forming a conductive layer, a semiconductor layer, and an insulating layer on an insulating substrate and processing these into respective components. In the manufacture of a display panel substrate, the conductive layer is added to a gate electrode of a TFT and also to a scanning signal line (gate line) integrated therewith. In addition, the conductive layer provided further applies a voltage to a source-drain electrode, an image signal line (source line), and a dimming layer (or light emitting layer). It is processed into electrodes and the like. Similarly, the semiconductor layer is formed on the entire surface of the substrate, and then processed into a shape as a channel layer (active layer) of each TFT. In addition, a semiconductor layer containing impurities as a contact layer is It is formed separately or is formed by injecting impurities into a predetermined region of a semiconductor layer formed in advance.

One way to respond to the increasing demand for lower prices is to simplify the process. In particular, reducing the number of photomasks used for etching each layer is a useful measure.

An example of a conventional method for manufacturing a liquid crystal display panel will be described.

A conductive layer is formed on the surface of an insulating substrate 1 made of glass or the like, and then the conductive layer is processed, as shown in FIG. 30 to form a TFT gate as a switching element. A storage capacitor electrode for forming a storage capacitor between the remote electrode 2 a and a counter electrode (not shown) disposed on a counter substrate (not shown)

2b, forming a scanning signal line (not shown) and the like. Here, the conductive layer is made of, for example, chromium, aluminum, tantalum, titanium, silver, copper, palladium, or a multilayer film thereof. The conductive layer is formed by sputtering, for example, and then processed into a predetermined pattern by etching using a photo resist as a mask.

Then, an insulating layer 3 made of silicon nitride, silicon oxide, or the like is formed so as to cover them, and a semiconductor layer made of amorphous silicon and impurities are formed on the upper surface thereof. A low-resistance semiconductor layer into which (for example, phosphorus) is implanted is formed. These are continuously formed, for example, by plasma CVD. The formed semiconductor layer is processed into a predetermined pattern by etching as shown in FIG. 31a. At this time, the high-resistance semiconductor layer disposed below is processed into an active layer 4a of the TFT. It is not always necessary to remove the portion of the semiconductor layer serving as the auxiliary capacitance as shown in the figure. In order to suppress the electrification of the scanning signal line 2.c in the area where the terminal for connecting the scanning signal line 2c to the external circuit is to be formed and the various wiring elements in the post-process, a source drain Connect to the wiring The area to be sought is covered with an insulating layer 3 as shown in FIGS. 31b and 31c.

To cover them evenly, a conductive layer made of chromium, anoreminium, tantalum, titanium, silver, copper, palladium, etc. is formed, for example, by sputtering rings. As shown in FIG. 32, an image signal line (not shown) and an image signal line are formed on the conductive layer by etching using a photo resist as a mask. It is processed into the source electrode wiring 7a, the drain electrode wiring 7b, etc. connected to the wires (not shown). The low-resistance semiconductor layer into which the impurities are implanted is processed into a pair of contact layers 5b. At this time, a part of the semiconductor layer 4a as an active layer to which no impurity is added is simultaneously etched.

As shown in FIG. 33a, an insulating layer 6 made of, for example, silicon nitride is formed to protect the exposed source electrode wiring 7a and the like, and then the insulating layer 6 is removed by etching. A contact window 6a is formed in a region above the drain electrode wiring 7b. At this time, as shown in FIGS. 33b and 33c, various wirings on the scanning signal line 2c in a region where a terminal for connecting to an external circuit is to be formed and in a later process Contact windows 6 are also formed in the insulating layer 6 disposed on the scanning signal line 2c in the region where connection with the source / drain wiring is to be performed in order to suppress element charging. b and 6 c are formed.

Then, to cover these, for example, indium tin oxide (I

A conductive layer made of a transparent conductor such as TO) is formed by sputtering or the like, and wiring elements such as pixel electrodes 8a are formed by photoetching. . In forming the conductive layer, the contact windows 6a, 6b and 6c are filled with a conductive material, so that the source electrode wiring 7a and the scanning signal line 2c are electrically connected. Between the two due to static electricity The potential difference of is eliminated.

By processing this conductive layer into a predetermined shape, a pixel electrode 8a electrically connected to the drain electrode wiring 7b is formed as shown in FIG. 34a. At this time, as shown in FIG. 34b, a connection portion for preventing static electricity is formed between the drain wiring 8 and the scanning signal line 2c. Further, as shown in FIG. 34c, the conductive material filled in the contact window 6c is removed by etching to form a connection terminal where the scanning signal line 2c is exposed. You.

A display panel substrate (array substrate) provided with various wirings, TFTs, pixel electrodes, etc. can be obtained.

According to the above method, five masks are used. The number of masks used in manufacturing affects the cost of manufacturing semiconductor elements and display panel substrates. That is, in order to provide a semiconductor element or a display panel substrate at lower cost, it is useful to reduce the number of masks used. Therefore, a method of processing a plurality of objects into different angles using a single photoresist by using a so-called gray-tone exposure technique is also used. . This makes it possible to manufacture with four masks. For example, the insulating layer, the semiconductor layer, and the low-resistance semiconductor layer are simultaneously processed.

As shown in Fig. 35a, a conductive layer is formed on the substrate 1 and further processed to form a gate electrode 2a, etc., and then an insulating layer, a semiconductor layer, a low resistance A semiconductor layer and a conductive layer are formed in the same manner as described above.

Area 1 shown in Figure 35b, where the source-drain region of the thin-film transistor is to be formed, is thicker, and area 2 or the channel region Expose the photoresist so that it remains thinly in the area where it is to be formed, leaving no other area (area 3). develop. By using such a resist, the conductive layer 7 of Eli 3 in the first etching, the high-resistance semiconductor layer 4 to which the impurity is not added, and the low-resistance semiconductor layer 4 to which the impurity is added in the first etching. 5 is removed. 0 ₂ Ri by the A Tsu Shi ring that had use, and to reduce the thickness of the entire Les Soo Bok to completely remove the registry Bok was residual presence in e Li A 2. Then, a portion of the conductive layer 7 of the area 2, the low-resistance semiconductor layer 5 doped with impurities, and a part of the high-resistance semiconductor layer 4 not doped with impurities are etched, as shown in FIG. 35B. The pattern shown is formed.

Hereinafter, a display panel substrate is obtained by forming the insulating layer 6 as shown in FIG. 35c and further forming the conductive layer 8 as shown in FIG. 35d.

However, processing using the gray-tone exposure technique tends to cause variations in the distance between the formed contact layers 5b, that is, the channel length of the thin-film transistor. Therefore, the characteristics of the element to be formed tend to vary. Also, the yield is low.

In the manufacture of the liquid crystal display panel substrate described above, intentional short-circuiting of the drain wiring and the gate wiring should avoid electrostatic breakdown of the active layer in a later-step rubbing treatment of the liquid crystal alignment film. The main purpose is to remove the short-circuited part when processing the later conductive film into a pixel electrode or when processing the substrate to a predetermined size for mounting on a display panel. Is done.

Thus, reducing the number of masks requires at the same time sufficient anti-static measures. In other words, simply reducing the number of masks will result in insufficient anti-static measures. In addition, even in the above method, since the gate wiring and the drain wiring are electrically isolated at the stage before the short circuit, the wiring element is formed even before the rubbing process. Various after Processing may cause components to become charged, and the active layer and insulating layer of the TFT may be destroyed by static electricity.

Therefore, there has been a demand for a reduction in the number of masks used for etching and a more sufficient countermeasure against static electricity. Further, there has been a further demand for facilitating the formation of the extraction electrode in order to simplify the process. A silicon nitride film or a semiconductor thin film as an insulating layer is generally formed by a parallel plate type plasma CVD device. Figure 36a and Figure 36b show the basic configuration of the CVD device. Inside the vacuum container 33 mainly composed of aluminum, an upper electrode (force source) 31 and a substrate 1 having a function of uniformly supplying gas from the outside are supported and heated. A lower electrode (anode) 32 having a mechanism for activating the plasma is provided, and a frame 4 for the purpose of fixing the substrate 1 and the purpose of limiting the plasma generation region is provided. 0 is set.

Provided in the vacuum vessel 3 3 feed gas, for example amorphous Shitsushi Li co if down film is formed (not shown) S i H ₄ and H 2 is an external feeder yo Ri upper electrodes 3 1 It is supplied uniformly on the substrate 1 through the provided conduit. When a voltage is applied between the two electrodes, a plasma of the source gas is generated, and an amorphous silicon film is formed on the substrate 1.

The relationship between the lower electrode 32, the substrate 1, and the frame 40 is shown in FIG. As shown in the figure, the bottom surface of the frame 40 is arranged so as to be in close contact with the substrate 1 including the end of the region where the film is formed.

A slight gap between the substrate 1 and the frame 40 due to the effects of surface irregularities caused by the processing accuracy of the substrate 1, the lower electrode 32 or the frame 40, and the effects of deformation due to heat stress, etc. There will be gaps. If there is such a gap, a film-forming species (radical, ion, etc.) generated by plasma enters the gap, and a film is formed on the substrate in the gap area. I'll let you go. The film formed in such a region is different in quality and the like from the film formed in other regions on the glass substrate, so that the film is peeled off in a vacuum vessel or a thin film transistor (TFT) is formed. (Lanister) Array The film may come off during the manufacturing process such as a photo process or a cleaning process. The film thus peeled off remains on the substrate as foreign matter (particles, dust, etc.), and the source / drain of the TFT and the gate come into electrical contact. As a result, the production yield is reduced due to the occurrence of such defects. Disclosure of the invention

An object of the present invention is to solve the above problems and to manufacture a display panel substrate with good productivity and low cost using a small number of masks. That is, the present invention provides a method for reducing the number of masks and at the same time achieving both countermeasures against static electricity and formation of extraction electrodes.

Another object of the present invention is to provide a thin film forming apparatus suitable for manufacturing such a display panel substrate and capable of stably manufacturing a high quality thin film. To

According to the method for manufacturing a display panel substrate of the present invention, an insulating substrate, a plurality of conductive layers formed thereon, and an element obtained by processing the insulating layer and the semiconductor layer are provided. In the manufacture of a display panel substrate equipped with a conductive layer, another conductive layer electrically connected to a wiring element formed by processing a conductive layer disposed at a lowermost layer among a plurality of conductive layers. Form a layer.

In the present invention, a conductive layer electrically connected to a previously formed wiring element is formed in order to prevent electrostatic breakdown of an insulating element and the like.

In general, by interposing another conductive layer between the oxide conductive material such as ITO provided on the uppermost layer, electrolytic corrosion easily occurs in the lowermost conductive layer, but the cost is low. Aluminum or aluminum with excellent conductivity A single-layer film of an alloy can be used.

Preferably, the conductive layer and the laminated insulating and semiconducting layers are applied to different notches using a single heat sink register. Work. For example, the removal of an insulating layer in a region where a connection terminal for connecting an external circuit and a scanning signal line is to be formed by using a gray-scale exposure technique and To prevent static electricity, remove the insulating layer in the area where the terminal for connecting the scan signal line and the source / drain wiring is to be formed. Use the same age registry as the ones. Although the gray-tone technology has difficulties in dimensional accuracy, reproducibility, stability, etc., it is not the channel part of the thin-film transistor, but the above-mentioned connection. It is used for the formation of elements that do not require relatively high precision such as connection terminals and do not directly affect the characteristics of thin film transistors, so that the yield is stable and good. Thus, it becomes possible to manufacture a display panel substrate.

When an insulating layer or a semiconductor layer is formed on a wiring element formed on a lower layer by exposing a part of the wiring element, a conductive layer formed on the upper layer is further formed. Can easily obtain a contact with the wiring element in the lower layer.

The conductive layer, the insulating layer, or the semiconductor layer is selectively formed only in a predetermined region by using, for example, a shield that selectively covers a peripheral portion of the insulating substrate. By connecting the film to the external circuit (circuit for driving the liquid crystal display) by forming the film while masking it with ceramics, etc. This eliminates the need for a mask to form the connection between the gate wiring and the source drain wiring to prevent the destruction of the elements due to static electricity during the process and the terminals. The number of masks can be reduced.

The wiring elements disposed in the lower layer are, for example, the scanning signal lines and the wiring elements maintained at the same potential as the scanning signal lines, and are formed in another layer. It is electrically connected to the source / drain wiring formed by processing the conductive layer.

Preferably, the wiring element is processed while the conductive layer is connected to the previously formed wiring element. The connection part of each wiring element is provided, for example, at the end of the board. For example, the insulating layer and the semiconductor layer are selectively formed only in a predetermined region in a region where the conductive layer is formed. The conductive layer is formed in a region including the wiring member exposed from the insulating layer, for example, in a region where the conductive layer is formed first. Thus, the formed conductive layer is easily electrically connected to the previously formed wiring element.

That is, the region where the insulating layer and the semiconductor layer are formed is set to be smaller than the region where the conductive layer is formed.

As can be seen from the cross-sectional view of the thin-film transistor, when the transparent electrode (ITO) is arranged on the top of the array, the thin-film transistor is formed by the flattening film. Since it is possible to form the ITo after reducing the concavities and convexities such as the above, it is possible to increase the opening ratio. Brief explanation of drawings

FIG. 1 is a schematic longitudinal sectional view of a display panel substrate according to one embodiment of the present invention.

FIG. 2 is a schematic longitudinal sectional view showing a state after one manufacturing process of the display panel substrate.

FIG. 3 is a schematic longitudinal sectional view showing a main part of the display panel substrate.

FIG. 4 is a schematic longitudinal sectional view showing a state after another manufacturing process of the display panel substrate.

Figure 5a shows the relationship between the substrate and the mask during thin film formation in the same process. FIG. 5B is a schematic longitudinal sectional view of the relevant part shown in FIG.

FIG. 6A is a schematic longitudinal sectional view showing a state after another manufacturing process of the display panel substrate, and FIG. 6B is a plan view of a wiring connection portion of the display panel substrate. FIG. 6C is a plan view of the connection terminal of the display panel substrate.

FIG. 7 is a schematic longitudinal sectional view showing a state of the display panel substrate after another manufacturing process.

FIG. 8A is a schematic longitudinal sectional view showing a state of the display panel substrate after another manufacturing process, and FIG. 8B is a wiring connection of the display panel substrate. FIG. 8C is a plan view of a connection terminal of the display panel substrate.

FIG. 9 is a schematic longitudinal sectional view showing a state of the display panel substrate after another manufacturing process.

FIG. 10a is a schematic longitudinal sectional view showing a state of the same display panel substrate after another manufacturing process, and FIG. 10b is a schematic sectional view of the same display panel substrate. FIG. 10C is a plan view of a wiring connection portion, and FIG. 10C is a plan view of a connection terminal of the display panel substrate.

FIG. 11 is a schematic longitudinal sectional view showing a state of the display panel substrate after the further manufacturing process.

FIG. 12a is a schematic longitudinal sectional view showing the display panel substrate after further manufacturing processes, and FIG. 12b is a display panel substrate. FIG. 12c is a plan view of the wiring connection portion of FIG. 12, and FIG. 12c is a plan view of the connection terminal of the display panel substrate.

FIG. 13a is a schematic longitudinal sectional view showing the display panel substrate after further manufacturing processes, and FIG. 13b is a view showing the same display panel substrate. FIG. 13C is a plan view of a wiring connection portion of the display panel substrate, and FIG. 13C is a plan view of a connection terminal of the display panel substrate.

FIG. 14A is a schematic longitudinal sectional view showing a state after a manufacturing process of a display panel substrate according to another embodiment of the present invention, and FIG. 14B is a display panel substrate of the same. FIG. 14C is a plan view of the wiring connection portion of FIG. 14, and FIG. 14C is a plan view of the connection terminal of the display panel substrate.

FIG. 15a is a schematic longitudinal sectional view showing a state after another manufacturing process of the display panel substrate, and FIG. 15b is a wiring connection of the display panel substrate. FIG. 15c is a plan view of a connection terminal of the display panel substrate.

FIG. 16 is a schematic longitudinal sectional view showing a state of the display panel substrate after another manufacturing process.

FIG. 17a is a schematic longitudinal sectional view showing a state after another manufacturing process of the display panel substrate, and FIG. 17b is a wiring connection of the display panel substrate. FIG. 17C is a plan view of a connection terminal of the display panel substrate.

FIG. 18a is a schematic longitudinal sectional view showing a state after another manufacturing process of the display panel substrate, and FIG. 18b is a wiring connection of the display panel substrate. 18c is a plan view of a connection terminal of the display panel substrate. FIG.

FIG. 19a is a schematic longitudinal sectional view showing a state after another manufacturing process of the display panel substrate, and FIG. 19b is a wiring connection of the display panel substrate. FIG. 19c is a plan view of the connection terminal of the display panel substrate.

FIG. 20a is a schematic longitudinal sectional view showing a state after one manufacturing process of a display panel substrate according to another embodiment of the present invention, and FIG. FIG. 20C is a longitudinal sectional view of a wiring connection portion of the panel substrate, and FIG. 20C is a longitudinal sectional view of a connection terminal of the display panel substrate.

FIG. 21 a is a schematic longitudinal sectional view showing a state after another manufacturing process of the display panel substrate, and FIG. 21 b is a wiring connection of the display panel substrate. FIG. 21 c is a vertical cross-sectional view of the connection terminal of the display panel substrate.

FIGS. 22a and 22b are schematic longitudinal sectional views showing the relationship between a substrate and a mask when a thin film is formed in one manufacturing process of the display panel substrate. .

FIG. 23a is a schematic longitudinal sectional view showing a state after another manufacturing process of the display panel substrate, and FIG. 23b is a wiring connection of the display panel substrate. FIG. 23c is a longitudinal sectional view of a connection terminal of the display panel substrate.

FIG. 24a is a schematic longitudinal sectional view showing a state of the display panel substrate after further manufacturing processes, and FIG. 24b is a view showing the same state of the display panel substrate. FIG. 24c is a longitudinal sectional view of a wiring connection portion of the substrate, and FIG. 24c is a longitudinal sectional view of a connection terminal of the same display panel substrate.

FIG. 25a is a schematic longitudinal sectional view showing a state of the display panel substrate after another manufacturing process, and FIG. 25b is a view of the display panel substrate. FIG. 25c is a vertical cross-sectional view of the connection terminal of the display panel substrate, and FIG. 25d is a vertical cross-sectional view of the connection terminal of the same display panel substrate. FIG. 3 is a longitudinal sectional view showing a relationship between the mask and the mask.

FIG. 26 is a longitudinal sectional view of a main part showing a frame used in the thin film forming apparatus according to one embodiment of the present invention.

FIG. 27a is a longitudinal sectional view of a main part showing a relationship between the frame and a substrate on which a thin film is to be formed, and FIG. 27b is a sectional view of the same frame. And thin FIG. 3 is a longitudinal sectional view of a main part showing a relationship with a thin film on which a film is formed.

FIG. 28 is a characteristic diagram showing the relationship between the occurrence of film peeling and the position of the tip of the projecting portion of the frame.

FIG. 29 is a longitudinal sectional view of a main part showing a frame used in a thin film forming apparatus according to another embodiment of the present invention.

FIG. 30 is a schematic longitudinal sectional view showing a state after one manufacturing process of a conventional display panel substrate.

FIG. 31 a is a schematic longitudinal sectional view showing a state after another manufacturing process of the display panel substrate, and FIG. 31 b is a wiring connection of the display panel substrate. FIG. 31 c is a vertical cross-sectional view of the connection terminal of the display panel substrate.

FIG. 32 is a schematic longitudinal sectional view showing a state after another manufacturing process of the display panel substrate.

FIG. 33a is a schematic longitudinal sectional view showing the same state of the display panel substrate after another manufacturing process, and FIG. 33b is a view showing the same state of the display panel substrate. FIG. 33c is a longitudinal sectional view of a connection terminal of the display panel substrate of the same display panel substrate.

FIG. 34a is a schematic longitudinal sectional view showing a state of the display panel substrate after another manufacturing process, and FIG. 34b is a view showing the display panel substrate. FIG. 34 is a longitudinal sectional view of the wiring connection part, and FIG. 34 is a longitudinal sectional view of the connection terminal.

Figure 3 5 a ~ Figure 3 5 d, respectively, other conventional display panel Keru Contact to the method of manufacturing the relay board Ru Ah in longitudinal sectional view schematically showing a state after each step _c Figure 3 6 a is FIG. 36B is a schematic longitudinal sectional view showing the thin film forming apparatus, and FIG. 36B is a horizontal sectional view thereof.

Figure 37 shows the frame and thin film used in a conventional thin film forming apparatus. FIG. 3 is a longitudinal sectional view of a main part showing a relationship with a substrate to be formed.

(Explanation of sign)

1 board

2, 7 8

2 a gate electrode

2 b Storage capacitance electrode

2 c Scan signal line

3, 6 10 Insulation layer

33 aa gate insulating layer

4, 4a semiconductor layer

5, 5a Low resistance semiconductor layer

5 b Contact layer

6 Protective film

6a 6b, 6c Contact window

7 a Source electrode wiring

7 b Drain electrode wiring

7 c 7 e Source 'Drain wiring

7d cover layer

8a Pixel electrode

8 b Terminal material

8c drain wiring

1 0 a Insulated sidewall

20 a 20 c titanium film

20 b Aluminum film

3 0, 4 0 Mask 3 1 Upper electrode

3 2 Lower electrode

33 Embodiment of the Invention of Vacuum Vessel Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, a liquid crystal display panel substrate using a thin film transistor will be described as an example. Example 1

FIG. 1 schematically shows the structure of the display panel substrate of this embodiment. This display panel substrate is an array substrate for a so-called active matrix type liquid crystal display panel, and forms an electric field between the substrate and a counter electrode disposed on the counter substrate. In order to maintain the voltage between the two electrodes while the area where the pixel electrode is arranged, the area where the TFT for controlling the signal output to the pixel electrode is arranged, and the signal to the pixel electrode are not recognized. The storage capacity is roughly divided into the areas where the storage capacity is arranged. Further, a lead electrode for a scanning signal line is formed at the end.

The gate electrode 2a and the auxiliary capacitance electrode 2b are formed by processing the same conductive layer, and are also electrically connected. Above the gate electrode 2a, a semiconductor layer 4a made of amorphous silicon is formed as an active layer of the TFT with the gate insulating layer 3a interposed therebetween. The scanning signal line 2c formed integrally with the gate electrode 2a is electrically connected to a layer made of a transparent conductor integrated with the pixel electrode 8a at an end of the substrate 1. You. The source wiring is also electrically connected to these. As shown in Fig. 2, the scanning signal lines, gate electrodes, and storage capacitors are formed on the surface of the insulating substrate 1 (for example, # 1 737 made by Corning) by sputtering. The conductive layer 2 to be processed into an electrode or the like is formed. For example, as shown in FIG. 3, the conductive layer 2 has a laminated structure of a titanium film 20a, an aluminum film 2Ob, and a titanium film 20c (Ti / AI / Ti = 1. 0 0 η m

/ 300 η m / 100 η m). In addition, chrome, tantalum, silver, copper, palladium, etc. are used. The thickness is determined in consideration of the resistance value.

On the conductive layer 2 thus formed, as shown in FIG. 4, an insulating layer 3 made of, for example, silicon nitride and having a thickness of 200 nm, and an amorphous layer undoped. Semiconductor layer 4 made of crystalline silicon and having a thickness of 100 nm, and amorphous silicon doped with phosphorus as an impurity and having a thickness of 20 nm. A low-resistance semiconductor layer 5 is formed by laminating by chemical vapor deposition (CVD). Here, as shown in FIGS. 5A and 5B, a region where a terminal for connecting to the external circuit of the scanning signal line on the periphery of the substrate 1 is formed, and a source A ceramic mask 30 is disposed on the surface of the substrate 1 so as to cover the region where the connection between the drain wiring and the gate electrode wiring is formed, and these films are formed. . Therefore, as shown in FIG. 4, the main surface of conductive layer 2 is exposed in these regions. Of course, these areas may be exposed using the gray-tone exposure technology shown earlier. For the insulating layer 2, silicon oxide or aluminum oxide is used in addition to silicon nitride. The thickness of each layer is determined in consideration of the required characteristics of the thin film transistor and variations in the manufacturing process.

The formed conductive layer 2, insulating layer 3, semiconductor layer 4 and low-resistance semiconductor layer 5 are shown in FIG. 6A, by draining using a heat resist. It is processed into the patterns shown in Fig. 6b and Fig. 6c. That is, the conductive layer 2 is processed into a gate electrode 2 a, a storage capacitor electrode 2 b, a scanning signal line 2 c, and the like, and an insulating layer 3, a semiconductor layer 4, and a low-resistance semiconductor layer disposed thereon. 5 is added to the same pattern except for a region for forming a connection portion between wirings shown in FIG. 6b and a region for forming a connection terminal shown in FIG. 6c. For example, RIE (reactive ion etching) using an etching gas containing BCI ₃ gas as a main component is used. In addition, although it depends on the size of the thin film transistor to be formed, liquid etching may be used. In addition, as described above, a gray-in exposure technique may be used. That is, the thin film transistor portion and the auxiliary capacitance portion are exposed so that the resist remains as thick as possible, and the portion where the insulating layer 3 on the conductive layer 2 is to be removed, that is, the portion where the scanning signal line is connected to the external circuit. At the place where connection terminals are to be arranged and the place where the scanning signal line is to be connected to the source / drain wiring, exposure is performed so that a certain amount of the resist remains, and the resist remains at the other parts. Exposure so that there is no image. Dry etching is performed in this state to process the low-resistance semiconductor layer 5, the high-resistance semiconductor layer 4, the insulating layer 3, and the conductive layer 2 in a region where no resist is formed. Next, the location where the connection terminal for connecting the scanning signal line to the external circuit and the location where the scanning signal line and the source / drain wiring are to be connected to each other are to be registered using the register 02. Then, the low-resistance semiconductor layer 5, the high-resistance semiconductor layer 4, and the insulating layer 3 are removed therefrom. As a result, a pattern having the same function as the pattern shown above can be formed.

Next, as shown in FIG. 7, an insulating layer 10 made of silicon nitride and having a thickness of 500 nm is formed by CVD. The insulating layer 10 is made of a material other than silicon nitride that can maintain insulation properties, such as silicon oxide or aluminum oxide. A room can also be used. Also, the film formation method is not limited to CVD, and a spin coating method using liquid glass or the like may be used. Films formed by the spin coating method are preferred because of their high flatness. Next, anisotropic etching such as gas phase etching is performed from above. By properly managing the etching conditions, as shown in FIG. 8A, the insulating layer 10 on the flat portion such as the upper part of the low-resistance semiconductor layer 5 is removed, and the etching is performed.

-Insulating side walls 10a are formed to cover these side surfaces, leaving the insulating layer 10 only on the side surfaces of the gate electrode 2a and the gate insulating layer 3a. As shown in FIGS. 8B and 8C, the insulating side wall 10a is also formed on the periphery of the exposed area of the scanning signal line 2c. These insulating side walls 10a can be formed using so-called dry etching, in which the film is etched by discharge of a gas containing chlorine or fluorine. For example, B C

1 ₃ intends line the RIE Dee Tsu quenching who was use the gas as a main component. Generally gas used is a _{_{C l 2, BCI 3, SF}} 6, CF 4, NF 3, CIF 3, CHF 3 and the like. Another etching method is C

Any method that has anisotropy in the etching direction such as PM (chemical mechanical polishing) may be used.

Next, as shown in FIG. 9, a Ti / AI / Ti laminated film is formed as a conductive layer 7 for processing into resource and drain wirings by snorting. . As the conductive layer 7, Cr, Ta, Ag, Pd, Cu, or the like may be used. The film thicknesses were 1 OO nm, 300 nm and 1 OO nm, respectively. The film thickness can be adjusted according to the resistance value. The conductive layer 7 is formed at the end of the substrate 1 by the scanning signal line formed earlier.

Formed over the exposed end of 2c. Then, as shown in FIG. 10a, turning is performed by etching using a heat source register, so that the source electrode wiring 7a and the drain are formed. Electrode wiring 7b, source The wiring 7c and the like are formed. Therefore, these wirings are formed in a state where they are electrically connected to each other. As shown in FIG. 1Ob, the connecting portion of the end of the substrate 1 for preventing static electricity covers the exposed scanning signal line 2c and the source drain wiring 7c. Is formed. At the same time, as shown in Figure 10c, the area where the terminal for connecting to the external circuit is to be formed is covered with the exposed cover layer 7d isolated from other source / drain wiring. Is formed covering the exposed end of the scanning signal line 2c. Further, the low-resistance semiconductor layer 5a is processed into a contact layer 5b. The call Kodewa BC 1 ₃ gas was RIE who was use a picture pitch Ngugasu as a main component. At the time of this etching, a part of the high resistance semiconductor layer 4a in the channel region of the thin film transistor is also etched at the same time. Here, if it is possible to etch only the low-resistance semiconductor layer 5a without etching the high-resistance semiconductor layer 4a in the channel region, the high-resistance semiconductor layer 4a is etched. No need to ping. In this case, since the thickness of the high-resistance semiconductor layer 4a can be reduced, there are advantages such as improvement in the transistor characteristics and uniformity.

Next, as shown in FIG. 11, as a protective film 6 for protecting the thin film transistor from the adsorption of moisture or the like, for example, a 300 nm-thick nitriding cage. A base film is formed. Then, as shown in FIGS. 12a, 12b and 12c, the contact windows 6a and 6b are formed by etching using a heat register. And form 6 c. Although not shown, at this time, a high-resistance semiconductor 4a arranged in the same pattern on the gate electrode 2a, the scanning signal line 2c, and the like is attached to each element. May be separated. However, if the characteristics can be satisfied as an array substrate for a liquid crystal display device, it is not necessary to perform such separation.

Finally, as shown in Fig. 13a, it consists of a transparent conductor such as ITO. The conductive layer is formed by sputtering, which is further processed into pixel electrodes 8a, terminal members 8b, etc. by etching using a photo resist. Thus, an array substrate for a liquid crystal display device can be obtained. As shown in FIG. 13b, a conductive layer made of a transparent conductor is not arranged on the periphery of the connection portion, or is removed by etching. On the other hand, as shown in FIG. 13c, the connection terminal is provided with a terminal member 8b for contacting with an external circuit (not shown) so as to seal the contact window 6c. Is done.

Here, as shown in FIG. 13b, at the connection between the scanning signal line and the source / drain wiring, the scanning signal line 2c and the source / drain are placed from above the insulating substrate 1. The wiring 7c is stacked in order, and as shown in FIG. 3c, the connection terminal of the scanning signal line 2c is formed simultaneously with the scanning signal line 2c and the source / drain wiring 7c. A terminal member 8b made of a transparent conductor formed at the same time as the cover layer 7d and the pixel electrode is sequentially laminated.

In the connection terminal section and the connection section for preventing static electricity, the scanning signal line is disposed below as in the present embodiment, and the surface thereof is covered with source / drain wiring or the like. The wires are connected to the ITO via source'drain wires. Therefore, it is possible to use a single-layer scan signal line made of aluminum or aluminum alloy, which was difficult to connect directly to the ITO conductive layer due to electrolytic corrosion. become. Scan signal lines that have higher electrical resistance and are easier to form than scan signal lines with a three-layer structure of Ti / AI / Ti that have been commonly used in the past due to concerns about electrolytic corrosion. Can be used.

In addition, by using a mask for avoiding the formation of a semiconductor layer or the like in a region where these connection terminals and connection portions are formed, a drain window is required to form the contact window. Same as forming it on the electrode wiring As described above, an opening may be formed only in the protective film disposed on the upper layer. In other words, the time required for forming the contact window for the connection terminal portion and the connection portion is equal to the time required for forming the contact window for the drain electrode wiring. Therefore, since the formation of these contact windows ends at the same time, from the completion of the formation of one contact window to the completion of the formation of the other contact window, Eliminates sludge, which is a concern due to excessive processing time. Also, etching in an oxygen atmosphere, which has been performed as a measure against sludge, becomes unnecessary. Therefore, etching can be performed in an oxygen-free atmosphere, and a conductive material that is easily oxidized, such as silver, copper, or palladium, can be used. Example 2

Also in the present embodiment, an array substrate for a liquid crystal display device will be described as an example.

A conductive layer to be processed into scanning signal lines, gate electrodes, storage capacitor electrodes, etc. by sputtering on the surface of an insulating substrate (for example, # 1737 made by Corning). To form The conductive layer has, for example, a titanium film, an aluminum film, and a laminated structure of a titanium film (T i / A I / T i = 100 nm / 300 nm / 100 nm). In addition, chrome, evening, silver, copper, palladium, etc. are used. The thickness is determined in consideration of the resistance value and the like.

On top of the formed conductive layer, for example, a 200-nm thick layer of silicon nitride and an undoped amorphous silicon A semiconductor layer having a thickness of 100 nm is formed by lamination by CVD. Here, the area where the terminals for connecting the scanning signal lines on the periphery of the substrate to the external circuit are arranged, and the source for preventing electrostatic breakdown. These films are formed by disposing a ceramic mask on the surface of the substrate so as to cover the area where the connection between the drain wiring and the gate wiring is disposed.

Then, as shown in FIG. 14a, FIG. 14b and FIG. 14c, a conductive layer, an insulating layer and a conductive layer are formed by a draining process using a heat resist. The high-resistance amorphous silicon is simultaneously patterned to form a conductive layer into a gate electrode 2a, a storage capacitor electrode 2b, a scanning signal line 2c, and the like. As a result, the insulating layer is the same as the element obtained by processing the lower conductive layer, such as the gate electrode 2a, except for the region where the connection terminal at the end of the substrate 1 is to be formed. The pattern is processed into the gate insulating layer 3a, and the semiconductor layer 4 is processed into the same pattern. Here, we performed RIE using an etching gas containing BCI ₃ gas as a main component. Although it depends on the size of the thin film individual transistor, liquid phase etching using an etching solution may be performed instead of gas phase etching.

Of course, a similar pattern may be formed by using a gray-tone exposure technique.

Next, as shown in FIGS. 15a, 15b, and 15c, the side surfaces of the gate electrode 2a and the like were anisotropically etched in the same manner as in Example 1. An insulating side wall 10a is formed over the insulating side wall.

Thereafter, as shown in FIG. 16, the low-resistance semiconductor layer 5 is formed as a low-resistance semiconductor layer 5 by CVD, for example, a 20 nm-thick amorphous silicon layer doped with phosphorus. A capacitor film is formed. Further, a Ti / AI / Tί laminated film is formed as a conductive layer 7 for processing into source drain wiring by a sputtering method. As the conductive layer 7, Cr, Ta, Ag, Pd, Cu, or the like may be used. The film thickness was 100 nm, 300 nm, and 100 nm, respectively. The formed conductive layer 7 is patterned as shown in FIGS. 17a, 17b and 17c by etching using a heat sink registry. Then, a source electrode wiring 7a, a drain electrode wiring 7b, a source 'drain wiring 7c, a cover layer 7d, and the like are formed. Also, the low-resistance semiconductor layer 5 is processed into a contact layer 5b. Here, gas phase etching was performed by RIE using an etching gas containing BCl ₃ gas as a main component.

Then, as shown in FIGS. 18a, 18b and 18c, a protective film 6 is formed on the surface of the substrate 1 to protect TFΤ from moisture adsorption or the like. For example, a silicon nitride film having a thickness of 300 nm is formed. Then, the protective film 6 is processed into a predetermined pattern by etching using the photo resist. At this time, contact windows 6 a and

Form 6b and 6c. A protective film 6 is formed in the hatched regions in FIGS. 18b and 18c, and the cover is arranged such that the cover layers 7d and the like disposed below the center are exposed in the center of the drawing. A window 6 is formed. In addition, although not shown, since the high-resistance amorphous silicon 4 is connected on the scanning signal line 2c and the like at this time, etching is simultaneously performed so as to separate it. Go. However, if the characteristics of the array for a liquid crystal display device can be satisfied, it is not necessary to perform such separation.

Finally, as shown in FIG. 19a, a conductive layer made of a transparent conductor such as IT0 for processing into the pixel electrode 8a or the like is formed by a sputtering method, and An array substrate for a liquid crystal display device can be obtained by performing notching by etching using an auto-register.

As shown in Figure 19b, the scanning signal line 2c and the source ■ drain wiring

At the connection point 7c, the scanning signal line 2c and the SO The drain wiring 7c is stacked in order. As shown in FIG. 19c, the connection terminal of the scanning signal line 2c is connected to the scanning signal line 2c, the source and the drain. A cover layer 7 d formed at the same time as the inner wiring 7 c and a terminal member 8 b made of a transparent conductor formed at the same time as the pixel electrode are sequentially laminated. Yes. Example 3

In the present embodiment, another example of a method for easily processing a connection terminal to an external circuit and a connection portion between wirings for preventing static electricity will be described. According to the present embodiment, there is no need for a mask or the like to form them.

In the same manner as in the above embodiment, a conductive layer to be processed into a scanning signal line, a gate electrode, and the like is formed on the surface of the insulating substrate. The conductive layer is, for example, a laminated structure of a titanium film, an aluminum film, and a titanium film (Ti / AI / Ti = 100 nm / 300 nm / 100 nm). Has. In addition, chromium, tantalum, silver, copper, palladium, etc. are used. The thickness is determined in consideration of the resistance value and the like.

As shown in FIG. 20a, the formed conductive layer is formed by a gate electrode 2a, a storage capacitor electrode 2b, and a scanning signal line 2 by etching using a photomask. It is processed into c etc. At this time, the area where the connection part is to be formed for the purpose of preventing static electricity and the area where the connection terminal to the external circuit is to be formed are shown in FIGS. 20b and 20b. It is shown in c.

Then, as shown in FIGS. 21a, 21b and 21c, the gate insulating layer has a thickness of 200 nm and is made of silicon nitride. Layer 3, high-resistance semiconductor 4 made of hydrogenated amorphous silicon which is processed into an active layer with a thickness of 100 nm, and contact with a thickness of 20 nm A low-resistance semiconductor 5 made of amorphous silicon doped with phosphorus to be processed into a layer is formed. It is formed by plasma CVD. Here, as shown in FIGS. 22a and 22b, a mask 30 covering these regions is provided so that no film is formed on these regions. In addition, by making the end of the conductive layer 3 protrude from the side surface of each layer formed thereon, a connection portion and the like are formed as shown in FIGS. 21B and 21C. The end of the scanning signal line 2c in the area to be exposed can be exposed.

The mask 30 is made of, for example, ceramics such as aluminum oxide, metal such as stainless steel, quartz, glass, or SiC.

Furthermore, a Ti / AI / Ti stacked film is formed as a conductive layer 7 for processing into drain wiring by using a snorkel ring. As the conductive layer 7, Cr, Ta, Ag, Pd, Cu, or the like may be used. The film thicknesses were 1 OO nm, 200 nm and 1 OO nm, respectively. Then, as shown in FIG. 23a, FIG. 23b and FIG. 23c, the semiconductor layer 4a and the like are separated for each TFT by dry etching using a heat mask. Divide into pieces.

Next, a conductive layer made of a transparent conductor such as ITO is formed by sputtering or the like so as to cover these. At this time, the transparent conductive layer is disposed so as to cover the exposed end of the scanning signal line 2c in the region where the connection terminal and the like are to be formed. Thus, the formed source wiring and drain wiring are electrically connected to the gate wiring.

As shown in FIGS. 24a, 24b and 24c, a film made of a transparent conductor is formed on the pixel electrode 8a and the like by etching using the heat resist as a mask. At the same time, the conductive film 7 is processed to form the source electrode wiring 7a, the drain electrode wiring 7b, the source / drain wiring 7c and 7e, and the like. Further, the low resistance semiconductor layer 5 is divided and processed into a contact layer 5b. Here, an etchant whose main component is BCI ₃ gas Gas-phase etching was performed by RIE using gugas.

Thereafter, a protective film 6 made of, for example, silicon nitride is formed by plasma CVD, and an array substrate is obtained as shown in FIGS. 25A, 25B and 25C. Also in this case, as shown in Fig. 25d, protect the unnecessary parts, that is, the connection terminals, etc., by covering them with a mask 30 as shown in Fig. The film 6 is formed. Example 4

In the present embodiment, an improved thin film forming apparatus used for forming a thin film by the above-described plasma CVD will be described.

In the thin film forming apparatus of the present invention, the mask frame 40 shown in FIG. 26 is used in the conventional plasma CVD apparatus shown in FIGS. 36a and 36b. The substrate 1 is placed on the lower electrode 32 serving also as the substrate holder, and the frame 40 is placed on the substrate so as to press the substrate 1. A gap is provided on the leading end side of the frame 40 between the frame 1 and the substrate 1 as shown in FIG. 27a. In this space, the generation of plasma is limited.

In this region as well, although a film is formed under the leading end of the frame 40 as shown in FIG. 27b, the leading end of the frame 40 does not directly contact the formed film. From this, a good quality film can be obtained.

Figure 28 shows the effect of the height of the tip and the length of the plasma-limited region on the suppression of film peeling. As can be seen, the height of the lower end of the top of the frame has an effect. However, considering the smoothness of the base plate and the frame, the height of the lower end portion needs to be substantially about 0.1 mm. In this case, sufficient effects can be obtained if the length of the plasma-limited region is at least 1 mm. The same effect can be obtained by using a frame having the shape shown in FIG. 29 as a mask. Industrial availability

According to the present invention, a display panel substrate can be manufactured with a small number of masks. Also, it is excellent in measures against static electricity and it is easy to form connection terminals with external circuits. Therefore, it greatly contributes to low-cost and stable production of display panel substrates.

Claims

The scope of the claims

1. A method for manufacturing a display panel substrate comprising: an insulating substrate; and a plurality of conductive layers formed on the insulating substrate, and elements obtained by processing the insulating layer and the semiconductor layer. Accordingly, a display panel substrate is formed, in which another conductive layer is formed by electrically connecting to a wiring element formed by processing the conductive layer disposed at the lowermost layer among the plurality of conductive layers. Production method.

2. An insulating layer formed on the surface of the insulating substrate so as to cover the element is processed into a wall-shaped insulating element in close contact with the side surface of the element by anisotropic etching. A method for manufacturing a display panel substrate according to claim 1.

3. The lowermost conductive layer is made of aluminum or an aluminum alloy, and the exposed surface of the lowermost conductive layer is exposed to the outside. The method for manufacturing a display panel substrate according to claim 1, wherein another conductive layer is formed so as to cover.

4. The conductive layer disposed on the lowermost layer and the insulating layer and the semiconductor layer disposed on the uppermost layer are provided with different patterns by using a single photo resist. The method for producing a display panel substrate according to claim 1, wherein the substrate is processed into a substrate.

5. The connection terminal for keeping the same potential as other wiring elements in the later manufacturing process, or the connection terminal to the external circuit, in the conductive layer disposed at the lowermost layer in the later manufacturing process. 5. The method for producing a display panel substrate according to claim 4, wherein the substrate is processed into a pattern containing the same.

6. The method for manufacturing a display panel substrate according to claim 1, wherein the insulating layer or the semiconductor layer is formed by exposing a part of the wiring element above the wiring element.

7. The conductive layer, the insulating layer, or the semiconductor layer is selectively formed in a predetermined region by using a shield that selectively covers a peripheral portion of the insulating substrate. A method for manufacturing a display panel substrate according to claim 1.

8. The method for manufacturing a display panel substrate according to claim 7, wherein the shield is mainly made of aluminum oxide.

9. The method for manufacturing a display panel substrate according to claim 1, wherein the wiring element includes a scanning signal line and a wiring element maintained at the same potential as the scanning signal line.

10. An insulating substrate, a plurality of conductive layers formed on the insulating substrate, and an element obtained by processing the insulating layer and the semiconductor layer are provided, and the plurality of conductive layers are processed. A display panel substrate in which the wiring elements formed by the above are electrically connected to each other.

11. The display panel substrate according to claim 10, wherein terminals for connecting the wiring elements to each other are provided outside a region where the insulating layer is formed.

12. The display panel substrate according to claim 10, wherein terminals for connecting the wiring elements to each other are arranged in a region that is cut off when assembling the display panel.

13. An insulating substrate, a plurality of conductive layers formed on the insulating substrate, and an element obtained by processing the insulating layer and the semiconductor layer are provided, and the plurality of conductive layers are processed. A display panel substrate, wherein terminals for connecting the wiring element formed by the above to a circuit outside the system are provided outside a region where the insulating layer is formed.

14. The first terminal has a multi-layered structure in which a conductive layer forming a scanning signal line, a conductive layer forming a video signal line, and a conductive layer forming a pixel electrode are stacked. The display panel substrate described in 3.

15. A container, a means for supplying a raw material gas into the container, a means for generating plasma in the container, and a base contained in the container. A fixing means for heating the plate; and a fixing member for fixing the substrate at a predetermined position, wherein the fixing member includes a fixing part for bringing the substrate into close contact with the fixing part and a side face of the fixing part. Thin film forming equipment that includes protruding protrusions.

16. The thin film forming apparatus according to claim 15, wherein a tip of the protruding portion protrudes by 0.1 mm or more from a side surface of the fixing portion.

17. The thin film forming apparatus according to claim 15, wherein a distance between a lower end portion of a tip of the protruding portion and a surface of the substrate is 1 mm or more.

18. The thin-film forming apparatus according to 15, wherein the fixing portion has a frame shape, and the protruding portion is formed in a fringe shape on an inner surface of the fixing portion.

19. The thin-film forming apparatus according to 15, wherein the protruding portion defines a region on the substrate where plasma is generated.

Claims of amendment

[September 24, 2001 (24.09.01) Accepted by the International Bureau: Claims at the time of filing

1, 7 and 14 have been amended; other claims remain unchanged. (Page 3)]

1. (after correction) Manufacture of a display panel substrate including: an insulating substrate; and a plurality of conductive layers formed on the insulating substrate, and an element obtained by processing the insulating layer and the semiconductor layer. A method of processing a conductive layer disposed at a lowermost layer among a plurality of the conductive layers, without forming an insulating layer therebetween on a wiring element formed by processing the conductive layer. A method for manufacturing a display panel substrate which is formed by electrically connecting other conductive layers.

3. The exposed surface of the lowermost conductive layer is aluminum or aluminum alloy, and the lowermost conductive layer is an exposed surface of the lowermost conductive layer. 2. The method for manufacturing a display panel substrate according to claim 1, wherein another conductive layer is formed over the substrate.

4. The conductive layer disposed on the lowermost layer and the insulating layer and the semiconductor layer disposed on the uppermost layer are processed into different patterns by using a single heat resist. A method for manufacturing a display panel substrate according to claim 1.

5. A pattern including a connection terminal for keeping the potential of the conductive layer disposed on the lowermost layer equal to that of another wiring element in a later manufacturing process, or a connection terminal to an external circuit. The method for producing a display panel substrate according to claim 4, wherein the substrate is processed into a substrate.

7. (After correction) The insulating layer and the semiconductor layer are

33

Paper captured (Article 19 of the Convention) 2. The method for manufacturing a display panel substrate according to claim 1, wherein a predetermined area is selectively formed using a shield that selectively covers a peripheral portion including a region where the conductive layer is formed.

9. The method of manufacturing a display panel substrate according to claim 1, wherein the wiring element includes a scanning signal line and a wiring element maintained at the same potential as the scanning signal line.

10. A wiring formed by processing a plurality of the conductive layers, comprising: an insulating substrate; a plurality of conductive layers formed on the insulating substrate; and an element obtained by processing the insulating layer and the semiconductor layer. A display panel substrate in which elements are electrically connected to each other.

12. The display panel substrate according to claim 10, wherein terminals for connecting the wiring elements to each other are arranged in a region that is cut off during assembly to the display panel.

13. A wiring formed by processing a plurality of the conductive layers, comprising: an insulating substrate; a plurality of conductive layers formed on the insulating substrate; and an element obtained by processing the insulating layer and the semiconductor layer. A display panel substrate in which a terminal for connecting an element to a circuit outside the system is provided outside a region where the insulating layer is formed.

14. After the correction, the terminal is made of aluminum or an aluminum alloy without interposing an insulating layer between the conductive layer forming the scanning signal line and the conductive layer forming the scanning signal line. Configure stacked video signal lines

34 Captured Paper (Article Articles of the Convention) 14. The display panel substrate according to claim 13, wherein the substrate for a display panel has a multilayer structure in which a conductive layer formed and a conductive layer forming a pixel electrode are stacked.

15. A container, a unit for supplying a source gas into the container, a unit for generating plasma in the container, a unit for heating a substrate housed in the container, A thin film forming apparatus, comprising: a fixing member fixed to a location, wherein the fixing member includes a fixing portion that is in close contact with the substrate and a protruding portion protruding from a side surface of the fixing portion.

17. The thin film forming apparatus according to claim 15, wherein a distance between a lower end of the tip of the protruding portion and a surface of the substrate is 1 mm or more.

18. The thin film forming apparatus according to 15, wherein the fixing portion has a frame shape, and the projecting portion is formed in a fringe shape on an inner surface of the fixing portion.

19. The thin film forming apparatus according to 15, wherein the protruding portion defines a region where plasma is generated on the substrate.

35 Amended paper (Article 5 of the Convention) Statements under Article 19 (1) of the Convention In order to clarify the differences from the cited references, amendments have been made to reduce the scope of claims 1, 7, and 14.

In claim 1, an amendment has been made so that the upper conductive layer is formed without an insulating layer therebetween.

In section 7, the area covered by the shield is corrected to include the area where the conductive layer is formed.

In Item 14, the correction was made so that the terminal was made of aluminum or its alloy, and the upper conductive layer was formed without an insulating layer between them, as in Item 1.