CN113161292A - Manufacturing method of array substrate, array substrate and display panel - Google Patents
Manufacturing method of array substrate, array substrate and display panel Download PDFInfo
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- CN113161292A CN113161292A CN202110391323.8A CN202110391323A CN113161292A CN 113161292 A CN113161292 A CN 113161292A CN 202110391323 A CN202110391323 A CN 202110391323A CN 113161292 A CN113161292 A CN 113161292A
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- 239000000758 substrate Substances 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 170
- 239000010409 thin film Substances 0.000 claims abstract description 121
- 239000010408 film Substances 0.000 claims abstract description 81
- 238000000151 deposition Methods 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 48
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 24
- 238000009413 insulation Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 21
- 239000002245 particle Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Abstract
The invention discloses a manufacturing method of an array substrate, the array substrate and a display panel, wherein the manufacturing method of the array substrate comprises the following steps: providing a substrate; sequentially forming a first metal layer, a gate insulating layer and an active layer on a substrate; sequentially forming at least two layers of doped amorphous silicon thin films on the active layer, wherein the doped amorphous silicon thin films form doped layers; wherein the doped amorphous silicon thin film is deposited by adopting a plasma chemical vapor deposition method. At least two layers of doped amorphous silicon films are formed by adopting a plasma chemical vapor deposition method for deposition and different deposition powers, wherein one layer of doped amorphous silicon film is deposited by adopting low radio frequency power, and the other layer of doped amorphous silicon film is deposited by adopting high radio frequency power to form doped amorphous silicon films with different compactedness, so that the film quality is improved, the influence on the doped amorphous silicon films and the active layer during the deposition of the second metal layer is reduced, and the image residue is prevented.
Description
Technical Field
The invention belongs to the technical field of manufacturing methods of array substrates, and particularly relates to a manufacturing method of an array substrate, the array substrate and a display panel.
Background
The traditional array substrate is simple in film formation but has larger film quality defects by utilizing a plasma chemical vapor deposition method and adopting high radio frequency power to deposit the amorphous silicon film in a heavily doped region at one time; when the source electrode and the drain electrode are deposited, the film quality of the doped amorphous silicon film is easy to damage. When the display displays a fixed picture for a long time, conductive ions are gathered on the surface of the orientation layer, when the ions are gathered to a sufficient driving voltage, liquid crystal molecules can generate a polarization phenomenon, the driving voltage does not act on the liquid crystal molecules, and when the next picture is switched, the gathered ions can not leave the surface of the orientation layer immediately, so that the problem of image retention can be easily caused.
Disclosure of Invention
The main purpose of the embodiments of the present invention is to provide a manufacturing method of an array substrate, an array substrate and a display panel, which are intended to improve the defect that image sticking is easily generated on the display screen.
In order to solve the above technical problems, the present invention provides a method for manufacturing an array substrate, where the method for manufacturing an array substrate includes:
providing a substrate;
sequentially forming a first metal layer, a gate insulating layer and an active layer on the substrate;
sequentially forming at least two layers of doped amorphous silicon thin films on the active layer, wherein the doped amorphous silicon thin films form doped layers;
the doped amorphous silicon thin film is deposited by adopting a plasma chemical vapor deposition method, at least one layer of doped amorphous silicon thin film is deposited by adopting low radio frequency power, and at least one layer of doped amorphous silicon thin film is deposited by adopting high radio frequency power.
Further, the step of sequentially forming at least two doped amorphous silicon thin films on the active layer includes:
depositing a first layer of doped amorphous silicon film on the active layer by adopting high radio frequency power;
and depositing a second layer of doped amorphous silicon film on the side, deviating from the active layer, of the first layer of doped amorphous silicon film by adopting low radio frequency power.
Further, the thickness range of the first layer of doped amorphous silicon thin film is 200-300 angstroms; the thickness of the second layer of doped amorphous silicon thin film ranges from 100 angstroms to 200 angstroms.
Further, the step of sequentially forming at least two doped amorphous silicon thin films on the active layer includes:
depositing a first layer of doped amorphous silicon film on the active layer by adopting low radio frequency power;
depositing a second layer of doped amorphous silicon film on the side, away from the active layer, of the first layer of doped amorphous silicon film by adopting high radio frequency power;
and depositing a third layer of doped amorphous silicon film on the side, away from the first layer of doped amorphous silicon film, of the second layer of doped amorphous silicon film by adopting low radio frequency power.
Further, the thickness of the first doped amorphous silicon thin film is between 100-125 angstroms, the thickness of the second doped amorphous silicon thin film is between 150-200 angstroms, and the thickness of the third doped amorphous silicon thin film is between 100-125 angstroms.
Further, the range of the high radio frequency power is more than or equal to 6.2 KW; the range of the low radio frequency power is less than or equal to 5 KW.
Further, after the step of sequentially forming at least two layers of doped amorphous silicon thin films on the active layer and forming the doped layer by the at least two layers of doped amorphous silicon thin films, the method further includes: depositing a second metal layer on the doped layer.
The present invention also provides an array substrate, including: a substrate; a first metal layer disposed on the substrate; the grid electrode insulating layer is arranged on the first metal layer, and the active layer is arranged on the grid electrode insulating layer; the doping layer comprises at least two layers of doped amorphous silicon thin films; the doped amorphous silicon thin film is manufactured by adopting a plasma chemical vapor deposition method.
Further, the doped layer comprises two layers of doped amorphous silicon thin films, and the thicknesses of the two layers of doped amorphous silicon thin films are different.
The invention also provides a display panel, which comprises a color film substrate and the array substrate; the color film substrate is arranged in the light emergent direction of the array substrate.
The embodiment of the invention provides a manufacturing method of an array substrate, the array substrate and a display panel, and the invention adopts a plasma chemical vapor deposition method for deposition, and adopts different deposition powers to form at least two layers of doped amorphous silicon films, wherein one layer of the doped amorphous silicon film adopts low radio frequency power deposition, and the other layer adopts high radio frequency power deposition to form doped amorphous silicon films with different compactness, thereby being beneficial to improving the film quality, reducing the influence on the doped amorphous silicon film and an active layer when a second metal layer is deposited, and further preventing the occurrence of image residue.
Drawings
Fig. 1 is a schematic flow chart illustrating a manufacturing method of an array substrate according to a first embodiment of the present invention;
FIG. 2 is a detailed flow chart of step S30 in the second embodiment of the method for fabricating an array substrate according to the present invention;
FIG. 3 is a schematic flow chart illustrating another detailed process of step S30 in the third embodiment of the method for fabricating an array substrate according to the present invention;
fig. 4 is a schematic flow chart illustrating a manufacturing method of an array substrate according to a fourth embodiment of the present invention;
fig. 5 is a schematic structural diagram of the array substrate according to the present invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 100 | |
31 | Doping layer |
| 11 | |
41 | Source electrode |
| 12 | A first metal layer | 42 | |
| 13 | |
51 | |
| 21 | Active layer |
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The present invention provides a method for manufacturing an array substrate, please refer to fig. 1, where fig. 1 is a schematic flow chart of a first embodiment of a method for manufacturing an array substrate provided by the present invention, and the method for manufacturing an array substrate includes:
step S10, providing a substrate;
specifically, a substrate is provided and cleaned to remove contaminants, such as minute particles or particles, from the substrate.
Step S20, sequentially forming a first metal layer, a gate insulating layer and an active layer on a substrate;
specifically, after cleaning the substrate, a first metal layer is deposited on the substrate, a gate electrode is formed through a photolithography process, and then a gate insulating layer and an active layer are sequentially and continuously deposited.
Step S30, sequentially forming at least two layers of doped amorphous silicon thin films on the active layer, wherein the at least two layers of doped amorphous silicon thin films form doped layers;
the doped amorphous silicon thin film is deposited by adopting a plasma chemical vapor deposition method, at least one layer of doped amorphous silicon thin film is deposited by adopting low radio frequency power, and at least one layer of doped amorphous silicon thin film is deposited by adopting high radio frequency power.
Specifically, the doped amorphous silicon thin film is generally deposited with one layer of doped amorphous silicon thin film at one time by adopting a plasma chemical vapor deposition method, and the doped amorphous silicon thin film is easy to damage when a second metal layer is deposited on the doped amorphous silicon thin film (the second metal layer forms a source electrode and a drain electrode through a photoetching process); according to the embodiment of the invention, at least two layers of doped amorphous silicon thin films are formed in sequence, and the two layers of doped amorphous silicon thin films are deposited by adopting different powers, so that the film quality is favorably improved, and the influence on the doped amorphous silicon thin films and the active layer when the second metal layer is deposited is reduced. Depositing the doped amorphous silicon thin film by adopting a plasma chemical vapor deposition method, depositing at least one layer of the doped amorphous silicon thin film by adopting low radio frequency power, and depositing at least one layer of the doped amorphous silicon thin film by adopting high radio frequency power; when the doped amorphous silicon thin film is deposited by the high radio frequency and the low radio frequency, the rate of depositing the doped amorphous silicon thin film by the low radio frequency power is lower than that of depositing the doped amorphous silicon thin film by the high radio frequency power, the deposited doped amorphous silicon thin film by the low radio frequency power has better compactness, the film quality is favorably improved by the matched use of the low radio frequency power deposition and the high radio frequency power deposition, the influence on the doped amorphous silicon thin film and the active layer when the second metal layer is deposited is reduced, and the problem of image residue of the display panel is further prevented.
Further, referring to fig. 2, a second embodiment of the manufacturing method of the array substrate according to the present invention is provided based on the first embodiment, and step S30 includes:
step S311, depositing a first layer of doped amorphous silicon thin film on the active layer by adopting high radio frequency power;
specifically, a plasma chemical vapor deposition method is adopted on the active layer to deposit a first doped amorphous silicon film, high radio frequency power is adopted when the first doped amorphous silicon film is deposited, the first doped amorphous silicon film deposited by the high radio frequency power has good uniformity, the deposition rate is high, and the rapid forming can be realized.
And S312, depositing a second doped amorphous silicon thin film on the side, away from the active layer, of the first doped amorphous silicon thin film by adopting low radio frequency power.
Specifically, a plasma chemical vapor deposition method is adopted on the first doped amorphous silicon film to deposit a second doped amorphous silicon film, low radio frequency power is adopted when the second doped amorphous silicon film is deposited, the density of the second doped amorphous silicon film deposited by the low radio frequency power is compact, and the second doped amorphous silicon film or the first doped amorphous silicon film can be prevented from being damaged when a source/drain electrode is deposited on the doped layer.
Further, the thickness range of the first layer of doped amorphous silicon thin film is 200-300 angstroms; the thickness range of the second layer of doped amorphous silicon thin film is 100-200 angstroms.
Specifically, the total thickness of the doped amorphous silicon thin film is about 400 angstroms, the total thickness of the doped amorphous silicon thin film, the thickness of the first doped amorphous silicon thin film and the thickness of the second doped amorphous silicon thin film are set according to a certain rule, 400 ═ X + (400-X), X is the thickness of the first doped amorphous silicon thin film, and 400-X is the thickness of the second doped amorphous silicon thin film; when the film thickness is more than or equal to 100 angstroms and less than 150 angstroms, depositing to form a film by adopting a plasma chemical vapor deposition method with the power of 5KW or less; when the film thickness is more than 150 angstrom, a plasma chemical vapor deposition method with the power of 6.2KW or more is adopted to deposit the film. For example, when X is 300 angstroms, the film is deposited by a plasma CVD method with a power of 6.2KW or more, and when 400-X is 100 angstroms, the film is deposited by a plasma CVD method with a power of 5KW or less.
Further, referring to fig. 3, a third embodiment of the manufacturing method of the array substrate according to the present invention is provided based on the first embodiment, and step S30 includes:
step S321, depositing a first layer of doped amorphous silicon thin film on the active layer by adopting low radio frequency power;
specifically, a plasma chemical vapor deposition method is adopted on the active layer to deposit a first doped amorphous silicon thin film, low radio frequency power is adopted when the first doped amorphous silicon thin film is deposited, and the density of the first doped amorphous silicon thin film deposited by the low radio frequency power is compact.
Step S322, depositing a second layer of doped amorphous silicon film on the side, away from the active layer, of the first layer of doped amorphous silicon film by adopting high radio frequency power;
specifically, a plasma chemical vapor deposition method is adopted on the first layer of doped amorphous silicon film to deposit a second layer of doped amorphous silicon film, high radio frequency power is adopted when the second layer of doped amorphous silicon film is deposited, and the deposition rate of the second layer of doped amorphous silicon film deposited by the high radio frequency power is high.
And step S3, depositing a third layer of doped amorphous silicon film on the side, away from the first layer of doped amorphous silicon film, of the second layer of doped amorphous silicon film by adopting low radio frequency power.
Specifically, a plasma chemical vapor deposition method is adopted on the second layer of doped amorphous silicon thin film to deposit a third layer of doped amorphous silicon thin film, low radio frequency power is adopted when the second layer of doped amorphous silicon thin film is deposited, and the third layer of doped amorphous silicon thin film is deposited by adopting the same low radio frequency power.
Further, the thickness of the first doped amorphous silicon thin film is between 100-125 angstroms, the thickness of the second doped amorphous silicon thin film is between 150-200 angstroms, and the thickness of the third doped amorphous silicon thin film is between 100-125 angstroms.
Specifically, the thickness of the doped layer is generally about 400 angstroms, the first doped amorphous silicon thin film, the second doped amorphous silicon thin film and the third doped amorphous silicon thin film are arranged according to a certain rule, 400 ═ X + (400-2X) + X, X is the thickness of the first doped amorphous silicon thin film and the second doped amorphous silicon thin film, 400-2X is the thickness of the second doped amorphous silicon thin film, and when the thickness of the film is greater than or equal to 100 angstroms and less than 150 angstroms, the film is deposited by using a plasma chemical vapor deposition method with the power of 5KW and less; when the film thickness is more than 150 angstrom, a plasma chemical vapor deposition method with the power of 6.2KW or more is adopted to deposit the film. For example, the first layer of doped amorphous silicon film is 100 angstroms, and is deposited into a film by adopting a plasma chemical vapor deposition method with the power of 5KW or below; the first layer of the doped amorphous silicon film is 200 angstroms and is deposited into a film by adopting a plasma chemical vapor deposition method with the power of 6.2KW or more; when the third layer of the doped amorphous silicon thin film is 100, a film is formed by adopting a plasma chemical vapor deposition method with the power of 5KW or below.
Further, the range of the high radio frequency power is more than or equal to 6.2 KW; the range of the low radio frequency power is less than or equal to 5 KW.
Specifically, the value of low radio frequency power in the plasma chemical vapor deposition method is less than or equal to 5KW, and the value of high radio frequency power is greater than or equal to 6.2 KW. The high-radio-frequency power deposition film has a high deposition rate, the low-radio-frequency power deposition film has high compactness, most of free particles can be prevented from freely moving in the doping layer, the doping layer can be rapidly deposited through the layered arrangement of the low-radio-frequency power film formation and the high-radio-frequency power film formation, and most of the free particles can be prevented from freely moving in the doping layer.
Further, referring to fig. 4, fig. 4 is a flowchart illustrating a fourth embodiment of a method for manufacturing an array substrate according to the present invention, where the method for sequentially forming at least two doped amorphous silicon thin films on the active layer, and after the step of forming a doped layer by the at least two doped amorphous silicon thin films, further includes:
step S40, depositing a second metal layer on the doped layer.
Specifically, a second metal layer is deposited on the doped layer by adopting a physical vapor deposition method, and patterns required by the source electrode and the drain electrode are etched on the second metal layer by adopting a wet method, so that the source electrode and the drain electrode are formed.
The present invention further provides an array substrate, as shown in fig. 5, the array substrate 100 includes: a substrate 11; a first metal layer 12, wherein the first metal layer 12 is disposed on the substrate 11, and a gate insulating layer 13 is disposed on the first metal layer 12; an active layer 21, the active layer 21 being disposed on the gate insulating layer; and a doped layer 31, wherein the doped layer 31 comprises at least two layers of doped amorphous silicon thin films; the doped amorphous silicon thin film is manufactured by adopting a plasma chemical vapor deposition method.
It should be noted that, in this embodiment, the doped layer 31 includes at least two doped amorphous silicon thin films, at least one doped amorphous silicon thin film is deposited by using a low radio frequency power deposition method of a plasma chemical vapor deposition method, and at least one doped amorphous silicon thin film is deposited by using a high radio frequency power deposition method of a plasma chemical vapor deposition method; when the doped amorphous silicon thin film is deposited by the high radio frequency and the low radio frequency, the rate of depositing the doped amorphous silicon thin film by the low radio frequency power is lower than that of depositing the doped amorphous silicon thin film by the high radio frequency power, and the deposited doped amorphous silicon thin film by the low radio frequency power has better compactness.
A passivation layer is formed on the source and drain electrodes 41 and 42, and a pixel electrode 51 is formed on the passivation layer.
Further, the doped layer 31 includes two layers of the doped amorphous silicon thin films, and the thicknesses of the two layers of the doped amorphous silicon thin films are different.
It should be noted that, in this embodiment, the two doped amorphous silicon thin films have different thicknesses, the thicknesses of the two doped amorphous silicon thin films may be respectively 300 angstroms and 100 angstroms, the doped amorphous silicon thin film with the thickness of 300 angstroms is deposited by using high radio frequency power, the power of the high radio frequency power deposition is above 6.2KW, and the doped amorphous silicon thin film with the thickness of 300 angstroms can be rapidly deposited by using the high radio frequency power deposition; the doped amorphous silicon thin film with the thickness of 100 angstroms is deposited by adopting low radio frequency power, the power of the low radio frequency power deposition is 5.0KW or below, the doped amorphous silicon thin film deposited by adopting the low radio frequency power has better compactness, free particles can be effectively prevented from freely moving on the doped amorphous silicon thin film, and further image residue is prevented from occurring. The doped amorphous silicon thin film with the thickness of 300 angstroms is arranged on the active layer 21, and the doped amorphous silicon thin film with the thickness of 100 angstroms is arranged on the doped amorphous silicon thin film with the thickness of 300 angstroms.
In an implementation manner, the doping layer 31 includes three layers of the doped amorphous silicon thin films, the thicknesses of the three layers of the doped amorphous silicon thin films are different, and the thicknesses of the three layers of the doped amorphous silicon thin films can be 100 angstroms, 200 angstroms and 100 angstroms respectively; the doped amorphous silicon thin film with the thickness of 100 angstroms is deposited by adopting low radio frequency, the power of the low radio frequency power deposition is 5.0KW or below, and the doped amorphous silicon thin film deposited by adopting the low radio frequency power has better compactness; thickness is 200 angstroms doped amorphous silicon thin film adopts high radio frequency deposition, the power of high radio frequency power deposition is more than 6.2KW, adopts high radio frequency power deposition can deposit out 200 angstroms thickness's doped amorphous silicon thin film fast, and thickness is 200 angstroms doped amorphous silicon thin film establishes two-layer thickness and is 100 angstroms between the doped amorphous silicon thin film, is the high thickness of compactness 100 angstroms doped amorphous silicon thin film establishes in both sides, prevents more effectively that free particle from on the doped amorphous silicon thin film free movement, and then prevents that the remaining problem of image from appearing.
The invention also provides a display panel, which comprises a color film substrate and the array substrate 100; the color film substrate is mounted in the light-emitting direction of the array substrate 100.
It should be noted that, in this embodiment, the display panel is used for displaying image and text information and manufacturing a display screen, and the display panel includes a color film substrate and an array substrate, where the color film substrate is mounted in the light outgoing direction of the array substrate 100.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. The manufacturing method of the array substrate is characterized by comprising the following steps:
providing a substrate;
sequentially forming a first metal layer, a gate insulating layer and an active layer on the substrate;
sequentially forming at least two layers of doped amorphous silicon thin films on the active layer, wherein the doped amorphous silicon thin films form doped layers;
the doped amorphous silicon thin film is deposited by adopting a plasma chemical vapor deposition method, at least one layer of doped amorphous silicon thin film is deposited by adopting low radio frequency power, and at least one layer of doped amorphous silicon thin film is deposited by adopting high radio frequency power.
2. The method for manufacturing the array substrate according to claim 1, wherein the step of sequentially forming at least two doped amorphous silicon thin films on the active layer comprises:
depositing a first layer of doped amorphous silicon film on the active layer by adopting high radio frequency power;
and depositing a second layer of doped amorphous silicon film on the side, deviating from the active layer, of the first layer of doped amorphous silicon film by adopting low radio frequency power.
3. The method for manufacturing the array substrate according to claim 2, wherein the thickness of the first doped amorphous silicon thin film ranges from 200 angstroms to 300 angstroms; the thickness of the second layer of doped amorphous silicon thin film ranges from 100 angstroms to 200 angstroms.
4. The method for manufacturing the array substrate according to claim 1, wherein the step of sequentially forming at least two doped amorphous silicon thin films on the active layer comprises:
depositing a first layer of doped amorphous silicon film on the active layer by adopting low radio frequency power;
depositing a second layer of doped amorphous silicon film on the side, away from the active layer, of the first layer of doped amorphous silicon film by adopting high radio frequency power;
and depositing a third layer of doped amorphous silicon film on the side, away from the first layer of doped amorphous silicon film, of the second layer of doped amorphous silicon film by adopting low radio frequency power.
5. The method as claimed in claim 4, wherein the first doped amorphous silicon thin film has a thickness of 100-125A, the second doped amorphous silicon thin film has a thickness of 150-200A, and the third doped amorphous silicon thin film has a thickness of 100-125A.
6. The method of claim 1, wherein the high rf power is in a range of 6.2KW or more; the range of the low radio frequency power is less than or equal to 5 KW.
7. The method for manufacturing the array substrate according to claim 1, wherein after the step of sequentially forming at least two doped amorphous silicon thin films on the active layer, the method further comprises:
depositing a second metal layer on the doped layer.
8. An array substrate, comprising:
a substrate;
a first metal layer disposed on the substrate;
the grid insulation layer is arranged on the first metal layer;
an active layer disposed on the gate insulating layer; and
the doping layer comprises at least two layers of doped amorphous silicon thin films;
the doped amorphous silicon thin film is manufactured by the manufacturing method of any one of claims 1 to 7.
9. The array substrate of claim 8, wherein the doped layer comprises two doped amorphous silicon thin films, and the thicknesses of the two doped amorphous silicon thin films are different.
10. A display panel, comprising a color film substrate and the array substrate according to claim 8 or 9; the color film substrate is arranged in the light emergent direction of the array substrate.
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