WO2012169397A1 - Thin-film transistor, method for producing same, and display element - Google Patents
Thin-film transistor, method for producing same, and display element Download PDFInfo
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- WO2012169397A1 WO2012169397A1 PCT/JP2012/063877 JP2012063877W WO2012169397A1 WO 2012169397 A1 WO2012169397 A1 WO 2012169397A1 JP 2012063877 W JP2012063877 W JP 2012063877W WO 2012169397 A1 WO2012169397 A1 WO 2012169397A1
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- semiconductor layer
- drain electrode
- source electrode
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- tft
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- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 192
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- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 3
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
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- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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- 238000001039 wet etching Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Definitions
- the present invention relates to a thin film transistor, a manufacturing method thereof, and a display element, and more particularly to a thin film transistor having a semiconductor layer made of an oxide semiconductor, a manufacturing method thereof, and a display element.
- a thin film transistor (hereinafter referred to as “TFT”) having a semiconductor layer made of an oxide semiconductor such as indium gallium zinc oxide (hereinafter referred to as “IGZO”) or zinc oxide (ZnO) is made of amorphous silicon.
- TFT thin film transistor
- IGZO indium gallium zinc oxide
- ZnO zinc oxide
- the semiconductor layer made of an oxide semiconductor is reduced when the entire substrate is heated in the subsequent manufacturing process. Specifically, the semiconductor layer is deprived of oxygen by the source electrode and the drain electrode and supplied with hydrogen from the source electrode and the drain electrode. Thus, immediately after the formation of the semiconductor layer, the entire semiconductor layer is a high resistance region.
- the semiconductor layer that is in direct contact with the source electrode and the drain electrode and the semiconductor layer near the ends of those electrodes become a low resistance region, and the semiconductor layer sandwiched between the low resistance regions on both sides Is a region whose resistance value is between the low resistance region and the high resistance region (hereinafter referred to as “medium resistance region”).
- the semiconductor layer operates as a resistance element.
- Patent Document 1 discloses a TFT that can restore good transistor characteristics by easily supplying oxygen from the outside to a semiconductor layer made of an oxide semiconductor. Specifically, after forming the source electrode and the drain electrode of the TFT, an opening for exposing the surface of the semiconductor layer is formed in the source electrode and the drain electrode. Next, oxygen is supplied to the semiconductor layer from the opening by performing oxygen annealing at a high temperature. As a result, the TFT recovers good transistor characteristics.
- Patent Document 1 openings are formed in a source electrode and a drain electrode in order to supply oxygen to a semiconductor layer.
- the contact area between the source and drain electrodes and the semiconductor layer is reduced by forming the opening, the contact resistance between the source and drain electrodes and the semiconductor layer is increased.
- the transistor characteristics are adversely affected, such as a reduction in the on-current of the TFT.
- an object of the present invention is to provide a thin film transistor capable of recovering good transistor characteristics while maintaining a low contact resistance between a source electrode and a drain electrode and a semiconductor layer made of an oxide semiconductor.
- a first aspect of the present invention is a thin film transistor having a semiconductor layer formed on an insulating substrate and made of an oxide semiconductor, A gate electrode formed on the insulating substrate; A gate insulating film formed to cover the gate electrode and including at least a first silicon oxide film; A source electrode and a drain electrode formed on the gate insulating film at a predetermined distance so as to sandwich the gate electrode; The semiconductor layer formed on the gate insulating film sandwiched between the source electrode and the drain electrode, and having one end and the other end electrically connected to either the back surface or the surface of the source electrode and the drain electrode, respectively , A passivation film that covers the source electrode, the drain electrode, and the semiconductor layer and includes at least a second silicon oxide film; The semiconductor layer has a narrower width in a channel region sandwiched between the source electrode and the drain electrode than a width in a region in contact with the back surface or the front surface of the source electrode and the drain electrode, The channel region is sandwiched between the first silicon oxide film and the second silicon oxide film.
- the channel region has a first cutout at least at one end in the width direction.
- the channel region has the first notch at both ends in the width direction.
- the channel region has at least one second cutout portion along a length direction of the channel region at a position spaced inward from an end portion in the width direction.
- the gate insulating film further includes a first silicon nitride film formed on a lower surface of the first silicon oxide film
- the passivation film further includes a second silicon nitride film formed on the surface of the second silicon oxide film.
- the source electrode and the drain electrode are formed on the semiconductor layer so as to face each other with a predetermined distance therebetween,
- the semiconductor layer is formed so that the one end is electrically connected to the back surface of the source electrode and the other end is electrically connected to the back surface of the drain electrode.
- a seventh aspect of the present invention is the sixth aspect of the present invention, An etching stopper layer made of silicon oxide formed on the semiconductor layer sandwiched between the source electrode and the drain electrode; The channel region is sandwiched between two first regions each having a low resistance value formed along the ends of the source electrode and the drain electrode, and the two first regions. A second region having a resistance value higher than that of the first region, The etching stopper layer is formed so as to cover at least the second region.
- the source electrode and the drain electrode are formed on the gate insulating film so as to face each other with a predetermined distance therebetween,
- the semiconductor layer has one end covering the end of the source electrode and electrically connected to the surface of the source electrode, and the other end covering the end of the drain electrode and electrically connected to the surface of the source electrode. It is formed so that it may be connected to.
- the oxide semiconductor constituting the semiconductor layer is amorphous.
- a tenth aspect of the present invention is a method of manufacturing a thin film transistor having a semiconductor layer formed on an insulating substrate and made of an oxide semiconductor, Forming a gate electrode on the insulating substrate; Forming a gate insulating film including at least a first silicon oxide film so as to cover the gate electrode; Forming a source electrode and a drain electrode on the gate insulating film at a predetermined distance so as to sandwich the gate electrode; and Forming the semiconductor layer on the gate insulating film sandwiched between the source electrode and the drain electrode so that one end and the other end are electrically connected to the source electrode and the drain electrode, respectively; Forming a passivation film that covers the source electrode, the drain electrode, and the semiconductor layer and includes at least a second silicon oxide film; And a step of performing a heat treatment after the formation of the passivation film,
- the step of forming the semiconductor layer includes a step of providing a notch in a channel region formed of the semiconductor layer sandwiched between the source electrode and the drain electrode using a
- the step of performing the heat treatment is characterized in that the heat treatment is performed at a temperature of 200 to 400 ° C. for 1 to 2 hours in an atmosphere containing at least oxygen.
- a twelfth aspect of the invention is an active matrix type display device for displaying an image, A plurality of pixel forming portions arranged in a matrix corresponding to a plurality of gate wirings, a plurality of source wirings intersecting with the plurality of gate wirings, and intersections of the plurality of gate wirings and the plurality of source wirings, respectively.
- a display unit comprising The pixel formation portion includes a thin film transistor according to any one of the first to ninth aspects that is turned on or off according to a signal applied to a corresponding gate wiring.
- the width of the semiconductor layer in the channel region is made smaller than the width of the semiconductor layer in the region in contact with the back surface or the surface of the source / drain electrode.
- the semiconductor layer of the channel region whose side surface area is increased is sandwiched between the first silicon oxide film and the second silicon oxide film.
- oxygen from the outside and oxygen contained in the first and second silicon oxide films are supplied to the channel region, so that the area of the low resistance region formed along the end portion of the source / drain electrode is reduced.
- a channel region sandwiched between two low resistance regions becomes a high resistance region.
- the width of the semiconductor layer in contact with the back surface or the front surface of the source / drain electrode is wider than the width of the semiconductor layer in the channel region, the contact resistance between the source / drain electrode and the semiconductor layer is kept low.
- the on / off ratio of the thin film transistor can be increased while keeping the contact resistance low.
- the channel region is provided with the first notch at one end in the width direction. For this reason, oxygen from the outside and oxygen contained in the first and second silicon oxide films are also supplied to the channel region from the side surface of the first notch. Accordingly, a high resistance region is formed in the channel region, so that the off-state current of the thin film transistor can be reduced.
- the channel region is provided with first notches at both ends in the width direction. Oxygen from the outside and oxygen contained in the first and second silicon oxide films are supplied to the channel region from the side surfaces of the first notches on both sides. Accordingly, a high-resistance region having a high resistance value is formed by the channel region, so that the off-state current of the thin film transistor can be further reduced.
- the channel region is provided with the second notch at a position away from the end in the width direction to the inside. Oxygen from the outside and oxygen contained in the first and second silicon oxide films are supplied to the channel region through the second notch.
- the off-state current of the thin film transistor can be further reduced.
- the larger the number of the second notches the more oxygen is supplied to the channel region, so that the off-state current of the thin film transistor can be further reduced.
- the gate insulating film includes the first silicon nitride film
- the withstand voltage of the gate insulating film can be ensured.
- the passivation film includes the second silicon nitride film, moisture entering the thin film transistor from the outside is blocked, so that the reliability of the thin film transistor can be improved.
- the on / off ratio can be increased.
- the etching stopper layer protects the surface of the semiconductor layer from being etched when the source / drain electrodes are formed. Further, the etching stopper layer is made of silicon oxide and is formed so as to cover at least the second region of the channel region. Thus, oxygen from the outside and oxygen contained in the passivation film are supplied to the second region by heat treatment performed after the formation of the passivation film. Therefore, the resistance value of the second region can be further increased and the off-state current of the thin film transistor can be further reduced.
- the ON / OFF ratio can be increased in the thin film transistor having the bottom contact structure.
- oxygen supplied from the outside to the semiconductor layer by annealing in an atmosphere containing oxygen is more amorphous than in the case where the oxide semiconductor constituting the semiconductor layer is microcrystalline. More when it is quality. As a result, the area of the low resistance region formed in the channel region is further narrowed, and the channel region sandwiched between the two low resistance regions becomes a high resistance region having a higher resistance value. Therefore, the off current of the thin film transistor can be reduced.
- a sufficient amount of oxygen is supplied also from the side surface of the semiconductor layer by performing a heat treatment at 200 to 400 ° C. for 1 to 2 hours in an atmosphere containing at least oxygen.
- a high resistance region can be formed in the channel region of the thin film transistor.
- the on / off ratio of the switching element can be increased by using the thin film transistor according to any one of the first to ninth inventions as the switching element of the pixel forming portion. .
- the display quality of the display device can be improved.
- FIGS. 4A to 4D are process cross-sectional views showing respective manufacturing processes of the TFT shown in FIG. (A) to (C) are process cross-sectional views showing respective manufacturing processes of the TFT shown in FIG.
- (A) is a figure which shows the positional relationship of a foreign material and a channel area
- (B) is a figure which shows the positional relationship of the foreign material and channel region at the time of providing a notch part in the both ends of a channel part. It is a figure which shows the influence of multiple reflection, and more specifically, (A) is a figure which shows the influence of multiple reflection when notch portions are not provided at both ends of the channel part, and (B) is the both ends of the channel part.
- (A) is a top view which shows the structure of the bottom gate type TFT which concerns on the modification of this embodiment
- (B) is a cross-sectional view of the TFT along the cutting line CC shown in (A)
- (C) is a cross-sectional view of the TFT along the cutting line DD shown in (A).
- (A) is a plane which shows the structure of the bottom gate type TFT which concerns on the 2nd Embodiment of this invention.
- FIG. 1 is a cross-sectional view of the TFT along the cutting line EE shown in (A)
- (C) is a cross-sectional view of the TFT along the cutting line FF shown in (A).
- FIG. It is a figure which shows the structure of the top gate type TFT which concerns on the 3rd Embodiment of this invention, More specifically, (A) is a plane which shows the structure of the top gate type TFT which concerns on the 3rd Embodiment of this invention.
- (B) is a cross-sectional view of the TFT along the cutting line GG shown in (A)
- (C) is a cross-sectional view of the TFT along the cutting line HH shown in (A).
- FIGS. 10A to 10D are process cross-sectional views illustrating respective manufacturing processes of the TFT shown in FIG.
- FIGS. 10A to 10C are process cross-sectional views showing respective manufacturing processes of the TFT shown in FIG. It is a figure which shows the structure of the bottom gate type TFT which concerns on the 4th Embodiment of this invention, More specifically, (A) is a plane which shows the structure of the bottom gate type TFT which concerns on the 4th Embodiment of this invention. (B) is a cross-sectional view of the TFT along the cutting line JJ shown in (A), and (C) is a cross-sectional view of the TFT along the cutting line KK shown in (A).
- FIGS. 14A to 14D are process cross-sectional views showing respective manufacturing processes of the TFT shown in FIG.
- FIGS. 14A to 14C are process cross-sectional views showing respective manufacturing processes of the TFT shown in FIG.
- It is a block diagram which shows the structure of the liquid crystal display device containing TFT shown in FIG.
- FIG. 17 is a plan view showing a pattern arrangement in a pixel formation portion provided in the liquid crystal panel shown in FIG. 16.
- FIG. 1 is a diagram showing a configuration of a bottom gate type TFT 100 according to the first embodiment of the present invention. More specifically, FIG. 1A shows a bottom gate type TFT according to the first embodiment of the present invention.
- FIG. 1B is a plan view showing the structure of the TFT 100
- FIG. 1B is a cross-sectional view of the TFT 100 along the cutting line AA shown in FIG. 1A
- FIG. 2 is a cross-sectional view of the TFT 100 taken along a cutting line BB shown in FIG.
- FIGS. 1A to 1C the structure of the TFT 100 will be described.
- a gate electrode 20 is formed on a transparent insulating substrate 15 such as a glass substrate.
- the gate electrode 20 may be made of any metal among, for example, titanium (Ti), molybdenum (Mo), aluminum (Al), tantalum (Ta), chromium (Cr), etc.
- Ti titanium
- Mo molybdenum
- Al aluminum
- Ta tantalum
- Cr chromium
- it may be constituted by a laminated metal film in which titanium, aluminum, and titanium are laminated in order from the surface side of 15.
- a gate insulating film 30 is formed so as to cover the entire insulating substrate 15 including the gate electrode 20.
- the gate insulating film 30 is formed by stacking a silicon oxide (SiO 2 ) film 32 (also referred to as “first silicon oxide film”) on a silicon nitride (SiNx) film 31 (also referred to as “first silicon nitride film”). It is comprised by the laminated insulating film.
- the reason why the silicon nitride film 31 is included is to ensure the withstand voltage of the gate insulating film 30.
- the reason why the silicon oxide film 32 is stacked on the silicon nitride film 31 is as follows. The first reason is to facilitate supply of oxygen from the silicon oxide film 32 to the semiconductor layer 40 described later. The second reason is that if the semiconductor layer 40 is formed on the surface of the silicon nitride film 31, a trap is formed at the interface and the reliability of the TFT 100 is likely to be lowered.
- An island-shaped semiconductor layer 40 is formed at a position on the surface of the gate insulating film 30 corresponding to the gate electrode 20.
- the semiconductor layer 40 is made of IGZO (indium gallium zinc oxide) containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O), and IGZO is an oxide semiconductor.
- IGZO indium gallium zinc oxide
- each end in the width direction of a region sandwiched between the source electrode 60a and the drain electrode 60b is cut out in a rectangular shape.
- the width of the region 40a (hereinafter referred to as “channel region 40a”) sandwiched between the source electrode 60a and the drain electrode 60b of the semiconductor layer 40 is narrower than the width of the lower portion of the source electrode 60a and the drain electrode 60b. ing.
- the channel region 40a sandwiched between the regions 41 from which the semiconductor layer 40 has been cut includes an end portion of the source electrode 60a and the drain electrode 60b.
- Two low-resistance regions 40b (also referred to as “first regions”) reduced by the source electrode 60a and the drain electrode 60b are formed along the end portions of the first and second electrodes.
- a high resistance region 40c (also referred to as “second region”) having a high resistance value is formed in the center of the channel region 40a sandwiched between the two low resistance regions 40b.
- the film thickness of the semiconductor layer 40 is preferably about 40 to 50 nm. This is because the following problems occur. That is, when the film thickness of the semiconductor layer 40 is thinner than 40 ⁇ m, the transistor characteristics of the TFT 100 become unstable, and the threshold voltage shifts due to temperature and gate stress voltage. On the other hand, when the film thickness is thicker than 50 nm, the controllability by the gate voltage is deteriorated, resulting in a problem that the off-current is increased.
- IGZO used as the semiconductor layer 40 of the TFT 100 contains indium, gallium, and zinc in the same ratio. However, they may be included in different proportions.
- the IGZO constituting the semiconductor layer 40 is most preferably amorphous, but may be microcrystalline.
- An oxide semiconductor that can be used as the semiconductor layer 40 of the TFT 100 is not limited to IGZO, and may be an In—Zn—O system, an In—Zn—Sn—O system, an In—Zn—Si—O system, or the like. Good. Specifically, IZO (indium zinc oxide), ITO (indium tin oxide), ZnO, SnO (tin oxide), WO (tungsten oxide), IO (indium oxide), or the like may be used.
- the source electrode 60a and the drain electrode 60b are arranged on the upper surface of the semiconductor layer 40 so as to face each other with a predetermined distance.
- the source electrode 60 a is formed so as to extend from the upper left surface of the semiconductor layer 40 to the left gate insulating film 30.
- the drain electrode 60 b is formed so as to extend from the right upper surface of the semiconductor layer 40 to the right gate insulating film 30.
- the low resistance region 40b of the channel region 40a is formed not only in the channel region 40a but also in the semiconductor layer 40e protruding in the width direction from the side surfaces of the source electrode 60a and the drain electrode 60b.
- the semiconductor layer 40e protruding from the side surface is for securing an alignment margin when forming the source electrode 60a and the drain electrode 60b, and its width is 1/10 of the width of the source electrode 60a and the drain electrode 60b. It is as follows.
- the low resistance region formed in the semiconductor layer 40e protruding from the side surface is not directly related to the present invention, the description thereof is omitted in this specification.
- the source electrode 60a and the drain electrode 60b may be made of any metal among, for example, titanium, aluminum, tantalum, tungsten, molybdenum, gold (Au), and the like, and from the surface side of the insulating substrate 15.
- titanium, aluminum, tantalum, tungsten, molybdenum, gold (Au), and the like may be comprised by the laminated metal film which laminated
- the right end portion of the source electrode 60a is disposed above the left side portion of the gate electrode 20, and the left end portion of the drain electrode 60b is disposed above the right side portion of the gate electrode 20. For this reason, when a predetermined voltage is applied to the gate electrode 20, electrons are induced in each low resistance region 40 b of the semiconductor layer 40 by the electric field from the gate electrode 20, thereby forming a high concentration carrier layer. By forming the high concentration carrier layer, the source electrode 60a and the drain electrode 60b are ohmically connected to the two low resistance regions 40b, respectively.
- a passivation film 90 is formed so as to cover the entire insulating substrate 15 including the source electrode 60a and the drain electrode 60b.
- the passivation film 90 is made of silicon oxide having a thickness of 200 to 300 nm (also referred to as “second silicon oxide film”).
- the passivation film 90 is a stacked insulating film in which a silicon oxide film (also referred to as “second silicon oxide film”) and a silicon nitride film (also referred to as “second silicon nitride film”) are sequentially stacked. May be. In this case, moisture entering from the outside is blocked by the silicon nitride film, so that each component of the TFT 100 can be prevented from being corroded by moisture. Thereby, the reliability of the TFT 100 can be ensured.
- a region where two low resistance regions 40b and a high resistance region 40c sandwiched between them are combined, that is, a region sandwiched between the source electrode 60a and the drain electrode 60b is referred to as a channel region 40a.
- a TFT in which a source electrode and a drain electrode covering a part of the upper surface of the semiconductor layer are sometimes referred to as a top contact TFT.
- a TFT in which the surface of the channel region is not covered with an etching stopper layer is sometimes referred to as a channel-etched TFT. Therefore, the TFT 100 is a TFT with a top contact structure and a TFT with a channel etch structure.
- FIGS. 2A to 2D and FIGS. 3A to 3C are process cross-sectional views showing each manufacturing process of the TFT 100.
- FIG. 2A to 2D and FIGS. 3A to 3C are process cross-sectional views showing each manufacturing process of the TFT 100.
- a metal film (not shown) to be the gate electrode 20 is formed on the insulating substrate 15 by a sputtering method so as to have a film thickness of 100 to 300 nm.
- a resist pattern (not shown) is formed on the surface of the metal film using a photolithography method.
- the metal film is etched by wet etching using the resist pattern as a mask to form the gate electrode 20. Thereafter, the resist pattern is peeled off.
- the insulating substrate 15 including the gate electrode 20 is switched by using a plasma chemical vapor deposition method (Chemical Vapor Deposition: hereinafter referred to as “plasma CVD method”) to switch the source gas.
- plasma CVD method Chemical Vapor Deposition: hereinafter referred to as “plasma CVD method”
- a silicon nitride film 31 and a silicon oxide film 32 are successively formed so as to cover the whole, and a gate insulating film 30 is formed.
- the thickness of the gate insulating film 30 is 300 to 400 nm.
- the thickness of the silicon oxide film 32 is preferably about 50 to 60% of the thickness of the gate insulating film 30.
- substrate temperature is set to 300 to 400 ° C.
- the oxide semiconductor film 45 is formed over the gate insulating film 30 by a sputtering method.
- the oxide semiconductor film 45 is made of, for example, IGZO containing indium, gallium, zinc, and oxygen.
- the oxide semiconductor film 45 uses a target in which indium oxide (In 2 O 3 ), gallium oxide (Ga 2 O 3 ), and zinc oxide (ZnO) are mixed in an equimolar amount and sintered, and DC (Direct Current).
- a film is formed by sputtering.
- the thickness of the oxide semiconductor film 45 is 40 to 50 nm.
- Sputtering is performed by introducing argon (Ar) gas having a flow rate of 100 to 300 sccm and oxygen (O 2 ) gas having a flow rate of 5 to 20 sccm into the chamber.
- the substrate temperature at this time is set to 200 to 400.degree. Since the oxide semiconductor film 45 immediately after deposition contains a large amount of oxygen, the entire oxide semiconductor film 45 is a high resistance region. Note that the oxide semiconductor film 45 may be formed by a coating method instead of the sputtering method.
- an amorphous IGZO film is formed by the above-described method, and then in an air atmosphere at 400 to 500 ° C. for about 1 to 2 hours. Annealing is performed.
- RTA Rapid Thermal Anneal
- RTA may be performed in an inert gas atmosphere such as nitrogen (N 2 ) instead of annealing in an air atmosphere. RTA is performed, for example, at 500 to 750 ° C. for about 1 to 10 minutes.
- a resist pattern 48 is formed on the surface of the oxide semiconductor film 45.
- the oxide semiconductor film 45 is etched by dry etching to form an island-shaped semiconductor layer 40.
- the resist pattern 48 is peeled off.
- notches are formed at both ends in the width direction of the channel region of the semiconductor layer 40. Note that in the process of forming the semiconductor layer 40 having the notch, it is only necessary to replace the mask with a changed pattern, and there is no need to change the process or add a new process.
- a source metal film (not shown) is formed by sputtering.
- the film thickness of the formed source metal film is 100 to 300 nm.
- a resist pattern 68 separated left and right at a predetermined distance is formed on the source metal film above the gate electrode 20 by photolithography. Since the distance between the left and right ends of the resist pattern 68 is formed to be shorter than the length of the gate electrode 20, the resist pattern 68 covers the left and right ends of the gate electrode 20.
- the source metal film is etched by dry etching to form a source electrode 60a and a drain electrode 60b.
- the source electrode 60 a extends from the upper left surface of the semiconductor layer 40 to the left gate insulating film 30.
- the drain electrode 60 b extends from the right upper surface of the semiconductor layer 40 to the right gate insulating film 30.
- the resist pattern 68 is peeled off.
- the etching stopper layer is not formed on the surface of the semiconductor layer 40, in order to suppress the etching of the surface of the semiconductor layer 40 as much as possible, an etching condition with a high selectivity between the source metal film and the semiconductor layer 40 is used. It is preferable to etch the source metal film.
- a passivation film 90 made of silicon oxide is formed by plasma CVD so as to cover the entire insulating substrate 15 including the source electrode 60a and the drain electrode 60b.
- the passivation film 90 is in contact with the semiconductor layer 40.
- the passivation film 90 is preferably made of silicon oxide in order to supply oxygen to IGZO constituting the semiconductor layer 40, and the film thickness is preferably 200 to 300 nm.
- the substrate temperature during film formation is 200 to 300.degree.
- the low resistance region 40b is formed in the vicinity of the source electrode 60a and the drain electrode 60b of the semiconductor layer 40 along the end portions thereof. Further, oxygen is also released from the high resistance region sandwiched between the two low resistance regions 40b, and the middle resistance region 40d is formed.
- annealing also referred to as “heat treatment” is performed in a dry air atmosphere at 200 to 400 ° C. for about 1 to 2 hours.
- oxygen from the outside and oxygen from silicon oxide constituting the passivation film 90 are supplied to the semiconductor layer 40 in which oxygen is reduced.
- the area of the low resistance region 40b formed at the time of forming the passivation film 90 is reduced, and oxygen is also supplied to the middle resistance region 40d to become the high resistance region 40c.
- annealing may be performed not in a dry air atmosphere but in an oxygen atmosphere or an atmosphere containing oxygen.
- the annealing of the passivation film 90 may be performed in an oxygen-free atmosphere, for example, a nitrogen atmosphere. Also in this case, a TFT having normal transistor characteristics is manufactured. This is presumably because oxygen was supplied from silicon oxide constituting the passivation film 90 or excessive oxygen was present in the channel region 40a.
- the Oxidation of the oxide semiconductor in the channel region 40a proceeds by incorporating oxygen, and the area of the low-resistance region 40b becomes narrow, and the middle-resistance region 40d becomes a high-resistance region 40c having a higher resistance value. Accordingly, the off current of the TFT 100 becomes 1 ⁇ 10 ⁇ 10 to 10 ⁇ 11 A, and the TFT 100 sufficiently functions as a switching element of the liquid crystal display device.
- the width of the source electrode 60a and the drain electrode 60b is made wider than the width of the channel region 40a of the semiconductor layer 40, and the surface of the semiconductor layer 40 is exposed to the source electrode 60a and the drain electrode 60b. There is no opening. Thereby, since the source electrode 60a and the drain electrode 60b are in electrical contact with the semiconductor layer 40 over the entire back surface, the contact resistance between the source electrode 60a and the drain electrode 60b and the semiconductor layer 40 can be kept low. As a result, a decrease in the on-current of the TFT 100 can be prevented, so that the on / off ratio can be increased.
- the oxygen supplied to the semiconductor layer 40 from the outside by annealing in a dry air atmosphere is larger when the oxide semiconductor constituting the semiconductor layer 40 is amorphous than when it is microcrystalline. Accordingly, when the oxide semiconductor is amorphous, the channel region 40a is further oxidized and the area of the low-resistance region 40b is further narrowed and the medium-resistance region is smaller than when the oxide semiconductor is microcrystalline. 40d becomes a high resistance region 40c having a higher resistance value. This is considered to be because oxygen from the outside is hardly supplied to the channel region 40a because the film density of the oxide semiconductor made of microcrystals is high.
- FIG. 4 is a diagram showing the positional relationship between the foreign matter 99 and the channel region 40a. More specifically, FIG. 4A shows the foreign matter 99 and the channel region when notch portions are not provided at both ends of the channel region 44a. 4B is a diagram showing the positional relationship between the foreign matter 99 and the channel region 40a when the notch portions 41 are provided at both ends of the channel region 40a.
- etching gas for example, a fluorine-based gas such as methane tetrafluoride (CF 4 ), or boron trichloride (BCl 3 ) or Cl 2 (chlorine). Chlorine gas such as) is used.
- a fluorine-based gas such as methane tetrafluoride (CF 4 ), or boron trichloride (BCl 3 ) or Cl 2 (chlorine).
- CF 4 methane tetrafluoride
- BCl 3 boron trichloride
- Cl 2 Cl 2
- These metal fluorides or metal chlorides adhering to the inner wall of the plasma CVD apparatus at the time of etching may be peeled off from the inner wall during the etching or after the etching is finished and fall onto the source metal film.
- one end of the fallen foreign material 99 is in electrical contact with the low resistance region 44b of the semiconductor layer 44 adjacent to the source electrode 60a in the subsequent process, and the other end is In some cases, the low resistance region 40b of the semiconductor layer 44 adjacent to the drain electrode 60b is in electrical contact.
- the source electrode 60a and the drain electrode 60b are short-circuited by being electrically connected via the two low-resistance regions 44b and the foreign matter 99.
- the TFT 100 even if the foreign matter 99 made of metal chloride or metal fluoride falls at the same position as in FIG. A notch 41 is formed by etching when the layer 40 is formed. In this case, the position where the foreign material 99 has fallen is the cutout portion 41, and thus the low resistance region 40b is not formed. For this reason, the source electrode 60a and the drain electrode 60b are not short-circuited by the foreign matter 99. Thus, in the TFT 100, the possibility of a short circuit between the source electrode 60a and the drain electrode 60b due to the foreign matter 99 can be reduced.
- FIG. 5 is a diagram showing the influence of multiple reflection. More specifically, FIG. 5A is a diagram showing the influence of multiple reflection when notches are not provided at both ends of the channel region 44a. FIG. 5B is a diagram showing the influence of multiple reflection when notches 41 are provided at both ends of the channel region 40a. As shown in FIG. 5A, the backlight light applied to the conventional TFT from the back surface side is directed toward the channel region 44a while being repeatedly reflected between the surface of the gate electrode 20 and the back surface of the drain electrode 60b. Go ahead.
- the backlight light When the backlight light reaches the channel region 44a, it is absorbed by the semiconductor layer 44 in the channel region 44a and generates conduction electrons in the channel region 44a. As described above, in a TFT not provided with a notch, a current easily flows due to multiple reflection of backlight light.
- the backlight light traveling while repeating multiple reflections between the surface of the gate electrode 20 and the back surface of the drain electrode 60b is The channel region 40a of the semiconductor layer 40 is reached.
- the cutout portion 41 the backlight light passes through the cutout portion 41.
- the backlight light is not absorbed by the channel region 40a, conduction electrons are not generated in the channel region 40a. For this reason, in TFT100, the electric current by the multiple reflection of backlight light can be suppressed.
- FIG. 6 is a diagram showing the relationship between the channel length and the channel width at the time of designing to operate as the TFT 100.
- FIG. 7 is an expected plan view showing the shape of the low resistance region, and more specifically, FIG. 7A is an expected plan view showing the shape of the low resistance region 44b in the case where the notch portion is not provided.
- FIG. 7B is an expected plan view showing the shape of the low resistance region 40b when the notch 41 is provided.
- the length of the low resistance region 40b in the channel direction formed in the channel region 40a is assumed to be constant regardless of the channel width. However, in practice, as shown in FIG. 6, when the channel width becomes narrower than 20 ⁇ m, the phenomenon that the channel length also becomes short accompanying it appears.
- the length of the low resistance region 44b in the channel direction is not constant but varies irregularly according to the channel width.
- the tip of the low resistance region 44b on the source electrode 60a side and the tip of the low resistance region 44b on the drain electrode 60b side overlap.
- the source electrode 60a and the drain electrode 60b may be electrically connected (see FIG. 7A).
- the TFT since the current cannot be controlled by the gate electrode 20, it always flows between the current source electrode 60a and the drain electrode 60b. In this case, the TFT operates not as a transistor but as a resistance element.
- the notch 41 is provided in the channel region 40 a of the semiconductor layer 40, the low resistance region 40 b is not formed in the notch 41. Therefore, as shown in FIG. 7B, when a portion (a portion indicated by a dotted line) in which the length in the channel direction of the low resistance region 40b is increased is formed at the same position as FIG. It is possible to prevent the tip of the low resistance region 40b on the source electrode 60a side and the tip of the low resistance region 40b on the drain electrode 60b side from overlapping each other. In addition, it is expected that the irregular shape change of the low resistance region 40b is suppressed to some extent by providing the notch 41. From these things, it is presumed that the possibility that the tips of the low resistance regions 40b overlap each other is reduced. For this reason, it is estimated that the TFT 100 is less likely to operate as a resistance element.
- FIG. 8 is a diagram illustrating a configuration of a bottom gate TFT 200 according to a modification of the present embodiment. More specifically, FIG. 8A illustrates a configuration of the bottom gate TFT 200 according to a modification of the present embodiment.
- 8B is a cross-sectional view of the TFT 200 along the cutting line CC shown in FIG. 8A
- FIG. 8C is a cross-sectional view shown in FIG. 8A.
- FIG. 10 is a cross-sectional view of the TFT 200 along line DD.
- the constituent elements of the TFT 200 the same constituent elements as those of the TFT 100 shown in FIGS. 1A to 1C are denoted by the same reference numerals, and different constituent elements will be mainly described.
- a notch 41 is provided only at one end of the channel region 40a.
- the width of the channel region 40a is wider in the TFT 200 than in the TFT 100.
- the same effects as the effects exhibited by the TFT 100 can be obtained.
- the notch 41 of the TFT 200 is provided only on one side, the effect is half of the effect produced by the TFT 100.
- FIG. 9 is a diagram showing a configuration of a bottom gate type TFT 300 according to the second embodiment of the present invention. More specifically, FIG. 9A shows a bottom gate type TFT according to the second embodiment of the present invention. 9B is a plan view showing the structure of the TFT 300, FIG. 9B is a cross-sectional view of the TFT 300 along the cutting line EE shown in FIG. 9A, and FIG. 9C is FIG. 2 is a cross-sectional view of the TFT 300 taken along a cutting line FF shown in FIG.
- the constituent elements of the TFT 300 the same constituent elements as those of the TFT 100 shown in FIGS. 1A to 1C are denoted by the same reference numerals, and different constituent elements will be mainly described.
- the notches 41 are provided at both ends of the channel region 40a of the semiconductor layer 40, but also the channel region 40a.
- a notch 42 (also referred to as “second notch”) is also provided at the center of the notch.
- the notch 42 has a rectangular shape whose length in the channel direction is determined by the ends of the source electrode 60a and the drain electrode 60b. In the cutout portion 42, the semiconductor layer 40 is cut off, so that the surface of the silicon oxide film 32 underneath is exposed.
- the mask used for forming the semiconductor layer 40 in the process shown in FIG. 2C among the manufacturing processes of the TFT 100 described in the first embodiment is replaced with a new notch 42. It is only necessary to replace the mask with the opening pattern to be added, and there is no need to change the process or add a new process.
- the channel region 40a has a rectangular notch whose length in the channel direction is determined by the ends of the source electrode 60a and the drain electrode 60b not only at both ends but also in the center. A portion 42 is formed.
- the TFT 300 has the same effect as that of the TFT 100. Specifically, by providing the notch portion 42, the area of the side surface of the semiconductor layer 40 is further increased. Therefore, oxygen from the outside and the silicon oxide film 32 are formed in the low resistance region 40b and the middle resistance region 40d. In addition, oxygen contained in the passivation film 90 is easily supplied.
- the oxide semiconductor constituting the channel region 40a is further oxidized by taking in more oxygen, and the area of the low resistance region 40b is further narrowed.
- the middle resistance region 40d becomes a high resistance region 40c having a higher resistance value. Therefore, the off current (leakage current) of the TFT 300 is 1 ⁇ 10 ⁇ 10 to 10 ⁇ 11 A, and the TFT 300 functions sufficiently as a switching element of the liquid crystal display device.
- the source electrode 60a and the drain electrode 60b are short-circuited by foreign matters generated when the source electrode 60a and the drain electrode 60b are formed, or the backlight is subjected to multiple reflection between the surface of the gate electrode 20 and the surface of the drain electrode 60b. It is possible to further reduce the possibility that a current is generated due to this. Furthermore, since the low resistance region 40b on the source electrode 60a side and the low resistance region 40b on the drain electrode 60b side overlap, the possibility that the source electrode 60a and the drain electrode 60b are short-circuited can be further reduced.
- the cutout portion 42 is formed at the center of the channel region 40a in the channel width direction.
- one or a plurality of the cutout portions 42 may be formed at an arbitrary position in the channel region 40a.
- one or a plurality of the notch portions 42 are formed at positions away from the end portions of the channel region 40a. May be.
- FIG. 10 is a diagram illustrating a configuration of a top-gate thin film transistor 400 according to the third embodiment of the present invention. More specifically, FIG. 10A illustrates a top according to the third embodiment of the present invention.
- FIG. 10B is a cross-sectional view of the TFT 400 taken along a cutting line GG shown in FIG. 10A
- FIG. 10C is a plan view showing the structure of the gate type thin film transistor 400.
- FIG. 11 is a cross-sectional view of the TFT 400 taken along a cutting line HH shown in FIG.
- the same components as those of the TFT 100 shown in FIGS. 1A to 1C are denoted by the same reference numerals, and different components will be mainly described.
- the source electrode 70a and the drain electrode 70b are formed on the gate insulating film 30 including the silicon nitride film 31 and the silicon oxide film 32. Is formed.
- a semiconductor layer 50 is formed on the surfaces of the source electrode 70a and the drain electrode 70b.
- the semiconductor layer 50 is electrically connected to the source electrode 70a and the drain electrode 70b on the back surface thereof.
- notches 51 hereinafter also referred to as “notches” or “first notches” are formed at both ends in the channel width direction.
- the entire insulating substrate 15 including the semiconductor layer 50, the source electrode 70 a and the drain electrode 70 b is covered with a passivation film 90.
- a region where two low resistance regions 50b and a high resistance region 50c sandwiched between them are combined, that is, a region sandwiched between the source electrode 60a and the drain electrode 60b is referred to as a channel region 50a.
- FIG. 11A to FIG. 11D and FIG. 12A to FIG. 12C are process cross-sectional views showing each manufacturing process of the TFT 400.
- FIGS. 11 (A) to 11 (D) and FIGS. 12 (A) to 11 (C) FIGS. 2 (A) to 2 (D) and FIGS. 3 (A) to 3
- the same steps as those shown in (C) will be briefly described, and different steps will be mainly described.
- membrane formed at each process, process conditions, etc. are the same as the case of 1st Embodiment, those description is abbreviate
- the gate electrode 20 is formed on the insulating substrate 15.
- a gate insulating film 30 including a silicon nitride film 31 and a silicon oxide film 32 is formed so as to cover the insulating substrate 15 including the gate electrode 20.
- a source metal film 75 is formed on the gate insulating film 30 by a sputtering method.
- a resist pattern 78 having an opening is formed over the gate electrode 20, the source metal film 75 is etched using the resist pattern 78 as a mask, and a source electrode 70a and a drain electrode 70b are formed. Form. Thereafter, the resist pattern 78 is peeled off.
- oxidation is performed by sputtering so as to cover the entire insulating substrate 15 including the gate insulating film 30, the source electrode 70a, and the drain electrode 70b sandwiched between the source electrode 70a and the drain electrode 70b.
- a physical semiconductor film 55 is formed.
- a resist pattern 58 is formed on the oxide semiconductor film 55 above the gate electrode 20 using a mask in which a pattern for forming the channel region 50a is formed. Since the oxide semiconductor film 55 immediately after film formation contains a large amount of oxygen, the entire oxide semiconductor film 55 is a high resistance region.
- the oxide semiconductor film 55 is etched using the resist pattern 58 as a mask to form the semiconductor layer 50. Thereafter, the resist pattern 58 is removed, and a passivation film 90 is formed so as to cover the entire insulating substrate 15 including the semiconductor layer 50, the source electrode 70a, and the drain electrode 70b.
- the insulating substrate 15 is heated when the passivation film 90 is formed. For this reason, the source electrode 70 a and the drain electrode 70 b take oxygen from the semiconductor layer 50 and supply the hydrogen to the semiconductor layer 50, thereby reducing the semiconductor layer 50.
- a low resistance region 50b (also referred to as “first region”) is formed in the semiconductor layer 50 close to the source electrode 70a and the drain electrode 70b. Further, oxygen is also released from the high resistance region sandwiched between the two low resistance regions 50b, and the middle resistance region 50d is formed.
- oxygen from the outside and oxygen contained in the silicon oxide film 32 and the passivation film 90 are supplied to the channel region 50a of the semiconductor layer 50 by annealing in a dry air atmosphere. .
- the area of the low resistance region 50b is reduced, and the resistance value of the middle resistance region 50d is increased to become the high resistance region 50c (also referred to as “second region”).
- the area of the low-resistance region 50b of the channel region 50a is narrowed and the channel region sandwiched between the low-resistance regions 50b is the same as the effect exhibited by the TFT 100 according to the first embodiment.
- a high resistance region 50c is formed in 50a. Further, it is possible to reduce the possibility that the source electrode 70a and the drain electrode 70b are short-circuited by a foreign substance, or that current is generated due to multiple reflection of backlight light. Furthermore, the possibility that the source electrode 70a and the drain electrode 70b are short-circuited by the overlap of the low resistance region 50b on the source electrode 70a side and the low resistance region 50b on the drain electrode 70b side can be reduced.
- FIG. 13 is a diagram showing a configuration of a bottom gate type TFT 500 according to the fourth embodiment of the present invention. More specifically, FIG. 13A shows a bottom gate type TFT according to the fourth embodiment of the present invention.
- FIG. 13B is a cross-sectional view of the TFT 500 taken along a cutting line JJ shown in FIG. 13A
- FIG. 13C is a plan view showing the structure of the TFT 500.
- FIG. 2 is a cross-sectional view of the TFT 500 along the cutting line KK shown in FIG.
- the constituent elements of the TFT 500 the same constituent elements as those of the TFT 100 shown in FIGS. 1A to 1C are denoted by the same reference numerals, and different constituent elements will be mainly described.
- both end portions of the channel region 40a of the semiconductor layer 40 are removed by etching to form a notch 41.
- the etching stopper layer 80 is formed on the channel region 40 a of the semiconductor layer 40. The etching stopper layer 80 protects the surface of the semiconductor layer 40 from being etched when the source metal film is etched to form the source electrode 60a and the drain electrode 60b.
- the etching stopper layer 80 is made of silicon oxide. For this reason, as will be described later, the etching stopper layer 80 can supply oxygen to the channel region 40 a of the semiconductor layer 40 together with the passivation film 90. Note that a TFT in which an etching stopper layer is formed on the surface of a semiconductor layer like the TFT 500 may be referred to as an etch stop TFT.
- FIGS. 14A to 14D and FIGS. 15A to 15C are process cross-sectional views illustrating each manufacturing process of the TFT 500.
- the same steps as those shown in (C) will be briefly described, and different steps will be mainly described.
- membrane formed in each process, process conditions, etc. are the same as the case of 1st Embodiment, those description is abbreviate
- the gate electrode 20 is formed on the insulating substrate 15.
- a gate insulating film 30 composed of a silicon nitride film 31 and a silicon oxide film 32 is formed so as to cover the entire insulating substrate 15 including the gate electrode 20.
- An oxide semiconductor film (not shown) is formed on the gate insulating film 30 by a sputtering method. Since the oxide semiconductor film immediately after deposition contains a large amount of oxygen, the entire oxide semiconductor film is a high-resistance region. As shown in FIG. 14C, a resist pattern 48 is formed over the oxide semiconductor film above the gate electrode 20. The oxide semiconductor film is etched using the resist pattern 48 as a mask to form the semiconductor layer 40. Thereafter, the resist pattern 48 is peeled off.
- a silicon oxide film 85 is formed by plasma CVD so as to cover the entire insulating substrate 15 including the semiconductor layer 40.
- the thickness of the silicon oxide film 85 is 50 to 200 nm.
- a resist pattern 88 is formed on the silicon oxide film 85.
- the silicon oxide film 85 is etched using the resist pattern 88 as a mask to form an etching stopper layer 80.
- the resist pattern 88 is peeled off, and a source metal film 65 is formed using a sputtering method so as to cover the entire insulating substrate 15 including the etching stopper layer 80.
- a resist pattern 68 separated on the left and right on the etching stopper layer is formed on the source metal film 65.
- the source metal film 65 is etched using the resist pattern 68 as a mask to form a source electrode 60a and a drain electrode 60b separated on the left and right on the etching stopper layer 80. Thereafter, the resist pattern 68 is peeled off.
- the entire insulating substrate 15 including the etching stopper layer 80, the source electrode 60a, and the drain electrode 60b is covered with a passivation film 90.
- the insulating substrate 15 is heated when the passivation film 90 is formed. Therefore, the source electrode 60 a and the drain electrode 60 b take oxygen from the semiconductor layer 40 and reduce the semiconductor layer 40 by supplying hydrogen to the semiconductor layer 40.
- the low resistance region 40b is formed in the semiconductor layer 40 in the vicinity of the ends of the source electrode 60a and the drain electrode 60b. Since the etching stopper layer is formed on the high resistance region sandwiched between the two low resistance regions 40b, oxygen is not easily released from the high resistance region and remains as the high resistance region 40c.
- oxygen is supplied from the silicon oxide constituting the etching stopper layer 80 to the IGZO constituting the channel region 40a.
- the low resistance region 40b takes in oxygen and its area becomes narrow.
- the area of the low-resistance region 40b of the channel region 40a is narrowed and the channel region sandwiched between the low-resistance regions 40b is the same as the effect exhibited by the TFT 100 according to the first embodiment.
- a high resistance region 40c is formed in 40a.
- the possibility that the source electrode 60a and the drain electrode 60b are short-circuited by the overlap of the low resistance region 40b on the source electrode 60a side and the low resistance region 40b on the drain electrode 60b side can be reduced.
- TFT> typical TFTs 100 to 500 are described among TFTs to which the present invention can be applied. However, other TFTs obtained by appropriately combining these TFTs 100 to 500 have the same effect.
- the notch 51 of the semiconductor layer 50 is provided not only at both ends in the width direction of the channel region 50a, but also by providing one or more between them. May be.
- the TFT 500 with the TFT 500, in the channel stop structure TFT one or a plurality of notches 41 of the semiconductor layer 40 are provided not only at both ends in the width direction of the channel region 40a but also between them. May be.
- the notch 51 of the semiconductor layer 50 is formed on one side in the width direction of the channel region 50a and on the inner side along the length direction of the channel region 50a. One or more may be provided at the position.
- FIG. 16 is a block diagram showing a configuration of the liquid crystal display device 10 including the TFT 100 according to the first embodiment.
- a liquid crystal display device 10 illustrated in FIG. 16 includes a liquid crystal panel 2 (also referred to as a “display unit”), a display control circuit 3, a gate driver 4, and a source driver 5.
- the liquid crystal panel 2 includes n (n is an integer of 1 or more) gate wirings G1 to Gn extending in the horizontal direction and m (m is an integer of 1 or more) extending in a direction intersecting the gate wirings G1 to Gn.
- Source wirings S1 to Sm are formed.
- Pixel forming portions Pij are arranged near intersections of the i-th gate line Gi (i is an integer of 1 to n) and the j-th source line Sj (j is an integer of 1 to m). .
- the display control circuit 3 is supplied with a control signal SC such as a horizontal synchronizing signal and a vertical synchronizing signal and an image signal DT from the outside of the liquid crystal display device 10. Based on these signals, the display control circuit 3 outputs a control signal SC1 to the gate driver 4, and outputs a control signal SC2 and an image signal DT to the source driver 5.
- a control signal SC such as a horizontal synchronizing signal and a vertical synchronizing signal and an image signal DT
- the gate driver 4 is connected to the gate lines G1 to Gn, and the source driver 5 is connected to the source lines S1 to Sm.
- the gate driver 4 sequentially applies a high level signal indicating the selected state to the gate lines G1 to Gn.
- the gate wirings G1 to Gn are sequentially selected one by one. For example, when the i-th gate line Gi is selected, the pixel formation portions Pi1 to Pim for one row are selected at once.
- the source driver 5 applies a signal voltage corresponding to the image signal DT to each of the source lines S1 to Sm. As a result, the signal voltage corresponding to the image signal DT is written into the pixel formation portions Pi1 to Pim for one selected row. In this way, the liquid crystal display device 10 displays an image on the liquid crystal panel 2.
- FIG. 17 is a plan view showing a pattern arrangement in the pixel formation portion Pij provided in the liquid crystal panel 2.
- the liquid crystal panel 2 is surrounded by an i-th gate line Gi extending in the horizontal direction, a j-th source line Sj extending in a direction intersecting the gate line Gi, the gate line Gi, and the source line Sj.
- a pixel forming portion Pij disposed in the region.
- the pixel formation portion Pij includes a TFT 100 shown in FIGS. 1A to 1C as a TFT functioning as a switching element.
- the gate electrode 20 of the TFT 100 is electrically connected to the gate wiring Gi.
- An island-shaped semiconductor layer 40 is formed above the gate electrode 20.
- One end of the semiconductor layer 40 is electrically connected to the source electrode 60a connected to the source wiring Sj, and the other end of the semiconductor layer 40 is electrically connected to the drain electrode 60b. Further, the drain electrode 60 b is electrically connected to the pixel electrode 7 through the contact hole 6.
- the pixel electrode 7 and a counter electrode constitute a pixel capacitor that holds a signal voltage corresponding to the image signal DT for a predetermined time.
- the display quality of the liquid crystal display device 10 can be improved by using the TFT 100 having a large on / off ratio as a switching element of each pixel formation portion Pij provided in the liquid crystal panel 2.
- the reason why the display quality of the liquid crystal display device 10 is improved by increasing the on / off ratio will be described.
- the on-current may be increased and the off-current may be decreased.
- the signal voltage of the image signal DT supplied from the source wiring Sj can be charged to the pixel capacitor (the pixel capacitor and the auxiliary capacitor when the auxiliary capacitor is also formed) in a short time.
- the number of formation parts Pij can be increased.
- the signal voltage written in the pixel capacitor can be held for a long time by reducing the off-state current.
- the present invention can also be applied to an organic EL (Electro Luminescence) display device.
- the present invention is suitable for a thin film transistor used in a display device such as an active matrix liquid crystal display device, and is particularly suitable for a thin film transistor used as a switching element formed in the pixel formation portion.
- SYMBOLS 10 Liquid crystal display device 15 ... Insulating substrate 20 ... Gate electrode 30 ... Gate insulating film 31 ... Silicon nitride film 32 ... Silicon oxide film 40, 50 ... Semiconductor layer 40a, 50a ... Channel region 40b, 50b ... Low resistance region 40c, 50c ... high resistance regions 41, 51 ... notches 42 ... notches 60a, 70a ... source electrodes 60b, 70b ... drain electrodes 80 ... etching stopper layer 90 ... passivation film 100-500 ... TFT (thin film transistor)
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Abstract
A semiconductor layer (40) is formed from an oxide semiconductor in which the width of a channel region (40a) is smaller than the widths of source and drain electrodes (60a, 60b) and the area of the side surface is enlarged. The semiconductor layer (40) is sandwiched between a gate insulating film (30) and a passivation film (90) and is subjected to annealing in an atmosphere containing oxygen. As a consequence, external oxygen and the oxygen contained in the gate insulating film (30) and the passivation film (90) are supplied to the channel region (40a), the areas of low-resistance regions (40b) become small, and the region sandwiched by the two low-resistance regions (40b) becomes a high-resistance region (40c). Meanwhile, the contact resistance between the semiconductor layer (40) and the source and drain electrodes (60a, 60b) are kept low. As a result, the on and off ratio becomes large and suitable transistor properties are obtained.
Description
本発明は、薄膜トランジスタ、その製造方法、および表示素子に関し、特に、酸化物半導体からなる半導体層を有する薄膜トランジスタ、その製造方法、および表示素子に関する。
The present invention relates to a thin film transistor, a manufacturing method thereof, and a display element, and more particularly to a thin film transistor having a semiconductor layer made of an oxide semiconductor, a manufacturing method thereof, and a display element.
酸化インジウムガリウム亜鉛（以下、「ＩＧＺＯ」という）または酸化亜鉛（ＺｎＯ）等の酸化物半導体からなる半導体層を有する薄膜トランジスタ（Thin Film Transistor：以下、「ＴＦＴ」という）は、非晶質シリコンからなる半導体層を有するＴＦＴに比べて動作速度が速く、また多結晶シリコンからなる半導体層を有するＴＦＴに比べて、結晶化工程が不要になる等の優れた特徴を有している。
A thin film transistor (hereinafter referred to as “TFT”) having a semiconductor layer made of an oxide semiconductor such as indium gallium zinc oxide (hereinafter referred to as “IGZO”) or zinc oxide (ZnO) is made of amorphous silicon. Compared with a TFT having a semiconductor layer made of polycrystalline silicon, it has excellent features such as a higher operating speed than a TFT having a semiconductor layer and no need for a crystallization step.
しかし、酸化物半導体からなる半導体層は、その後の製造工程で基板全体が加熱される際に還元されてしまう。具体的には、半導体層は、ソース電極およびドレイン電極によって酸素を奪い取られるとともに、ソース電極およびドレイン電極から水素を供給される。このようにして、半導体層の形成直後には、半導体層の全体が高抵抗領域である。しかし、酸化物半導体を還元することによって、ソース電極およびドレイン電極と直接接する半導体層およびそれらの電極の端部に近い半導体層は低抵抗領域になり、両側の低抵抗領域に挟まれた半導体層は、その抵抗値が低抵抗領域と高抵抗領域との間である領域（以下、「中抵抗領域」という）になる。このような半導体層をチャネル層とするＴＦＴでは、オフ電流が大きくなったり、半導体層が抵抗素子として動作したりしてしまう。
However, the semiconductor layer made of an oxide semiconductor is reduced when the entire substrate is heated in the subsequent manufacturing process. Specifically, the semiconductor layer is deprived of oxygen by the source electrode and the drain electrode and supplied with hydrogen from the source electrode and the drain electrode. Thus, immediately after the formation of the semiconductor layer, the entire semiconductor layer is a high resistance region. However, by reducing the oxide semiconductor, the semiconductor layer that is in direct contact with the source electrode and the drain electrode and the semiconductor layer near the ends of those electrodes become a low resistance region, and the semiconductor layer sandwiched between the low resistance regions on both sides Is a region whose resistance value is between the low resistance region and the high resistance region (hereinafter referred to as “medium resistance region”). In a TFT having such a semiconductor layer as a channel layer, off current increases, or the semiconductor layer operates as a resistance element.
特許文献１には、酸化物半導体からなる半導体層に、外部から酸素を供給しやすくすることによって、良好なトランジスタ特性を回復させることができるＴＦＴが開示されている。具体的には、ＴＦＴのソース電極およびドレイン電極の形成後に、ソース電極およびドレイン電極に、半導体層の表面を露出させるための開口部を形成する。次に、高温下で酸素アニールを行うことにより、開口部から半導体層に酸素を供給する。これにより、ＴＦＴは良好なトランジスタ特性を回復する。
Patent Document 1 discloses a TFT that can restore good transistor characteristics by easily supplying oxygen from the outside to a semiconductor layer made of an oxide semiconductor. Specifically, after forming the source electrode and the drain electrode of the TFT, an opening for exposing the surface of the semiconductor layer is formed in the source electrode and the drain electrode. Next, oxygen is supplied to the semiconductor layer from the opening by performing oxygen annealing at a high temperature. As a result, the TFT recovers good transistor characteristics.
特許文献１では、半導体層に酸素を供給するために、ソース電極およびドレイン電極に開口部を形成する。しかし、開口部を形成することによって、ソース電極およびドレイン電極と半導体層との接触面積が減少するので、ソース電極およびドレイン電極と半導体層とのコンタクト抵抗が高くなる。これにより、ＴＦＴのオン電流が低下する等、トランジスタ特性が悪影響を受ける。
In Patent Document 1, openings are formed in a source electrode and a drain electrode in order to supply oxygen to a semiconductor layer. However, since the contact area between the source and drain electrodes and the semiconductor layer is reduced by forming the opening, the contact resistance between the source and drain electrodes and the semiconductor layer is increased. As a result, the transistor characteristics are adversely affected, such as a reduction in the on-current of the TFT.
そこで、ソース電極およびドレイン電極と酸化物半導体からなる半導体層とのコンタクト抵抗を低く保った状態で、良好なトランジスタ特性を回復させることができる薄膜トランジスタを提供することを目的とする。
Therefore, an object of the present invention is to provide a thin film transistor capable of recovering good transistor characteristics while maintaining a low contact resistance between a source electrode and a drain electrode and a semiconductor layer made of an oxide semiconductor.
本発明の第１の局面は、絶縁基板上に形成され、酸化物半導体からなる半導体層を有する薄膜トランジスタであって、
前記絶縁基板上に形成されたゲート電極と、
前記ゲート電極を覆うように形成され、少なくとも第１の酸化シリコン膜を含むゲート絶縁膜と、
前記ゲート電極を挟むように、所定の距離を隔てて前記ゲート絶縁膜上に形成されたソース電極およびドレイン電極と、
前記ソース電極および前記ドレイン電極によって挟まれた前記ゲート絶縁膜上に形成され、一端および他端が前記ソース電極および前記ドレイン電極の裏面または表面のいずれかとそれぞれ電気的に接続された前記半導体層と、
前記ソース電極、前記ドレイン電極、および前記半導体層を覆い、少なくとも第２の酸化シリコン膜を含むパッシベーション膜とを備え、
前記半導体層は、前記ソース電極および前記ドレイン電極の裏面または表面と接する領域における幅よりも、前記ソース電極と前記ドレイン電極とによって挟まれたチャネル領域における幅が狭く、
前記チャネル領域は、前記第１の酸化シリコン膜と前記第２の酸化シリコン膜とによって挟まれていることを特徴とする。 A first aspect of the present invention is a thin film transistor having a semiconductor layer formed on an insulating substrate and made of an oxide semiconductor,
A gate electrode formed on the insulating substrate;
A gate insulating film formed to cover the gate electrode and including at least a first silicon oxide film;
A source electrode and a drain electrode formed on the gate insulating film at a predetermined distance so as to sandwich the gate electrode;
The semiconductor layer formed on the gate insulating film sandwiched between the source electrode and the drain electrode, and having one end and the other end electrically connected to either the back surface or the surface of the source electrode and the drain electrode, respectively ,
A passivation film that covers the source electrode, the drain electrode, and the semiconductor layer and includes at least a second silicon oxide film;
The semiconductor layer has a narrower width in a channel region sandwiched between the source electrode and the drain electrode than a width in a region in contact with the back surface or the front surface of the source electrode and the drain electrode,
The channel region is sandwiched between the first silicon oxide film and the second silicon oxide film.
前記絶縁基板上に形成されたゲート電極と、
前記ゲート電極を覆うように形成され、少なくとも第１の酸化シリコン膜を含むゲート絶縁膜と、
前記ゲート電極を挟むように、所定の距離を隔てて前記ゲート絶縁膜上に形成されたソース電極およびドレイン電極と、
前記ソース電極および前記ドレイン電極によって挟まれた前記ゲート絶縁膜上に形成され、一端および他端が前記ソース電極および前記ドレイン電極の裏面または表面のいずれかとそれぞれ電気的に接続された前記半導体層と、
前記ソース電極、前記ドレイン電極、および前記半導体層を覆い、少なくとも第２の酸化シリコン膜を含むパッシベーション膜とを備え、
前記半導体層は、前記ソース電極および前記ドレイン電極の裏面または表面と接する領域における幅よりも、前記ソース電極と前記ドレイン電極とによって挟まれたチャネル領域における幅が狭く、
前記チャネル領域は、前記第１の酸化シリコン膜と前記第２の酸化シリコン膜とによって挟まれていることを特徴とする。 A first aspect of the present invention is a thin film transistor having a semiconductor layer formed on an insulating substrate and made of an oxide semiconductor,
A gate electrode formed on the insulating substrate;
A gate insulating film formed to cover the gate electrode and including at least a first silicon oxide film;
A source electrode and a drain electrode formed on the gate insulating film at a predetermined distance so as to sandwich the gate electrode;
The semiconductor layer formed on the gate insulating film sandwiched between the source electrode and the drain electrode, and having one end and the other end electrically connected to either the back surface or the surface of the source electrode and the drain electrode, respectively ,
A passivation film that covers the source electrode, the drain electrode, and the semiconductor layer and includes at least a second silicon oxide film;
The semiconductor layer has a narrower width in a channel region sandwiched between the source electrode and the drain electrode than a width in a region in contact with the back surface or the front surface of the source electrode and the drain electrode,
The channel region is sandwiched between the first silicon oxide film and the second silicon oxide film.
本発明の第２の局面は、本発明の第１の局面において、
前記チャネル領域は、少なくとも幅方向のいずれか一方の端部に第１の切り欠き部を有することを特徴とする。 According to a second aspect of the present invention, in the first aspect of the present invention,
The channel region has a first cutout at least at one end in the width direction.
前記チャネル領域は、少なくとも幅方向のいずれか一方の端部に第１の切り欠き部を有することを特徴とする。 According to a second aspect of the present invention, in the first aspect of the present invention,
The channel region has a first cutout at least at one end in the width direction.
本発明の第３の局面は、本発明の第２の局面において、
前記チャネル領域は、幅方向の両端部に前記第１の切り欠き部を有することを特徴とする。 According to a third aspect of the present invention, in the second aspect of the present invention,
The channel region has the first notch at both ends in the width direction.
前記チャネル領域は、幅方向の両端部に前記第１の切り欠き部を有することを特徴とする。 According to a third aspect of the present invention, in the second aspect of the present invention,
The channel region has the first notch at both ends in the width direction.
本発明の第４の局面は、本発明の第１から第３のいずれかの局面において、
前記チャネル領域は、幅方向の端部から内側に離れた位置に、前記チャネル領域の長さ方向に沿って少なくとも１つの第２の切り欠き部を有することを特徴とする。 According to a fourth aspect of the present invention, in any one of the first to third aspects of the present invention,
The channel region has at least one second cutout portion along a length direction of the channel region at a position spaced inward from an end portion in the width direction.
前記チャネル領域は、幅方向の端部から内側に離れた位置に、前記チャネル領域の長さ方向に沿って少なくとも１つの第２の切り欠き部を有することを特徴とする。 According to a fourth aspect of the present invention, in any one of the first to third aspects of the present invention,
The channel region has at least one second cutout portion along a length direction of the channel region at a position spaced inward from an end portion in the width direction.
本発明の第５の局面は、本発明の第１の局面において、
前記ゲート絶縁膜は、前記第１の酸化シリコン膜の下面に形成された第１の窒化シリコン膜をさらに含み、
前記パッシベーション膜は、第２の酸化シリコン膜の表面に形成された第２の窒化シリコン膜をさらに含むことを特徴とする。 According to a fifth aspect of the present invention, in the first aspect of the present invention,
The gate insulating film further includes a first silicon nitride film formed on a lower surface of the first silicon oxide film,
The passivation film further includes a second silicon nitride film formed on the surface of the second silicon oxide film.
前記ゲート絶縁膜は、前記第１の酸化シリコン膜の下面に形成された第１の窒化シリコン膜をさらに含み、
前記パッシベーション膜は、第２の酸化シリコン膜の表面に形成された第２の窒化シリコン膜をさらに含むことを特徴とする。 According to a fifth aspect of the present invention, in the first aspect of the present invention,
The gate insulating film further includes a first silicon nitride film formed on a lower surface of the first silicon oxide film,
The passivation film further includes a second silicon nitride film formed on the surface of the second silicon oxide film.
本発明の第６の局面は、本発明の第１の局面において、
前記ソース電極と前記ドレイン電極とは、前記半導体層上に、所定の距離を隔てて対向するように形成され、
前記半導体層は、前記一端が前記ソース電極の裏面と電気的に接続され、前記他端が前記ドレイン電極の裏面と電気的に接続されるように形成されていることを特徴とする。 According to a sixth aspect of the present invention, in the first aspect of the present invention,
The source electrode and the drain electrode are formed on the semiconductor layer so as to face each other with a predetermined distance therebetween,
The semiconductor layer is formed so that the one end is electrically connected to the back surface of the source electrode and the other end is electrically connected to the back surface of the drain electrode.
前記ソース電極と前記ドレイン電極とは、前記半導体層上に、所定の距離を隔てて対向するように形成され、
前記半導体層は、前記一端が前記ソース電極の裏面と電気的に接続され、前記他端が前記ドレイン電極の裏面と電気的に接続されるように形成されていることを特徴とする。 According to a sixth aspect of the present invention, in the first aspect of the present invention,
The source electrode and the drain electrode are formed on the semiconductor layer so as to face each other with a predetermined distance therebetween,
The semiconductor layer is formed so that the one end is electrically connected to the back surface of the source electrode and the other end is electrically connected to the back surface of the drain electrode.
本発明の第７の局面は、本発明の第６の局面において、
前記ソース電極と前記ドレイン電極とに挟まれた前記半導体層上に形成された、酸化シリコンからなるエッチングストッパ層をさらに備え、
前記チャネル領域は、前記ソース電極と前記ドレイン電極の端部に沿ってそれぞれ形成された、抵抗値が低い２つの第１の領域と、前記２つの第１の領域によって挟まれ、前記２つの第１の領域よりも抵抗値が高い第２の領域とを含み、
前記エッチングストッパ層は、少なくとも前記第２の領域を覆うように形成されていることを特徴とする。 A seventh aspect of the present invention is the sixth aspect of the present invention,
An etching stopper layer made of silicon oxide formed on the semiconductor layer sandwiched between the source electrode and the drain electrode;
The channel region is sandwiched between two first regions each having a low resistance value formed along the ends of the source electrode and the drain electrode, and the two first regions. A second region having a resistance value higher than that of the first region,
The etching stopper layer is formed so as to cover at least the second region.
前記ソース電極と前記ドレイン電極とに挟まれた前記半導体層上に形成された、酸化シリコンからなるエッチングストッパ層をさらに備え、
前記チャネル領域は、前記ソース電極と前記ドレイン電極の端部に沿ってそれぞれ形成された、抵抗値が低い２つの第１の領域と、前記２つの第１の領域によって挟まれ、前記２つの第１の領域よりも抵抗値が高い第２の領域とを含み、
前記エッチングストッパ層は、少なくとも前記第２の領域を覆うように形成されていることを特徴とする。 A seventh aspect of the present invention is the sixth aspect of the present invention,
An etching stopper layer made of silicon oxide formed on the semiconductor layer sandwiched between the source electrode and the drain electrode;
The channel region is sandwiched between two first regions each having a low resistance value formed along the ends of the source electrode and the drain electrode, and the two first regions. A second region having a resistance value higher than that of the first region,
The etching stopper layer is formed so as to cover at least the second region.
本発明の第８の局面は、本発明の第１の局面において、
前記ソース電極と前記ドレイン電極とは、前記ゲート絶縁膜上に所定の距離を隔てて対向するように形成され、
前記半導体層は、前記一端が前記ソース電極の端部を覆って前記ソース電極の表面と電気的に接続され、前記他端が前記ドレイン電極の端部を覆って前記ソース電極の表面と電気的に接続されるように形成されていることを特徴とする。 According to an eighth aspect of the present invention, in the first aspect of the present invention,
The source electrode and the drain electrode are formed on the gate insulating film so as to face each other with a predetermined distance therebetween,
The semiconductor layer has one end covering the end of the source electrode and electrically connected to the surface of the source electrode, and the other end covering the end of the drain electrode and electrically connected to the surface of the source electrode. It is formed so that it may be connected to.
前記ソース電極と前記ドレイン電極とは、前記ゲート絶縁膜上に所定の距離を隔てて対向するように形成され、
前記半導体層は、前記一端が前記ソース電極の端部を覆って前記ソース電極の表面と電気的に接続され、前記他端が前記ドレイン電極の端部を覆って前記ソース電極の表面と電気的に接続されるように形成されていることを特徴とする。 According to an eighth aspect of the present invention, in the first aspect of the present invention,
The source electrode and the drain electrode are formed on the gate insulating film so as to face each other with a predetermined distance therebetween,
The semiconductor layer has one end covering the end of the source electrode and electrically connected to the surface of the source electrode, and the other end covering the end of the drain electrode and electrically connected to the surface of the source electrode. It is formed so that it may be connected to.
本発明の第９の局面は、本発明の第１の局面において、
前記半導体層を構成する酸化物半導体は非晶質であることを特徴とする。 According to a ninth aspect of the present invention, in the first aspect of the present invention,
The oxide semiconductor constituting the semiconductor layer is amorphous.
前記半導体層を構成する酸化物半導体は非晶質であることを特徴とする。 According to a ninth aspect of the present invention, in the first aspect of the present invention,
The oxide semiconductor constituting the semiconductor layer is amorphous.
本発明の第１０の局面は、絶縁基板上に形成され、酸化物半導体からなる半導体層を有する薄膜トランジスタの製造方法であって、
前記絶縁基板上にゲート電極を形成する工程と、
前記ゲート電極を覆うように、少なくとも第１の酸化シリコン膜を含むゲート絶縁膜を形成する工程と、
前記ゲート電極を挟むように、所定の距離を隔てて前記ゲート絶縁膜上にソース電極およびドレイン電極を形成する工程と、
前記ソース電極および前記ドレイン電極によって挟まれた前記ゲート絶縁膜上に、一端および他端が前記ソース電極および前記ドレイン電極とそれぞれ電気的に接続されるように前記半導体層を形成する工程と、
前記ソース電極、前記ドレイン電極、および前記半導体層を覆い、少なくとも第２の酸化シリコン膜を含むパッシベーション膜を形成する工程と、
前記パッシベーション膜の形成後に熱処理を行う工程とを備え、
前記半導体層を形成する工程は、フォトリソグラフィ法を用いて、前記ソース電極と前記ドレイン電極とによって挟まれた前記半導体層からなるチャネル領域に切り欠き部を設ける工程を含み
前記熱処理を行う工程は、前記チャネル領域を前記第１の酸化シリコン膜と前記第２の酸化シリコン膜とによって挟んだ状態で行うことを特徴とする。 A tenth aspect of the present invention is a method of manufacturing a thin film transistor having a semiconductor layer formed on an insulating substrate and made of an oxide semiconductor,
Forming a gate electrode on the insulating substrate;
Forming a gate insulating film including at least a first silicon oxide film so as to cover the gate electrode;
Forming a source electrode and a drain electrode on the gate insulating film at a predetermined distance so as to sandwich the gate electrode; and
Forming the semiconductor layer on the gate insulating film sandwiched between the source electrode and the drain electrode so that one end and the other end are electrically connected to the source electrode and the drain electrode, respectively;
Forming a passivation film that covers the source electrode, the drain electrode, and the semiconductor layer and includes at least a second silicon oxide film;
And a step of performing a heat treatment after the formation of the passivation film,
The step of forming the semiconductor layer includes a step of providing a notch in a channel region formed of the semiconductor layer sandwiched between the source electrode and the drain electrode using a photolithography method. , Wherein the channel region is sandwiched between the first silicon oxide film and the second silicon oxide film.
前記絶縁基板上にゲート電極を形成する工程と、
前記ゲート電極を覆うように、少なくとも第１の酸化シリコン膜を含むゲート絶縁膜を形成する工程と、
前記ゲート電極を挟むように、所定の距離を隔てて前記ゲート絶縁膜上にソース電極およびドレイン電極を形成する工程と、
前記ソース電極および前記ドレイン電極によって挟まれた前記ゲート絶縁膜上に、一端および他端が前記ソース電極および前記ドレイン電極とそれぞれ電気的に接続されるように前記半導体層を形成する工程と、
前記ソース電極、前記ドレイン電極、および前記半導体層を覆い、少なくとも第２の酸化シリコン膜を含むパッシベーション膜を形成する工程と、
前記パッシベーション膜の形成後に熱処理を行う工程とを備え、
前記半導体層を形成する工程は、フォトリソグラフィ法を用いて、前記ソース電極と前記ドレイン電極とによって挟まれた前記半導体層からなるチャネル領域に切り欠き部を設ける工程を含み
前記熱処理を行う工程は、前記チャネル領域を前記第１の酸化シリコン膜と前記第２の酸化シリコン膜とによって挟んだ状態で行うことを特徴とする。 A tenth aspect of the present invention is a method of manufacturing a thin film transistor having a semiconductor layer formed on an insulating substrate and made of an oxide semiconductor,
Forming a gate electrode on the insulating substrate;
Forming a gate insulating film including at least a first silicon oxide film so as to cover the gate electrode;
Forming a source electrode and a drain electrode on the gate insulating film at a predetermined distance so as to sandwich the gate electrode; and
Forming the semiconductor layer on the gate insulating film sandwiched between the source electrode and the drain electrode so that one end and the other end are electrically connected to the source electrode and the drain electrode, respectively;
Forming a passivation film that covers the source electrode, the drain electrode, and the semiconductor layer and includes at least a second silicon oxide film;
And a step of performing a heat treatment after the formation of the passivation film,
The step of forming the semiconductor layer includes a step of providing a notch in a channel region formed of the semiconductor layer sandwiched between the source electrode and the drain electrode using a photolithography method. , Wherein the channel region is sandwiched between the first silicon oxide film and the second silicon oxide film.
第１１の発明は、本発明の第１０の局面において、
前記熱処理を行う工程は、少なくとも酸素を含む雰囲気中で、２００～４００℃の温度で、１～２時間の熱処理を行うことを特徴とする。 In an eleventh aspect of the present invention, in a tenth aspect of the present invention,
The step of performing the heat treatment is characterized in that the heat treatment is performed at a temperature of 200 to 400 ° C. for 1 to 2 hours in an atmosphere containing at least oxygen.
前記熱処理を行う工程は、少なくとも酸素を含む雰囲気中で、２００～４００℃の温度で、１～２時間の熱処理を行うことを特徴とする。 In an eleventh aspect of the present invention, in a tenth aspect of the present invention,
The step of performing the heat treatment is characterized in that the heat treatment is performed at a temperature of 200 to 400 ° C. for 1 to 2 hours in an atmosphere containing at least oxygen.
第１２の発明は、画像を表示するアクティブマトリクス型の表示装置であって、
複数のゲート配線と、前記複数のゲート配線と交差する複数のソース配線と、前記複数のゲート配線と前記複数のソース配線との交差点にそれぞれ対応してマトリクス状に配置された複数の画素形成部とを備える表示部とを備え、
前記画素形成部は、対応するゲート配線に印加される信号に応じてオンまたはオフする第１から第９のいずれかの局面に係る薄膜トランジスタを含むことを特徴とする。 A twelfth aspect of the invention is an active matrix type display device for displaying an image,
A plurality of pixel forming portions arranged in a matrix corresponding to a plurality of gate wirings, a plurality of source wirings intersecting with the plurality of gate wirings, and intersections of the plurality of gate wirings and the plurality of source wirings, respectively. And a display unit comprising
The pixel formation portion includes a thin film transistor according to any one of the first to ninth aspects that is turned on or off according to a signal applied to a corresponding gate wiring.
複数のゲート配線と、前記複数のゲート配線と交差する複数のソース配線と、前記複数のゲート配線と前記複数のソース配線との交差点にそれぞれ対応してマトリクス状に配置された複数の画素形成部とを備える表示部とを備え、
前記画素形成部は、対応するゲート配線に印加される信号に応じてオンまたはオフする第１から第９のいずれかの局面に係る薄膜トランジスタを含むことを特徴とする。 A twelfth aspect of the invention is an active matrix type display device for displaying an image,
A plurality of pixel forming portions arranged in a matrix corresponding to a plurality of gate wirings, a plurality of source wirings intersecting with the plurality of gate wirings, and intersections of the plurality of gate wirings and the plurality of source wirings, respectively. And a display unit comprising
The pixel formation portion includes a thin film transistor according to any one of the first to ninth aspects that is turned on or off according to a signal applied to a corresponding gate wiring.
本発明の第１の局面によれば、チャネル領域における半導体層の幅を、ソース／ドレイン電極の裏面または表面と接する領域における半導体層の幅よりも狭くする。これにより、側面の面積を大きくなったチャネル領域の半導体層を、第１の酸化シリコン膜と第２の酸化シリコン膜とによって挟む。その結果、外部からの酸素と、第１および第２の酸化シリコン膜に含まれる酸素がチャネル領域に供給されるので、ソース／ドレイン電極の端部に沿って形成された低抵抗領域の面積が狭くなるとともに、２つの低抵抗領域に挟まれたチャネル領域が高抵抗領域になる。また、ソース／ドレイン電極の裏面または表面と接する半導体層の幅は、チャネル領域の半導体層の幅よりも広いので、ソース／ドレイン電極と半導体層とのコンタクト抵抗は低く保たれる。これにより、コンタクト抵抗を低く保った状態で、薄膜トランジスタのオン・オフ比を大きくすることができる。
According to the first aspect of the present invention, the width of the semiconductor layer in the channel region is made smaller than the width of the semiconductor layer in the region in contact with the back surface or the surface of the source / drain electrode. Thus, the semiconductor layer of the channel region whose side surface area is increased is sandwiched between the first silicon oxide film and the second silicon oxide film. As a result, oxygen from the outside and oxygen contained in the first and second silicon oxide films are supplied to the channel region, so that the area of the low resistance region formed along the end portion of the source / drain electrode is reduced. In addition to being narrowed, a channel region sandwiched between two low resistance regions becomes a high resistance region. Further, since the width of the semiconductor layer in contact with the back surface or the front surface of the source / drain electrode is wider than the width of the semiconductor layer in the channel region, the contact resistance between the source / drain electrode and the semiconductor layer is kept low. Thus, the on / off ratio of the thin film transistor can be increased while keeping the contact resistance low.
本発明の第２の局面によれば、チャネル領域には、その幅方向の一方の端部に第１の切り欠き部が設けられている。このため、外部からの酸素と、第１および第２の酸化シリコン膜に含まれる酸素が、第１の切り欠き部の側面からもチャネル領域に供給される。これにより、チャネル領域に高抵抗領域が形成されるので、薄膜トランジスタのオフ電流を小さくすることができる。
According to the second aspect of the present invention, the channel region is provided with the first notch at one end in the width direction. For this reason, oxygen from the outside and oxygen contained in the first and second silicon oxide films are also supplied to the channel region from the side surface of the first notch. Accordingly, a high resistance region is formed in the channel region, so that the off-state current of the thin film transistor can be reduced.
本発明の第３の局面によれば、チャネル領域には、その幅方向の両端部に第１の切り欠き部が設けられている。外部からの酸素と、第１および第２の酸化シリコン膜に含まれる酸素が、両側の第１の切り欠き部の側面からチャネル領域に供給される。これにより、チャネル領域により抵抗値の高い高抵抗領域が形成されるので、薄膜トランジスタのオフ電流をより小さくすることができる。
According to the third aspect of the present invention, the channel region is provided with first notches at both ends in the width direction. Oxygen from the outside and oxygen contained in the first and second silicon oxide films are supplied to the channel region from the side surfaces of the first notches on both sides. Accordingly, a high-resistance region having a high resistance value is formed by the channel region, so that the off-state current of the thin film transistor can be further reduced.
本発明の第４の局面によれば、チャネル領域には、その幅方向の端部から内側に離れた位置に第２の切り欠き部が設けられている。外部からの酸素と、第１および第２の酸化シリコン膜に含まれる酸素が、第２の切り欠き部を介してチャネル領域に供給される。これにより、薄膜トランジスタのオフ電流をさらに小さくすることができる。また、第２の切り欠き部の個数が多ければ多いほど、チャネル領域に多くの酸素が供給されるので、薄膜トランジスタのオフ電流をより一層小さくすることができる。
According to the fourth aspect of the present invention, the channel region is provided with the second notch at a position away from the end in the width direction to the inside. Oxygen from the outside and oxygen contained in the first and second silicon oxide films are supplied to the channel region through the second notch. Thus, the off-state current of the thin film transistor can be further reduced. Further, the larger the number of the second notches, the more oxygen is supplied to the channel region, so that the off-state current of the thin film transistor can be further reduced.
本発明の第５の局面によれば、ゲート絶縁膜が第１の窒化シリコン膜を含むことにより、ゲート絶縁膜の絶縁耐圧を確保することができる。また、パッシベーション膜が第２の窒化シリコン膜を含むことにより、外部から薄膜トランジスタに侵入する水分が阻止されるので、薄膜トランジスタの信頼性を向上させることができる。
According to the fifth aspect of the present invention, since the gate insulating film includes the first silicon nitride film, the withstand voltage of the gate insulating film can be ensured. In addition, since the passivation film includes the second silicon nitride film, moisture entering the thin film transistor from the outside is blocked, so that the reliability of the thin film transistor can be improved.
本発明の第６の局面によれば、トップコンタクト構造の薄膜トランジスタにおいて、オン・オフ比を大きくすることができる。
According to the sixth aspect of the present invention, in the thin film transistor having the top contact structure, the on / off ratio can be increased.
本発明の第７の局面によれば、上記第７の発明によれば、エッチングストッパ層は、ソース／ドレイン電極の形成時に半導体層の表面がエッチングされないように保護する。さらに、エッチングストッパ層は酸化シリコンからなり、少なくともチャネル領域の第２の領域を覆うように形成されている。これにより、パッシベーション膜の形成後に行なう熱処理により、外部からの酸素と、パッシベーション膜に含まれる酸素が、第２の領域に供給される。このため、第２の領域の抵抗値をより一層高くして、薄膜トランジスタのオフ電流をより一層小さくすることができる。
According to the seventh aspect of the present invention, according to the seventh aspect, the etching stopper layer protects the surface of the semiconductor layer from being etched when the source / drain electrodes are formed. Further, the etching stopper layer is made of silicon oxide and is formed so as to cover at least the second region of the channel region. Thus, oxygen from the outside and oxygen contained in the passivation film are supplied to the second region by heat treatment performed after the formation of the passivation film. Therefore, the resistance value of the second region can be further increased and the off-state current of the thin film transistor can be further reduced.
本発明の第８の局面によれば、ボトムコンタクト構造の薄膜トランジスタにおいて、オン・オフ比を大きくすることができる。
According to the eighth aspect of the present invention, the ON / OFF ratio can be increased in the thin film transistor having the bottom contact structure.
本発明の第９の局面によれば、酸素を含む雰囲気中でのアニールによって外部から半導体層に供給される酸素は、半導体層を構成する酸化物半導体が微結晶である場合よりも、非晶質である場合により多くなる。これにより、チャネル領域に形成される低抵抗領域の面積がより一層狭くなるとともに、２つの低抵抗領域に挟まれたチャネル領域はより一層抵抗値が高い高抵抗領域になる。このため、薄膜トランジスタのオフ電流を小さくすることができる。
According to the ninth aspect of the present invention, oxygen supplied from the outside to the semiconductor layer by annealing in an atmosphere containing oxygen is more amorphous than in the case where the oxide semiconductor constituting the semiconductor layer is microcrystalline. More when it is quality. As a result, the area of the low resistance region formed in the channel region is further narrowed, and the channel region sandwiched between the two low resistance regions becomes a high resistance region having a higher resistance value. Therefore, the off current of the thin film transistor can be reduced.
本発明の第１０の局面によれば、第１の局面と同様の効果を奏する。
According to the tenth aspect of the present invention, there are the same effects as in the first aspect.
本発明の第１１の局面によれば、少なくとも酸素を含む雰囲気中において、２００～４００℃で、１～２時間の熱処理を行うことにより、半導体層の側面からも十分な量の酸素を供給して、薄膜トランジスタのチャネル領域に高抵抗領域を形成することができる。
According to the eleventh aspect of the present invention, a sufficient amount of oxygen is supplied also from the side surface of the semiconductor layer by performing a heat treatment at 200 to 400 ° C. for 1 to 2 hours in an atmosphere containing at least oxygen. Thus, a high resistance region can be formed in the channel region of the thin film transistor.
本発明の第１２の局面によれば、画素形成部のスイッチング素子として、第１から第９のいずれかの発明に係る薄膜トランジスタを用いることにより、スイッチング素子のオン・オフ比を大きくすることができる。これにより、表示装置の表示品位を向上させることができる。
According to the twelfth aspect of the present invention, the on / off ratio of the switching element can be increased by using the thin film transistor according to any one of the first to ninth inventions as the switching element of the pixel forming portion. . Thereby, the display quality of the display device can be improved.
＜１．第１の実施形態＞
＜１．１ ＴＦＴの構成＞
図１は、本発明の第１の実施形態に係るボトムゲート型ＴＦＴ１００の構成を示す図であり、より詳しくは、図１（Ａ）は、本発明の第１の実施形態に係るボトムゲート型ＴＦＴ１００の構成を示す平面図であり、図１（Ｂ）は、図１（Ａ）に示す切断線Ａ－Ａに沿ったＴＦＴ１００の断面図であり、図１（Ｃ）は、図１（Ａ）に示す切断線Ｂ－Ｂに沿ったＴＦＴ１００の断面図である。図１（Ａ）～図１（Ｃ）を参照して、ＴＦＴ１００の構成を説明する。 <1. First Embodiment>
<1.1 TFT configuration>
FIG. 1 is a diagram showing a configuration of a bottomgate type TFT 100 according to the first embodiment of the present invention. More specifically, FIG. 1A shows a bottom gate type TFT according to the first embodiment of the present invention. FIG. 1B is a plan view showing the structure of the TFT 100, FIG. 1B is a cross-sectional view of the TFT 100 along the cutting line AA shown in FIG. 1A, and FIG. 2 is a cross-sectional view of the TFT 100 taken along a cutting line BB shown in FIG. With reference to FIGS. 1A to 1C, the structure of the TFT 100 will be described.
＜１．１ ＴＦＴの構成＞
図１は、本発明の第１の実施形態に係るボトムゲート型ＴＦＴ１００の構成を示す図であり、より詳しくは、図１（Ａ）は、本発明の第１の実施形態に係るボトムゲート型ＴＦＴ１００の構成を示す平面図であり、図１（Ｂ）は、図１（Ａ）に示す切断線Ａ－Ａに沿ったＴＦＴ１００の断面図であり、図１（Ｃ）は、図１（Ａ）に示す切断線Ｂ－Ｂに沿ったＴＦＴ１００の断面図である。図１（Ａ）～図１（Ｃ）を参照して、ＴＦＴ１００の構成を説明する。 <1. First Embodiment>
<1.1 TFT configuration>
FIG. 1 is a diagram showing a configuration of a bottom
ガラス基板等の透明な絶縁基板１５上に、ゲート電極２０が形成されている。ゲート電極２０は、例えばチタン（Ｔｉ）、モリブデン（Ｍｏ）、アルミニウム（Ａｌ）、タンタル（Ｔａ）、クロム（Ｃｒ）等のうち、いずれかの金属によって構成されていてもよく、また、絶縁基板１５の表面側から、例えばチタン、アルミニウム、チタンを順に積層した積層金属膜によって構成されていてもよい。
A gate electrode 20 is formed on a transparent insulating substrate 15 such as a glass substrate. The gate electrode 20 may be made of any metal among, for example, titanium (Ti), molybdenum (Mo), aluminum (Al), tantalum (Ta), chromium (Cr), etc. For example, it may be constituted by a laminated metal film in which titanium, aluminum, and titanium are laminated in order from the surface side of 15.
ゲート電極２０を含む絶縁基板１５の全体を覆うように、ゲート絶縁膜３０が形成されている。ゲート絶縁膜３０は、窒化シリコン（ＳｉＮｘ）膜３１（「第１の窒化シリコン膜」ともいう）上に酸化シリコン（ＳｉＯ2）膜３２（「第１の酸化シリコン膜」ともいう）を積層した積層絶縁膜により構成されている。窒化シリコン膜３１を含むのは、ゲート絶縁膜３０の絶縁耐圧を確保するためである。また、窒化シリコン膜３１上に酸化シリコン膜３２を積層したのは、次の理由による。第１の理由は、酸化シリコン膜３２から後述する半導体層４０に酸素を供給しやすくするためである。第２の理由は、窒化シリコン膜３１の表面に半導体層４０を形成すれば、その界面にトラップが形成されてＴＦＴ１００の信頼性が低下しやすくなるためである。
A gate insulating film 30 is formed so as to cover the entire insulating substrate 15 including the gate electrode 20. The gate insulating film 30 is formed by stacking a silicon oxide (SiO 2 ) film 32 (also referred to as “first silicon oxide film”) on a silicon nitride (SiNx) film 31 (also referred to as “first silicon nitride film”). It is comprised by the laminated insulating film. The reason why the silicon nitride film 31 is included is to ensure the withstand voltage of the gate insulating film 30. The reason why the silicon oxide film 32 is stacked on the silicon nitride film 31 is as follows. The first reason is to facilitate supply of oxygen from the silicon oxide film 32 to the semiconductor layer 40 described later. The second reason is that if the semiconductor layer 40 is formed on the surface of the silicon nitride film 31, a trap is formed at the interface and the reliability of the TFT 100 is likely to be lowered.
ゲート電極２０に対応するゲート絶縁膜３０の表面上の位置に、島状の半導体層４０が形成されている。半導体層４０は、インジウム（Ｉｎ）、ガリウム（Ｇａ）、亜鉛（Ｚｎ）および酸素（Ｏ）を含むＩＧＺＯ（酸化インジウムガリウム亜鉛）からなり、ＩＧＺＯは酸化物半導体である。半導体層４０では、ソース電極６０ａとドレイン電極６０ｂに挟まれた領域の幅方向の各端部がそれぞれ矩形状に切り取られている。これにより、半導体層４０のソース電極６０ａとドレイン電極６０ｂとに挟まれた領域４０ａ（以下、「チャネル領域４０ａ」という）の幅は、ソース電極６０ａおよびドレイン電極６０ｂの下部の幅よりも狭くなっている。
An island-shaped semiconductor layer 40 is formed at a position on the surface of the gate insulating film 30 corresponding to the gate electrode 20. The semiconductor layer 40 is made of IGZO (indium gallium zinc oxide) containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O), and IGZO is an oxide semiconductor. In the semiconductor layer 40, each end in the width direction of a region sandwiched between the source electrode 60a and the drain electrode 60b is cut out in a rectangular shape. Thus, the width of the region 40a (hereinafter referred to as “channel region 40a”) sandwiched between the source electrode 60a and the drain electrode 60b of the semiconductor layer 40 is narrower than the width of the lower portion of the source electrode 60a and the drain electrode 60b. ing.
半導体層４０が切り取られた領域４１（以下、「切り欠き部４１」または「第１の切り欠き部」ともいう）に挟まれたチャネル領域４０ａには、ソース電極６０ａの端部とドレイン電極６０ｂの端部に沿って、ソース電極６０ａおよびドレイン電極６０ｂによりそれぞれ還元された２つの低抵抗領域４０ｂ（「第１の領域」ともいう）が形成されている。２つの低抵抗領域４０ｂに挟まれたチャネル領域４０ａの中央には、抵抗値が高い高抵抗領域４０ｃ（「第２の領域」ともいう）が形成されている。
The channel region 40a sandwiched between the regions 41 from which the semiconductor layer 40 has been cut (hereinafter also referred to as “notch portions 41” or “first notch portions”) includes an end portion of the source electrode 60a and the drain electrode 60b. Two low-resistance regions 40b (also referred to as “first regions”) reduced by the source electrode 60a and the drain electrode 60b are formed along the end portions of the first and second electrodes. A high resistance region 40c (also referred to as “second region”) having a high resistance value is formed in the center of the channel region 40a sandwiched between the two low resistance regions 40b.
半導体層４０の膜厚は、４０～５０ｎｍ程度が好ましい。これは、以下の問題が生じるからである。すなわち、半導体層４０の膜厚が４０μｍよりも薄くなると、ＴＦＴ１００のトランジスタ特性が不安定になり、また温度およびゲートストレス電圧による閾値電圧のシフトが生じるという問題が生じる。一方、膜厚が５０ｎｍよりも厚くなると、ゲート電圧による制御性が悪くなり、オフ電流が大きくなるという問題が生じる。
The film thickness of the semiconductor layer 40 is preferably about 40 to 50 nm. This is because the following problems occur. That is, when the film thickness of the semiconductor layer 40 is thinner than 40 μm, the transistor characteristics of the TFT 100 become unstable, and the threshold voltage shifts due to temperature and gate stress voltage. On the other hand, when the film thickness is thicker than 50 nm, the controllability by the gate voltage is deteriorated, resulting in a problem that the off-current is increased.
ＴＦＴ１００の半導体層４０として用いられるＩＧＺＯには、インジウムとガリウムと亜鉛とが同じ割合で含まれている。しかし、それらは異なる割合で含まれていてもよい。また、半導体層４０を構成するＩＧＺＯは非晶質であることが最も好ましいが、微結晶であってもよい。
IGZO used as the semiconductor layer 40 of the TFT 100 contains indium, gallium, and zinc in the same ratio. However, they may be included in different proportions. The IGZO constituting the semiconductor layer 40 is most preferably amorphous, but may be microcrystalline.
ＴＦＴ１００の半導体層４０として使用可能な酸化物半導体は、ＩＧＺＯに限定されず、Ｉｎ－Ｚｎ－Ｏ系、Ｉｎ－Ｚｎ－Ｓｎ－Ｏ系、またはＩｎ－Ｚｎ－Ｓｉ－Ｏ系等であってもよい。具体的には、ＩＺＯ（酸化インジウム亜鉛）、ＩＴＯ（酸化インジウム錫）、ＺｎＯ、ＳｎＯ（酸化錫）、ＷＯ（酸化タングステン）、ＩＯ（酸化インジウム）等であってもよい。
An oxide semiconductor that can be used as the semiconductor layer 40 of the TFT 100 is not limited to IGZO, and may be an In—Zn—O system, an In—Zn—Sn—O system, an In—Zn—Si—O system, or the like. Good. Specifically, IZO (indium zinc oxide), ITO (indium tin oxide), ZnO, SnO (tin oxide), WO (tungsten oxide), IO (indium oxide), or the like may be used.
半導体層４０の上面に、所定の距離を隔てて対向するように、ソース電極６０ａとドレイン電極６０ｂが配置されている。ソース電極６０ａは半導体層４０の左上面から左側のゲート絶縁膜３０上まで延在するように形成されている。ドレイン電極６０ｂは半導体層４０の右上面から右側のゲート絶縁膜３０上まで延在するように形成されている。
The source electrode 60a and the drain electrode 60b are arranged on the upper surface of the semiconductor layer 40 so as to face each other with a predetermined distance. The source electrode 60 a is formed so as to extend from the upper left surface of the semiconductor layer 40 to the left gate insulating film 30. The drain electrode 60 b is formed so as to extend from the right upper surface of the semiconductor layer 40 to the right gate insulating film 30.
なお、チャネル領域４０ａの低抵抗領域４０ｂは、チャネル領域４０ａだけではなく、ソース電極６０ａおよびドレイン電極６０ｂの側面から幅方向にはみ出した半導体層４０ｅにも形成されている。しかし、側面からはみ出した半導体層４０ｅは、ソース電極６０ａおよびドレイン電極６０ｂを形成する際のアライメントマージンを確保するためのものであり、その幅はソース電極６０ａおよびドレイン電極６０ｂの幅の１／１０以下である。このように、側面からはみ出した半導体層４０ｅに形成されている低抵抗領域は、本発明と直接関係していないので、本明細書ではその説明を省略する。
The low resistance region 40b of the channel region 40a is formed not only in the channel region 40a but also in the semiconductor layer 40e protruding in the width direction from the side surfaces of the source electrode 60a and the drain electrode 60b. However, the semiconductor layer 40e protruding from the side surface is for securing an alignment margin when forming the source electrode 60a and the drain electrode 60b, and its width is 1/10 of the width of the source electrode 60a and the drain electrode 60b. It is as follows. Thus, since the low resistance region formed in the semiconductor layer 40e protruding from the side surface is not directly related to the present invention, the description thereof is omitted in this specification.
ソース電極６０ａおよびドレイン電極６０ｂは、例えば、チタン、アルミニウム、タンタル、タングステン、モリブデン、金（Ａｕ）等のうち、いずれかの金属によって構成されていてもよく、また、絶縁基板１５の表面側から、例えばチタン、アルミニウム、チタンを順に積層した積層金属膜によって構成されていてもよい。
The source electrode 60a and the drain electrode 60b may be made of any metal among, for example, titanium, aluminum, tantalum, tungsten, molybdenum, gold (Au), and the like, and from the surface side of the insulating substrate 15. For example, you may be comprised by the laminated metal film which laminated | stacked titanium, aluminum, and titanium in order.
ソース電極６０ａの右端部はゲート電極２０の左側部の上方に配置され、ドレイン電極６０ｂの左端部はゲート電極２０の右側部の上方に配置されている。このため、ゲート電極２０に所定の電圧が印加されたとき、ゲート電極２０からの電界によって、半導体層４０の各低抵抗領域４０ｂに電子が誘起され、高濃度キャリア層が形成される。高濃度キャリア層が形成されることにより、ソース電極６０ａおよびドレイン電極６０ｂは、２つの低抵抗領域４０ｂとそれぞれオーミック接続される。
The right end portion of the source electrode 60a is disposed above the left side portion of the gate electrode 20, and the left end portion of the drain electrode 60b is disposed above the right side portion of the gate electrode 20. For this reason, when a predetermined voltage is applied to the gate electrode 20, electrons are induced in each low resistance region 40 b of the semiconductor layer 40 by the electric field from the gate electrode 20, thereby forming a high concentration carrier layer. By forming the high concentration carrier layer, the source electrode 60a and the drain electrode 60b are ohmically connected to the two low resistance regions 40b, respectively.
ソース電極６０ａおよびドレイン電極６０ｂを含む絶縁基板１５の全体を覆うように、パッシベーション膜９０が形成されている。パッシベーション膜９０は、膜厚２００～３００ｎｍの酸化シリコンからなる（「第２の酸化シリコン膜」ともいう）。なお、パッシベーション膜９０は、酸化シリコン膜（「第２の酸化シリコン膜」ともいう）と、窒化シリコン膜（「第２の窒化シリコン膜」ともいう）とが順に積層された積層絶縁膜であってもよい。この場合、外部から侵入する水分は窒化シリコン膜によって阻止されるので、ＴＦＴ１００の各構成要素が水分によって腐食されることを防止できる。これにより、ＴＦＴ１００の信頼性を確保することができる。
A passivation film 90 is formed so as to cover the entire insulating substrate 15 including the source electrode 60a and the drain electrode 60b. The passivation film 90 is made of silicon oxide having a thickness of 200 to 300 nm (also referred to as “second silicon oxide film”). Note that the passivation film 90 is a stacked insulating film in which a silicon oxide film (also referred to as “second silicon oxide film”) and a silicon nitride film (also referred to as “second silicon nitride film”) are sequentially stacked. May be. In this case, moisture entering from the outside is blocked by the silicon nitride film, so that each component of the TFT 100 can be prevented from being corroded by moisture. Thereby, the reliability of the TFT 100 can be ensured.
後述するように、パッシベーション膜９０の形成後に行うアニールによって、酸素が減少した半導体層４０に、外部からの酸素と、パッシベーション膜９０に含まれる酸素が供給され、チャネル領域４０ａに高抵抗領域４０ｃが形成される。このようにして形成された高抵抗領域４０ｃのチャネル方向の長さがＴＦＴ１００の実効チャネル長になる。
As will be described later, external oxygen and oxygen contained in the passivation film 90 are supplied to the semiconductor layer 40 in which oxygen has been reduced by annealing performed after the formation of the passivation film 90, and the high resistance region 40c is formed in the channel region 40a. It is formed. The length in the channel direction of the high resistance region 40 c formed in this way becomes the effective channel length of the TFT 100.
なお、本明細書では、２つの低抵抗領域４０ｂとそれらに挟まれた高抵抗領域４０ｃとを合わせた領域、すなわち、ソース電極６０ａとドレイン電極６０ｂとによって挟まれた領域をチャネル領域４０ａという。また、半導体層の上面の一部を覆うソース電極およびドレイン電極が形成されているＴＦＴをトップコンタクト構造のＴＦＴということがある。さらに、チャネル領域の表面がエッチングストッパ層によって覆われていないＴＦＴをチャネルエッチ構造のＴＦＴということがある。したがって、ＴＦＴ１００は、トップコンタクト構造のＴＦＴであり、チャネルエッチ構造のＴＦＴでもある。
In this specification, a region where two low resistance regions 40b and a high resistance region 40c sandwiched between them are combined, that is, a region sandwiched between the source electrode 60a and the drain electrode 60b is referred to as a channel region 40a. A TFT in which a source electrode and a drain electrode covering a part of the upper surface of the semiconductor layer are sometimes referred to as a top contact TFT. Furthermore, a TFT in which the surface of the channel region is not covered with an etching stopper layer is sometimes referred to as a channel-etched TFT. Therefore, the TFT 100 is a TFT with a top contact structure and a TFT with a channel etch structure.
＜１．２ ＴＦＴの製造方法＞
図２（Ａ）～図２（Ｄ）および図３（Ａ）～図３（Ｃ）は、ＴＦＴ１００の各製造工程を示す工程断面図である。 <1.2 TFT manufacturing method>
FIGS. 2A to 2D and FIGS. 3A to 3C are process cross-sectional views showing each manufacturing process of theTFT 100. FIG.
図２（Ａ）～図２（Ｄ）および図３（Ａ）～図３（Ｃ）は、ＴＦＴ１００の各製造工程を示す工程断面図である。 <1.2 TFT manufacturing method>
FIGS. 2A to 2D and FIGS. 3A to 3C are process cross-sectional views showing each manufacturing process of the
絶縁基板１５上に、スパッタリング法を用いて、ゲート電極２０となる金属膜（図示しない）を膜厚１００～３００ｎｍとなるように成膜する。次に、金属膜の表面に、フォトリソグラフィ法を用いてレジストパターン（図示しない）を形成する。次に、図２（Ａ）に示すように、レジストパターンをマスクにして、金属膜をウエットエッチング法によりエッチングし、ゲート電極２０を形成する。その後、レジストパターンを剥離する。
A metal film (not shown) to be the gate electrode 20 is formed on the insulating substrate 15 by a sputtering method so as to have a film thickness of 100 to 300 nm. Next, a resist pattern (not shown) is formed on the surface of the metal film using a photolithography method. Next, as shown in FIG. 2A, the metal film is etched by wet etching using the resist pattern as a mask to form the gate electrode 20. Thereafter, the resist pattern is peeled off.
図２（Ｂ）に示すように、プラズマ化学気相成長法（Chemical Vapor Deposition：以下、「プラズマＣＶＤ法」という）を用いて、原料ガスを切り換えることにより、ゲート電極２０を含む絶縁基板１５の全体を覆うように、窒化シリコン膜３１と酸化シリコン膜３２を連続して成膜し、ゲート絶縁膜３０を形成する。ゲート絶縁膜３０の膜厚は３００～４００ｎｍである。このとき、酸化シリコン膜３２の膜厚は、ゲート絶縁膜３０の膜厚の５０～６０％程度であることが好ましい。なお、成膜時の絶縁基板１５の温度（以下、「基板温度」という）を３００～４００℃とする。
As shown in FIG. 2B, the insulating substrate 15 including the gate electrode 20 is switched by using a plasma chemical vapor deposition method (Chemical Vapor Deposition: hereinafter referred to as “plasma CVD method”) to switch the source gas. A silicon nitride film 31 and a silicon oxide film 32 are successively formed so as to cover the whole, and a gate insulating film 30 is formed. The thickness of the gate insulating film 30 is 300 to 400 nm. At this time, the thickness of the silicon oxide film 32 is preferably about 50 to 60% of the thickness of the gate insulating film 30. The temperature of the insulating substrate 15 during film formation (hereinafter referred to as “substrate temperature”) is set to 300 to 400 ° C.
図２（Ｃ）に示すように、ゲート絶縁膜３０上に、スパッタリング法を用いて、酸化物半導体膜４５を成膜する。酸化物半導体膜４５は、例えば、インジウム、ガリウム、亜鉛および酸素を含むＩＧＺＯからなる。酸化物半導体膜４５は、酸化インジウム（Ｉｎ2Ｏ3）と酸化ガリウム（Ｇａ2Ｏ3）と酸化亜鉛（ＺｎＯ）をそれぞれ等モルずつ混合して焼結したターゲットを用い、ＤＣ（Direct Current）スパッタリング法により成膜する。酸化物半導体膜４５の膜厚は４０～５０ｎｍである。なお、スパッタリングは、チャンバ内に、流量１００～３００ｓｃｃｍのアルゴン（Ａｒ）ガスと、流量５～２０ｓｃｃｍの酸素（Ｏ2）ガスを導入して行われる。このときの基板温度を２００～４００℃とする。成膜直後の酸化物半導体膜４５には酸素が多く含まれているので、酸化物半導体膜４５の全体が高抵抗領域になっている。なお、酸化物半導体膜４５は、スパッタリング法の代わりに、塗布方式を用いて成膜してもよい。
As illustrated in FIG. 2C, the oxide semiconductor film 45 is formed over the gate insulating film 30 by a sputtering method. The oxide semiconductor film 45 is made of, for example, IGZO containing indium, gallium, zinc, and oxygen. The oxide semiconductor film 45 uses a target in which indium oxide (In 2 O 3 ), gallium oxide (Ga 2 O 3 ), and zinc oxide (ZnO) are mixed in an equimolar amount and sintered, and DC (Direct Current). A film is formed by sputtering. The thickness of the oxide semiconductor film 45 is 40 to 50 nm. Sputtering is performed by introducing argon (Ar) gas having a flow rate of 100 to 300 sccm and oxygen (O 2 ) gas having a flow rate of 5 to 20 sccm into the chamber. The substrate temperature at this time is set to 200 to 400.degree. Since the oxide semiconductor film 45 immediately after deposition contains a large amount of oxygen, the entire oxide semiconductor film 45 is a high resistance region. Note that the oxide semiconductor film 45 may be formed by a coating method instead of the sputtering method.
また、酸化物半導体膜４５が微結晶のＩＧＺＯ膜である場合には、非晶質のＩＧＺＯ膜を上述の方法によって成膜後に、４００～５００℃の大気雰囲気中で、１～２時間程度のアニールを行なう。または、大気雰囲気中でアニールを行なう代わりに、窒素（Ｎ2）等の不活性ガス雰囲気中で、ＲＴＡ（Rapid Thermal Anneal）を行なってもよい。ＲＴＡは、例えば５００～７５０℃において、１～１０分程度行なう。
In the case where the oxide semiconductor film 45 is a microcrystalline IGZO film, an amorphous IGZO film is formed by the above-described method, and then in an air atmosphere at 400 to 500 ° C. for about 1 to 2 hours. Annealing is performed. Alternatively, RTA (Rapid Thermal Anneal) may be performed in an inert gas atmosphere such as nitrogen (N 2 ) instead of annealing in an air atmosphere. RTA is performed, for example, at 500 to 750 ° C. for about 1 to 10 minutes.
図２（Ｄ）に示すように、酸化物半導体膜４５の表面にレジストパターン４８を形成する。レジストパターン４８をマスクとして酸化物半導体膜４５をドライエッチング法によりエッチングし、島状の半導体層４０を形成する。その後、レジストパターン４８を剥離する。このとき、半導体層４０のチャネル領域の幅方向の両端部に、切り欠き部（図示しない）が形成される。なお、切り欠き部を有する半導体層４０を形成する工程では、パターンを変更したマスクに代えるだけでよく、工程を変更したり新たな工程を追加したりする必要はない。
As shown in FIG. 2D, a resist pattern 48 is formed on the surface of the oxide semiconductor film 45. Using the resist pattern 48 as a mask, the oxide semiconductor film 45 is etched by dry etching to form an island-shaped semiconductor layer 40. Thereafter, the resist pattern 48 is peeled off. At this time, notches (not shown) are formed at both ends in the width direction of the channel region of the semiconductor layer 40. Note that in the process of forming the semiconductor layer 40 having the notch, it is only necessary to replace the mask with a changed pattern, and there is no need to change the process or add a new process.
スパッタリング法を用いて、ソースメタル膜（図示しない）を成膜する。成膜されたソースメタル膜の膜厚は１００～３００ｎｍである。次に、図３（Ａ）に示すように、フォトリソグラフィ法を用いて、ゲート電極２０の上方のソースメタル膜上に、所定の距離を隔てて左右に分離されたレジストパターン６８を形成する。レジストパターン６８の左右の端部間の距離は、ゲート電極２０の長さよりも短くなるように形成されているので、レジストパターン６８は、ゲート電極２０の左右の端部をそれぞれ覆っている。
A source metal film (not shown) is formed by sputtering. The film thickness of the formed source metal film is 100 to 300 nm. Next, as shown in FIG. 3A, a resist pattern 68 separated left and right at a predetermined distance is formed on the source metal film above the gate electrode 20 by photolithography. Since the distance between the left and right ends of the resist pattern 68 is formed to be shorter than the length of the gate electrode 20, the resist pattern 68 covers the left and right ends of the gate electrode 20.
レジストパターン６８をマスクにして、ドライエッチング法により、ソースメタル膜をエッチングし、ソース電極６０ａとドレイン電極６０ｂを形成する。これにより、ソース電極６０ａは、半導体層４０の左上面から左側のゲート絶縁膜３０上まで延在する。ドレイン電極６０ｂは、半導体層４０の右上面から右側のゲート絶縁膜３０上まで延在する。その後、レジストパターン６８を剥離する。なお、半導体層４０の表面にはエッチングストッパ層が形成されていないので、半導体層４０の表面がエッチングされることを極力抑えるため、ソースメタル膜と半導体層４０との選択比が高いエッチング条件でソースメタル膜をエッチングすることが好ましい。
Using the resist pattern 68 as a mask, the source metal film is etched by dry etching to form a source electrode 60a and a drain electrode 60b. Thereby, the source electrode 60 a extends from the upper left surface of the semiconductor layer 40 to the left gate insulating film 30. The drain electrode 60 b extends from the right upper surface of the semiconductor layer 40 to the right gate insulating film 30. Thereafter, the resist pattern 68 is peeled off. In addition, since the etching stopper layer is not formed on the surface of the semiconductor layer 40, in order to suppress the etching of the surface of the semiconductor layer 40 as much as possible, an etching condition with a high selectivity between the source metal film and the semiconductor layer 40 is used. It is preferable to etch the source metal film.
図３（Ｂ）に示すように、ソース電極６０ａおよびドレイン電極６０ｂを含む絶縁基板１５の全体を覆うように、プラズマＣＶＤ法を用いて、酸化シリコンからなるパッシベーション膜９０を成膜する。パッシベーション膜９０は、半導体層４０と接触している。パッシベーション膜９０は、半導体層４０を構成するＩＧＺＯに酸素を供給するために、酸化シリコンからなることが好ましく、その膜厚は２００～３００ｎｍであることが好ましい。また、成膜時の基板温度は２００～３００℃である。このように、パッシベーション膜９０の成膜時に基板を加熱するので、ソース電極６０ａおよびドレイン電極６０ｂは、半導体層４０から酸素を奪い取るとともに、半導体層４０に水素を供給することによって、半導体層４０を還元する。これにより、半導体層４０のソース電極６０ａおよびドレイン電極６０ｂの近傍に、それらの端部に沿って低抵抗領域４０ｂが形成される。また、２つの低抵抗領域４０ｂに挟まれた高抵抗領域からも酸素が抜け、中抵抗領域４０ｄが形成される。
As shown in FIG. 3B, a passivation film 90 made of silicon oxide is formed by plasma CVD so as to cover the entire insulating substrate 15 including the source electrode 60a and the drain electrode 60b. The passivation film 90 is in contact with the semiconductor layer 40. The passivation film 90 is preferably made of silicon oxide in order to supply oxygen to IGZO constituting the semiconductor layer 40, and the film thickness is preferably 200 to 300 nm. The substrate temperature during film formation is 200 to 300.degree. Thus, since the substrate is heated when the passivation film 90 is formed, the source electrode 60 a and the drain electrode 60 b take oxygen from the semiconductor layer 40 and supply hydrogen to the semiconductor layer 40, thereby forming the semiconductor layer 40. Reduce. Thereby, the low resistance region 40b is formed in the vicinity of the source electrode 60a and the drain electrode 60b of the semiconductor layer 40 along the end portions thereof. Further, oxygen is also released from the high resistance region sandwiched between the two low resistance regions 40b, and the middle resistance region 40d is formed.
次に、２００～４００℃のドライエア雰囲気中で、１～２時間程度のアニール（「熱処理」ともいう）を行う。ドライエア中でアニールすることにより、酸素が減少した半導体層４０に、外部からの酸素と、パッシベーション膜９０を構成する酸化シリコンからの酸素が供給される。これにより、パッシベーション膜９０の成膜時に形成された低抵抗領域４０ｂの面積が狭くなるとともに、中抵抗領域４０ｄにも酸素が供給されて高抵抗領域４０ｃになる。なお、アニールは、ドライエア雰囲気中ではなく、酸素雰囲気中または酸素を含む雰囲気中で行ってもよい。また、パッシベーション膜９０のアニールは、酸素を含まない雰囲気、例えば窒素雰囲気中で行なってもよい。この場合も、正常なトランジスタ特性を有するＴＦＴが製造される。これは、パッシベーション膜９０を構成する酸化シリコンから酸素が供給されたり、チャネル領域４０ａに過剰に酸素が存在したりしていたためであると推測される。
Next, annealing (also referred to as “heat treatment”) is performed in a dry air atmosphere at 200 to 400 ° C. for about 1 to 2 hours. By annealing in dry air, oxygen from the outside and oxygen from silicon oxide constituting the passivation film 90 are supplied to the semiconductor layer 40 in which oxygen is reduced. As a result, the area of the low resistance region 40b formed at the time of forming the passivation film 90 is reduced, and oxygen is also supplied to the middle resistance region 40d to become the high resistance region 40c. Note that annealing may be performed not in a dry air atmosphere but in an oxygen atmosphere or an atmosphere containing oxygen. Further, the annealing of the passivation film 90 may be performed in an oxygen-free atmosphere, for example, a nitrogen atmosphere. Also in this case, a TFT having normal transistor characteristics is manufactured. This is presumably because oxygen was supplied from silicon oxide constituting the passivation film 90 or excessive oxygen was present in the channel region 40a.
＜１．３ 効果＞
半導体層４０のチャネル領域４０ａに切り欠き部４１を設けることにより、半導体層４０の側面の表面積が大きくなる。一方、半導体層４０の側面は、ゲート絶縁膜３０を構成する酸化シリコン膜３２と、酸化シリコンからなるパッシベーション膜９０とによって挟まれているので、半導体層４０のチャネル領域４０ａの側面の面積が大きくなれば、チャネル領域４０ａと、酸化シリコン膜３２およびパッシベーション膜９０との接触面積が大きくなる。ドライエア雰囲気中でアニールを行うことにより、半導体層４０を構成するチャネル領域４０ａの酸化物半導体に、外部からの酸素と、酸化シリコン膜３２およびパッシベーション膜９０に含まれる十分な量の酸素が供給される。チャネル領域４０ａの酸化物半導体は、酸素を取り込むことによって酸化が進み、低抵抗領域４０ｂの面積が狭くなるとともに、中抵抗領域４０ｄはより抵抗値が高い高抵抗領域４０ｃになる。これにより、ＴＦＴ１００のオフ電流は１×１０-10～１０-11Ａになり、ＴＦＴ１００は液晶表示装置のスイッチング素子として十分に機能する。 <1.3 Effect>
By providing thenotch 41 in the channel region 40 a of the semiconductor layer 40, the surface area of the side surface of the semiconductor layer 40 is increased. On the other hand, since the side surface of the semiconductor layer 40 is sandwiched between the silicon oxide film 32 constituting the gate insulating film 30 and the passivation film 90 made of silicon oxide, the area of the side surface of the channel region 40a of the semiconductor layer 40 is large. Then, the contact area between the channel region 40a, the silicon oxide film 32, and the passivation film 90 is increased. By performing annealing in a dry air atmosphere, oxygen from the outside and a sufficient amount of oxygen contained in the silicon oxide film 32 and the passivation film 90 are supplied to the oxide semiconductor in the channel region 40a constituting the semiconductor layer 40. The Oxidation of the oxide semiconductor in the channel region 40a proceeds by incorporating oxygen, and the area of the low-resistance region 40b becomes narrow, and the middle-resistance region 40d becomes a high-resistance region 40c having a higher resistance value. Accordingly, the off current of the TFT 100 becomes 1 × 10 −10 to 10 −11 A, and the TFT 100 sufficiently functions as a switching element of the liquid crystal display device.
半導体層４０のチャネル領域４０ａに切り欠き部４１を設けることにより、半導体層４０の側面の表面積が大きくなる。一方、半導体層４０の側面は、ゲート絶縁膜３０を構成する酸化シリコン膜３２と、酸化シリコンからなるパッシベーション膜９０とによって挟まれているので、半導体層４０のチャネル領域４０ａの側面の面積が大きくなれば、チャネル領域４０ａと、酸化シリコン膜３２およびパッシベーション膜９０との接触面積が大きくなる。ドライエア雰囲気中でアニールを行うことにより、半導体層４０を構成するチャネル領域４０ａの酸化物半導体に、外部からの酸素と、酸化シリコン膜３２およびパッシベーション膜９０に含まれる十分な量の酸素が供給される。チャネル領域４０ａの酸化物半導体は、酸素を取り込むことによって酸化が進み、低抵抗領域４０ｂの面積が狭くなるとともに、中抵抗領域４０ｄはより抵抗値が高い高抵抗領域４０ｃになる。これにより、ＴＦＴ１００のオフ電流は１×１０-10～１０-11Ａになり、ＴＦＴ１００は液晶表示装置のスイッチング素子として十分に機能する。 <1.3 Effect>
By providing the
しかも、ＴＦＴ１００では、ソース電極６０ａおよびドレイン電極６０ｂの幅を、半導体層４０のチャネル領域４０ａの幅よりも広くするとともに、ソース電極６０ａおよびドレイン電極６０ｂに、半導体層４０の表面を露出させるための開口部を設けていない。これにより、ソース電極６０ａおよびドレイン電極６０ｂは、その裏面全体で半導体層４０と電気的に接触するので、ソース電極６０ａおよびドレイン電極６０ｂと、半導体層４０とのコンタクト抵抗を低く保つことができる。これにより、ＴＦＴ１００のオン電流の低下を防ぐことができるので、オン・オフ比を大きくすることができる。
Moreover, in the TFT 100, the width of the source electrode 60a and the drain electrode 60b is made wider than the width of the channel region 40a of the semiconductor layer 40, and the surface of the semiconductor layer 40 is exposed to the source electrode 60a and the drain electrode 60b. There is no opening. Thereby, since the source electrode 60a and the drain electrode 60b are in electrical contact with the semiconductor layer 40 over the entire back surface, the contact resistance between the source electrode 60a and the drain electrode 60b and the semiconductor layer 40 can be kept low. As a result, a decrease in the on-current of the TFT 100 can be prevented, so that the on / off ratio can be increased.
また、ドライエア雰囲気中でのアニールによって、外部から半導体層４０に供給される酸素は、半導体層４０を構成する酸化物半導体が微結晶である場合よりも、非晶質である場合により多くなる。これにより、酸化物半導体が非晶質である場合には、微結晶である場合よりも、チャネル領域４０ａの酸化がより一層進み、低抵抗領域４０ｂの面積がより一層狭くなるとともに、中抵抗領域４０ｄはより一層抵抗値が高い高抵抗領域４０ｃになる。これは、微結晶からなる酸化物半導体の膜密度が高いので、外部からの酸素がチャネル領域４０ａに供給されにくくなるためであると考えられる。
Further, the oxygen supplied to the semiconductor layer 40 from the outside by annealing in a dry air atmosphere is larger when the oxide semiconductor constituting the semiconductor layer 40 is amorphous than when it is microcrystalline. Accordingly, when the oxide semiconductor is amorphous, the channel region 40a is further oxidized and the area of the low-resistance region 40b is further narrowed and the medium-resistance region is smaller than when the oxide semiconductor is microcrystalline. 40d becomes a high resistance region 40c having a higher resistance value. This is considered to be because oxygen from the outside is hardly supplied to the channel region 40a because the film density of the oxide semiconductor made of microcrystals is high.
また、ＴＦＴ１００のチャネル領域４０ａに切り欠き部４１を設けることにより、異物９９を介した短絡を防ぐことができる。図４は、異物９９とチャネル領域４０ａとの位置関係を示す図であり、より詳しくは、図４（Ａ）はチャネル領域４４ａの両端部に切り欠き部を設けない場合の異物９９とチャネル領域４０ａとの位置関係を示す図であり、図４（Ｂ）はチャネル領域４０ａの両端部に切り欠き部４１を設けた場合の異物９９とチャネル領域４０ａとの位置関係を示す図である。ソース電極６０ａおよびドレイン電極６０ｂをドライエッチング法によって形成する際に、エッチングガスとして、例えば四フッ化メタン（ＣＦ4）等のフッ素系ガス、または、三塩化ホウ素（ＢＣｌ3）やＣｌ2（塩素）等の塩素系ガスが使用される。これらのガスを用いて、例えば、モリブデンからなるソースメタル膜をエッチングした場合には、ＭｏＦｘまたはＭｏＣｌｘが生成される。また、フッ素系ガスを用いてアルミニウムからなるソースメタル膜をエッチングした場合には、ＡｌＦｘが生成される。エッチング時にプラズマＣＶＤ装置の内壁に付着したこれらの金属フッ化物または金属塩化物は、エッチング中またはエッチング終了後に内壁から剥がれてソース金属膜上に落下する場合がある。このとき、図４（Ａ）に示すように、落下した異物９９の一端が、その後の工程によって、ソース電極６０ａに隣接する半導体層４４の低抵抗領域４４ｂと電気的に接触し、他端がドレイン電極６０ｂに隣接する半導体層４４の低抵抗領域４０ｂと電気的に接触する場合がある。この場合、ソース電極６０ａとドレイン電極６０ｂは、２つの低抵抗領域４４ｂと異物９９を介して電気的に接続されることにより短絡する。
Further, by providing the notch 41 in the channel region 40 a of the TFT 100, a short circuit through the foreign material 99 can be prevented. FIG. 4 is a diagram showing the positional relationship between the foreign matter 99 and the channel region 40a. More specifically, FIG. 4A shows the foreign matter 99 and the channel region when notch portions are not provided at both ends of the channel region 44a. 4B is a diagram showing the positional relationship between the foreign matter 99 and the channel region 40a when the notch portions 41 are provided at both ends of the channel region 40a. When the source electrode 60a and the drain electrode 60b are formed by a dry etching method, as an etching gas, for example, a fluorine-based gas such as methane tetrafluoride (CF 4 ), or boron trichloride (BCl 3 ) or Cl 2 (chlorine). Chlorine gas such as) is used. For example, when a source metal film made of molybdenum is etched using these gases, MoFx or MoClx is generated. In addition, when a source metal film made of aluminum is etched using a fluorine-based gas, AlFx is generated. These metal fluorides or metal chlorides adhering to the inner wall of the plasma CVD apparatus at the time of etching may be peeled off from the inner wall during the etching or after the etching is finished and fall onto the source metal film. At this time, as shown in FIG. 4A, one end of the fallen foreign material 99 is in electrical contact with the low resistance region 44b of the semiconductor layer 44 adjacent to the source electrode 60a in the subsequent process, and the other end is In some cases, the low resistance region 40b of the semiconductor layer 44 adjacent to the drain electrode 60b is in electrical contact. In this case, the source electrode 60a and the drain electrode 60b are short-circuited by being electrically connected via the two low-resistance regions 44b and the foreign matter 99.
しかし、ＴＦＴ１００では、図４（Ｂ）に示すように、図４（Ａ）と同じ位置に金属塩化物または金属フッ化物からなる異物９９が落下しても、異物９９が落下した位置では、半導体層４０を形成する際のエッチングによって切り欠き部４１が形成されている。この場合、異物９９が落下した位置は、切り欠き部４１であるため、低抵抗領域４０ｂは形成されていない。このため、ソース電極６０ａとドレイン電極６０ｂとが異物９９によって短絡することはない。このように、ＴＦＴ１００では、異物９９によるソース電極６０ａとドレイン電極６０ｂとの短絡の可能性を減らすことができる。
However, in the TFT 100, as shown in FIG. 4B, even if the foreign matter 99 made of metal chloride or metal fluoride falls at the same position as in FIG. A notch 41 is formed by etching when the layer 40 is formed. In this case, the position where the foreign material 99 has fallen is the cutout portion 41, and thus the low resistance region 40b is not formed. For this reason, the source electrode 60a and the drain electrode 60b are not short-circuited by the foreign matter 99. Thus, in the TFT 100, the possibility of a short circuit between the source electrode 60a and the drain electrode 60b due to the foreign matter 99 can be reduced.
また、ＴＦＴ１００のチャネル領域４０ａに切り欠き部４１を設けることにより、絶縁基板１５側からＴＦＴ１００に入射したバックライト光の多重反射に起因する電流の発生を防ぐことができる。図５は、多重反射の影響を示す図であり、より詳しくは、図５（Ａ）はチャネル領域４４ａの両端部に切り欠き部を設けない場合の多重反射の影響を示す図であり、図５（Ｂ）はチャネル領域４０ａの両端部に切り欠き部４１を設けた場合の多重反射の影響を示す図である。図５（Ａ）に示すように、裏面側から従来のＴＦＴに照射されたバックライト光は、ゲート電極２０の表面とドレイン電極６０ｂの裏面との間で反射を繰り返しながら、チャネル領域４４ａに向かって進む。バックライト光はチャネル領域４４ａに到達すると、チャネル領域４４ａで半導体層４４に吸収され、チャネル領域４４ａに伝導電子を発生させる。このように、切り欠き部を設けていないＴＦＴでは、バックライト光の多重反射による電流が流れやすくなる。
Also, by providing the notch 41 in the channel region 40a of the TFT 100, it is possible to prevent the generation of current due to multiple reflection of the backlight light incident on the TFT 100 from the insulating substrate 15 side. FIG. 5 is a diagram showing the influence of multiple reflection. More specifically, FIG. 5A is a diagram showing the influence of multiple reflection when notches are not provided at both ends of the channel region 44a. FIG. 5B is a diagram showing the influence of multiple reflection when notches 41 are provided at both ends of the channel region 40a. As shown in FIG. 5A, the backlight light applied to the conventional TFT from the back surface side is directed toward the channel region 44a while being repeatedly reflected between the surface of the gate electrode 20 and the back surface of the drain electrode 60b. Go ahead. When the backlight light reaches the channel region 44a, it is absorbed by the semiconductor layer 44 in the channel region 44a and generates conduction electrons in the channel region 44a. As described above, in a TFT not provided with a notch, a current easily flows due to multiple reflection of backlight light.
一方、図５（Ｂ）に示すように、半導体層４０に切り欠き部４１を設けることにより、ゲート電極２０の表面とドレイン電極６０ｂの裏面との間で多重反射を繰り返しながら進むバックライト光は、半導体層４０のチャネル領域４０ａに到達する。バックライト光が到達したチャネル領域４０ａが切り欠き部４１である場合には、バックライト光は切り欠き部４１を通過する。この場合、バックライト光は、チャネル領域４０ａに吸収されないので、チャネル領域４０ａに伝導電子を発生させない。このため、ＴＦＴ１００では、バックライト光の多重反射による電流を抑制することができる。
On the other hand, as shown in FIG. 5B, by providing the notch 41 in the semiconductor layer 40, the backlight light traveling while repeating multiple reflections between the surface of the gate electrode 20 and the back surface of the drain electrode 60b is The channel region 40a of the semiconductor layer 40 is reached. When the channel region 40 a to which the backlight light reaches is the cutout portion 41, the backlight light passes through the cutout portion 41. In this case, since the backlight light is not absorbed by the channel region 40a, conduction electrons are not generated in the channel region 40a. For this reason, in TFT100, the electric current by the multiple reflection of backlight light can be suppressed.
図６は、ＴＦＴ１００として動作する設計時のチャネル長とチャネル幅との関係を示す図である。図７は、低抵抗領域の形状を示す予想平面図であり、より詳しくは、図７（Ａ）は、切り欠き部を設けない場合の低抵抗領域４４ｂの形状を示す予想平面図であり、図７（Ｂ）は、切り欠き部４１を設けた場合の低抵抗領域４０ｂの形状を示す予想平面図である。上述のＴＦＴ１００の説明では、チャネル領域４０ａに形成されるチャネル方向の低抵抗領域４０ｂの長さは、チャネル幅に依らず一定であるとした。しかし、実際には、図６に示すように、チャネル幅が２０μｍよりも狭くなると、それに伴ってチャネル長も短くなるという現象が現われる。この現象から、チャネル領域４４ａでは、低抵抗領域４４ｂのチャネル方向の長さは一定ではなく、チャネル幅に応じて不規則に変化していると推測される。このように、低抵抗領域４４ｂの形状が不規則に変化しているとするならば、ソース電極６０ａ側の低抵抗領域４４ｂの先端と、ドレイン電極６０ｂ側の低抵抗領域４４ｂの先端とが重なり合うことによって、ソース電極６０ａとドレイン電極６０ｂとが電気的に接続される場合があると推測される（図７（Ａ）参照）。このようなＴＦＴでは、ゲート電極２０によって電流を制御することができないので、電流ソース電極６０ａとドレイン電極６０ｂとの間に常時流れる。この場合、ＴＦＴは、トランジスタとしてではなく、抵抗素子として動作する。
FIG. 6 is a diagram showing the relationship between the channel length and the channel width at the time of designing to operate as the TFT 100. FIG. 7 is an expected plan view showing the shape of the low resistance region, and more specifically, FIG. 7A is an expected plan view showing the shape of the low resistance region 44b in the case where the notch portion is not provided. FIG. 7B is an expected plan view showing the shape of the low resistance region 40b when the notch 41 is provided. In the description of the TFT 100 described above, the length of the low resistance region 40b in the channel direction formed in the channel region 40a is assumed to be constant regardless of the channel width. However, in practice, as shown in FIG. 6, when the channel width becomes narrower than 20 μm, the phenomenon that the channel length also becomes short accompanying it appears. From this phenomenon, it is presumed that in the channel region 44a, the length of the low resistance region 44b in the channel direction is not constant but varies irregularly according to the channel width. Thus, if the shape of the low resistance region 44b is irregularly changed, the tip of the low resistance region 44b on the source electrode 60a side and the tip of the low resistance region 44b on the drain electrode 60b side overlap. Thus, it is estimated that the source electrode 60a and the drain electrode 60b may be electrically connected (see FIG. 7A). In such a TFT, since the current cannot be controlled by the gate electrode 20, it always flows between the current source electrode 60a and the drain electrode 60b. In this case, the TFT operates not as a transistor but as a resistance element.
しかし、半導体層４０のチャネル領域４０ａに切り欠き部４１を設ければ、切り欠き部４１に低抵抗領域４０ｂが形成されることはない。そこで、図７（Ｂ）に示すように、図７（Ａ）と同じ位置に、低抵抗領域４０ｂのチャネル方向の長さが長くなる部分（点線で表わした部分）が形成される場合に、ソース電極６０ａ側の低抵抗領域４０ｂの先端と、ドレイン電極６０ｂ側の低抵抗領域４０ｂの先端とが重なり合うことを防ぐことができる。また、切り欠き部４１を設けることにより、低抵抗領域４０ｂの不規則な形状の変化もある程度抑制されると予想される。これらのことからも、低抵抗領域４０ｂの先端同士が重なり合う可能性が低下すると推測される。このため、ＴＦＴ１００は、抵抗素子として動作する可能性が低くなると推測される。
However, if the notch 41 is provided in the channel region 40 a of the semiconductor layer 40, the low resistance region 40 b is not formed in the notch 41. Therefore, as shown in FIG. 7B, when a portion (a portion indicated by a dotted line) in which the length in the channel direction of the low resistance region 40b is increased is formed at the same position as FIG. It is possible to prevent the tip of the low resistance region 40b on the source electrode 60a side and the tip of the low resistance region 40b on the drain electrode 60b side from overlapping each other. In addition, it is expected that the irregular shape change of the low resistance region 40b is suppressed to some extent by providing the notch 41. From these things, it is presumed that the possibility that the tips of the low resistance regions 40b overlap each other is reduced. For this reason, it is estimated that the TFT 100 is less likely to operate as a resistance element.
＜１．４ 変形例＞
図８は、本実施形態の変形例に係るボトムゲート型ＴＦＴ２００の構成を示す図であり、より詳しくは、図８（Ａ）は、本実施形態の変形例に係るボトムゲート型ＴＦＴ２００の構成を示す平面図であり、図８（Ｂ）は、図８（Ａ）に示す切断線Ｃ－Ｃに沿ったＴＦＴ２００の断面図であり、図８（Ｃ）は、図８（Ａ）に示す切断線Ｄ－Ｄに沿ったＴＦＴ２００の断面図である。ＴＦＴ２００の構成要素のうち、図１（Ａ）～図１（Ｃ）に示すＴＦＴ１００の構成要素と同一の構成要素については同じ参照符号を付し、異なる構成要素を中心に説明する。 <1.4 Modification>
FIG. 8 is a diagram illustrating a configuration of abottom gate TFT 200 according to a modification of the present embodiment. More specifically, FIG. 8A illustrates a configuration of the bottom gate TFT 200 according to a modification of the present embodiment. 8B is a cross-sectional view of the TFT 200 along the cutting line CC shown in FIG. 8A, and FIG. 8C is a cross-sectional view shown in FIG. 8A. FIG. 10 is a cross-sectional view of the TFT 200 along line DD. Among the constituent elements of the TFT 200, the same constituent elements as those of the TFT 100 shown in FIGS. 1A to 1C are denoted by the same reference numerals, and different constituent elements will be mainly described.
図８は、本実施形態の変形例に係るボトムゲート型ＴＦＴ２００の構成を示す図であり、より詳しくは、図８（Ａ）は、本実施形態の変形例に係るボトムゲート型ＴＦＴ２００の構成を示す平面図であり、図８（Ｂ）は、図８（Ａ）に示す切断線Ｃ－Ｃに沿ったＴＦＴ２００の断面図であり、図８（Ｃ）は、図８（Ａ）に示す切断線Ｄ－Ｄに沿ったＴＦＴ２００の断面図である。ＴＦＴ２００の構成要素のうち、図１（Ａ）～図１（Ｃ）に示すＴＦＴ１００の構成要素と同一の構成要素については同じ参照符号を付し、異なる構成要素を中心に説明する。 <1.4 Modification>
FIG. 8 is a diagram illustrating a configuration of a
図８（Ａ）に示すように、ＴＦＴ２００では、図１（Ａ）に示すＴＦＴ１００の場合と異なり、チャネル領域４０ａの一方の端部のみに切り欠き部４１を設けている。これにより、ＴＦＴ１００の場合に比べて、ＴＦＴ２００では、チャネル領域４０ａの幅が広くなる。また、半導体層４０を形成する際に、パターンを変更したマスクに代えるだけでよく、ＴＦＴ１００の製造工程を変更したり、新たな工程を追加したりする必要はない。
As shown in FIG. 8A, in the TFT 200, unlike the TFT 100 shown in FIG. 1A, a notch 41 is provided only at one end of the channel region 40a. As a result, the width of the channel region 40a is wider in the TFT 200 than in the TFT 100. Further, when forming the semiconductor layer 40, it is only necessary to replace the mask with a changed pattern, and it is not necessary to change the manufacturing process of the TFT 100 or add a new process.
チャネル領域４０ａの一方の端部のみに切り欠き部４１を形成したＴＦＴ２００でも、上述のＴＦＴ１００が奏する各効果と同様の効果を奏すことができる。しかし、ＴＦＴ２００の切り欠き部４１は片側にしか設けられていないので、その効果はＴＦＴ１００が奏する効果の半分になる。
Even in the TFT 200 in which the notch 41 is formed only at one end of the channel region 40a, the same effects as the effects exhibited by the TFT 100 can be obtained. However, since the notch 41 of the TFT 200 is provided only on one side, the effect is half of the effect produced by the TFT 100.
＜２．第２の実施形態＞
＜２．１ ＴＦＴの構成＞
図９は、本発明の第２の実施形態に係るボトムゲート型ＴＦＴ３００の構成を示す図であり、より詳しくは、図９（Ａ）は、本発明の第２の実施形態に係るボトムゲート型ＴＦＴ３００の構成を示す平面図であり、図９（Ｂ）は、図９（Ａ）に示す切断線Ｅ－Ｅに沿ったＴＦＴ３００の断面図であり、図９（Ｃ）は、図９（Ａ）に示す切断線Ｆ－Ｆに沿ったＴＦＴ３００の断面図である。ＴＦＴ３００の構成要素のうち、図１（Ａ）～図１（Ｃ）に示すＴＦＴ１００の構成要素と同一の構成要素については同じ参照符号を付し、異なる構成要素を中心に説明する。 <2. Second Embodiment>
<2.1 TFT configuration>
FIG. 9 is a diagram showing a configuration of a bottomgate type TFT 300 according to the second embodiment of the present invention. More specifically, FIG. 9A shows a bottom gate type TFT according to the second embodiment of the present invention. 9B is a plan view showing the structure of the TFT 300, FIG. 9B is a cross-sectional view of the TFT 300 along the cutting line EE shown in FIG. 9A, and FIG. 9C is FIG. 2 is a cross-sectional view of the TFT 300 taken along a cutting line FF shown in FIG. Among the constituent elements of the TFT 300, the same constituent elements as those of the TFT 100 shown in FIGS. 1A to 1C are denoted by the same reference numerals, and different constituent elements will be mainly described.
＜２．１ ＴＦＴの構成＞
図９は、本発明の第２の実施形態に係るボトムゲート型ＴＦＴ３００の構成を示す図であり、より詳しくは、図９（Ａ）は、本発明の第２の実施形態に係るボトムゲート型ＴＦＴ３００の構成を示す平面図であり、図９（Ｂ）は、図９（Ａ）に示す切断線Ｅ－Ｅに沿ったＴＦＴ３００の断面図であり、図９（Ｃ）は、図９（Ａ）に示す切断線Ｆ－Ｆに沿ったＴＦＴ３００の断面図である。ＴＦＴ３００の構成要素のうち、図１（Ａ）～図１（Ｃ）に示すＴＦＴ１００の構成要素と同一の構成要素については同じ参照符号を付し、異なる構成要素を中心に説明する。 <2. Second Embodiment>
<2.1 TFT configuration>
FIG. 9 is a diagram showing a configuration of a bottom
図９（Ａ）～図９（Ｃ）に示すように、ＴＦＴ３００では、ＴＦＴ１００と異なり、半導体層４０のチャネル領域４０ａの両端部に切り欠き部４１が設けられているだけでなく、チャネル領域４０ａの中央にも切り欠き部４２（「第２の切り欠き部」ともいう）が設けられている。切り欠き部４２は、チャネル方向の長さがソース電極６０ａとドレイン電極６０ｂの端部によって決まる矩形状である。切り欠き部４２では、半導体層４０が切り取られているので、その下層の酸化シリコン膜３２の表面が露出している。
As shown in FIGS. 9A to 9C, in the TFT 300, unlike the TFT 100, not only the notches 41 are provided at both ends of the channel region 40a of the semiconductor layer 40, but also the channel region 40a. A notch 42 (also referred to as “second notch”) is also provided at the center of the notch. The notch 42 has a rectangular shape whose length in the channel direction is determined by the ends of the source electrode 60a and the drain electrode 60b. In the cutout portion 42, the semiconductor layer 40 is cut off, so that the surface of the silicon oxide film 32 underneath is exposed.
ＴＦＴ３００の製造工程は、第１の実施形態で説明したＴＦＴ１００の製造工程のうち、図２（Ｃ）に示す工程において、半導体層４０を形成する際に使用するマスクを、新たな切り欠き部４２となる開口部のパターンを追加したマスクに代えるだけでよく、工程を変更したり新たな工程を追加したりする必要はない。
In the manufacturing process of the TFT 300, the mask used for forming the semiconductor layer 40 in the process shown in FIG. 2C among the manufacturing processes of the TFT 100 described in the first embodiment is replaced with a new notch 42. It is only necessary to replace the mask with the opening pattern to be added, and there is no need to change the process or add a new process.
＜２．２ 効果＞
本実施形態に係るＴＦＴ３００によれば、チャネル領域４０ａには、その両端部だけでなく、中央にも、チャネル方向の長さがソース電極６０ａとドレイン電極６０ｂの端部によって決まる矩形状の切り欠き部４２が形成されている。これにより、ＴＦＴ３００は、ＴＦＴ１００の場合と同様の効果を奏する。具体的には、切り欠き部４２を設けることによって、半導体層４０の側面の面積がより一層大きくなるので、低抵抗領域４０ｂ、および中抵抗領域４０ｄに、外部からの酸素と、酸化シリコン膜３２およびパッシベーション膜９０に含まれる酸素が供給されやすくなる。これにより、ＴＦＴ３００では、ＴＦＴ１００の場合と比較して、チャネル領域４０ａを構成する酸化物半導体は、酸素をより多く取り込むことによってより一層酸化され、低抵抗領域４０ｂの面積はより一層狭くなるとともに、中抵抗領域４０ｄはより一層抵抗値が高い高抵抗領域４０ｃになる。このため、ＴＦＴ３００のオフ電流（リーク電流）は１×１０-10～１０-11Ａになり、ＴＦＴ３００は液晶表示装置のスイッチング素子として十分に機能する。 <2.2 Effect>
According to theTFT 300 according to this embodiment, the channel region 40a has a rectangular notch whose length in the channel direction is determined by the ends of the source electrode 60a and the drain electrode 60b not only at both ends but also in the center. A portion 42 is formed. Thereby, the TFT 300 has the same effect as that of the TFT 100. Specifically, by providing the notch portion 42, the area of the side surface of the semiconductor layer 40 is further increased. Therefore, oxygen from the outside and the silicon oxide film 32 are formed in the low resistance region 40b and the middle resistance region 40d. In addition, oxygen contained in the passivation film 90 is easily supplied. Thereby, in the TFT 300, compared with the TFT 100, the oxide semiconductor constituting the channel region 40a is further oxidized by taking in more oxygen, and the area of the low resistance region 40b is further narrowed. The middle resistance region 40d becomes a high resistance region 40c having a higher resistance value. Therefore, the off current (leakage current) of the TFT 300 is 1 × 10 −10 to 10 −11 A, and the TFT 300 functions sufficiently as a switching element of the liquid crystal display device.
本実施形態に係るＴＦＴ３００によれば、チャネル領域４０ａには、その両端部だけでなく、中央にも、チャネル方向の長さがソース電極６０ａとドレイン電極６０ｂの端部によって決まる矩形状の切り欠き部４２が形成されている。これにより、ＴＦＴ３００は、ＴＦＴ１００の場合と同様の効果を奏する。具体的には、切り欠き部４２を設けることによって、半導体層４０の側面の面積がより一層大きくなるので、低抵抗領域４０ｂ、および中抵抗領域４０ｄに、外部からの酸素と、酸化シリコン膜３２およびパッシベーション膜９０に含まれる酸素が供給されやすくなる。これにより、ＴＦＴ３００では、ＴＦＴ１００の場合と比較して、チャネル領域４０ａを構成する酸化物半導体は、酸素をより多く取り込むことによってより一層酸化され、低抵抗領域４０ｂの面積はより一層狭くなるとともに、中抵抗領域４０ｄはより一層抵抗値が高い高抵抗領域４０ｃになる。このため、ＴＦＴ３００のオフ電流（リーク電流）は１×１０-10～１０-11Ａになり、ＴＦＴ３００は液晶表示装置のスイッチング素子として十分に機能する。 <2.2 Effect>
According to the
また、ソース電極６０ａおよびドレイン電極６０ｂを形成する際に生じる異物によってソース電極６０ａとドレイン電極６０ｂが短絡したり、バックライト光がゲート電極２０の表面とドレイン電極６０ｂの表面との間で多重反射することによる電流が発生したりする可能性をより一層減らすことができる。さらに、ソース電極６０ａ側の低抵抗領域４０ｂとドレイン電極６０ｂ側の低抵抗領域４０ｂとが重なり合うことによって、ソース電極６０ａとドレイン電極６０ｂとが短絡する可能性をより一層減らすことができる。
In addition, the source electrode 60a and the drain electrode 60b are short-circuited by foreign matters generated when the source electrode 60a and the drain electrode 60b are formed, or the backlight is subjected to multiple reflection between the surface of the gate electrode 20 and the surface of the drain electrode 60b. It is possible to further reduce the possibility that a current is generated due to this. Furthermore, since the low resistance region 40b on the source electrode 60a side and the low resistance region 40b on the drain electrode 60b side overlap, the possibility that the source electrode 60a and the drain electrode 60b are short-circuited can be further reduced.
なお、本実施形態では、切り欠き部４２は、チャネル領域４０ａのチャネル幅方向の中央に形成されるとしたが、チャネル領域４０ａ内の任意の位置に、１個または複数個形成してもよい。また、チャネル領域４０ａの両端部または片側に切り欠き部４１が形成されていない場合でも、１個または複数個の切り欠き部４２を、チャネル領域４０ａの端部から内側に離れた位置に形成してもよい。
In the present embodiment, the cutout portion 42 is formed at the center of the channel region 40a in the channel width direction. However, one or a plurality of the cutout portions 42 may be formed at an arbitrary position in the channel region 40a. . Further, even when the notch portions 41 are not formed at both ends or one side of the channel region 40a, one or a plurality of the notch portions 42 are formed at positions away from the end portions of the channel region 40a. May be.
＜３．第３の実施形態＞
＜３．１ ＴＦＴの構成＞
図１０は、本発明の第３の実施形態に係るトップゲート型の薄膜トランジスタ４００の構成を示す図であり、より詳しくは、図１０（Ａ）は、本発明の第３の実施形態に係るトップゲート型の薄膜トランジスタ４００の構成を示す平面図であり、図１０（Ｂ）は、図１０（Ａ）に示す切断線Ｇ－Ｇに沿ったＴＦＴ４００の断面図であり、図１０（Ｃ）は、図１０（Ａ）に示す切断線Ｈ－Ｈに沿ったＴＦＴ４００の断面図である。ＴＦＴ４００の構成要素のうち、図１（Ａ）～図１（Ｃ）に示すＴＦＴ１００の構成要素と同一の構成要素については同じ参照符号を付し、異なる構成要素を中心に説明する。 <3. Third Embodiment>
<3.1 TFT configuration>
FIG. 10 is a diagram illustrating a configuration of a top-gatethin film transistor 400 according to the third embodiment of the present invention. More specifically, FIG. 10A illustrates a top according to the third embodiment of the present invention. FIG. 10B is a cross-sectional view of the TFT 400 taken along a cutting line GG shown in FIG. 10A, and FIG. 10C is a plan view showing the structure of the gate type thin film transistor 400. FIG. 11 is a cross-sectional view of the TFT 400 taken along a cutting line HH shown in FIG. Among the components of the TFT 400, the same components as those of the TFT 100 shown in FIGS. 1A to 1C are denoted by the same reference numerals, and different components will be mainly described.
＜３．１ ＴＦＴの構成＞
図１０は、本発明の第３の実施形態に係るトップゲート型の薄膜トランジスタ４００の構成を示す図であり、より詳しくは、図１０（Ａ）は、本発明の第３の実施形態に係るトップゲート型の薄膜トランジスタ４００の構成を示す平面図であり、図１０（Ｂ）は、図１０（Ａ）に示す切断線Ｇ－Ｇに沿ったＴＦＴ４００の断面図であり、図１０（Ｃ）は、図１０（Ａ）に示す切断線Ｈ－Ｈに沿ったＴＦＴ４００の断面図である。ＴＦＴ４００の構成要素のうち、図１（Ａ）～図１（Ｃ）に示すＴＦＴ１００の構成要素と同一の構成要素については同じ参照符号を付し、異なる構成要素を中心に説明する。 <3. Third Embodiment>
<3.1 TFT configuration>
FIG. 10 is a diagram illustrating a configuration of a top-gate
図１０（Ａ）～図１０（Ｃ）に示すように、ＴＦＴ４００では、ＴＦＴ１００と異なり、窒化シリコン膜３１と酸化シリコン膜３２とからなるゲート絶縁膜３０上に、ソース電極７０ａとドレイン電極７０ｂが形成されている。ソース電極７０ａおよびドレイン電極７０ｂの表面上に半導体層５０が形成されている。半導体層５０は、その裏面で、ソース電極７０ａおよびドレイン電極７０ｂと電気的に接続されている。半導体層５０のチャネル領域５０ａには、チャネル幅方向の両端部に切り欠き部５１（以下、「切り欠き部」または「第１の切り欠き部」ともいう）が形成されている。半導体層５０、ソース電極７０ａおよびドレイン電極７０ｂを含む絶縁基板１５の全体がパッシベーション膜９０で覆われている。
As shown in FIGS. 10A to 10C, in the TFT 400, unlike the TFT 100, the source electrode 70a and the drain electrode 70b are formed on the gate insulating film 30 including the silicon nitride film 31 and the silicon oxide film 32. Is formed. A semiconductor layer 50 is formed on the surfaces of the source electrode 70a and the drain electrode 70b. The semiconductor layer 50 is electrically connected to the source electrode 70a and the drain electrode 70b on the back surface thereof. In the channel region 50a of the semiconductor layer 50, notches 51 (hereinafter also referred to as “notches” or “first notches”) are formed at both ends in the channel width direction. The entire insulating substrate 15 including the semiconductor layer 50, the source electrode 70 a and the drain electrode 70 b is covered with a passivation film 90.
なお、本明細書では、２つの低抵抗領域５０ｂとそれらに挟まれた高抵抗領域５０ｃとを合わせた領域、すなわち、ソース電極６０ａとドレイン電極６０ｂとによって挟まれた領域をチャネル領域５０ａという。また、ＴＦＴ４００のように、ソース電極およびドレイン電極の表面と電気的接続された半導体層が形成されたＴＦＴを、ボトムコンタクト構造のＴＦＴということがある。
In the present specification, a region where two low resistance regions 50b and a high resistance region 50c sandwiched between them are combined, that is, a region sandwiched between the source electrode 60a and the drain electrode 60b is referred to as a channel region 50a. A TFT in which a semiconductor layer electrically connected to the surfaces of the source electrode and the drain electrode, such as the TFT 400, is sometimes referred to as a bottom contact TFT.
＜３．２ ＴＦＴの製造方法＞
図１１（Ａ）～図１１（Ｄ）および図１２（Ａ）～図１２（Ｃ）は、ＴＦＴ４００の各製造工程を示す工程断面図である。図１１（Ａ）～図１１（Ｄ）および図１２（Ａ）～図１１（Ｃ）に示す製造工程のうち、図２（Ａ）～図２（Ｄ）および図３（Ａ）～図３（Ｃ）に示す工程と同じ工程については簡単に説明し、異なる工程を中心に説明する。なお、各工程で成膜された各膜の膜厚、プロセス条件等は、第１の実施形態の場合と同じであるので、それらの説明を省略する。 <3.2 TFT manufacturing method>
FIG. 11A to FIG. 11D and FIG. 12A to FIG. 12C are process cross-sectional views showing each manufacturing process of theTFT 400. Of the manufacturing steps shown in FIGS. 11 (A) to 11 (D) and FIGS. 12 (A) to 11 (C), FIGS. 2 (A) to 2 (D) and FIGS. 3 (A) to 3 The same steps as those shown in (C) will be briefly described, and different steps will be mainly described. In addition, since the film thickness of each film | membrane formed at each process, process conditions, etc. are the same as the case of 1st Embodiment, those description is abbreviate | omitted.
図１１（Ａ）～図１１（Ｄ）および図１２（Ａ）～図１２（Ｃ）は、ＴＦＴ４００の各製造工程を示す工程断面図である。図１１（Ａ）～図１１（Ｄ）および図１２（Ａ）～図１１（Ｃ）に示す製造工程のうち、図２（Ａ）～図２（Ｄ）および図３（Ａ）～図３（Ｃ）に示す工程と同じ工程については簡単に説明し、異なる工程を中心に説明する。なお、各工程で成膜された各膜の膜厚、プロセス条件等は、第１の実施形態の場合と同じであるので、それらの説明を省略する。 <3.2 TFT manufacturing method>
FIG. 11A to FIG. 11D and FIG. 12A to FIG. 12C are process cross-sectional views showing each manufacturing process of the
図１１（Ａ）に示すように、絶縁基板１５上にゲート電極２０を形成する。次に、図１１（Ｂ）に示すように、ゲート電極２０を含む絶縁基板１５を覆うように、窒化シリコン膜３１および酸化シリコン膜３２からなるゲート絶縁膜３０を形成する。
As shown in FIG. 11A, the gate electrode 20 is formed on the insulating substrate 15. Next, as shown in FIG. 11B, a gate insulating film 30 including a silicon nitride film 31 and a silicon oxide film 32 is formed so as to cover the insulating substrate 15 including the gate electrode 20.
図１１（Ｃ）に示すように、ゲート絶縁膜３０上に、スパッタリング法によってソースメタル膜７５を成膜する。次に、図１１（Ｄ）に示すように、ゲート電極２０上に開口部を有するレジストパターン７８を形成し、レジストパターン７８をマスクとしてソースメタル膜７５をエッチングし、ソース電極７０ａとドレイン電極７０ｂを形成する。その後、レジストパターン７８を剥離する。
As shown in FIG. 11C, a source metal film 75 is formed on the gate insulating film 30 by a sputtering method. Next, as shown in FIG. 11D, a resist pattern 78 having an opening is formed over the gate electrode 20, the source metal film 75 is etched using the resist pattern 78 as a mask, and a source electrode 70a and a drain electrode 70b are formed. Form. Thereafter, the resist pattern 78 is peeled off.
図１２（Ａ）に示すように、ソース電極７０ａとドレイン電極７０ｂとによって挟まれたゲート絶縁膜３０、ソース電極７０ａおよびドレイン電極７０ｂを含む絶縁基板１５の全体を覆うように、スパッタリング法によって酸化物半導体膜５５を成膜する。ゲート電極２０の上方の酸化物半導体膜５５上に、チャネル領域５０ａを形成するためのパターンが形成されたマスクを使用してレジストパターン５８を形成する。成膜直後の酸化物半導体膜５５には酸素が多く含まれているので、酸化物半導体膜５５の全体が高抵抗領域になっている。
As shown in FIG. 12A, oxidation is performed by sputtering so as to cover the entire insulating substrate 15 including the gate insulating film 30, the source electrode 70a, and the drain electrode 70b sandwiched between the source electrode 70a and the drain electrode 70b. A physical semiconductor film 55 is formed. A resist pattern 58 is formed on the oxide semiconductor film 55 above the gate electrode 20 using a mask in which a pattern for forming the channel region 50a is formed. Since the oxide semiconductor film 55 immediately after film formation contains a large amount of oxygen, the entire oxide semiconductor film 55 is a high resistance region.
図１２（Ｂ）に示すように、レジストパターン５８をマスクとして酸化物半導体膜５５をエッチングし、半導体層５０を形成する。その後、レジストパターン５８を剥離し、半導体層５０、ソース電極７０ａおよびドレイン電極７０ｂを含む絶縁基板１５の全体を覆うように、パッシベーション膜９０を成膜する。パッシベーション膜９０の成膜時に絶縁基板１５が加熱される。このため、ソース電極７０ａおよびドレイン電極７０ｂは、半導体層５０から酸素を奪い取るとともに、半導体層５０に水素を供給することによって、半導体層５０を還元する。これにより、ソース電極７０ａおよびドレイン電極７０ｂに近い半導体層５０に低抵抗領域５０ｂ（「第１の領域」ともいう）が形成される。また、２つの低抵抗領域５０ｂに挟まれた高抵抗領域からも酸素が抜け、中抵抗領域５０ｄが形成される。
As shown in FIG. 12B, the oxide semiconductor film 55 is etched using the resist pattern 58 as a mask to form the semiconductor layer 50. Thereafter, the resist pattern 58 is removed, and a passivation film 90 is formed so as to cover the entire insulating substrate 15 including the semiconductor layer 50, the source electrode 70a, and the drain electrode 70b. The insulating substrate 15 is heated when the passivation film 90 is formed. For this reason, the source electrode 70 a and the drain electrode 70 b take oxygen from the semiconductor layer 50 and supply the hydrogen to the semiconductor layer 50, thereby reducing the semiconductor layer 50. Thus, a low resistance region 50b (also referred to as “first region”) is formed in the semiconductor layer 50 close to the source electrode 70a and the drain electrode 70b. Further, oxygen is also released from the high resistance region sandwiched between the two low resistance regions 50b, and the middle resistance region 50d is formed.
図１２（Ｃ）に示すように、ドライエア雰囲気中でアニールすることにより、外部からの酸素と、酸化シリコン膜３２とパッシベーション膜９０に含まれる酸素が、半導体層５０のチャネル領域５０ａに供給される。これにより、低抵抗領域５０ｂの面積が狭くなるとともに、中抵抗領域５０ｄの抵抗値が高くなって高抵抗領域５０ｃ（「第２の領域」ともいう）になる。
As shown in FIG. 12C, oxygen from the outside and oxygen contained in the silicon oxide film 32 and the passivation film 90 are supplied to the channel region 50a of the semiconductor layer 50 by annealing in a dry air atmosphere. . As a result, the area of the low resistance region 50b is reduced, and the resistance value of the middle resistance region 50d is increased to become the high resistance region 50c (also referred to as “second region”).
＜３．３ 効果＞
本実施形態に係るＴＦＴ４００によれば、第１の実施形態に係るＴＦＴ１００が奏する効果と同様に、チャネル領域５０ａの低抵抗領域５０ｂの面積が狭くなるとともに、低抵抗領域５０ｂに挟まれたチャネル領域５０ａに高抵抗領域５０ｃが形成される。また、異物によりソース電極７０ａとドレイン電極７０ｂが短絡したり、バックライト光の多重反射により電流が発生したりする可能性を減らすことができる。さらに、ソース電極７０ａ側の低抵抗領域５０ｂとドレイン電極７０ｂ側の低抵抗領域５０ｂとが重なり合うことによってソース電極７０ａとドレイン電極７０ｂとが短絡する可能性を減らすことができる。 <3.3 Effects>
According to theTFT 400 according to the present embodiment, the area of the low-resistance region 50b of the channel region 50a is narrowed and the channel region sandwiched between the low-resistance regions 50b is the same as the effect exhibited by the TFT 100 according to the first embodiment. A high resistance region 50c is formed in 50a. Further, it is possible to reduce the possibility that the source electrode 70a and the drain electrode 70b are short-circuited by a foreign substance, or that current is generated due to multiple reflection of backlight light. Furthermore, the possibility that the source electrode 70a and the drain electrode 70b are short-circuited by the overlap of the low resistance region 50b on the source electrode 70a side and the low resistance region 50b on the drain electrode 70b side can be reduced.
本実施形態に係るＴＦＴ４００によれば、第１の実施形態に係るＴＦＴ１００が奏する効果と同様に、チャネル領域５０ａの低抵抗領域５０ｂの面積が狭くなるとともに、低抵抗領域５０ｂに挟まれたチャネル領域５０ａに高抵抗領域５０ｃが形成される。また、異物によりソース電極７０ａとドレイン電極７０ｂが短絡したり、バックライト光の多重反射により電流が発生したりする可能性を減らすことができる。さらに、ソース電極７０ａ側の低抵抗領域５０ｂとドレイン電極７０ｂ側の低抵抗領域５０ｂとが重なり合うことによってソース電極７０ａとドレイン電極７０ｂとが短絡する可能性を減らすことができる。 <3.3 Effects>
According to the
＜４．第４の実施形態＞
＜４．１ ＴＦＴの構成＞
図１３は、本発明の第４の実施形態に係るボトムゲート型ＴＦＴ５００の構成を示す図であり、より詳しくは、図１３（Ａ）は、本発明の第４の実施形態に係るボトムゲート型ＴＦＴ５００の構成を示す平面図であり、図１３（Ｂ）は、図１３（Ａ）に示す切断線Ｊ－Ｊに沿ったＴＦＴ５００の断面図であり、図１３（Ｃ）は、図１３（Ａ）に示す切断線Ｋ－Ｋに沿ったＴＦＴ５００の断面図である。ＴＦＴ５００の構成要素のうち、図１（Ａ）～図１（Ｃ）に示すＴＦＴ１００の構成要素と同一の構成要素については同じ参照符号を付し、異なる構成要素を中心に説明する。 <4. Fourth Embodiment>
<4.1 TFT configuration>
FIG. 13 is a diagram showing a configuration of a bottomgate type TFT 500 according to the fourth embodiment of the present invention. More specifically, FIG. 13A shows a bottom gate type TFT according to the fourth embodiment of the present invention. FIG. 13B is a cross-sectional view of the TFT 500 taken along a cutting line JJ shown in FIG. 13A, and FIG. 13C is a plan view showing the structure of the TFT 500. FIG. 2 is a cross-sectional view of the TFT 500 along the cutting line KK shown in FIG. Among the constituent elements of the TFT 500, the same constituent elements as those of the TFT 100 shown in FIGS. 1A to 1C are denoted by the same reference numerals, and different constituent elements will be mainly described.
＜４．１ ＴＦＴの構成＞
図１３は、本発明の第４の実施形態に係るボトムゲート型ＴＦＴ５００の構成を示す図であり、より詳しくは、図１３（Ａ）は、本発明の第４の実施形態に係るボトムゲート型ＴＦＴ５００の構成を示す平面図であり、図１３（Ｂ）は、図１３（Ａ）に示す切断線Ｊ－Ｊに沿ったＴＦＴ５００の断面図であり、図１３（Ｃ）は、図１３（Ａ）に示す切断線Ｋ－Ｋに沿ったＴＦＴ５００の断面図である。ＴＦＴ５００の構成要素のうち、図１（Ａ）～図１（Ｃ）に示すＴＦＴ１００の構成要素と同一の構成要素については同じ参照符号を付し、異なる構成要素を中心に説明する。 <4. Fourth Embodiment>
<4.1 TFT configuration>
FIG. 13 is a diagram showing a configuration of a bottom
図１３（Ａ）～図１３（Ｃ）に示すように、ＴＦＴ５００でも、ＴＦＴ１００と同様に、半導体層４０のチャネル領域４０ａの両端部がエッチングによって除去され、切り欠き部４１が形成されている。しかし、ＴＦＴ５００では、ＴＦＴ１００と異なり、半導体層４０のチャネル領域４０ａ上に、エッチングストッパ層８０が形成されている。エッチングストッパ層８０は、ソースメタル膜をエッチングしてソース電極６０ａとドレイン電極６０ｂとを形成する際に、半導体層４０の表面がエッチングされないように保護している。
As shown in FIGS. 13A to 13C, in the TFT 500 as well as the TFT 100, both end portions of the channel region 40a of the semiconductor layer 40 are removed by etching to form a notch 41. However, in the TFT 500, unlike the TFT 100, the etching stopper layer 80 is formed on the channel region 40 a of the semiconductor layer 40. The etching stopper layer 80 protects the surface of the semiconductor layer 40 from being etched when the source metal film is etched to form the source electrode 60a and the drain electrode 60b.
また、エッチングストッパ層８０は酸化シリコンからなる。このため、後述するように、エッチングストッパ層８０は、パッシベーション膜９０とともに、半導体層４０のチャネル領域４０ａに酸素を供給することができる。なお、ＴＦＴ５００のように、半導体層の表面にエッチングストッパ層が形成されたＴＦＴを、エッチストップ構造のＴＦＴということがある。
The etching stopper layer 80 is made of silicon oxide. For this reason, as will be described later, the etching stopper layer 80 can supply oxygen to the channel region 40 a of the semiconductor layer 40 together with the passivation film 90. Note that a TFT in which an etching stopper layer is formed on the surface of a semiconductor layer like the TFT 500 may be referred to as an etch stop TFT.
＜４．２ ＴＦＴの製造方法＞
図１４（Ａ）～図１４（Ｄ）および図１５（Ａ）～図１５（Ｃ）は、ＴＦＴ５００の各製造工程を示す工程断面図である。図１４（Ａ）～図１４（Ｄ）および図１５（Ａ）～図１５（Ｃ）に示す製造工程のうち、図２（Ａ）～図２（Ｄ）および図３（Ａ）～図３（Ｃ）に示す工程と同じ工程について簡単に説明し、異なる工程を中心に説明する。なお、各工程で成膜された各膜の膜厚、プロセス条件等は、第１の実施形態の場合と同じであるため、それらの説明を省略する。 <4.2 TFT manufacturing method>
FIGS. 14A to 14D and FIGS. 15A to 15C are process cross-sectional views illustrating each manufacturing process of theTFT 500. FIG. Of the manufacturing steps shown in FIGS. 14 (A) to 14 (D) and FIGS. 15 (A) to 15 (C), FIGS. 2 (A) to 2 (D) and FIGS. 3 (A) to 3 (C). The same steps as those shown in (C) will be briefly described, and different steps will be mainly described. In addition, since the film thickness of each film | membrane formed in each process, process conditions, etc. are the same as the case of 1st Embodiment, those description is abbreviate | omitted.
図１４（Ａ）～図１４（Ｄ）および図１５（Ａ）～図１５（Ｃ）は、ＴＦＴ５００の各製造工程を示す工程断面図である。図１４（Ａ）～図１４（Ｄ）および図１５（Ａ）～図１５（Ｃ）に示す製造工程のうち、図２（Ａ）～図２（Ｄ）および図３（Ａ）～図３（Ｃ）に示す工程と同じ工程について簡単に説明し、異なる工程を中心に説明する。なお、各工程で成膜された各膜の膜厚、プロセス条件等は、第１の実施形態の場合と同じであるため、それらの説明を省略する。 <4.2 TFT manufacturing method>
FIGS. 14A to 14D and FIGS. 15A to 15C are process cross-sectional views illustrating each manufacturing process of the
図１４（Ａ）に示すように、絶縁基板１５上にゲート電極２０を形成する。次に、図１４（Ｂ）に示すように、ゲート電極２０を含む絶縁基板１５の全体を覆うように、窒化シリコン膜３１および酸化シリコン膜３２からなるゲート絶縁膜３０を形成する。
As shown in FIG. 14A, the gate electrode 20 is formed on the insulating substrate 15. Next, as shown in FIG. 14B, a gate insulating film 30 composed of a silicon nitride film 31 and a silicon oxide film 32 is formed so as to cover the entire insulating substrate 15 including the gate electrode 20.
ゲート絶縁膜３０上に、スパッタリング法によって酸化物半導体膜（図示しない）を成膜する。成膜直後の酸化物半導体膜には酸素が多く含まれているので、酸化物半導体膜の全体が高抵抗領域になっている。図１４（Ｃ）に示すように、ゲート電極２０の上方の酸化物半導体膜上にレジストパターン４８を形成する。レジストパターン４８をマスクとして酸化物半導体膜をエッチングし、半導体層４０を形成する。その後、レジストパターン４８を剥離する。
An oxide semiconductor film (not shown) is formed on the gate insulating film 30 by a sputtering method. Since the oxide semiconductor film immediately after deposition contains a large amount of oxygen, the entire oxide semiconductor film is a high-resistance region. As shown in FIG. 14C, a resist pattern 48 is formed over the oxide semiconductor film above the gate electrode 20. The oxide semiconductor film is etched using the resist pattern 48 as a mask to form the semiconductor layer 40. Thereafter, the resist pattern 48 is peeled off.
図１４（Ｄ）に示すように、プラズマＣＶＤ法を用いて、半導体層４０を含む絶縁基板１５の全体を覆うように酸化シリコン膜８５を形成する。酸化シリコン膜８５の膜厚は５０～２００ｎｍとする。次に、酸化シリコン膜８５上にレジストパターン８８を形成する。
As shown in FIG. 14D, a silicon oxide film 85 is formed by plasma CVD so as to cover the entire insulating substrate 15 including the semiconductor layer 40. The thickness of the silicon oxide film 85 is 50 to 200 nm. Next, a resist pattern 88 is formed on the silicon oxide film 85.
図１５（Ａ）に示すように、レジストパターン８８をマスクとして酸化シリコン膜８５をエッチングし、エッチングストッパ層８０を形成する。次に、レジストパターン８８を剥離し、スパッタリング法を用いて、エッチングストッパ層８０を含む絶縁基板１５の全体を覆うようにソースメタル膜６５を成膜する。
As shown in FIG. 15A, the silicon oxide film 85 is etched using the resist pattern 88 as a mask to form an etching stopper layer 80. Next, the resist pattern 88 is peeled off, and a source metal film 65 is formed using a sputtering method so as to cover the entire insulating substrate 15 including the etching stopper layer 80.
図１５（Ｂ）に示すように、ソースメタル膜６５上に、エッチングストッパ層上で左右に分離されたレジストパターン６８を形成する。レジストパターン６８をマスクとしてソースメタル膜６５をエッチングし、エッチングストッパ層８０上で左右に分離されたソース電極６０ａとドレイン電極６０ｂとを形成する。その後、レジストパターン６８を剥離する。
As shown in FIG. 15B, a resist pattern 68 separated on the left and right on the etching stopper layer is formed on the source metal film 65. The source metal film 65 is etched using the resist pattern 68 as a mask to form a source electrode 60a and a drain electrode 60b separated on the left and right on the etching stopper layer 80. Thereafter, the resist pattern 68 is peeled off.
図１５（Ｃ）に示すように、エッチングストッパ層８０、ソース電極６０ａおよびドレイン電極６０ｂを含む絶縁基板１５の全体をパッシベーション膜９０で覆う。パッシベーション膜９０の成膜時に絶縁基板１５が加熱される。このため、ソース電極６０ａおよびドレイン電極６０ｂは、半導体層４０から酸素を奪い取るとともに、半導体層４０に水素を供給することによって、半導体層４０を還元する。これにより、ソース電極６０ａおよびドレイン電極６０ｂの端部の近傍の半導体層４０に低抵抗領域４０ｂが形成される。なお、２つの低抵抗領域４０ｂに挟まれた高抵抗領域上にエッチングストッパ層が形成されているので、高抵抗領域から酸素が抜けにくく、そのまま高抵抗領域４０ｃとして残る。
As shown in FIG. 15C, the entire insulating substrate 15 including the etching stopper layer 80, the source electrode 60a, and the drain electrode 60b is covered with a passivation film 90. The insulating substrate 15 is heated when the passivation film 90 is formed. Therefore, the source electrode 60 a and the drain electrode 60 b take oxygen from the semiconductor layer 40 and reduce the semiconductor layer 40 by supplying hydrogen to the semiconductor layer 40. As a result, the low resistance region 40b is formed in the semiconductor layer 40 in the vicinity of the ends of the source electrode 60a and the drain electrode 60b. Since the etching stopper layer is formed on the high resistance region sandwiched between the two low resistance regions 40b, oxygen is not easily released from the high resistance region and remains as the high resistance region 40c.
さらに、ドライエア雰囲気中でアニールを行うことにより、酸素が、エッチングストッパ層８０を構成する酸化シリコンからチャネル領域４０ａを構成するＩＧＺＯに供給される。これにより、低抵抗領域４０ｂは酸素を取込み、その面積が狭くなる。
Furthermore, by performing annealing in a dry air atmosphere, oxygen is supplied from the silicon oxide constituting the etching stopper layer 80 to the IGZO constituting the channel region 40a. As a result, the low resistance region 40b takes in oxygen and its area becomes narrow.
＜４．３ 効果＞
本実施形態に係るＴＦＴ５００によれば、第１の実施形態に係るＴＦＴ１００が奏する効果と同様に、チャネル領域４０ａの低抵抗領域４０ｂの面積が狭くなるとともに、低抵抗領域４０ｂに挟まれたチャネル領域４０ａに高抵抗領域４０ｃが形成される。また、異物によるソース電極６０ａとドレイン電極６０ｂが短絡したり、バックライト光の多重反射による電流が発生したりする可能性を減らすことができる。さらに、ソース電極６０ａ側の低抵抗領域４０ｂとドレイン電極６０ｂ側の低抵抗領域４０ｂとが重なり合うことによってソース電極６０ａとドレイン電極６０ｂとが短絡する可能性を減らすことができる。 <4.3 Effects>
According to theTFT 500 according to the present embodiment, the area of the low-resistance region 40b of the channel region 40a is narrowed and the channel region sandwiched between the low-resistance regions 40b is the same as the effect exhibited by the TFT 100 according to the first embodiment. A high resistance region 40c is formed in 40a. In addition, it is possible to reduce the possibility that the source electrode 60a and the drain electrode 60b are short-circuited due to foreign matter, or a current is generated due to multiple reflection of backlight light. Furthermore, the possibility that the source electrode 60a and the drain electrode 60b are short-circuited by the overlap of the low resistance region 40b on the source electrode 60a side and the low resistance region 40b on the drain electrode 60b side can be reduced.
本実施形態に係るＴＦＴ５００によれば、第１の実施形態に係るＴＦＴ１００が奏する効果と同様に、チャネル領域４０ａの低抵抗領域４０ｂの面積が狭くなるとともに、低抵抗領域４０ｂに挟まれたチャネル領域４０ａに高抵抗領域４０ｃが形成される。また、異物によるソース電極６０ａとドレイン電極６０ｂが短絡したり、バックライト光の多重反射による電流が発生したりする可能性を減らすことができる。さらに、ソース電極６０ａ側の低抵抗領域４０ｂとドレイン電極６０ｂ側の低抵抗領域４０ｂとが重なり合うことによってソース電極６０ａとドレイン電極６０ｂとが短絡する可能性を減らすことができる。 <4.3 Effects>
According to the
＜５．ＴＦＴの変形例＞
上記第１～第４の実施形態では、本発明を適用可能なＴＦＴのうち、典型的なＴＦＴ１００～５００について説明した。しかし、これらのＴＦＴ１００～５００を適宜組み合わせて得られる他のＴＦＴについても同様の効果を奏する。例えば、ＴＦＴ４００にＴＦＴ３００を組み合わせることにより、ボトムコンタクト構造のＴＦＴにおいて、半導体層５０の切り欠き部５１をチャネル領域５０ａの幅方向の両端部だけでなく、さらにそれらの間に１個または複数個設けてもよい。また、ＴＦＴ５００にＴＦＴ３００を組み合わせることにより、チャネルストップ構造のＴＦＴにおいて、半導体層４０の切り欠き部４１をチャネル領域４０ａの幅方向の両端部だけでなく、さらにそれらの間に１個または複数個設けてもよい。また、ＴＦＴ４００にＴＦＴ２００とＴＦＴ３００を組み合わせることにより、ボトムコンタクト構造のＴＦＴに、半導体層５０の切り欠き部５１をチャネル領域５０ａの幅方向の片側と、チャネル領域５０ａの長さ方向に沿ってその内側の位置に１個または複数個設けてもよい。 <5. Modification Examples of TFT>
In the first to fourth embodiments,typical TFTs 100 to 500 are described among TFTs to which the present invention can be applied. However, other TFTs obtained by appropriately combining these TFTs 100 to 500 have the same effect. For example, by combining the TFT 400 with the TFT 400, in the TFT having the bottom contact structure, the notch 51 of the semiconductor layer 50 is provided not only at both ends in the width direction of the channel region 50a, but also by providing one or more between them. May be. Further, by combining the TFT 500 with the TFT 500, in the channel stop structure TFT, one or a plurality of notches 41 of the semiconductor layer 40 are provided not only at both ends in the width direction of the channel region 40a but also between them. May be. In addition, by combining the TFT 200 and the TFT 300 with the TFT 400, the notch 51 of the semiconductor layer 50 is formed on one side in the width direction of the channel region 50a and on the inner side along the length direction of the channel region 50a. One or more may be provided at the position.
上記第１～第４の実施形態では、本発明を適用可能なＴＦＴのうち、典型的なＴＦＴ１００～５００について説明した。しかし、これらのＴＦＴ１００～５００を適宜組み合わせて得られる他のＴＦＴについても同様の効果を奏する。例えば、ＴＦＴ４００にＴＦＴ３００を組み合わせることにより、ボトムコンタクト構造のＴＦＴにおいて、半導体層５０の切り欠き部５１をチャネル領域５０ａの幅方向の両端部だけでなく、さらにそれらの間に１個または複数個設けてもよい。また、ＴＦＴ５００にＴＦＴ３００を組み合わせることにより、チャネルストップ構造のＴＦＴにおいて、半導体層４０の切り欠き部４１をチャネル領域４０ａの幅方向の両端部だけでなく、さらにそれらの間に１個または複数個設けてもよい。また、ＴＦＴ４００にＴＦＴ２００とＴＦＴ３００を組み合わせることにより、ボトムコンタクト構造のＴＦＴに、半導体層５０の切り欠き部５１をチャネル領域５０ａの幅方向の片側と、チャネル領域５０ａの長さ方向に沿ってその内側の位置に１個または複数個設けてもよい。 <5. Modification Examples of TFT>
In the first to fourth embodiments,
＜６．第５の実施形態＞
図１６は、第１の実施形態に係るＴＦＴ１００を含む液晶表示装置１０の構成を示すブロック図である。図１６に示す液晶表示装置１０は、液晶パネル２（「表示部」ともいう）と、表示制御回路３と、ゲートドライバ４と、ソースドライバ５とを含む。液晶パネル２には、水平方向に延びるｎ本（ｎは１以上の整数）のゲート配線Ｇ１～Ｇｎと、ゲート配線Ｇ１～Ｇｎと交差する方向に延びるｍ本（ｍは１以上の整数）のソース配線Ｓ１～Ｓｍが形成されている。ｉ番目のゲート配線Ｇｉ（ｉは１以上ｎ以下の整数）とｊ番目のソース配線Ｓｊ（ｊは１以上ｍ以下の整数）との交点近傍には、それぞれ画素形成部Ｐｉｊが配置されている。 <6. Fifth Embodiment>
FIG. 16 is a block diagram showing a configuration of the liquidcrystal display device 10 including the TFT 100 according to the first embodiment. A liquid crystal display device 10 illustrated in FIG. 16 includes a liquid crystal panel 2 (also referred to as a “display unit”), a display control circuit 3, a gate driver 4, and a source driver 5. The liquid crystal panel 2 includes n (n is an integer of 1 or more) gate wirings G1 to Gn extending in the horizontal direction and m (m is an integer of 1 or more) extending in a direction intersecting the gate wirings G1 to Gn. Source wirings S1 to Sm are formed. Pixel forming portions Pij are arranged near intersections of the i-th gate line Gi (i is an integer of 1 to n) and the j-th source line Sj (j is an integer of 1 to m). .
図１６は、第１の実施形態に係るＴＦＴ１００を含む液晶表示装置１０の構成を示すブロック図である。図１６に示す液晶表示装置１０は、液晶パネル２（「表示部」ともいう）と、表示制御回路３と、ゲートドライバ４と、ソースドライバ５とを含む。液晶パネル２には、水平方向に延びるｎ本（ｎは１以上の整数）のゲート配線Ｇ１～Ｇｎと、ゲート配線Ｇ１～Ｇｎと交差する方向に延びるｍ本（ｍは１以上の整数）のソース配線Ｓ１～Ｓｍが形成されている。ｉ番目のゲート配線Ｇｉ（ｉは１以上ｎ以下の整数）とｊ番目のソース配線Ｓｊ（ｊは１以上ｍ以下の整数）との交点近傍には、それぞれ画素形成部Ｐｉｊが配置されている。 <6. Fifth Embodiment>
FIG. 16 is a block diagram showing a configuration of the liquid
表示制御回路３には、液晶表示装置１０の外部から水平同期信号や垂直同期信号等の制御信号ＳＣと画像信号ＤＴが供給される。表示制御回路３は、これらの信号に基づき、ゲートドライバ４に対して制御信号ＳＣ１を出力し、ソースドライバ５に対して制御信号ＳＣ２と画像信号ＤＴを出力する。
The display control circuit 3 is supplied with a control signal SC such as a horizontal synchronizing signal and a vertical synchronizing signal and an image signal DT from the outside of the liquid crystal display device 10. Based on these signals, the display control circuit 3 outputs a control signal SC1 to the gate driver 4, and outputs a control signal SC2 and an image signal DT to the source driver 5.
ゲートドライバ４はゲート配線Ｇ１～Ｇｎに接続され、ソースドライバ５はソース配線Ｓ１～Ｓｍに接続されている。ゲートドライバ４は、選択状態を示すハイレベルの信号をゲート配線Ｇ１～Ｇｎに順に与える。これにより、ゲート配線Ｇ１～Ｇｎが１本ずつ順に選択される。例えば、ｉ番目のゲート配線Ｇｉが選択されたとき、１行分の画素形成部Ｐｉ１～Ｐｉｍが一括して選択される。ソースドライバ５は、各ソース配線Ｓ１～Ｓｍに対して画像信号ＤＴに応じた信号電圧を与える。これにより、選択された１行分の画素形成部Ｐｉ１～Ｐｉｍに画像信号ＤＴに応じた信号電圧が書き込まれる。このようにして、液晶表示装置１０は液晶パネル２に画像を表示する。
The gate driver 4 is connected to the gate lines G1 to Gn, and the source driver 5 is connected to the source lines S1 to Sm. The gate driver 4 sequentially applies a high level signal indicating the selected state to the gate lines G1 to Gn. As a result, the gate wirings G1 to Gn are sequentially selected one by one. For example, when the i-th gate line Gi is selected, the pixel formation portions Pi1 to Pim for one row are selected at once. The source driver 5 applies a signal voltage corresponding to the image signal DT to each of the source lines S1 to Sm. As a result, the signal voltage corresponding to the image signal DT is written into the pixel formation portions Pi1 to Pim for one selected row. In this way, the liquid crystal display device 10 displays an image on the liquid crystal panel 2.
図１７は、液晶パネル２に設けられた画素形成部Ｐｉｊ内のパターン配置を示す平面図である。図１７に示すように、液晶パネル２は、水平方向に延びるｉ番目のゲート配線Ｇｉと、ゲート配線Ｇｉと交差する方向に延びるｊ番目のソース配線Ｓｊと、ゲート配線Ｇｉとソース配線Ｓｊに囲まれた領域に配置された画素形成部Ｐｉｊとを含む。画素形成部Ｐｉｊは、スイッチング素子として機能するＴＦＴとして、図１（Ａ）～図１（Ｃ）に示すＴＦＴ１００を含む。ＴＦＴ１００のゲート電極２０はゲート配線Ｇｉと電気的に接続されている。ゲート電極２０の上方には、島状の半導体層４０が形成されている。半導体層４０の一端は、ソース配線Ｓｊに接続されたソース電極６０ａと電気的に接続され、半導体層４０の他端は、ドレイン電極６０ｂと電気的に接続されている。さらに、ドレイン電極６０ｂは、コンタクトホール６を介して画素電極７と電気的に接続されている。画素電極７は、対向電極（図示しない）と共に、画像信号ＤＴに応じた信号電圧を所定時間保持する画素容量を構成する。
FIG. 17 is a plan view showing a pattern arrangement in the pixel formation portion Pij provided in the liquid crystal panel 2. As shown in FIG. 17, the liquid crystal panel 2 is surrounded by an i-th gate line Gi extending in the horizontal direction, a j-th source line Sj extending in a direction intersecting the gate line Gi, the gate line Gi, and the source line Sj. And a pixel forming portion Pij disposed in the region. The pixel formation portion Pij includes a TFT 100 shown in FIGS. 1A to 1C as a TFT functioning as a switching element. The gate electrode 20 of the TFT 100 is electrically connected to the gate wiring Gi. An island-shaped semiconductor layer 40 is formed above the gate electrode 20. One end of the semiconductor layer 40 is electrically connected to the source electrode 60a connected to the source wiring Sj, and the other end of the semiconductor layer 40 is electrically connected to the drain electrode 60b. Further, the drain electrode 60 b is electrically connected to the pixel electrode 7 through the contact hole 6. The pixel electrode 7 and a counter electrode (not shown) constitute a pixel capacitor that holds a signal voltage corresponding to the image signal DT for a predetermined time.
液晶パネル２に設けられた各画素形成部Ｐｉｊのスイッチング素子として、オン・オフ比が大きなＴＦＴ１００を用いることにより、液晶表示装置１０の表示品位を向上させることができる。ここで、オン・オフ比を大きくすれば、液晶表示装置１０の表示品位が向上する理由を説明する。オン・オフ比を大きくするためには、オン電流を大きくするとともに、オフ電流を小さくすればよい。オン電流を大きくすることによって、ソース配線Ｓｊから与えられる画像信号ＤＴの信号電圧を、短時間で画素容量（補助容量も形成されている場合には画素容量と補助容量）に充電できるので、画素形成部Ｐｉｊの数を増やすことができる。また、オフ電流を小さくすることによって、画素容量に書き込まれた信号電圧を長時間保持することができるからである。
The display quality of the liquid crystal display device 10 can be improved by using the TFT 100 having a large on / off ratio as a switching element of each pixel formation portion Pij provided in the liquid crystal panel 2. Here, the reason why the display quality of the liquid crystal display device 10 is improved by increasing the on / off ratio will be described. In order to increase the on / off ratio, the on-current may be increased and the off-current may be decreased. By increasing the on-current, the signal voltage of the image signal DT supplied from the source wiring Sj can be charged to the pixel capacitor (the pixel capacitor and the auxiliary capacitor when the auxiliary capacitor is also formed) in a short time. The number of formation parts Pij can be increased. In addition, the signal voltage written in the pixel capacitor can be held for a long time by reducing the off-state current.
なお、図１６および図１７では、ＴＦＴ１００を用いた場合について説明したが、ＴＦＴ１００の代わりに、ＴＦＴ２００～５００のいずれかを用いてもよい。
16 and 17, the case where the TFT 100 is used has been described, but any one of the TFTs 200 to 500 may be used instead of the TFT 100.
また、上述の説明では、ＴＦＴ１００を液晶表示装置１０に適用する場合について説明したが、有機ＥＬ（Electro Luminescence）表示装置に適用することもできる。
In the above description, the case where the TFT 100 is applied to the liquid crystal display device 10 has been described. However, the present invention can also be applied to an organic EL (Electro Luminescence) display device.
本発明は、アクティブマトリクス型液晶表示装置等のような表示装置に用いられる薄膜トランジスタに適しており、特に、その画素形成部に形成されるスイッチング素子として用いられる薄膜トランジスタに適している。
The present invention is suitable for a thin film transistor used in a display device such as an active matrix liquid crystal display device, and is particularly suitable for a thin film transistor used as a switching element formed in the pixel formation portion.
１０…液晶表示装置
１５…絶縁基板
２０…ゲート電極
３０…ゲート絶縁膜
３１…窒化シリコン膜
３２…酸化シリコン膜
４０、５０…半導体層
４０ａ、５０ａ…チャネル領域
４０ｂ、５０ｂ…低抵抗領域
４０ｃ、５０ｃ…高抵抗領域
４１、５１…切り欠き部
４２…切り欠き部
６０ａ、７０ａ…ソース電極
６０ｂ、７０ｂ…ドレイン電極
８０…エッチングストッパ層
９０…パッシベーション膜
１００～５００…ＴＦＴ（薄膜トランジスタ） DESCRIPTION OFSYMBOLS 10 ... Liquid crystal display device 15 ... Insulating substrate 20 ... Gate electrode 30 ... Gate insulating film 31 ... Silicon nitride film 32 ... Silicon oxide film 40, 50 ... Semiconductor layer 40a, 50a ... Channel region 40b, 50b ... Low resistance region 40c, 50c ... high resistance regions 41, 51 ... notches 42 ... notches 60a, 70a ... source electrodes 60b, 70b ... drain electrodes 80 ... etching stopper layer 90 ... passivation film 100-500 ... TFT (thin film transistor)
１５…絶縁基板
２０…ゲート電極
３０…ゲート絶縁膜
３１…窒化シリコン膜
３２…酸化シリコン膜
４０、５０…半導体層
４０ａ、５０ａ…チャネル領域
４０ｂ、５０ｂ…低抵抗領域
４０ｃ、５０ｃ…高抵抗領域
４１、５１…切り欠き部
４２…切り欠き部
６０ａ、７０ａ…ソース電極
６０ｂ、７０ｂ…ドレイン電極
８０…エッチングストッパ層
９０…パッシベーション膜
１００～５００…ＴＦＴ（薄膜トランジスタ） DESCRIPTION OF
Claims (12)
- 絶縁基板上に形成され、酸化物半導体からなる半導体層を有する薄膜トランジスタであって、
前記絶縁基板上に形成されたゲート電極と、
前記ゲート電極を覆うように形成され、少なくとも第１の酸化シリコン膜を含むゲート絶縁膜と、
前記ゲート電極を挟むように、所定の距離を隔てて前記ゲート絶縁膜上に形成されたソース電極およびドレイン電極と、
前記ソース電極および前記ドレイン電極によって挟まれた前記ゲート絶縁膜上に形成され、一端および他端が前記ソース電極および前記ドレイン電極の裏面または表面のいずれかとそれぞれ電気的に接続された前記半導体層と、
前記ソース電極、前記ドレイン電極、および前記半導体層を覆い、少なくとも第２の酸化シリコン膜を含むパッシベーション膜とを備え、
前記半導体層は、前記ソース電極および前記ドレイン電極の裏面または表面と接する領域における幅よりも、前記ソース電極と前記ドレイン電極とによって挟まれたチャネル領域における幅が狭く、
前記チャネル領域は、前記第１の酸化シリコン膜と前記第２の酸化シリコン膜とによって挟まれていることを特徴とする、薄膜トランジスタ。 A thin film transistor formed on an insulating substrate and having a semiconductor layer made of an oxide semiconductor,
A gate electrode formed on the insulating substrate;
A gate insulating film formed to cover the gate electrode and including at least a first silicon oxide film;
A source electrode and a drain electrode formed on the gate insulating film at a predetermined distance so as to sandwich the gate electrode;
The semiconductor layer formed on the gate insulating film sandwiched between the source electrode and the drain electrode, and having one end and the other end electrically connected to either the back surface or the surface of the source electrode and the drain electrode, respectively ,
A passivation film that covers the source electrode, the drain electrode, and the semiconductor layer and includes at least a second silicon oxide film;
The semiconductor layer has a narrower width in a channel region sandwiched between the source electrode and the drain electrode than a width in a region in contact with the back surface or the front surface of the source electrode and the drain electrode,
The thin film transistor according to claim 1, wherein the channel region is sandwiched between the first silicon oxide film and the second silicon oxide film. - 前記チャネル領域は、少なくとも幅方向のいずれか一方の端部に第１の切り欠き部を有することを特徴とする、請求項１に記載の薄膜トランジスタ。 2. The thin film transistor according to claim 1, wherein the channel region has a first cutout at least at one end in the width direction.
- 前記チャネル領域は、幅方向の両端部に前記第１の切り欠き部を有することを特徴とする、請求項２に記載の薄膜トランジスタ。 3. The thin film transistor according to claim 2, wherein the channel region has the first notch at both ends in the width direction.
- 前記チャネル領域は、幅方向の端部から内側に離れた位置に、前記チャネル領域の長さ方向に沿って少なくとも１つの第２の切り欠き部を有することを特徴とする、請求項１から３のいずれかに記載の薄膜トランジスタ。 The channel region has at least one second cutout portion along a length direction of the channel region at a position spaced inward from an end portion in the width direction. The thin film transistor according to any one of the above.
- 前記ゲート絶縁膜は、前記第１の酸化シリコン膜の下面に形成された第１の窒化シリコン膜をさらに含み、
前記パッシベーション膜は、第２の酸化シリコン膜の表面に形成された第２の窒化シリコン膜をさらに含むことを特徴とする、請求項１に記載の薄膜トランジスタ。 The gate insulating film further includes a first silicon nitride film formed on a lower surface of the first silicon oxide film,
The thin film transistor according to claim 1, wherein the passivation film further includes a second silicon nitride film formed on a surface of the second silicon oxide film. - 前記ソース電極と前記ドレイン電極とは、前記半導体層上に、所定の距離を隔てて対向するように形成され、
前記半導体層は、前記一端が前記ソース電極の裏面と電気的に接続され、前記他端が前記ドレイン電極の裏面と電気的に接続されるように形成されていることを特徴とする、請求項１に記載の薄膜トランジスタ。 The source electrode and the drain electrode are formed on the semiconductor layer so as to face each other with a predetermined distance therebetween,
The semiconductor layer is formed so that the one end is electrically connected to the back surface of the source electrode and the other end is electrically connected to the back surface of the drain electrode. 2. The thin film transistor according to 1. - 前記ソース電極と前記ドレイン電極とに挟まれた前記半導体層上に形成された、酸化シリコンからなるエッチングストッパ層をさらに備え、
前記チャネル領域は、前記ソース電極と前記ドレイン電極の端部に沿ってそれぞれ形成された、抵抗値が低い２つの第１の領域と、前記２つの第１の領域によって挟まれ、前記２つの第１の領域よりも抵抗値が高い第２の領域とを含み、
前記エッチングストッパ層は、少なくとも前記第２の領域を覆うように形成されていることを特徴とする、請求項６に記載の薄膜トランジスタ。 An etching stopper layer made of silicon oxide formed on the semiconductor layer sandwiched between the source electrode and the drain electrode;
The channel region is sandwiched between two first regions each having a low resistance value formed along the ends of the source electrode and the drain electrode, and the two first regions. A second region having a resistance value higher than that of the first region,
The thin film transistor according to claim 6, wherein the etching stopper layer is formed so as to cover at least the second region. - 前記ソース電極と前記ドレイン電極とは、前記ゲート絶縁膜上に所定の距離を隔てて対向するように形成され、
前記半導体層は、前記一端が前記ソース電極の端部を覆って前記ソース電極の表面と電気的に接続され、前記他端が前記ドレイン電極の端部を覆って前記ソース電極の表面と電気的に接続されるように形成されていることを特徴とする、請求項１に記載の薄膜トランジスタ。 The source electrode and the drain electrode are formed on the gate insulating film so as to face each other with a predetermined distance therebetween,
The semiconductor layer has one end covering the end of the source electrode and electrically connected to the surface of the source electrode, and the other end covering the end of the drain electrode and electrically connected to the surface of the source electrode. The thin film transistor according to claim 1, wherein the thin film transistor is connected to the thin film transistor. - 前記半導体層を構成する酸化物半導体は非晶質であることを特徴とする、請求項１に記載の薄膜トランジスタ。 2. The thin film transistor according to claim 1, wherein the oxide semiconductor constituting the semiconductor layer is amorphous.
- 絶縁基板上に形成され、酸化物半導体からなる半導体層を有する薄膜トランジスタの製造方法であって、
前記絶縁基板上にゲート電極を形成する工程と、
前記ゲート電極を覆うように、少なくとも第１の酸化シリコン膜を含むゲート絶縁膜を形成する工程と、
前記ゲート電極を挟むように、所定の距離を隔てて前記ゲート絶縁膜上にソース電極およびドレイン電極を形成する工程と、
前記ソース電極および前記ドレイン電極によって挟まれた前記ゲート絶縁膜上に、一端および他端が前記ソース電極および前記ドレイン電極とそれぞれ電気的に接続されるように前記半導体層を形成する工程と、
前記ソース電極、前記ドレイン電極、および前記半導体層を覆い、少なくとも第２の酸化シリコン膜を含むパッシベーション膜を形成する工程と、
前記パッシベーション膜の形成後に熱処理を行う工程とを備え、
前記半導体層を形成する工程は、フォトリソグラフィ法を用いて、前記ソース電極と前記ドレイン電極とによって挟まれた前記半導体層からなるチャネル領域に切り欠き部を設ける工程を含み
前記熱処理を行う工程は、前記チャネル領域を前記第１の酸化シリコン膜と前記第２の酸化シリコン膜とによって挟んだ状態で行うことを特徴とする、薄膜トランジスタの製造方法。 A method of manufacturing a thin film transistor having a semiconductor layer formed on an insulating substrate and made of an oxide semiconductor,
Forming a gate electrode on the insulating substrate;
Forming a gate insulating film including at least a first silicon oxide film so as to cover the gate electrode;
Forming a source electrode and a drain electrode on the gate insulating film at a predetermined distance so as to sandwich the gate electrode; and
Forming the semiconductor layer on the gate insulating film sandwiched between the source electrode and the drain electrode so that one end and the other end are electrically connected to the source electrode and the drain electrode, respectively;
Forming a passivation film that covers the source electrode, the drain electrode, and the semiconductor layer and includes at least a second silicon oxide film;
And a step of performing a heat treatment after the formation of the passivation film,
The step of forming the semiconductor layer includes a step of providing a notch in a channel region formed of the semiconductor layer sandwiched between the source electrode and the drain electrode using a photolithography method. A method for manufacturing a thin film transistor, wherein the channel region is sandwiched between the first silicon oxide film and the second silicon oxide film. - 前記熱処理を行う工程は、少なくとも酸素を含む雰囲気中で、２００～４００℃の温度で、１～２時間の熱処理を行うことを特徴とする、請求項１０に記載の薄膜トランジスタの製造方法。 11. The method of manufacturing a thin film transistor according to claim 10, wherein the heat treatment is performed in an atmosphere containing at least oxygen at a temperature of 200 to 400 ° C. for 1 to 2 hours.
- 画像を表示するアクティブマトリクス型の表示装置であって、
複数のゲート配線と、前記複数のゲート配線と交差する複数のソース配線と、前記複数のゲート配線と前記複数のソース配線との交差点にそれぞれ対応してマトリクス状に配置された複数の画素形成部とを備える表示部とを備え、
前記画素形成部は、対応するゲート配線に印加される信号に応じてオンまたはオフする請求項１から請求項９のいずれか１項に記載の薄膜トランジスタを含むことを特徴とする、表示装置。 An active matrix type display device for displaying an image,
A plurality of pixel forming portions arranged in a matrix corresponding to a plurality of gate wirings, a plurality of source wirings intersecting with the plurality of gate wirings, and intersections of the plurality of gate wirings and the plurality of source wirings, respectively. And a display unit comprising
10. The display device according to claim 1, wherein the pixel formation portion includes the thin film transistor according to claim 1 which is turned on or off in accordance with a signal applied to a corresponding gate wiring.
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