JPH09129891A - Thin film semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching element having high redundancy. SOLUTION: A dual gate LDD-TFT (thin film transistor having a low concentration impurity region) has the structure wherein two LDD-TFT's are connected in series. As a switching element for a picture element, two dual gate LDD-TFT' s are connected in parallel. In each of the dual gate LDD-TFT's, the region of a semiconductor layer 2 overlapping the gate electrodes 4a, 4b, and the low concentration impurity regions 9a1 , 9a2 , 9b1 , 9b2 , 9c1 , 9c2 , 9d1 , 9d2 which are formed sandwiching the region of the semiconductor layer 2 are formed more thinnly than high concentration impurity regions 8a, 8b which function as a source region and a drain region. Thereby a switching element which has the following can be realized: electric characteristics required for the switching element of a liquid crystal display, and high redundancy wherein repairing work is unnecessary.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used as a switching element of a liquid crystal display device.

[0002]

2. Description of the Related Art Generally, a thin film transistor (hereinafter referred to as a TFT) used as a switching element of a liquid crystal display device has a large on-current and a small leak current (off current), that is, an on / off current. A high ratio is required. In the case of a liquid crystal display device, a high on-current is needed to charge the pixel electrodes in a short time, and a low off-current is required to hold the charged charges for one frame. is there.

Further, in order to realize a liquid crystal display device having good display quality and display quality without display unevenness and point-defect picture elements, variations in electrical characteristics of TFTs used as switching elements of respective picture elements are required. It is necessary to hold down. For example, if there is a pixel TFT having a large off current value of the TFT, the charged electric charge cannot be retained for one frame, and a sufficient voltage cannot be applied to the liquid crystal. Therefore, the light transmission characteristics of the liquid crystal of the picture element driven by the TFT are changed, and as a result, a point defect picture element such as a bright spot or display unevenness occurs, resulting in deterioration of display quality and display quality. It will be.

Polysilicon TF is used as a TFT capable of supplying a high ON current required for a liquid crystal display device.
T is used. However, in general, polysilicon TF
T has a drawback that the leak current when off is large. It is considered that the leak current is mainly due to a high electric field applied to the junction between the channel region of the TFT and the drain region or the source region. In order to reduce the leak current, an LDD structure in which a lightly doped drain region (Lightly Doped Drain) is provided between the channel region and the drain region (or the source region) is generally adopted, whereby the channel region and the drain region are drained. A method of relaxing the high electric field applied to the junction with the region is adopted. Further, a method has also been proposed in which the semiconductor layer in which the channel region and the drain region are formed is thinned to reduce the cross-sectional area of the junction and thereby suppress the leak current. Furthermore, in Japanese Patent Laid-Open No. 4-286335,
TFT having LDD structure described above (LDD-TFT)
It is shown that the off-current can be further reduced by forming a dual gate structure in which two are connected in series.

11 and 12 are a sectional view and a plan view of a conventional dual gate LDD-TFT in which the thickness of a channel region and a low concentration impurity region is reduced.

In this LDD-TFT, the semiconductor layer 2 and the gate electrodes 4a and 4b are formed on the insulating substrate 1 with the insulating film 3 interposed therebetween, and two TFTs are connected in series. Has become. Gate electrodes 4a, 4 of the semiconductor layer 2
The portions overlapping with b are the channel regions 6a and 6b. In the semiconductor layer 2, low-concentration impurity regions 9a, 9b, 9c, 9d are formed on both sides of each of the channel regions 6a, 6b, and further low-concentration impurity regions 9a, 9b, 9 are formed.
High-concentration impurity regions 8a and 8b are formed on the opposite sides of the channel regions 6a and 6b of c and 9d. The high-concentration impurity regions 8a and 8b are provided in the interlayer insulating film 10, and the contact hole 11 that also penetrates the insulating film 3 is formed.
It is connected to the electrodes 12a and 12b through a and 11b and functions as a source region and a drain region.

The channel regions 6a, 6b and the low-concentration impurity regions 9a, 9b, 9c, 9d are formed to be thinner than the source and drain regions 8a, 8b, as can be seen from FIG. Since the source and drain regions 8a and 8b are formed thicker than the channel regions 6a and 6b and the low-concentration impurity regions 9a, 9b, 9c, and 9d, the source and drain regions 8 are formed.
The resistance in a and 8b does not increase, and a large on-current can be maintained. In addition, the low-concentration impurity regions 9a and 9
The LDD structure provided with b, 9c and 9d and the electric field relaxation effect obtained by the dual gate structure and the reduction of the leak current are realized by thinning the channel region 6 and the low concentration impurity regions 9a, 9b, 9c and 9d. ing.

[0008]

As described above, in the polysilicon TFT, by adopting the structure shown in FIGS. 11 and 12, for example, the on current can be improved and the off current can be reduced. However, a liquid crystal display device is required to have good display quality and display quality without display unevenness and point defect pixels, and when a polysilicon TFT is used as a pixel switching element of a liquid crystal display device, such It is difficult to meet the demand. Variations in electrical characteristics (off characteristics) of polysilicon TFTs, deterioration of characteristics due to electrostatic breakdown, dust adhesion during the wafer process, resist pattern failure, etc., mixing of oxygen or nitrogen in the atmosphere, contamination of metal impurities, etc. If the characteristics of the pixel TFT are deteriorated due to the disorder of crystallinity or the formation of defects due to the electric circuit, and the electrical circuit is broken (open) or short-circuited (short-circuited), it does not operate as the original switching element and is originally applied to the liquid crystal. The desired voltage cannot be applied. Therefore, in the picture element in which the characteristics of the TFT as the switching element have deteriorated, the light transmission characteristics of the liquid crystal change as compared with the case where the switching element operates normally, and as a result, point defects such as bright spots occur. Picture elements or display irregularities occur, which deteriorate display quality and display quality.

For example, since the semiconductor layer of the polysilicon TFT is made of polycrystalline silicon, that is, crystal grains are gathered together, crystal grain boundaries exist between the crystal grains. Since the crystallinity in the vicinity of the crystal grain boundaries is inferior to that in the crystal grains, there is a great risk that the electrical characteristics, particularly the off characteristics, deteriorate. Therefore, in the polysilicon TFT in which the channel region or the low-concentration impurity region is formed of polycrystalline silicon, for example, when the crystal grain boundary is formed between the source and the drain, the leakage current becomes extremely large as compared with other TFTs. There is a risk that a TFT in which the electrical characteristics (OFF characteristics) are extremely deteriorated due to the positional relationship between the crystal grain boundaries and the channel region or the low-concentration impurity region such that the TFT becomes stochastic. That is, T
When a crystal grain boundary is included so as to cross the channel region or the low-concentration impurity region of the FT, a leak current easily flows along the crystal grain boundary, so that the off current sharply increases.
Therefore, such a polysilicon TFT causes unevenness and point defect picture elements in the display of the liquid crystal display device, and significantly deteriorates the display quality and the display quality. For this reason,
If such a polysilicon TFT is used as the picture element TFT of the liquid crystal display device even if only one,
This is a fatal defect for the liquid crystal display device.

Further, deterioration of TFT characteristics due to electrostatic breakdown is one of the important factors that deteriorate the display quality and display quality of the liquid crystal display device. Due to electrostatic breakdown during the manufacturing process of a liquid crystal display device, the insulating film is destroyed, so that the gate electrode is short-circuited with the source or drain electrode or, in a worse case, the patterned semiconductor layer is destroyed. A disconnection between the electrode and the drain electrode is a serious problem.

To solve these problems, it has been conventionally practiced to give redundancy to the picture element TFT by using two TFTs connected in parallel as a switching element for one picture element. It is being appreciated. For example, Japanese Unexamined Patent Publication
Japanese Patent No. 165125 discloses a method of relieving a defective pixel by connecting a plurality of pixel TFTs and storage capacitors in parallel to one pixel and cutting a defective element with a laser or the like. . However, according to this method, it is possible to identify a TFT with a sudden increase in leak current,
Repair work of cutting is required, which requires a great deal of time. Therefore, there is a problem that throughput is lowered and cost is increased.

Further, in Japanese Patent Laid-Open No. 2-193122, two independent TFTs are electrically connected in parallel by dividing a semiconductor layer of a pixel TFT into a plurality of layers on a drain electrode side or a source electrode side. A method is disclosed in which they are connected to each other and function as TFTs for defect relief. However, in this method, there is no redundancy with respect to the defective TFT caused by the abrupt increase of the leak current which is stochastically described above, so that the defective pixel due to the defective pixel TFT is prevented. It is not a means.

Some of the defects that may occur in the pixel TFT of the liquid crystal display device have been listed above. In addition to these, the causes of the pixel TFT defects such as dust adhesion during the wafer process or resist pattern defects may occur. There are many possibilities. Regarding the pixel TFT, in order to manufacture a liquid crystal display device with a high yield rate, a structure having redundancy with respect to the causes of the defects described above is required.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a thin film semiconductor device having high redundancy which does not require repair work, and It is an object of the present invention to provide a liquid crystal display device using a thin film semiconductor device as a switching element and having a high yield rate.

[0015]

A thin film semiconductor device according to the present invention is a thin film semiconductor device having at least two transistor groups connected to one pixel, the at least two transistor groups being connected in series. And each of the transistor groups has at least two transistors connected in parallel.
Two thin film transistors, each of which is formed with a semiconductor layer having a channel region, at least one low-concentration impurity region, and a high-concentration impurity region, and an insulating film interposed between the semiconductor layer and the semiconductor layer. And the channel region is formed in a region of the semiconductor layer that overlaps the electrode, and the at least one low-concentration impurity region is in a region of the semiconductor layer adjacent to the channel region. The high-concentration impurity region is formed in the semiconductor layer on the side of the low-concentration impurity region remote from the channel region, thereby achieving the above object.

Another thin film semiconductor device of the present invention is a thin film semiconductor device having at least two transistor groups connected to one pixel, wherein the at least two transistor groups are connected in parallel. Each of the groups has at least two thin film transistors connected in series, and each of the thin film transistors has a semiconductor layer having a channel region, at least one low concentration impurity region, and a high concentration impurity region, and the semiconductor layer. An electrode formed by sandwiching an insulating film between the layer and the layer, the channel region is formed in a region overlapping with the electrode of the semiconductor layer, and the at least one low-concentration impurity region is formed by: The high-concentration impurity region is formed in a region of the semiconductor layer adjacent to the channel region, and the high-concentration impurity region is formed in the semiconductor layer in the low-concentration region. From the channel region of the impurity region is formed on the far side, to achieve the above object by its.

At least one of the transistor groups
At least a pair of adjacent thin film transistors in one transistor group may be connected between corresponding thin film transistors in the adjacent transistor groups.

Each of the at least two thin film transistors further comprises a further electrode connected to the high concentration impurity region, the thickness of the semiconductor layer in the channel region and the at least one low concentration impurity region. May be thinner than the thickness in the high concentration impurity region.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION A dual gate LDD-TFT having a structure in which two LDD-TFTs are directly connected is intended to reduce leakage current. However, the inventor of the present application, as described below,
It was confirmed that the DD-TFT has a redundancy effect.

In FIG. 1, a thin film LDD-TFT in which a channel region and a low concentration impurity region are thin is actually manufactured,
The IV characteristic when connected in series is shown. (A) shows the IV characteristics when the thin film LDD-TFTs 1 and 2 having normal characteristics are connected in series, and (b) shows the thin film LDD-TFT 2 having normal characteristics and the off-current increases sharply. The IV characteristic is shown when the thin film LDD-TFT 3 is directly connected. As shown in FIG. 1A, when two thin film LDD-TFTs having normal characteristics are connected in series, the on-current becomes about 1/2 of the average value of the on-current of each thin film LDD-TFT. The off current was about 1/3. On the other hand, thin film LDD-TF connected in series
When one of the T's has a characteristic such that the off current increases sharply, as shown in FIG.
The off-current is also the same as when thin film LDD-TFTs with normal characteristics are connected in series.
The value was almost the same as when the TFTs were connected in series.
That is, as shown in FIG. 1B, by connecting a thin film LDD-TFT in which the off current increases sharply in series with a thin film LDD-TFT having normal characteristics, there is a redundancy effect of preventing an increase in the leak current at the off time. Is confirmed. Thus, if two LDD-TFTs are connected in series, one L
Even if the leakage current of the DD-TFT suddenly increases, the other LDD
-It is possible to prevent a rapid increase in off current due to the redundancy effect of the TFT.

However, the dual-gate LDD-TFT in which a plurality of LDD-TFTs are connected in series has redundancy for a short circuit failure, but has no redundancy for an open failure. Absent. Therefore, if even one LDD-TFT connected in series is electrically opened (disconnected), the dual-gate LDD-T
The FT source-drain is open (broken).

On the other hand, in the structure in which a plurality of LDD-TFTs are connected in parallel, there is redundancy with respect to open defects,
There is no redundancy for short defects. Therefore, if even one LDD-TFT connected in parallel is electrically short-circuited (short-circuited), unless a repair work such as electrically disconnecting the defective TFT with a laser is not performed, it goes without saying.
A short circuit occurs between the source and drain of the parallel LDD-TFT.

An embodiment of the pixel TFT of the present invention will be described below with reference to FIGS. 2 and 3.

2 and 3 are plan views of a pixel TFT according to the first embodiment and a pixel TFT according to the second embodiment of the present invention, respectively. The same components as those shown in FIG. 12 are designated by the same reference numerals. In either embodiment, one picture element TFT has a structure in which two dual gate LDD-TFTs are connected in parallel. Therefore, one picture element TF
T is composed of four LDD-TFTs. However, in the first embodiment, the dual gate LD
Since the D-TFTs are connected to each other in the high concentration impurity region 8c between the gate electrodes 4a and 4b, two L
It can be regarded as a structure in which two DD-TFTs connected in parallel are connected in series. Gate electrode 4 of semiconductor layer
Areas overlapping with a and 4b are each dual gate LDD-TF
It is a channel region of T.

Next, the source-drain resistance in the pixel TFT of the present invention is determined by the LDDs constituting the pixel TFT.
Description will be made in comparison with the conventional dual gate LDD-TFT and parallel LDD-TFT when the TFT is normal, short-circuited and open.

Tables 1 and 2 show the conventional dual-gate LDD-TFT and the conventional parallel LDD-T, respectively.
In the FT, the two LDD-TFTa that make up this
The source-drain resistances are shown when and b are normal, short-circuited and open. Here, the resistance between the source and drain of one LDD-TFT is R.

[0027]

[Table 1]

[0028]

[Table 2]

The source-drain resistance of the pixel TFT is 0.
Or, when it is ∞, the pixel TFT is obviously defective, causing point defects. Therefore, as shown in Table 1 and Table 2, the conventional dual gate LDD-T is used.
Connect to it if both LDD-TFTs are defective in the FT and if one is open, and in the conventional parallel LDD-TFT if both are defective and one is shorted The formed picture element becomes a point defect.

However, when the source-drain resistance of the picture element TFT is 1 / 2R to 2R, each LDD-TF.
By appropriately controlling the impurity concentration of the low-concentration impurity region of T and the thickness of the channel region, desired on-current and off-current can be obtained even if the source-drain resistance changes in the range of 1 / 2R to 2R. It is possible. Therefore, point defects do not occur.

A method of controlling the on-current and the off-current will be described with reference to FIGS. 4 and 5. FIG.
Shows the dependence of the on-current of the LDD-TFT on the resistance of the low concentration impurity region. Further, in FIG. 5, the thickness of the channel region and the on-current and the drain-source voltage V _DS = 10 V and the gate voltage V _G = − when the drain-source voltage V _DS = 0.1 V, the gate voltage V _G = 5 V, are shown. The relationship between the off-current at 10 V and the thickness of the channel region is shown. As can be seen from FIG. 4, if the sheet resistance value of the low-concentration impurity region of the LDD-TFT is changed, the value of ON current can be changed. The sheet resistance value of the low concentration impurity region can be controlled by the amount of impurities injected into the low concentration impurity region. Therefore, in the conventional pixel TFT, in order to make the on-current value equal to or higher than the value required to normally switch the pixel, when the source-drain resistance of the pixel TFT is 2R which is the largest, The amount of impurities to be injected into the low-concentration impurity regions of each LDD-TFT may be set so that the required on-current can be obtained. on the other hand,
The off-current also increases in the same manner as the on-current with the increase of the impurity implantation amount in the low-concentration impurity region. However, as shown in FIG. 5, by reducing the thickness of the channel region, it is possible to reduce only the off current without reducing the on current. Therefore, both on-current and off-current can be set to desired values.

As described above, in the conventional dual gate LDD-TFT, one LDD-TFT is short-circuited, and in the conventional parallel LDD-TFT, one is shorted.
There is redundancy for the case where one LDD-TFT is opened, but when one LDD-TFT is opened, the parallel LDD-TF is used.
It can be seen that in T there is no redundancy for the case where one is shorted.

Next, consider the case of the pixel TFT of the present invention.

In Table 3 and Table 4, in the picture element TFT according to the first embodiment of the present invention, when the four LDD-TFTs a to d constituting them are normal, respectively, and short-circuited, And the source-drain resistance when it is open. Tables 5, 6 and 7 show that the picture element TF according to the second embodiment of the present invention.
In T, the four LDD-TFTa constituting these are
Shown are the source-drain resistances in the case where each of d is normal, the case of being short-circuited, and the case of being open.

[0035]

[Table 3]

[0036]

[Table 4]

[0037]

[Table 5]

[0038]

[Table 6]

[0039]

[Table 7]

The source-drain resistance of the pixel TFT is 0.
Or, when it is ∞, the pixel TFT is obviously defective, causing point defects. However, in other cases, that is, when the source-drain resistance is 1 / 2R to 2R, as described above, the four LDD-TFTs are used.
By setting the concentration of the low-concentration impurity region and the film thickness of the channel region in advance, it is possible to obtain the desired off-current and on-current, so that the pixel does not become a point defect. . From Table 3 to Table 7, the pixel TFT of the present invention
In both the first and second embodiments,
It can be seen that there is a redundancy effect both when one of the four LDD-TFTs forming the pixel TFT is short-circuited and when any one of them is open.

Based on the above results, FIG. 6 shows the non-defective rate of the conventional dual gate LDD-TFT, the conventional parallel LDD-TFT and the liquid crystal display panel using the TFT according to the present invention as the pixel TFT. In FIG. 6, the vertical axis represents the non-defective rate of the liquid crystal display panel, and the horizontal axis represents the defective rate of the LDD-TFT forming the pixel TFT. From FIG. 6, it can be seen that the non-defective rate of the liquid crystal display panel is dramatically improved by using the TFT according to the present invention.

A specific calculation example of the non-defective rate of the liquid crystal display panel will be shown below.

First, the conventional dual gate LDD-TF
When T is used as a pixel TFT, the probability that the pixel TFT becomes defective is calculated. The pixel TFT becomes defective when the source-drain resistance is 0 or ∞ as described above. From Table 1, the source-drain resistance is 0.
Or ∞ is 2. (2) One LDD-TF
If T becomes open, 3. Both LDD of (1)
-If the TFT is short-circuited, 3. Both LDs in (2)
2. When the D-TFT is opened, and 3. (3)
One is short-circuited and the other is open. Hereinafter, in each case, the probability that the pixel TFT becomes defective will be calculated. Here, the probability that one LDD-TFT is opened is 1/100000 = 0.0000.
1 and the probability of short circuit is 1/100000 = 0.0
Set to 0001.

2. In the case of (2), the probability that the picture element TFT will be defective is (probability that one is open) × (picture element TF
The probability that T becomes a non-defective product) × (the number of combinations). The probability that a pixel TFT will be a good product is 1- (1 LDD-TF
Since it is calculated by (probability that T is open)-(probability that one LDD-TFT is short-circuited), it is 0.999998 in this case. Therefore, the probability of the pixel TFT being defective is (0.00001) × (0.9999) × 2 = 1.9
9.996 × 10 ⁻⁵ , and 3. In the case of (1), (0.00001) ² × 1 × 1 = 1 × 10 ^-10 3. In the case of (2), (0.00001) ² × 1 × 1 = 1 × 10 ^-10 3. In the case of (3), (0.00001) ² × 1 × 2 = 2 × 10 ^-10 Therefore, when the conventional dual gate LDD-TFT is used, the probability that one pixel TFT becomes defective is
The sum of the above probabilities is 2 × 10 ⁻⁵ . From this, the probability that one picture element TFT will be a good product is 1-2 × 10 ⁻⁵ = 0.99.
It becomes 998. If the number of pixel TFTs used in one liquid crystal display panel is, for example, ^{100,000, the non} -defective rate of the liquid crystal display panel becomes (0.99998) ¹⁰⁰⁰⁰⁰ = 0.135, which is extremely low. Conventional parallel LDD-
Similar results are obtained from Table 2 when the TFT is used as the pixel TFT.

Next, the non-defective rate of the liquid crystal display panel using the pixel TFT according to the first embodiment of the present invention will be calculated. As described above, the pixel TFT becomes defective when the source-drain resistance becomes 0 or ∞.
From Table 3 and Table 4, the source-drain resistance becomes 0 or ∞ when two of the four LDD-TFTs are short-circuited. 2. If two of (1) and 2 are open. When 3 of (2) are short-circuited 4. (1) When 3 pieces are opened 4. (2) When one is short-circuited and two are open 4. In case (3), two of them are shorted and one is open. 4. In the case of (4) and when all of the four LDD-TFTs become defective. It is. Hereinafter, in each case, the probability that the pixel TFT becomes defective is calculated in the same manner as the above-mentioned procedure. 3. In the case of (1), (0.00001) ² × (0.99998) ² × 2 = 1.
99992 × 10 ^-10 3. In the case of (1), (0.00001) ² × (0.99998) ² × 2 = 1.
99992 × 10 ^-10 3. In the case of (2), (0.00001) ² × (0.99998) ² × 2 = 1.
99992 × 10 ^-10 4. In the case of (1), (0.00001) ³ × (0.99998) × 4 = 3.
9992 × 10 ^-15 4. In the case of (2), (0.00001) ³ × (0.9999) × 4 = 3.
9992 × 10 ^-15 4. In the case of (3), (0.00001) ³ × (0.99998) × 4 = 3.
9992 × 10 ^-15 4. In the case of (4), (0.00001) ³ × (0.9999) × 8 = 7.
9984 × 10 ^-15 5. In the case of, (0.00001) ⁴ × 16 = 1.6 × 10 ⁻¹⁹ Therefore, the picture element TF according to the first embodiment of the present invention
The probability that T1 pieces are defective is 5.99995 × 10 ⁻¹⁰ because it is the sum of the above probabilities. From this, the probability that one pixel TFT will be a good product is 1-5.9995 × 10.
^-10 becomes 0.999999999994. Therefore, the non-defective rate of the liquid crystal display panel is (0.99999999994) ¹⁰⁰⁰⁰⁰ = 0.999994. As described above, the pixel TFT according to the first embodiment
By using, it is possible to dramatically improve the non-defective rate of the liquid crystal display panel. Pixel TFT according to the second embodiment
Similarly, in the case of using, it is possible to dramatically improve the non-defective rate of the liquid crystal display panel.

In the first and second embodiments, the pixel TFT of the present invention has been described by taking as an example the configuration in which two LDD-TFTs are connected in series and connected in two columns in parallel.
It is needless to say that the same effect can be obtained even in a configuration in which a plurality of LDD-TFTs connected in series are connected in parallel. In addition, a picture element TF connected to one picture element
Even if a structure in which a plurality of LDD-TFTs connected in parallel are connected in series is used as T, the same effect as that described above can be obtained.

As described above, according to the present invention, open defects and short defects can be avoided without special repair work, so that the yield rate of liquid crystal display panels can be dramatically improved.

Subsequently, a concrete embodiment of the present invention will be described with reference to FIGS.

FIG. 7 shows a thin film transistor 100 of the present invention.
It is a schematic cross-sectional view showing the structure of. The thin film transistor 100 includes four thin film LDs formed on the insulating substrate 1.
It is composed of D-TFTs 100a, 100b, 100c, 100d. These four thin film LDD-TFTs are serially connected in pairs of two and are connected in parallel. FIG.
3 is a cross-sectional view taken along the line AA ′ in FIG. 2, showing thin film LDD-TFTs 100a and 100b connected in series.
Only two of these are shown. Thin film LD not shown
The same applies to the structures of the D-TFTs 100c and 100d.

Thin film LDD-TFTs 100a, 100b
Each has a semiconductor layer 2 made of polysilicon formed on an insulating substrate 1. In the semiconductor layer 2,
Channel regions 6a ₁ and 6b _{1 of} each thin film LDD-TFT,
Low-concentration impurity regions 9a ₁ , 9b ₁ , 9c ₁ , 9d ₁ and high-concentration impurity regions 8a, 8b, 8c are formed. The channel regions 6a ₁ and 6b ₁ and the low concentration impurity regions 9a ₁ ;
9b ₁ , 9c ₁ and 9d ₁ are high-concentration impurity regions 8a and 8b.
It is formed thinner than. A gate insulating film 3 is formed on the semiconductor layer 2, and the gate electrode 4 is formed on the gate insulating film 3 just above the channel regions 6a ₁ and 6b _1.
a, 4b are formed. Subsequently, an interlayer insulating film 10 is formed on the gate insulating film 3 and the gate electrodes 4a and 4b, and penetrates both the interlayer insulating film 10 and the gate insulating film 3 to form a source which is a high concentration impurity region. Contact hole 11 reaching region 8a and drain region 8b
a and 11b are formed. Furthermore, the electrode 12 is formed so as to be connected to the source region 8a and the drain region 8b via the contact holes 11a and 11b.
a and 12b are formed.

The thin film transistor B- of the thin film transistor shown in FIG.
The cross section taken along the line B ′ is similar to that of FIG. 7 except that the central high-concentration impurity region 8c becomes regions 8c ₁ and 8c ₂ .

A method of manufacturing the thin film transistor 100 having such a structure will be described with reference to FIGS.
This will be described below. 8 and 9 are schematic cross-sectional views illustrating a method of manufacturing the thin film transistor 100 over time.

First, as shown in FIG. 8A, a semiconductor layer 2 made of polysilicon is formed on an insulating substrate 1.
As the insulating substrate 1, for example, an insulating substrate such as quartz or a Si substrate covered with an insulating film such as SiO ₂ or Si ₃ N ₄ is used. Further, the semiconductor 2 is, for example, Si ₂ H ₆ (disilane) with N ₂ or He added as a source gas, and is 1000 to 1200 Å by a low pressure CVD method at 450 to 475 ° C. and 25 to 50 Pa. It is formed by depositing an amorphous silicon layer and then heat treating it to polycrystallize it. This heat treatment is 600
Annealing is performed for 12 to 24 hours in a heat treatment furnace in a N ₂ atmosphere at ℃. By the above method, it is possible to obtain polysilicon having a large grain size of 2 to 3 μm. Subsequently, the formed semiconductor layer 2 is formed in a region between a transistor row connected in series and a transistor row connected in parallel to the semiconductor row 2 by a normal photolithography technique as shown in FIG. 2 or 3. Then, patterning is performed in the shape of an island in which is removed.

In addition to the above-described low pressure CVD method, plasma CVD method or sputtering method may be used for forming the amorphous silicon film. A laser annealing method may be used for polycrystallizing the amorphous silicon.

Next, a 200 Å silicon oxide film 21 is deposited on the exposed portion of the substrate 1 and the entire surface of the semiconductor layer 2, and subsequently a 400 Å silicon nitride film 22 is deposited on the silicon oxide film 21. . For depositing the silicon oxide film 21 and the silicon nitride film 22, a reduced pressure C
The VD method is used. Next, the silicon nitride film 22 and the silicon oxide film 21 in the area where thinning is to be performed are removed by etching (FIG. 8B).

Thereafter, by performing oxidation using dry O ₂ at 1050 ° C., the portion of the semiconductor layer 2 which is not covered with the silicon nitride film 22 becomes thin, and thick polysilicon is provided above it. The oxide film 23 is formed.
The thickness of the polysilicon oxide film 23 thus formed is 1600Å, and the thickness of the remaining silicon oxide film 21 is 200Å. In this oxidation step, the silicon nitride film 22 suppresses the oxidation, so that the oxidation is promoted in the portion of the semiconductor layer 2 which is not covered with the silicon nitride film 22, and the semiconductor layer 2 having a thin portion is obtained ( FIG. 8 (c)).

Next, after removing the remaining silicon nitride film 22, silicon oxide film 21 and polysilicon oxide film 23, a gate insulating film 3 of 800 to 1000 Å is formed on the entire surface of the substrate 1 and the semiconductor layer 2 by the CVD method. It is formed to a thickness (FIG. 8D).

After forming only the silicon nitride film 21, the silicon oxide film above the region to be thinned may be etched and then thinned by oxidation using dry O ₂ .

Further, the thinning of the semiconductor layer 2 can also be performed by a process using etching as described below.

A silicon oxide film 21 having a thickness of about 300 Å is formed on the exposed portion of the substrate 1 and the entire surface of the semiconductor film 2 by the CVD method, and then the silicon oxide film in the region to be thinned is removed by etching ( FIG. 9A). next,
As shown in FIG. 9B, the remaining silicon oxide film 21
Using the as a mask, the region of the semiconductor layer 2 to be the channel region and the low concentration impurity region is etched by about 800Å. Then, the remaining silicon oxide film 2
1 is removed, the gate insulating film 3 is formed on the entire surface of the substrate 1 and the semiconductor layer 2 by the CVD method to a thickness of 800 to 1000.
Å thickness.

When the gate insulating film 3 is formed by the above-described method, a phosphorus-doped polysilicon layer is deposited on the gate insulating film 3 by about 4000 Å. By patterning this into a predetermined shape, the gate electrodes 4a and 4b are formed right above the region to be the channel region. Subsequently, as shown in FIG. 9C, P ⁺ ions are implanted into the semiconductor layer 2 using the gate electrodes 4a and 4b as a mask to form the low concentration impurity region 5. Thereby, the gate electrodes 4a, 4b
The semiconductor layer below the regions becomes the channel regions 6a ₁ and 6b ₁ .
The dose of ion implantation at this time is 5 × 10 ¹² to reduce the variation in the electrical characteristics of the TFT.
It is set to 5 × 10 ¹⁴ cm ⁻² (5 × 10 ^{17 to} 5 × 10 ¹⁹ cm ⁻³ ). As can be seen from the relationship between the dose amount of ion implantation and the diffusion resistance of ion-implanted polysilicon shown in FIG. 13, when the dose amount is 5 × 10 ¹² cm ⁻² or less, the variation amount of the diffusion resistance with respect to the dose amount. Suddenly increases, and the dispersion of the diffusion resistance value becomes large. Also, the dose amount is 5 × 1
When it is 0 ¹⁴ cm ⁻² or more, the electric field relaxation effect in the low concentration impurity region is lost. The resistance value of the low concentration impurity region is TF
Since there is a correlation with the electrical characteristics of T, particularly the on-current and the off-current, it is desirable to set the dose amount of ion implantation in the above range in order to reduce variations in the electrical characteristics of the TFT.

Next, as shown in FIG. 9D, P ⁺ ions are implanted using the resist 7 as a mask. As a result, high concentration impurity regions 8a, 8b and 8c are formed. Further, in the portion of the semiconductor layer 2 below the resist 7 except the channel regions 6a ₁ and 6b ₁ , the low concentration impurity regions 9 are formed.
a ₁ , 9b ₁ , 9c ₁ , 9d ₁ are formed. The dose amount of ion implantation at this time is 3 × 10 ¹⁵ cm ^-2 .

Next, after removing the resist 7, the interlayer insulating film 10 is formed over the entire surface of the substrate, and thereafter 950.
Impurities are activated by heat treatment at 30 ° C. for 30 minutes (FIG. 10A). As a material for the interlayer insulating film 10, for example, silicon dioxide is used.

After that, the contact holes 11a and 11b are formed by removing the interlayer insulating film 10 and the gate insulating film 3 so as to reach the high concentration impurity regions 8a and 8b. Then, the contact holes 11a, 11
The electrode 12 is formed by partially filling b with a conductive material such as aluminum.
a and 12b are formed (FIG. 10B). As described above, the thin film LDD-TFTs 100a, 100b connected in series,
And a thin film LDD-TFT 100c connected in series,
A thin film transistor 100 having 100d, in which the columns of TFTs 100a and 100b are connected in parallel to the columns of TFTs 100c and 100d, is completed.

As described above, in this embodiment, two thin film LDD-
A thin film transistor having a configuration in which two TFTs connected in series are connected in parallel has been described. However, a thin film transistor having a configuration in which a plurality of LDD-TFTs connected in series are connected in parallel in a plurality of columns can be manufactured by the same procedure.

In this embodiment, the thin film transistor is composed of the thin film LDD-TFT in which the thickness of the channel region and the low concentration impurity region of the semiconductor layer is smaller than the thickness of the high concentration impurity region. However, even when the LDD-TFT not thinned is used, the above-described redundancy effect can be obtained. Therefore, if we are not particular about suppressing the off-current of the thin film transistor,
It is also possible to use an LDD-TFT that has not been thinned.

[0067]

As described above, the thin film transistor of the present invention has a structure in which a plurality of thin film LDD-TFTs connected in series are connected in parallel in a plurality of columns.
With this configuration, a redundancy effect with respect to open defects and short defects can be obtained. Therefore, the thin film transistor of the present invention can dramatically improve the non-defective rate of the liquid crystal display panel.

[Brief description of the drawings]

FIG. 1 is a diagram showing IV characteristics in a structure in which two LDD-TFTs are connected, where (a) shows a case where they are connected in series and (b) shows a case where they are connected in parallel.

FIG. 2 is a plan view showing one of the embodiments of the present invention.

FIG. 3 is a plan view showing another embodiment of the present invention.

FIG. 4 is a graph showing the relationship between the on-current of an LDD-TFT and the resistance of a low concentration impurity region.

FIG. 5 is a graph showing the relationship between the on / off current of the LDD-TFT and the thickness of the channel region.

FIG. 6 is a graph showing the relationship between the non-defective rate of the liquid crystal display panel and the number of defective pixel TFTs.

FIG. 7 is a schematic cross-sectional view of a thin film transistor of the present invention.

FIG. 8 is a schematic cross-sectional view for sequentially explaining the method of manufacturing the thin film transistor of the present invention.

FIG. 9 is a schematic cross-sectional view for sequentially explaining the method of manufacturing the thin film transistor of the present invention.

FIG. 10 is a schematic cross-sectional view for explaining the method of manufacturing a thin film transistor of the invention over time.

FIG. 11 is a schematic cross-sectional view of a conventional dual gate LDD-TFT.

FIG. 12 is a plan view of a conventional dual gate LDD-TFT.

FIG. 13 is a graph showing the relationship between the diffusion resistance of polysilicon and the dose amount.

[Description of Reference Signs] 1 insulating substrate 2 semiconductor layer 3 gate insulating film 4a, 4b gate electrode 6a, 6b channel region 8a source region 8b drain region 9a, 9b, 9c, 9d low concentration impurity region 10 interlayer insulating film 11a, 11b Contact holes 12a, 12b Electrodes 100a, 100b Thin film LDD-TFT

Claims (4)

[Claims] 1. A thin-film semiconductor device having at least two transistor groups connected to one pixel, wherein the at least two transistor groups are connected in series, and each of the transistor groups is connected in parallel. At least two thin film transistors, each of which has a semiconductor layer having a channel region, at least one low-concentration impurity region, and a high-concentration impurity region, and an insulating film sandwiched between the semiconductor layer. And the channel region is formed in a region of the semiconductor layer overlapping with the electrode, and the at least one low-concentration impurity region is adjacent to the channel region of the semiconductor layer. And the high concentration impurity region is formed from the channel region of the low concentration impurity region in the semiconductor layer. Thin film semiconductor device formed on the far side. 2. A thin film semiconductor device having at least two transistor groups connected to one pixel, wherein the at least two transistor groups are connected in parallel, and each of the transistor groups is connected in series. Each of the thin film transistors, and each of the thin film transistors has an insulating film between the semiconductor layer having a channel region, at least one low concentration impurity region, and a high concentration impurity region, and the semiconductor layer. An electrode formed so as to be sandwiched therebetween, the channel region is formed in a region of the semiconductor layer overlapping with the electrode, and the at least one low-concentration impurity region is formed in the channel region of the semiconductor layer. The high-concentration impurity region is formed in an adjacent region, and the high-concentration impurity region is formed in the semiconductor layer in the channel region of the low-concentration impurity region A thin film semiconductor device that is formed on the side farther from. 3. The thin film semiconductor device according to claim 2, wherein at least a pair of adjacent thin film transistors in at least one transistor group of the transistor groups is connected between corresponding thin film transistors in the adjacent transistor group. . 4. Each of the at least two thin film transistors further comprises a further electrode connected to the high concentration impurity region, the semiconductor layer in the channel region and the at least one low concentration impurity region. The thin film semiconductor device according to claim 1, wherein the thin film semiconductor device has a thickness smaller than that in the high concentration impurity region.