KR0155306B1 - Thin film transistor with double gate and method thereof - Google Patents
Thin film transistor with double gate and method thereofInfo
- Publication number
- KR0155306B1 KR0155306B1 KR1019940036359A KR19940036359A KR0155306B1 KR 0155306 B1 KR0155306 B1 KR 0155306B1 KR 1019940036359 A KR1019940036359 A KR 1019940036359A KR 19940036359 A KR19940036359 A KR 19940036359A KR 0155306 B1 KR0155306 B1 KR 0155306B1
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- South Korea
- Prior art keywords
- thin film
- double
- gate
- film transistor
- forming
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- 239000010409 thin film Substances 0.000 title claims abstract description 72
- 238000000034 method Methods 0.000 title claims description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 239000010410 layer Substances 0.000 claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 239000010408 film Substances 0.000 claims description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 17
- 150000002500 ions Chemical class 0.000 claims description 11
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 5
- 238000002425 crystallisation Methods 0.000 claims description 5
- 230000008025 crystallization Effects 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 239000011159 matrix material Substances 0.000 abstract description 3
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 2
- 239000007789 gas Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000012153 distilled water Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 고화질의 액티브 매트릭스 액정표시장치에 유용한 다결정 실리콘에 관한 것으로서, 특히 이중게이트를 구비한 박막트랜지스터 및 그의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to polycrystalline silicon useful in high quality active matrix liquid crystal displays, and more particularly, to a thin film transistor having a double gate and a method of manufacturing the same.
본 발명은 이중 게이트 구조나 이중채널, 이중 게이트 구조를 갖는 박막 트랜지스터의 게이트 전극과 게이트 전극 사이에 있는 활성층의 저항값 즉 N-채널 박막 트랜지스터의 경우는 n+저항을, P-채널 박막 트랜지스터의 경우는 p+저항값을 각각 n-, p-저항값으로 조절하여 게이트 전극과 게이트 전극사이의 저항길이를 줄이므로써 소자가 차지하는 면적을 줄임과 동시에 누설전류를 감소 시킬 수 있다.The present invention provides a resistance value of an active layer between a gate electrode and a gate electrode of a thin film transistor having a double gate structure, a double channel or a double gate structure, that is, n + resistance in the case of an N-channel thin film transistor, and a P-channel thin film transistor. By reducing the resistance length between the gate electrode and the gate electrode by adjusting the p + resistance value to n − and p − resistance values, respectively, the area occupied by the device can be reduced and the leakage current can be reduced.
Description
제1도는 본 발명에 의한 이중게이트 박막 트랜지스터의 단면도.1 is a cross-sectional view of a double gate thin film transistor according to the present invention.
제2도는 제1도의 평면도.2 is a plan view of FIG.
제3도(a)∼(f)는 본 발명에 의한 박막 트랜지스터의 제조방법을 각 단계별로 나타낸 공정단면도.3 (a) to 3 (f) are process cross-sectional views showing the manufacturing method of the thin film transistor according to the present invention in each step.
제4도(a)∼(c)는 본 발명에 다른실시예에 의해 제작된 구조를 나타낸 도면도이다.4 (a) to 4 (c) are diagrams showing a structure manufactured according to another embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 투명성 절연기판 2 : 다결정 실리콘 박막(활성충)1 Transparent Insulation Substrate 2 Polycrystalline Silicon Thin Film (Active Charge)
3 : 게이트 산화막 4 : 게이트 전극3: gate oxide film 4: gate electrode
5 : 감광막(photoresist)5: photoresist
6 : 소오스, 드레인 영역(N-채널일 경우 N+, P-채널일 경우 P+)6: source, drain region (N + for N-channel, P + for P-channel)
7 : 산화막 8 : 소오스, 드레인 전극7: oxide film 8: source, drain electrode
10 : 저농도 도핑영역10: low concentration doping area
본 발명은 고화질의 액티브 매트릭스 액정표시장치에 유용한 다결정 실리콘 박막 트랜지스터에 관한 것으로서, 특히 이중게이트를 구비한 박막트랜지스터 및 그의 제조방법에 관한 것이다. 일반적으로, 다결정 실리콘 박막 트랜지스터는 고화질의 액티브 매트릭스 액정표시장치(active matrix LCD; Lipuid Crystal Display)에서 패널의 픽셀스위치(pixel switch) 또는 주변 구동집적회로(drive IC)에 이용되고 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to polycrystalline silicon thin film transistors useful in high quality active matrix liquid crystal displays, and more particularly, to a thin film transistor having a double gate and a method of manufacturing the same. In general, polycrystalline silicon thin film transistors are used in pixel switches or peripheral drive ICs of panels in high-definition active matrix LCDs (lipuid crystal displays).
종래의 다결정 실리콘 박막트랜지스터 구조는 OFF상태에서 누설전류가 많아 TFT-LCD의 픽셀어레이 구동소자로서 부적합하다. 일반적으로 누설전류는 게이트전극과 드레인전극 사이에 걸리는 전기장의 세기와 활성층으로 사용되는 다결정 실리콘박막의 결함에 의하여 좌우되므로 누설전류를 줄이기 위해서는 게이트전극과 드레인전극 사이의 전기장의 세기와 다결성 실리콘 박막의 결함을 줄일 필요가 있다.The conventional polycrystalline silicon thin film transistor structure has a large leakage current in the OFF state, which is not suitable as a pixel array driving element of a TFT-LCD. Generally, the leakage current depends on the strength of the electric field between the gate electrode and the drain electrode and the defect of the polycrystalline silicon thin film used as the active layer. Therefore, in order to reduce the leakage current, the electric field strength between the gate electrode and the drain electrode and the polysilicon thin film are reduced. It is necessary to reduce the defects.
누설전류를 줄이기 위한 다결정 실리콘 박막 트랜지스터의 구조로써는 LDD(Lightly Doped Drain)나 이중 게이트, 다중 게이트, OFFSET구조 등이 발표되고 있다.As a structure of a polycrystalline silicon thin film transistor to reduce leakage current, a lightly doped drain (LDD), a double gate, a multi-gate, and an offset structure have been announced.
LDD 구조와 OFFSET 구조는 누설전류를 감소시킬 수 있으나 이와 함께 구동 전류가 감소되는 단점이 있다.LDD structure and OFFSET structure can reduce the leakage current, but also has the disadvantage that the driving current is reduced.
이중 게이트 구조나 다중 게이트 구조는 구동 전류의 감소는 적으나 OFF 상태에서 게이트 전압의 증가에 따라 누설전류가 증가하여 누설전류를 줄이기 위하여서는 게이트 전극과 게이트 전극 사이의 활성층 간격을 길게 할 필요가 있다.In the double gate structure or the multi-gate structure, the driving current decreases little, but the leakage current increases with the increase of the gate voltage in the OFF state, so that the active layer gap between the gate electrode and the gate electrode needs to be increased to reduce the leakage current. .
게이트 전극과 게이트 전극 사이의 저항길이를 길게 할 경우 소자가 차지하는 면적이 크므로 개구율이 큰 고정세, 고화질 TFT-LCD 디스플레이의 구동소자로서 응용하기에는 문제가 있다.When the resistance length between the gate electrode and the gate electrode is increased, the area occupied by the element is large, and therefore, there is a problem in application as a driving element of a high definition, high definition TFT-LCD display having a large aperture ratio.
본 발명은 이중 게이트 구조나 이중채널, 이중 게이트 구조를 갖는 박막 트랜지스터의 게이트 전극과 게이트 전극 사이에 있는 활성층의 저항값, 즉 N -채널 박막 트랜지스터의 경우는 n+저항을, P-채널 박막 트랜지스터의 경우는 p+저항값을 각각 n-, p-저항값으로 조절하여 게이트 전극과 게이트 전극사이의 저항길이를 줄이므로써 소자가 차지하는 면적을 줄임과 동시에 누설전류를 감소 시킬 수 있는 박막 트랜지스터 및 제조방법을 제공하는데 그 목적이 있다.The present invention provides a resistance value of an active layer between a gate electrode and a gate electrode of a thin film transistor having a double gate structure, a double channel structure, or a double gate structure, that is, n + resistance in the case of an N-channel thin film transistor. In this case, a thin film transistor and a manufacturing method which can reduce the area occupied by the device and reduce the leakage current by reducing the resistance length between the gate electrode and the gate electrode by adjusting the p + resistance value to n- and p-resistance values, respectively. The purpose is to provide.
상기 목적을 달성하기 위한 본 발명은 이중게이트(Double Gate) 및 이들의 하부에 게이트산화막을 개재하여 오버랩되는 활성층 영역에 각각 형성된 이중채널을 구비한 다결정실리콘 박막 트랜지스터에 있어서, 상기 이중게이트 사이의 활성층의 저항값을 조절하여 누설 전류를 감소시키기 위하여 상기 이중게이트의 하나의 게이트와 다른 하나의 게이트 사이의 활성층에 소정 도전형의 저농도 도핑영역을 구비한 것을 특징으로 한다.According to an aspect of the present invention, there is provided a polysilicon thin film transistor having a double gate and a double channel formed in an active layer region overlapping each other with a double gate and a gate oxide layer thereunder, wherein the active layer between the double gates. In order to reduce the leakage current by adjusting the resistance value of the active layer between one gate and the other gate of the double gate is characterized in that the low concentration doping region of a predetermined conductivity type.
본 발명에 의한 박막트랜지스터의 제조방법은 a)투명성 절연기판상에 비정질 실리콘 박막을 저압화학기상증착법(LPCVD)으로 증착한후 결정화를 위한 열처리 공정을 수행하여 다결정 실리콘박막을 형성하는 공정; b)상기 다결정실리콘 박막을 패터닝하여 트랜지스터의 활성영역을 정의하는 공정; c)상기 활성영역이 정의된 기판의 전면에 게이트 산화막을 형성하는 공정; d)상기 게이트 산화막의 소정부위에 이중(double)게이트를 형성하는 공정; e)상기 이중 게이트를 마스크로 사용하여 저농도 불순물을 이온주입하여 이중게이트 사이의 활성영역에 누설전류를 감소시키기 위한 저농도 도핑 영역을 형성하는 공정; f)상기 이중게이트 사이에 감광막 패턴을 형성하고, 이 패턴을 마스크로 이용한 이온주입공정을 통하여 상기 활성영역에 고농도의 소오스/드레인 영역을 형성하는 공정; 및 g)금속전극을 형성하기 위한 배선공정으로 이루어 진다.A method of manufacturing a thin film transistor according to the present invention comprises the steps of: a) forming a polycrystalline silicon thin film by performing an annealing process for crystallization after depositing an amorphous silicon thin film on a transparent insulating substrate by low pressure chemical vapor deposition (LPCVD); b) patterning the polysilicon thin film to define an active region of a transistor; c) forming a gate oxide film on the entire surface of the substrate in which the active region is defined; d) forming a double gate at a predetermined portion of the gate oxide film; e) implanting low concentration impurities into the active region between the double gates by using the double gate as a mask to form a low concentration doped region for reducing a leakage current; f) forming a photoresist pattern between the double gates and forming a high concentration source / drain region in the active region through an ion implantation process using the pattern as a mask; And g) a wiring process for forming a metal electrode.
본 발명의 다른 특징은 첨부도면을 참조하여 설명되는 실시예에 의해 보다 명확해질 것이다.Other features of the present invention will become more apparent from the embodiments described with reference to the accompanying drawings.
제1도는 본 발명에 의하여 제안된 이중 게이트 구조 및 이중채널, 이중 게이트 구조를 갖는 박막 트랜지스터의 단면도이다.1 is a cross-sectional view of a thin film transistor having a double gate structure and a double channel, double gate structure proposed by the present invention.
제2도는 제1도의 평면도이다.2 is a plan view of FIG.
본 발명의 박막 트랜지스터의 구조에 대한 제조공정을 제3도를 참조하면서 상세히 설명하고자 한다. 제3(a)도와 같이, 증류수로 세척한 산화막이 성장된 실리콘 웨이퍼, 석영 혹은 유리기판(1) 위에 SiH4가스 또는 Si2H6가스를 사용하여 비정질 실리콘 박막을 저압 화학기상증착(LPCVD)방법으로 두께 200Å∼1000Å증착한다.The manufacturing process for the structure of the thin film transistor of the present invention will be described in detail with reference to FIG. As shown in FIG. 3 (a), low pressure chemical vapor deposition (LPCVD) is performed on an amorphous silicon thin film using SiH 4 gas or Si 2 H 6 gas on a silicon wafer, quartz or glass substrate 1 on which an oxide film washed with distilled water is grown. It deposits 200-1000 micrometers in thickness by the method.
이때 SiH4가스를 사용할 경우 일반적으로 550℃에서 수행되며, Si2H6가스를 사용할 경우 470℃정도에서 비정질 실리콘 박막을 증착한다.In this case, the SiH 4 gas is generally performed at 550 ° C., and the Si 2 H 6 gas is deposited at about 470 ° C. to deposit an amorphous silicon thin film.
증착된 비정질 실리콘 박막을 600℃이하의 열전기로 또는 산소분위기의 고압 열전기로에서 열처리에서 결정화한다.The deposited amorphous silicon thin film is crystallized by heat treatment in a thermoelectric furnace below 600 ° C. or in a high pressure thermoelectric furnace in an oxygen atmosphere.
비정질 실리콘 박막을 결정화하는 또다른 방법으로서는 급속 열처리 방법으로 결정핵을 생성한 후 600℃이하 열전기로 또는 산소 분위기의 고압 열전기로에서 열처리하여 다결정 실리콘 박막(2)을 형성한다.As another method of crystallizing an amorphous silicon thin film, crystal nuclei are formed by a rapid heat treatment method and then heat-treated in a thermoelectric furnace at 600 ° C. or lower or in a high-pressure thermoelectric furnace in an oxygen atmosphere to form a polycrystalline silicon thin film 2.
결정화된 다결정 실리콘 박막(2)을 사진 식각법으로 제3(b)도와 같이 활성층을 정의하고 식각하여 활성층 영역을 형성한다. 활성층 영역위에 제3(c)도와 같이, 게이트 산화막을 형성하기 위하여 800℃∼1000℃의 고온 열전기로에서 산화막을 성장하거나 혹은 저압 화학 기상증착이나 플라즈마 화학기상증착(PECVD)방법으로 두께 300Å∼1000Å의 게이트 산화막(3)을 증착한후 600℃ 이하 열전기로에서 열처리한다.The crystallized polycrystalline silicon thin film 2 is defined and etched as shown in FIG. 3 (b) by photolithography to form an active layer region. To form a gate oxide film on the active layer region as shown in FIG. 3 (c), the oxide film is grown in a high temperature thermoelectric furnace at 800 ° C to 1000 ° C or by a low pressure chemical vapor deposition or a plasma chemical vapor deposition (PECVD) method. The gate oxide film 3 was deposited and then heat treated in a thermoelectric furnace at 600 ° C. or lower.
그 다음 열처리된 게이트 산화막위에 다결정 실리콘 박막이나 실리사이드, 금속막을 증착한후 사진 식각법으로 게이트 전극(4)을 형성한다.Next, a polycrystalline silicon thin film, silicide, or metal film is deposited on the heat-treated gate oxide film, and then the gate electrode 4 is formed by photolithography.
게이트 전극과 게이트 전극 사이의 저항값을 조절하기 위하여 제3(d)도와 같이, N-채널 다결정 실리콘 박막 트랜지스터인 경우는 P+(인) 이온이나 As+(비소)이온을, P-채널 다결정 실리콘 박막 트랜지스터의 경우는 BF2이온이나 B+(붕소)이온을 각각 1×1012/㎠∼1×1014/㎠농도로 주입한다.In order to adjust the resistance value between the gate electrode and the gate electrode, as shown in FIG. 3 (d), in the case of an N-channel polycrystalline silicon thin film transistor, P + (phosphorus) ions or As + (arsenic) ions are used as the P-channel polycrystal. In the case of a silicon thin film transistor, BF 2 ions and B + (boron) ions are implanted at a concentration of 1 × 10 12 / cm 2 to 1 × 10 14 / cm 2, respectively.
그 다음 제3(e)도와 같이, 게이트 전극과 게이트 전극 사이에 감광막(5)을 이용하여 사진전사 방법으로 마스크를 형성한 후 N-채널박막 트랜지스터일 경우 P+(인) 이온이나 As+(비소)이온을 1×1015∼5×1515/㎠ 농도로 주입하고, p-채널 박막 트랜지스터일 경우 B+(붕소)나 BF2를 1×1015∼5×1015/㎠ 농도로 주입하여 소오스, 드레인(6)을 형성한다.Next, as shown in FIG. 3 (e), a mask is formed between the gate electrode and the gate electrode using the photosensitive film 5 by phototransfer method, and in the case of an N-channel thin film transistor, P + (phosphorus) ions or As + ( Arsenic) ion is implanted at a concentration of 1 × 10 15 to 5 × 15 15 / cm 2, and in the case of a p-channel thin film transistor, B + (boron) or BF 2 is implanted at a concentration of 1 × 10 15 to 5 × 10 15 / cm 2 To form the source and drain 6.
이어, 제3(f)도와 같이, 저압 화학 기상증착방법으로 두께 5000Å∼10000Å의 산화막(7)을 증착한후 이온주입된 불순물을 활성화한다.Subsequently, as shown in FIG. 3 (f), an oxide film 7 having a thickness of 5000 kPa to 10000 kPa is deposited by a low pressure chemical vapor deposition method, and ion implanted impurities are activated.
사진 식각법을 이용하여 전극 접촉 부분을 만든 다음 금속막 또는 투명 전도막을 이용하여 전극 접촉 부분을 만든 다음 금속막 또는 투명 전도막을 스퍼터링 방법으로 증착한다.The electrode contact portion is made using photolithography, and then the electrode contact portion is made using a metal film or a transparent conductive film, and then the metal film or the transparent conductive film is deposited by a sputtering method.
사진 식각방법으로 게이트, 소오스, 드레인 전극(8)을 형성한 후 수소화하여 본 발명의 다결정 실리콘 박막 트랜지스터 구조를 제조한다.The gate, source, and drain electrodes 8 are formed by a photolithography method and then hydrogenated to fabricate the polycrystalline silicon thin film transistor structure of the present invention.
또다른 실시예로서, 제4도와 같이 다결정 실리콘 박막 대신에 활성층으로 다결정 실리콘/다결정 Si1-xGex/다결정 실리콘으로 구성된 3층 박막이나, 다결정 실리콘/다결정 Si1-xGex으로 구성된 이중막, 또는 다결정 Si1-xGex단층 박막을 활용하여 본 발명의 박막 트랜지스터 구조를 제조할 수 있다.In another embodiment, a three-layer thin film composed of polycrystalline silicon / polycrystalline Si 1-x Ge x / polycrystalline silicon as an active layer instead of the polycrystalline silicon thin film as shown in FIG. 4, or a double layer composed of polycrystalline silicon / polycrystalline Si 1-x Ge x The thin film transistor structure of the present invention can be manufactured using a film or a polycrystalline Si 1-x Ge x single layer thin film.
먼저, 3층 박막을 활성층으로 사용하는 경우를 제4(a)도를 참조하여 서술하고자 한다.First, the case where a three-layer thin film is used as an active layer will be described with reference to FIG. 4 (a).
증류수로 세척한 산화막이 성장된 실리콘 웨이퍼, 석영 혹은 유리 기판(1)위에 SiH4가스 또는 Si2H6가스를 사용하여 저압 화학 기상 증착방법(LPCVD)이나 급열 화학 기상증착방법(RTCVD)으로 두께 50Å∼500Å의 비정질 실리콘 박막(2a)을 증착한다.SiH 4 gas or Si 2 H 6 gas is used on the silicon wafer, quartz or glass substrate (1) on which the oxide film washed with distilled water is grown, and the thickness is reduced by low pressure chemical vapor deposition (LPCVD) or rapid chemical vapor deposition (RTCVD). An amorphous silicon thin film 2a of 50 kV to 500 kV is deposited.
SiH4가스를 사용할 경우는 증착온도가 500℃∼580℃, Si2H6가스를 사용할 경우는 증착온도가 400℃∼500℃에서 수행한다.When using SiH 4 gas, the deposition temperature is performed at 500 ° C. to 580 ° C., and when using Si 2 H 6 gas, the deposition temperature is performed at 400 ° C. to 500 ° C.
증착된 비정질 실리콘 박막위에 같은 방법으로 GeH4와 Si2H6가스 또는 SiH4가스를 혼합하여 두께 50Å∼500Å의 비정질 Si1-xGex박막(2b)을 증착한다.GeH 4 and Si 2 H 6 gas or SiH 4 gas are mixed on the deposited amorphous silicon thin film in the same manner to deposit an amorphous Si 1-x Ge x thin film 2b having a thickness of 50 μs to 500 μs.
그 다음 상기 기술한 같은 방법으로 두께 50Å∼500Å의 비정질 실리콘 박막(2c)을 증착하여 3층 비정질 박막을 형성한다.Thereafter, an amorphous silicon thin film 2c having a thickness of 50 GPa to 500 GPa is deposited by the same method as described above to form a three-layer amorphous thin film.
증착된 비정질 박막을 600℃이하 열전기로 또는 산소 분위기의 고압 열전기로에서 열처리하여 결정화 하거나 급속 열처리방법(RTA)으로 결정핵을 생성한 후, 600℃이하의 열전기로 또는 산소 분위기의 고압 열전기로에서 열처리하여 결정립을 성장하여 다결정 3층 박막을 형성한다.The deposited amorphous thin film is crystallized by heat treatment in a thermoelectric furnace below 600 ° C. or in a high pressure thermoelectric furnace in an oxygen atmosphere, or after crystallization is generated by rapid thermal annealing (RTA). Heat treatment to grow the crystal grains to form a polycrystalline three-layer thin film.
결정화된 다결정 3층 박막을 사진 전사법으로 활성층을 정의하고 건식 식각방법으로 식각하여 활성층 영역을 형성한다.The crystallized polycrystalline three-layer thin film is defined by an active layer by a photo transfer method and etched by a dry etching method to form an active layer region.
그 다음 제3(c)도에서부터 제3(f)도까지 앞서 서술한 순서와 방법 대로 공정을 수행하여 제4(a)도와 같은 박막 트랜지스터 구조를 제조한다.Then, the process is performed from the third (c) to the third (f) in the order and method described above to manufacture the thin film transistor structure as shown in the fourth (a).
이중막을 활성층으로 사용할 경우는 산화막이 성장된 실리콘 웨이퍼, 석영 혹은 유리기판(1) 위에 Si1-xGex비정질 박막(2a)을 두께 50Å∼100Å증착한후 그 위의 비정질 실리콘 박막(2b)을 두께 50Å∼100Å으로 증착한다.In the case of using the double layer as an active layer, a Si 1-x Ge x amorphous thin film 2a is deposited on the silicon wafer, quartz or glass substrate 1 on which the oxide film is grown, and the amorphous silicon thin film 2b is deposited thereon. Is deposited to a thickness of 50 kPa to 100 kPa.
그 다음 증착된 이중막을 상기 서술한 바와 같은 방법으로 열처리 하여 결정화한 후 활성층으로 활용하여 상기 서술한 제3(c)도에서부터 제3(f)도까지 공정순서와 같은 방법으로 공정을 수행하여 제4(b)도와 같은 박막 트랜지스터를 제조한다.Then, the deposited double layer is heat-treated and crystallized in the same manner as described above, and then used as an active layer to carry out the process in the same manner as in the above-mentioned process from the third (c) to the third (f). A thin film transistor such as 4 (b) is manufactured.
Si1-xGex단층 박막을 활성층으로 활용할 경우 두께 200Å∼1500Å의 비정질 Si1-xGex박막(2)을 증착한후 상기 서술한 같은 방법으로 결정화하여 활성층으로 활용한다.When the Si 1-x Ge x single layer thin film is used as the active layer, an amorphous Si 1-x Ge x thin film (2) having a thickness of 200 Å to 1500 Å is deposited and crystallized in the same manner as described above to be used as the active layer.
그 다음 제3(c)도에서 제3(f)도까지의 공정순서와 같은 방법으로 제4(c)도와 같은 박막 트랜지스터를 제조한다.Then, a thin film transistor as shown in FIG. 4 (c) is manufactured in the same manner as the process sequence from FIG. 3 (c) to FIG. 3 (f).
이상 설명한 바와같이 본 발명에 의하면, 이중 게이트 구조 및 이중채널, 이중게이트 구조를 갖는 박막 트랜지스터의 게이트 전극과 게이트 전극 사이의 저항값을 조절함으로써, TFT-LCD 평판 디스플레이의 픽셀어레이(pixel array)구동소자에 활용할 경우, 누설전류와 소자면적을 줄임으로써 개구율 향상이 필요로 하는 고정세, 고화질의 TFT-LCD 평판 디스플레이를 제조하는데 활용할 수 있다.As described above, according to the present invention, a pixel array of a TFT-LCD flat panel display is controlled by adjusting a resistance value between a gate electrode and a gate electrode of a thin film transistor having a double gate structure, a double channel structure, and a double gate structure. When used in the device, it can be used to manufacture high-definition, high-definition TFT-LCD flat panel display that needs to improve aperture ratio by reducing leakage current and device area.
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940036359A KR0155306B1 (en) | 1994-12-23 | 1994-12-23 | Thin film transistor with double gate and method thereof |
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| Country | Link |
|---|---|
| KR (1) | KR0155306B1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100541274B1 (en) * | 1998-10-23 | 2006-03-09 | 삼성전자주식회사 | Thin film transistor |
| US8803155B2 (en) | 2010-07-27 | 2014-08-12 | Samsung Display Co., Ltd. | Thin-film transistor sensor and method of manufacturing the TFT sensor |
| CN109962114A (en) * | 2019-04-17 | 2019-07-02 | 京东方科技集团股份有限公司 | Double grid TFT, pixel circuit and its control method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100532082B1 (en) * | 2001-12-28 | 2005-11-30 | 엘지.필립스 엘시디 주식회사 | An poly-crystalline thin film transistor and a method of fabricating thereof |
-
1994
- 1994-12-23 KR KR1019940036359A patent/KR0155306B1/en not_active IP Right Cessation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100541274B1 (en) * | 1998-10-23 | 2006-03-09 | 삼성전자주식회사 | Thin film transistor |
| US8803155B2 (en) | 2010-07-27 | 2014-08-12 | Samsung Display Co., Ltd. | Thin-film transistor sensor and method of manufacturing the TFT sensor |
| CN109962114A (en) * | 2019-04-17 | 2019-07-02 | 京东方科技集团股份有限公司 | Double grid TFT, pixel circuit and its control method |
| CN109962114B (en) * | 2019-04-17 | 2021-02-02 | 京东方科技集团股份有限公司 | Double-gate TFT, pixel circuit and control method thereof |
| US11475833B2 (en) * | 2019-04-17 | 2022-10-18 | Beijing Boe Technology Development Co., Ltd. | Semiconductor apparatus, pixel circuit and control method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960026968A (en) | 1996-07-22 |
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