JP2000269133A - Manufacture of thin film semiconductor device - Google Patents

Manufacture of thin film semiconductor device

Info

Publication number
JP2000269133A
JP2000269133A JP11070276A JP7027699A JP2000269133A JP 2000269133 A JP2000269133 A JP 2000269133A JP 11070276 A JP11070276 A JP 11070276A JP 7027699 A JP7027699 A JP 7027699A JP 2000269133 A JP2000269133 A JP 2000269133A
Authority
JP
Japan
Prior art keywords
film
silicon
semiconductor
wavelength
semiconductor film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11070276A
Other languages
Japanese (ja)
Inventor
Mitsutoshi Miyasaka
光敏 宮坂
Tetsuya Ogawa
哲也 小川
Hidetada Tokioka
秀忠 時岡
Yukio Sato
行雄 佐藤
Mitsuo Inoue
満夫 井上
Tomohiro Sasagawa
智広 笹川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Mitsubishi Electric Corp
Original Assignee
Seiko Epson Corp
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Mitsubishi Electric Corp filed Critical Seiko Epson Corp
Priority to JP11070276A priority Critical patent/JP2000269133A/en
Publication of JP2000269133A publication Critical patent/JP2000269133A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a homegeneous and high-quality crystalline semiconductor film by forming a silicon oxide film which will be a base protective film, on a substrate, and forming a semiconductor film mainly made of silicon on the base protective film, and then casting the pulse laser light having a wavelength within a specified range on the semiconductor film. SOLUTION: A silicon oxide film is deposited on a substrate 101 by a plasma chemical vapor phase deposition method to form a base protective film 102. On the base protective film 102, an intrinsic amorphous silicon film is deposited. Second higher harmonic waves of the pulse laser light having a wavelength between 370 nm and 710 nm which is pulse-oscilated is cast on the amorphous silicon film to melt and recrystallize it into a crystalline silicon film. The crystalline silicon film is patterned to form an island 103 of a semiconductor film. Then, the island 103 of the semiconductor film is coated by a silicon oxide film 104. Immediately before this, the oxygen plasma is cast to deposit an oxide film, which is formed into a gate electrode 105 by a sputtering method.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本願発明は600℃程度以
下、好ましくは425℃程度以下の比較的低温にて結晶
性が窮めて優れている多結晶性半導体膜を形成する技術
に関する。取り分けこの技術を用いて多結晶硅素薄膜ト
ランジスタに代表される薄膜半導体装置の性能を著しく
向上せしめる製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for forming a polycrystalline semiconductor film having excellent crystallinity at a relatively low temperature of about 600 ° C. or less, preferably about 425 ° C. or less. In particular, the present invention relates to a manufacturing method for significantly improving the performance of a thin film semiconductor device represented by a polycrystalline silicon thin film transistor by using this technique.

【0002】[0002]

【従来の技術】多結晶硅素薄膜トランジスタ(p−Si
TFT)に代表される薄膜半導体装置を汎用ガラス基
板を使用し得る600℃程度以下、或いは非晶質硅素薄
膜トランジスタ(a−Si TFT)の製造温度と同程
度の425℃程度以下の低温にて製造する場合、従来以
下の如き製造方法が取られて居た。まず基板上に半導体
膜と成る非晶質硅素膜を50nm程度の厚みに低圧化学
気相堆積法(LPCVD法)で堆積する。次に此の非晶
質膜にXeClエキシマレーザー(波長308nm)を
照射して多結晶硅素膜(p−Si膜)とする。XeCl
エキシマレーザー光の非晶質硅素と多結晶硅素中での吸
収係数は其々0.139nm−1と0.149nm−1
と大きい為、半導体膜に入射したレーザー光の9割は表
面から15nm以内で吸収される。又、非晶質硅素での
吸収係数の方が多結晶硅素での吸収係数よりも7%程小
さくなって居る。その後、ゲート絶縁膜と成る酸化硅素
膜を化学気相堆積法(CVD法)や物理気相堆積法(P
VD法)にて形成する。次にタンタル等でゲート電極を
作成して、金属(ゲート電極)−酸化膜(ゲート絶縁
膜)−半導体(多結晶硅素膜)から成る電界効果トラン
ジスタ(MOS−FET)を構成させる。最後に層間絶
縁膜を此等の膜上に堆積し、コンタクトホールを開孔し
た後に金属薄膜にて配線を施して、薄膜半導体装置が完
成する。
2. Description of the Related Art Polycrystalline silicon thin film transistors (p-Si
TFTs) are manufactured at a low temperature of about 600 ° C. or less, at which a general-purpose glass substrate can be used, or at a low temperature of about 425 ° C. or less, which is about the same as the manufacturing temperature of an amorphous silicon thin film transistor (a-Si TFT). In such a case, the following manufacturing method has conventionally been adopted. First, an amorphous silicon film serving as a semiconductor film is deposited on a substrate to a thickness of about 50 nm by low pressure chemical vapor deposition (LPCVD). Next, the amorphous film is irradiated with a XeCl excimer laser (wavelength 308 nm) to form a polycrystalline silicon film (p-Si film). XeCl
Absorption coefficient in amorphous silicon and polycrystalline silicon in the excimer laser light其s 0.139Nm -1 and 0.149nm -1
90% of the laser light incident on the semiconductor film is absorbed within 15 nm from the surface. Also, the absorption coefficient of amorphous silicon is about 7% smaller than that of polycrystalline silicon. Thereafter, a silicon oxide film serving as a gate insulating film is formed by chemical vapor deposition (CVD) or physical vapor deposition (PCVD).
VD method). Next, a gate electrode is made of tantalum or the like to form a field effect transistor (MOS-FET) composed of a metal (gate electrode) -oxide film (gate insulating film) -semiconductor (polycrystalline silicon film). Finally, an interlayer insulating film is deposited on these films, a contact hole is opened, and wiring is formed with a metal thin film, thereby completing a thin film semiconductor device.

【0003】[0003]

【発明が解決しようとする課題】しかしながら此等従来
の薄膜半導体装置の製造方法では、エキシマレーザー光
のエネルギー密度制御が困難で、僅かなエネルギー密度
の変動に依っても半導体膜質が同一基板内に於いてすら
大きなばらつきを示して居た。又、膜厚や水素含有量に
応じて定まる閾値よりも照射エネルギー密度が僅かに大
きく成った丈でも半導体膜には激しい損傷が入り、半導
体特性や製品歩留まりの著しい低下を招いて居た。斯う
した事から基板内で均質な多結晶半導体膜を得るには、
レーザー光のエネルギー密度を最適値よりも可成り低く
設定する必要が有り、それ故に良好な多結晶薄膜を得る
にはエネルギー密度の不足が否めなかった。又、最適な
エネルギー密度でレーザー照射を施しても、多結晶膜を
構成する結晶粒を大きくする事が困難で、膜中に多くの
欠陥を残留させているのが実状であった。斯くした事実
に則し、従来の製造方法にてp−Si TFT等の薄膜
半導体装置を安定的に製造するには、完成した薄膜半導
体装置の電気特性を犠牲にせざるを得ないとの課題を有
して居た。
However, in the conventional method of manufacturing a thin film semiconductor device, it is difficult to control the energy density of the excimer laser light, and the semiconductor film can be formed on the same substrate even by a slight change in the energy density. Even in this case, there was great variation. In addition, even when the irradiation energy density is slightly larger than the threshold determined according to the film thickness or the hydrogen content, the semiconductor film is severely damaged, and the semiconductor characteristics and the product yield are remarkably reduced. In order to obtain a homogeneous polycrystalline semiconductor film in the substrate from such a thing,
It was necessary to set the energy density of the laser beam to be considerably lower than the optimum value. Therefore, in order to obtain a good polycrystalline thin film, it was inevitable that the energy density was insufficient. Further, even if laser irradiation is performed at an optimum energy density, it is difficult to increase the crystal grains constituting the polycrystalline film, and in fact, many defects remain in the film. In accordance with such a fact, in order to stably manufacture a thin film semiconductor device such as a p-Si TFT by a conventional manufacturing method, there is a problem that the electric characteristics of a completed thin film semiconductor device must be sacrificed. Had it.

【0004】そこで本発明は上述の諸事情を鑑み、その
目的とする所は600℃程度以下、理想的には425℃
程度以下との低温工程にて優良な薄膜半導体装置を安定
的に製造する方法を提供する事に有る。
Accordingly, the present invention has been made in view of the above-mentioned circumstances and aims at a temperature of about 600 ° C. or less, ideally 425 ° C.
It is an object of the present invention to provide a method for stably manufacturing an excellent thin film semiconductor device in a low-temperature process at a temperature lower than the order.

【0005】[0005]

【課題を解決するための手段】本発明は基板上に形成さ
れた硅素(Si)を主体とする結晶性半導体膜を能動層
として用いて居る薄膜半導体装置の製造方法に於いて、
基板上に下地保護膜と成る酸化硅素膜を形成する下地保
護膜形成工程と、此の下地保護膜上に硅素(Si)を主
体とした半導体膜を形成する第一工程と、半導体膜に3
70nm以上710nm以下の波長を有するパルスレー
ザー光を照射する第二工程とを含む事を特徴とする。そ
の際にパルスレーザー光の波長をλ(nm)とし、半導
体膜の膜厚をd(nm)とすると、波長λが440nm
以上710nm以下の場合、波長λと膜厚dとは 9.8×10αL2(λ−440)<d<53×10
αH2(λ−440) 但し、αL2=4.9×10−3 nm−1 αH2=5.4×10−3 nm−1 との関係式を満たして居るのが好ましい。更に、膜厚d
と波長λとが 9.8×10αL2(λ−440)<d<32×10
αM2(λ−440) 但し、αL2=4.9×10−3 nm−1 αM2=5.2×10−3 nm−1 との関係式を満たして居ればより好ましい。此の様なパ
ルスレーザー光として最も優れて居るのがNd:YAG
レーザー光の第二高調波(YAG2ωと略称する。その
波長は532nm)で有る。又、波長λが370nm以
上440nm以下の場合には、波長λと膜厚dとは 2.4×10αL1(λ−370)<d<11.2×1
αH1(λ−370) 但し、αL1=8.7×10−3 nm−1 αH1=9.6×10−3 nm−1 との関係式を満たして居るのが望ましい。より好ましく
は、波長λと膜厚dとが 2.4×10αL1(λ−370)<d<6.0×10
αM1(λ−370) 但し、αL1=8.7×10−3 nm−1 αM1=1.04×10−2 nm−1 との関係式を満たして居る事である。パルスレーザー光
のより好ましい波長は450nm程度以上650nm程
度以下で有り、理想的には約532nmである。
SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a thin film semiconductor device using a crystalline semiconductor film mainly composed of silicon (Si) formed on a substrate as an active layer.
A base protection film forming step of forming a silicon oxide film serving as a base protection film on the substrate; a first step of forming a semiconductor film mainly containing silicon (Si) on the base protection film;
A second step of irradiating a pulsed laser beam having a wavelength of 70 nm or more and 710 nm or less. At this time, if the wavelength of the pulse laser beam is λ (nm) and the thickness of the semiconductor film is d (nm), the wavelength λ is 440 nm.
In the case where the wavelength is not less than 710 nm, the wavelength λ and the film thickness d are 9.8 × 10 αL2 (λ-440) <d <53 × 10
αH2 (λ-440) However, it is preferable that the relational expression of αL2 = 4.9 × 10 −3 nm −1 and αH2 = 5.4 × 10 −3 nm −1 be satisfied. Further, the film thickness d
And λ are 9.8 × 10 αL2 (λ-440) <d <32 × 10
αM2 (λ-440) However, it is more preferable to satisfy the relational expression of αL2 = 4.9 × 10 −3 nm −1 and αM2 = 5.2 × 10 −3 nm −1 . Nd: YAG is the most excellent type of pulsed laser light.
It is the second harmonic of laser light (abbreviated as YAG2ω; its wavelength is 532 nm). When the wavelength λ is 370 nm or more and 440 nm or less, the wavelength λ and the film thickness d are 2.4 × 10 αL1 (λ-370) <d <11.2 × 1
0 αH1 (λ-370) where αL1 = 8.7 × 10 −3 nm −1 It is desirable that the relational expression of αH1 = 9.6 × 10 −3 nm −1 be satisfied. More preferably, the wavelength λ and the film thickness d are 2.4 × 10 αL1 (λ-370) <d <6.0 × 10
αM1 (λ-370) where αL1 = 8.7 × 10 −3 nm −1 αM1 = 1.04 × 10 −2 nm −1 . The more preferable wavelength of the pulse laser beam is about 450 nm or more and about 650 nm or less, and ideally about 532 nm.

【0006】パルスレーザー光は固体発光素子にて形成
されるのが望ましく、取り分けNd:YAGレーザー光
の第2高調波が適して居る。優良な薄膜半導体装置を製
造するには、パルスレーザー光が半導体膜に照射された
際の、半導体膜上に於けるレーザー光の照射エネルギー
密度の変動は、其の平均値に対して5%程度未満で有る
事が求められる。
It is desirable that the pulse laser light is formed by a solid-state light emitting element, and the second harmonic of Nd: YAG laser light is suitable. In order to manufacture an excellent thin film semiconductor device, when the pulsed laser light is irradiated on the semiconductor film, the fluctuation of the irradiation energy density of the laser light on the semiconductor film is about 5% of its average value. It is required to be less than.

【0007】[0007]

【発明の実施の形態】本発明はガラスの歪点温度が55
0℃程度から650℃程度と云った低耐熱性ガラス基
板、或いは高耐熱性プラスティック基板等の各種透明基
板上に形成された結晶性の半導体膜を能動層として用い
て居る薄膜半導体装置の製造方法に関わり、基板上に下
地保護膜と成る酸化硅素膜を形成する下地保護膜形成工
程と、此の下地保護膜上に硅素(Si)を主体とした半
導体膜を形成する第一工程と、斯様に形成された半導体
膜にパルスレーザー光を照射する第二工程とを含み、更
に先のパルスレーザー光の波長λが370nm以上71
0nm以下で有る事を以て其の特徴と成す。斯様なパル
スレーザー光の内でも、パルスレーザー光の多結晶硅素
中での吸収係数μpSiが10−3nm−1以上10
−2nm−1以下の場合がより好ましい。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a glass having a strain point temperature of 55.
Method for manufacturing thin-film semiconductor device using crystalline semiconductor film formed on various transparent substrates such as low heat-resistant glass substrate at about 0 ° C. to 650 ° C. or high heat-resistant plastic substrate as active layer And an underlying protective film forming step of forming a silicon oxide film serving as an underlying protective film on the substrate; a first step of forming a silicon (Si) -based semiconductor film on the underlying protective film; Irradiating a pulsed laser beam to the semiconductor film formed in the same manner as above.
The feature is achieved by being less than 0 nm. Among such pulse laser beams, the absorption coefficient μ pSi of the pulse laser beam in polycrystalline silicon is not less than 10 −3 nm −1 and not more than 10 −10 nm.
-2 nm -1 or less is more preferable.

【0008】第一工程では下地保護膜上に硅素(Si)
を主体とした半導体膜を形成する。半導体膜としては硅
素膜(Si)や硅素ゲルマニウム膜(Si
1−x:0<x<1)に代表される半導体物質が使用
され、硅素をその主構成元素(硅素原子構成比が80%
程度以上)とする。基板は液晶表示装置に用いられる透
明無アルカリガラス、或いはプラスティックやセラミッ
ク等の絶縁性基板が用いられるのが通常だが、基板の耐
熱性が550℃程度以上有れば、其の種類に囚われな
い。此等の基板の表面には半導体膜に対する下地保護膜
として、酸化硅素膜が100nm程度から10μm程度
堆積されて居る。下地保護膜としての酸化硅素膜は単に
半導体膜と基板との電気的絶縁性を取ったり、或いは基
板が含有する不純物の半導体膜への拡散混入を防ぐにの
みならず、下地酸化膜と結晶性半導体膜との界面を良質
な物とする。本願発明では、薄膜半導体装置の半導体膜
は10nm程度から200nm程度の厚みを有し、半導
体膜の膜厚方向全域に渡ってエネルギーバンドが曲がっ
て居る場合(SOIの完全空乏化モデルに相当する)が
主たる対象とされる。斯様な状況下ではゲート絶縁膜と
半導体膜との界面と共に、下地保護膜と半導体膜との界
面も電気伝導に無視出来ぬ関与を及ぼす。酸化硅素膜は
半導体膜と界面を成す際に界面捕獲準位を最も低減し得
る物質で有るから下地保護膜として適している訳で有
る。半導体膜は此の下地保護膜上に形成される。従って
下地保護膜としては半導体膜との界面に1012cm
−2程度以下の界面準位を有する酸化硅素膜の使用が本
願では望まれる。更に本発明では、従来技術に比べて半
導体膜の下部も高温に加熱される傾向が強い為に、基板
からの不純物拡散が生じ易い。此を防ぎ、高純度の半導
体膜を用いて優良なる薄膜半導体装置を本願発明にて作
成するには、密度の高い稠密な酸化硅素膜を下地保護膜
として使用するのが不可欠である。この様な酸化硅素膜
は、液温が25ア5℃で濃度が1.6ア0.2%の沸化水
素(HF)酸水溶液に於けるエッチング速度が1.5n
m/s以下となる物である。通常、下地保護膜はプラズ
マ化学気相堆積法(PECVD法)や低圧化学気相堆積
法(LPCVD法)、スパッター法と云った気相堆積法
で形成される。此等の内でも、特に本願発明に適した下
地保護膜を作成するには、PECVD法の中でも電子サ
イクロトロン共鳴PECVD法(ECR−PECVD
法)やヘリコンPECVD法、リモートPECVD法を
利用する事が好ましい。又、工業用周波数(13.56
MHz)や其の整数倍の周波数を用いた汎用のPECV
D法にて本願発明に適した酸化硅素膜を得るには、原料
物質としてTEOS(Si−(O−CHCH
と酸素(O)を使用し、酸素流量をTEOS流量の5
倍以上に設定して酸化硅素膜を堆積すれば良い。或いは
原料物質としてモノシラン(SiH)と亜酸化窒素
(NO)とを用い、希釈気体としてヘリウム(He)
乃至はアルゴン(Ar)と云った希ガスを用いて、総気
体流量中の希ガスの割合を90%程度以上(即ち総気体
流量中の原料物質の割合を10%程度未満)として酸化
硅素膜を堆積すれば良い。その際に基板温度は280℃
以上であることが望まれる。基板が高純度の石英から成
る時には下地保護膜と石英基板とが兼用される事も可能
で有るが、表面状態を常に一定として半導体膜品質の変
動を最小とするには、上述の方法にて下地保護膜を形成
するのが好ましい。
In the first step, silicon (Si) is formed on the underlying protective film.
A semiconductor film mainly composed of is formed. Silicon film (Si) or silicon germanium film as a semiconductor film (Si x G
e 1−x : A semiconductor material represented by 0 <x <1 is used, and silicon is used as a main constituent element (silicon atomic composition ratio is 80%).
Degree or more). As the substrate, a transparent non-alkali glass used for a liquid crystal display device, or an insulating substrate such as plastic or ceramic is usually used. However, as long as the substrate has a heat resistance of about 550 ° C. or more, the type is not limited. On the surfaces of these substrates, a silicon oxide film is deposited as a base protective film for the semiconductor film on the order of 100 nm to 10 μm. The silicon oxide film as a base protective film not only provides electrical insulation between the semiconductor film and the substrate, or prevents diffusion of impurities contained in the substrate into the semiconductor film, but also prevents the base oxide film from being crystalline. The interface with the semiconductor film is made of good quality. In the present invention, the semiconductor film of the thin-film semiconductor device has a thickness of about 10 nm to about 200 nm, and the energy band is bent over the entire region in the thickness direction of the semiconductor film (corresponding to a fully depleted SOI model). Is the main target. In such a situation, the interface between the underlying protective film and the semiconductor film, as well as the interface between the gate insulating film and the semiconductor film, has a considerable effect on electric conduction. Since a silicon oxide film is a substance that can reduce the interface trap level when forming an interface with a semiconductor film, it is suitable as a base protective film. The semiconductor film is formed on the underlying protective film. Therefore, as a base protective film, an interface with the semiconductor film is 10 12 cm.
It is desired in the present application to use a silicon oxide film having an interface state of about -2 or less. Further, in the present invention, the lower part of the semiconductor film is more likely to be heated to a high temperature than in the prior art, so that impurity diffusion from the substrate easily occurs. In order to prevent this and to produce an excellent thin film semiconductor device using a high-purity semiconductor film in the present invention, it is essential to use a dense silicon oxide film having a high density as a base protective film. Such a silicon oxide film has an etching rate of 1.5 n in an aqueous solution of hydrofluoric acid (HF) having a liquid temperature of 25 to 5 ° C. and a concentration of 1.6 to 0.2%.
m / s or less. Usually, the underlayer protective film is formed by a vapor deposition method such as a plasma enhanced chemical vapor deposition (PECVD), a low pressure chemical vapor deposition (LPCVD), or a sputtering method. Among them, in order to prepare a base protective film particularly suitable for the present invention, among the PECVD methods, an electron cyclotron resonance PECVD method (ECR-PECVD) is used.
Method), a helicon PECVD method, or a remote PECVD method. Also, the industrial frequency (13.56
MHz) or a general-purpose PECV using an integer multiple of that frequency
To obtain a silicon oxide film suitable for the present invention by the D method, TEOS as a raw material (Si- (O-CH 2 CH 3) 4)
And oxygen (O 2 ), and the oxygen flow rate was set at 5 times the TEOS flow rate.
It is sufficient to deposit the silicon oxide film by setting it to twice or more. Alternatively, monosilane (SiH 4 ) and nitrous oxide (N 2 O) are used as raw materials, and helium (He) is used as a diluent gas.
Alternatively, using a rare gas such as argon (Ar), the proportion of the rare gas in the total gas flow is about 90% or more (that is, the proportion of the raw material in the total gas flow is less than about 10%), and the silicon oxide film is used. Should be deposited. At that time, the substrate temperature was 280 ° C.
It is hoped that this is the case. When the substrate is made of high-purity quartz, the underlying protective film and the quartz substrate can be used in combination. It is preferable to form a base protective film.

【0009】下地保護膜上に非晶質状態又は多結晶状態
に有る半導体膜が化学気相堆積法(CVD法)で、好ま
しくは高次シラン(Si2n+2:n=2,3,
4)を原料気体の一種として用いて、堆積形成される。
半導体膜堆積にはプラズマ化学気相堆積法(PECVD
法)や低圧化学気相堆積法(LPCVD法)、常圧化学
気相堆積法(APCVD法)、スパッター法と云った各
種気相堆積法が可能で有るが、高純度の半導体膜が容易
に堆積されるとの立場からは、其の内でも特に低圧化学
気相堆積法(LPCVD法)が適して居る。低圧化学気
相堆積法は高真空型低圧化学気相堆積装置にて行われ
る。此は半導体膜の純度を高める事と、不純物に起因す
る結晶核の発生を最小として、本願発明で最終的に得ら
れる結晶性半導体膜を高純度で且つ大きな結晶粒から構
成される様にする為で有る。取り分け本願発明では、第
二工程にて半導体膜を厚み方向で比較的均一に加熱して
横方向への結晶成長を促進させるので、不純物に起因す
る結晶核の発生を最小とするならば、大きな結晶粒から
成る多結晶半導体薄膜を容易に得る事が可能となる。高
真空型とは半導体膜堆積直前の成膜室に於ける背景真空
度が5ラ10−7Torr程度以下とし得る装置で有
る。斯様な高真空型低圧化学気相堆積装置は単に成膜室
の気密性が優れて居るにのみならず、成膜室に於ける排
気速度が100sccm/mTorr(不活性ガスを1
00sccm成膜室に流した時に得られる平衡圧力が1
mTorrと成る排気速度)程度以上の排気能力を有し
て居る事が更に望まれる。斯うした高排気能力を有する
装置では1時間程度との比較的短時間で、基板等からの
脱ガス流量を充分に低減せしめ、生産性を高く保って
尚、高純度半導体薄膜の堆積を可能とするからで有る。
A semiconductor film in an amorphous state or a polycrystalline state is formed on a base protective film by a chemical vapor deposition method (CVD method), preferably a higher order silane (Si n H 2n + 2 : n = 2,3,3).
4) is used as a source gas to form a deposit.
Plasma chemical vapor deposition (PECVD) is used for semiconductor film deposition.
), Low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), and sputtering, but various types of vapor deposition are possible. From the standpoint of deposition, low pressure chemical vapor deposition (LPCVD) is particularly suitable. The low pressure chemical vapor deposition method is performed in a high vacuum type low pressure chemical vapor deposition apparatus. This is to increase the purity of the semiconductor film and minimize the generation of crystal nuclei due to impurities so that the crystalline semiconductor film finally obtained by the present invention is composed of high purity and large crystal grains. It is for the purpose. In particular, in the present invention, since the semiconductor film is relatively uniformly heated in the thickness direction in the second step to promote the crystal growth in the lateral direction, the generation of crystal nuclei due to impurities is minimized. A polycrystalline semiconductor thin film composed of crystal grains can be easily obtained. The high-vacuum type is an apparatus in which the degree of background vacuum in a film forming chamber immediately before semiconductor film deposition can be reduced to about 5 × 10 −7 Torr or less. Such a high-vacuum type low-pressure chemical vapor deposition apparatus not only has excellent airtightness in the film forming chamber, but also has a pumping speed in the film forming chamber of 100 sccm / mTorr (inert gas of 1 inert gas).
The equilibrium pressure obtained when flowing into the 00 sccm deposition chamber is 1
It is further desired to have a pumping capacity of at least about (a pumping speed of mTorr). In such a device having a high pumping capacity, the degas flow rate from the substrate or the like can be sufficiently reduced in a relatively short time of about one hour, and high-purity semiconductor thin film can be deposited while maintaining high productivity. Because it is.

【0010】非晶質硅素膜に代表される硅素を主体とす
る半導体膜は高次シラン(Si2n+2:nは2以
上の整数)を原料気体の一種として堆積されるのが好ま
しい。価格や安全性を考慮すると高次シランとしてはジ
シラン(Si)が最も適している。ジシランを低
圧化学気相堆積法に適応すると、425℃程度以下の低
温にて高純度の非晶質硅素膜を0.5nm/min程度
以上との比較的速い堆積速度にて得ることが出来る。本
願発明に適した良質な非晶質半導体膜を得るには、堆積
温度と堆積速度の制御が重要となる。堆積温度は430
℃程度以下で、且つ堆積速度が0.6nm/min程度
以上と成る様にジシラン流量や成膜時の圧力を定める必
要がある。
It is preferable that a semiconductor film mainly composed of silicon typified by an amorphous silicon film is deposited using high order silane (Si n H 2n + 2 : n is an integer of 2 or more) as a kind of source gas. In consideration of price and safety, disilane (Si 2 H 6 ) is most suitable as the higher order silane. When disilane is applied to low-pressure chemical vapor deposition, a high-purity amorphous silicon film can be obtained at a relatively low deposition rate of about 0.5 nm / min or more at a low temperature of about 425 ° C. or less. In order to obtain a high-quality amorphous semiconductor film suitable for the present invention, it is important to control the deposition temperature and the deposition rate. Deposition temperature is 430
It is necessary to determine the flow rate of disilane and the pressure at the time of film formation so that the temperature is about not higher than about ° C and the deposition rate is about 0.6 nm / min or more.

【0011】基板面積が2000cm程度以上有る大
型基板を用いる場合には、LPCVD法の使用が困難と
化す。其の様な状況下では、プラズマボックス型のPE
CVD装置にて半導体膜を堆積する。プラズマボックス
型のPECVD装置は、プラズマ処理を行う成膜室が其
れよりも大きな別の真空の部屋内に設置されて居るの
で、成膜室内の背景真空度を1ラ10−6Torr程度
以下とし得る。背景真空度は高真空型LPCVD装置に
劣るものの、半導体膜の堆積速度を3nm/min程度
以上と大きく出来るので、結果として不純物に起因する
結晶核の発生を最少とする高純度の半導体膜が得られ
る。PECVD法を本願発明に適応するには、成膜室内
の背景真空度を1ラ10−6Torr程度以下として、
且つ半導体膜の堆積速度を3nm/min程度以上とな
る条件にて半導体膜を堆積する。非晶質膜堆積時の基板
温度は350℃程度から450℃程度の間である。35
0℃程度よりも温度が高ければ非晶質膜中に含有される
水素量を8%程度以下と低減出来、第二工程の結晶化を
安定的に行うことが可能と成る。450℃程度よりも低
ければ非晶質膜を構成する非晶質粒が大きく成り、此の
非晶質膜を結晶化した際に得られる多結晶膜を構成する
結晶粒が大きく成る。第二工程に於けるレーザー結晶化
を安定的に進めるには非晶質半導体膜内の水素量を好ま
しくは硅素に対して5%程度未満とする。此の様に水素
含有量の少ない硅素膜は堆積速度を25nm/min以
下として成膜する。PECVD法を適応する場合には原
料気体としてジシランの他にモノシランを使用出来る。
When a large substrate having a substrate area of about 2000 cm 2 or more is used, it becomes difficult to use the LPCVD method. Under such circumstances, the plasma box type PE
A semiconductor film is deposited by a CVD device. In a plasma-box-type PECVD apparatus, a film formation chamber for performing a plasma treatment is installed in another vacuum chamber larger than the chamber, so that the background vacuum degree in the film formation chamber is not more than about 1 × 10 −6 Torr. And Although the degree of background vacuum is inferior to that of a high-vacuum LPCVD apparatus, the deposition rate of the semiconductor film can be increased to about 3 nm / min or more. As a result, a high-purity semiconductor film in which generation of crystal nuclei due to impurities is minimized is obtained. Can be PECVD method to adapt to the present invention, the background vacuum degree in the deposition chamber as more than about 1 la 10 -6 Torr,
In addition, the semiconductor film is deposited under the condition that the deposition rate of the semiconductor film is about 3 nm / min or more. The substrate temperature during the deposition of the amorphous film is between about 350 ° C. and 450 ° C. 35
If the temperature is higher than about 0 ° C., the amount of hydrogen contained in the amorphous film can be reduced to about 8% or less, and the crystallization in the second step can be performed stably. If the temperature is lower than about 450 ° C., the amorphous grains constituting the amorphous film become large, and the crystal grains constituting the polycrystalline film obtained when the amorphous film is crystallized become large. To stably promote laser crystallization in the second step, the amount of hydrogen in the amorphous semiconductor film is preferably set to less than about 5% with respect to silicon. Such a silicon film having a small hydrogen content is formed at a deposition rate of 25 nm / min or less. When the PECVD method is applied, monosilane can be used as a raw material gas in addition to disilane.

【0012】この様にして非晶質半導体膜又は多結晶半
導体膜が得られた後に、第二工程として此等半導体膜に
パルスレーザー光を照射して非晶質半導体膜の結晶化、
乃至は多結晶半導体膜の再結晶化を進める。レーザー光
としては連続発振の物も使用可能で有るが、パルス発振
のレーザー光の使用がより好ましい。其れは後述する様
に、本願発明は結晶の横成長を促進し、其の場合には連
続発振よりは、一回の照射毎に適当な距離を移動し得る
パルス発振の方が大きな結晶粒から成る多結晶半導体薄
膜が確実に得易いからで有る。半導体膜にレーザー光を
照射する際には波長λが370nm以上710nm以下
のパルスレーザー光を使用する。此等の光の非晶質硅素
中及び多結晶硅素中での吸収係数を図1に示す。図1の
横軸は光の波長で、縦軸が吸収係数である。破線(Amorp
hous Silicon)が非晶質硅素を表し、実線(Polysilicon)
は多結晶硅素を表して居る。図1から分かる様に、37
0nmから710nmの波長領域では光の吸収係数は多
結晶硅素中よりも非晶質硅素中での方が大きくなる。例
えば波長が532nmで有るYAG2ω光の非晶質硅素
での吸収係数μaSiと多結晶硅素での吸収係数μ
pSiは其々、 μaSi(YAG2ω)=0.01723nm−1 μpSi(YAG2ω)=0.00426nm−1 と、非晶質硅素での吸収係数の方が多結晶硅素での吸収
係数よりも4倍余りも大きく成って居る。多結晶膜は微
視的には結晶成分と非晶質成分とから構成されて居る。
結晶成分とは結晶粒内で積層欠陥等の欠陥が非常に少な
い部位で、略単結晶状態に有る箇所と言える。一方、非
晶質成分とは結晶粒界や結晶粒内の欠陥部等の構造秩序
に乱れが見られる部位で、所謂非晶質状態に有る箇所と
言える。レーザー光を照射して結晶化を進めるとの溶融
結晶化では、非溶融部が冷却固化過程に於ける結晶成長
の核と成る。高い構造秩序を有する結晶成分が結晶成長
核と成れば、其処から成長する結晶は矢張り高い構造秩
序を有する良質な結晶化膜と成る。此に反して、構造秩
序の乱れた部位が結晶成長核と成れば、積層欠陥等が冷
却固化過程に其処から成長するので、最終的に得られる
結晶化膜は欠陥等を含んだ低品質な物と化す。従って優
良な結晶化膜を得るには、多結晶膜中の結晶成分を溶融
させずに此を結晶成長の核とし、非晶質成分を優先的に
溶融させれば良い事に成る。本願発明では、照射レーザ
ー光の非晶質硅素に於ける吸収係数が多結晶硅素に於け
る吸収係数よりも大きいので、非晶質成分が結晶成分に
比べて優先的に加熱される。具体的には、結晶粒界や欠
陥部が容易に溶融し、略単結晶状態に有る良質な結晶成
分が結晶成長核と成るので、欠陥部や不対結合対等が大
幅に低減し、粒界も構造秩序の高い対応粒界が支配的と
成る。此の事は半導体膜の電気特性からすると、エネル
ギーバンド図に於ける禁制帯中央部付近の捕獲準位密度
を大きく減少させるとの効果をもたらす。又、斯様な半
導体膜を薄膜半導体装置の能動層(ソース領域やドレイ
ン領域、チャンネル形成領域)に用いると、オフ電流値
が小さく、急峻な閾値下特性を示し(サブスレーシュホ
ールドスィング値が小さく)、閾値電圧の低いトランジ
スタを得る事に成る。従来技術で此の様な優れた薄膜半
導体装置がなかなか製造出来なかったのは、溶融結晶化
に適した波長を有するレーザー光を使用しておらず、結
晶成分も非晶質成分をも一緒に溶融させて居た為と云え
よう。此処に述べた本願発明の原理が最も効果的に働く
のは、多結晶硅素での吸収係数の非晶質硅素での吸収係
数に対する比(μpSi/μaSi)が大きい時で有
る。図1を見ると、光の波長が450nm程度から65
0nm程度の時に先の比が大きく成る事が分かる。従っ
て本願発明の第二工程にて照射するパルスレーザー光の
最も好ましい波長は450nm程度以上650nm程度
以下と云える。波長が450nmの光の多結晶硅素中で
の吸収係数μpSiは1.127×10−2nm
−1で、波長が650nmの光の多結晶硅素中での吸収
係数μpSiは8.9×10−4nm−1で有る。従っ
て波長が450nm程度以上650nm程度以下のパル
スレーザー光を照射するとの第二工程は、パルスレーザ
ー光として多結晶硅素中での吸収係数μpSiが大凡1
−3nm−1以上10−2nm−1以下となる物を用
いて居る事になる。
After the amorphous semiconductor film or the polycrystalline semiconductor film is thus obtained, the semiconductor film is irradiated with a pulsed laser beam as a second step to crystallize the amorphous semiconductor film.
Alternatively, recrystallization of the polycrystalline semiconductor film is advanced. A continuous wave laser beam can be used as the laser beam, but a pulsed laser beam is more preferably used. That is, as will be described later, the present invention promotes the lateral growth of the crystal. In this case, the pulse oscillation that can move an appropriate distance for each irradiation is larger than the continuous oscillation, This is because a polycrystalline semiconductor thin film made of When the semiconductor film is irradiated with laser light, pulse laser light having a wavelength λ of 370 nm or more and 710 nm or less is used. FIG. 1 shows the absorption coefficients of these lights in amorphous silicon and polycrystalline silicon. The horizontal axis in FIG. 1 is the wavelength of light, and the vertical axis is the absorption coefficient. Dashed line (Amorp
hous Silicon) represents amorphous silicon, solid line (Polysilicon)
Represents polycrystalline silicon. As can be seen from FIG.
In the wavelength range from 0 nm to 710 nm, the light absorption coefficient is larger in amorphous silicon than in polycrystalline silicon. For example, the absorption coefficient μ aSi of YAG2ω light having a wavelength of 532 nm in amorphous silicon and the absorption coefficient μ of polycrystalline silicon
Each of pSi has μ aSi (YAG2ω) = 0.01723 nm −1 μpSi (YAG2ω) = 0.00426 nm −1, which means that the absorption coefficient of amorphous silicon is 4 times higher than that of polycrystalline silicon. More than twice as large. The polycrystalline film is microscopically composed of a crystalline component and an amorphous component.
A crystal component is a portion in a crystal grain where defects such as stacking faults are extremely small, and can be said to be a portion in a substantially single crystal state. On the other hand, the amorphous component is a portion where the structural order is disturbed, such as a crystal grain boundary or a defect portion in the crystal grain, and can be said to be a portion in a so-called amorphous state. In melt crystallization in which crystallization is promoted by irradiating a laser beam, a non-melted portion serves as a nucleus for crystal growth in a cooling and solidifying process. When a crystal component having a high structural order becomes a crystal growth nucleus, a crystal grown therefrom becomes a high-quality crystallized film having a high structural order. On the other hand, if the disordered structural order becomes the crystal growth nucleus, stacking faults etc. will grow from there during the cooling and solidification process, and the finally obtained crystallized film will have low quality including defects etc. It becomes something. Therefore, in order to obtain an excellent crystallized film, it is only necessary to melt the amorphous component preferentially without using the crystal component in the polycrystalline film as a nucleus for crystal growth. In the present invention, since the absorption coefficient of the irradiation laser light in amorphous silicon is larger than the absorption coefficient in polycrystalline silicon, the amorphous component is heated preferentially over the crystalline component. Specifically, the crystal grain boundaries and defect portions are easily melted, and a high-quality crystal component in a substantially single crystal state serves as a crystal growth nucleus. Also, corresponding grain boundaries with high structural order are dominant. This has the effect of significantly reducing the trap level density near the center of the forbidden band in the energy band diagram in view of the electrical characteristics of the semiconductor film. Further, when such a semiconductor film is used as an active layer (source region, drain region, channel formation region) of a thin film semiconductor device, the off-state current value is small, and a sharp sub-threshold characteristic is exhibited (the sub-threshold hold swing value is reduced). (Small) transistor having a low threshold voltage. The reason that such an excellent thin film semiconductor device could not be easily manufactured by the conventional technology is that laser light having a wavelength suitable for melt crystallization is not used, and both the crystalline component and the amorphous component are used together. It can be said that it had been melted. The principle of the present invention described here works most effectively when the ratio (μ pSi / μ aSi ) of the absorption coefficient of polycrystalline silicon to the absorption coefficient of amorphous silicon is large. Referring to FIG. 1, the wavelength of light is about 450 nm to 65 nm.
It can be seen that the above ratio becomes large at about 0 nm. Therefore, it can be said that the most preferable wavelength of the pulsed laser beam irradiated in the second step of the present invention is from about 450 nm to about 650 nm. The absorption coefficient μ pSi of light having a wavelength of 450 nm in polycrystalline silicon is 1.127 × 10 −2 nm.
−1 , the absorption coefficient μ pSi of light having a wavelength of 650 nm in polycrystalline silicon is 8.9 × 10 −4 nm −1 . Therefore, in the second step of irradiating a pulse laser beam having a wavelength of about 450 nm or more and about 650 nm or less, the absorption coefficient μ pSi in polycrystalline silicon is approximately 1 as the pulse laser light.
An object having a size of from 0 −3 nm −1 to 10 −2 nm −1 is used.

【0013】良質な多結晶半導体膜を得るにはレーザー
光の発振安定性が最も重要なので、パルスレーザー光は
固体発光素子にて形成されるのが望ましい。(本願では
此を固体レーザーと略称する。)従来のエキシマガスレ
ーザーでは、レーザー発振室内でのキセノン(Xe)や
塩素(Cl)などのガスの不均一性や、ガス自体の劣化
或いはハロゲンに依る発振室内の腐食等に起因して、発
振強度のばらつきが5%程有り、更に発振角のばらつき
も5%程度認められた。発振角のばらつきは照射領域面
積のばらつきをもたらすので、結果として半導体膜表面
でのエネルギー密度(単位面積あたりのエネルギー値)
は総計で10%以上も変動して居り、此が優良なる薄膜
半導体装置を製造する上での一つの阻害要因となってい
た。又、レーザー発振の長期安定性にも欠け、薄膜半導
体装置のロット間変動をもたらしていた。此に対して固
体レーザーには斯様な問題が存在し得ぬが故、レーザー
発振は窮めて安定で、半導体膜表面でのエネルギー密度
の変動を其の平均値に対して5%程度未満とし得るので
有る。本願発明をより効果的に実用するには、この様に
半導体膜表面でのレーザーエネルギー密度の変動が5%
程度未満となる固体レーザーの使用が求められる。更
に、固体レーザーの使用は薄膜半導体装置製造時に於け
るロット間変動を最小化するとの効果や、従来頻繁に行
われて居た煩雑なガス交換作業から薄膜半導体装置の製
造を解放し、以て薄膜半導体装置を製造する際の生産性
の向上や低価格化を導くとの効果を有する。先の波長や
吸収係数の要請と固体レーザーの要請とを同時に満たし
得るのがNd:YAGレーザー光の第二高調波(YAG
2ω光、波長532nm)である。従って、本願発明の
第二工程ではエネルギー密度の変動が平均値に対して5
%程度未満となるYAG2ω光を半導体膜に照射するの
が最も適している。
In order to obtain a high-quality polycrystalline semiconductor film, oscillation stability of laser light is the most important. Therefore, it is desirable that pulsed laser light is formed by a solid-state light emitting device. (In the present application, this is abbreviated as a solid-state laser.) In a conventional excimer gas laser, it depends on non-uniformity of gas such as xenon (Xe) or chlorine (Cl) in a laser oscillation chamber, deterioration of gas itself or halogen. Due to corrosion in the oscillation chamber and the like, the variation in oscillation intensity was about 5%, and the variation in oscillation angle was also about 5%. Variations in the oscillation angle lead to variations in the area of the irradiation region, and as a result, the energy density on the semiconductor film surface (energy value per unit area)
Fluctuated by more than 10% in total, which was one of the hindrance factors in manufacturing an excellent thin film semiconductor device. Further, the laser oscillation lacks long-term stability, causing lot-to-lot variation of thin film semiconductor devices. On the other hand, since such a problem cannot exist in the solid-state laser, the laser oscillation is extremely stable, and the fluctuation of the energy density on the surface of the semiconductor film is less than about 5% of its average value. It is possible. In order to more effectively use the present invention, the fluctuation of the laser energy density on the surface of the semiconductor film is 5%.
It is required to use a solid-state laser that is less than the degree. Furthermore, the use of solid-state lasers has the effect of minimizing lot-to-lot variations during thin-film semiconductor device manufacturing, and frees the production of thin-film semiconductor devices from the cumbersome gas exchange work that has been frequently performed in the past. This has the effect of leading to an improvement in productivity and a reduction in price when manufacturing a thin film semiconductor device. The requirement of the wavelength and the absorption coefficient and the requirement of the solid-state laser can be simultaneously satisfied by the second harmonic (YAG) of the Nd: YAG laser light.
2ω light, wavelength 532 nm). Therefore, in the second step of the present invention, the fluctuation of the energy density is 5% of the average value.
It is most suitable to irradiate the semiconductor film with YAG2ω light of less than about%.

【0014】さて、半導体膜中では光は吸収され、入射
光は指数関数的に其の強度を減衰させる。今、入射光強
度をI(0)とし、硅素を主体とした多結晶半導体膜中
での表面からの距離をx(nm)、場所xでの強度をI
(x)とすると、此等の間には吸収係数μpSiを用い
て次の関係が成り立つ。
Now, light is absorbed in the semiconductor film, and the intensity of the incident light is attenuated exponentially. Now, let the incident light intensity be I (0) , the distance from the surface in the silicon-based polycrystalline semiconductor film be x (nm), and the intensity at location x be I (0).
Assuming (x) , the following relationship is established between them using the absorption coefficient μ pSi .

【0015】 I(x)/I(0)=exp(−μpSi・x) (式1) 吸収係数μpSiが10−3nm−1の場合と10−2
nm−1の場合、及び本願発明のパルスレーザー光とし
て最も優れているNd:YAGレーザー光の第二高調波
(YAG2ω光)の場合と、従来技術のXeClエキシ
マレーザー光の場合とで式1の関係を図2に示す。硅素
膜が効率的に加熱される為には入射光の少なくとも10
%程度は半導体膜により吸収される必要があるので、図
2中には其の条件となる0.9の位置に横点線を引いて
ある。又、光の強度は其の儘硅素に加えられる熱量を意
味し、故に図2はレーザー光照射時に於ける硅素膜中で
の温度分布をも表している事になる。出願人等の研究に
依ると、従来のエキシマレーザー照射で半導体膜の表面
が激しく損傷を被る一方、其の下部では低品質な半導体
層が残り、其れが為優良なる多結晶半導体膜が得られぬ
理由は、表面と下部との間に存在する大きな温度差に由
来する。表面での損傷が生ぜず、且つ半導体膜の厚み方
向で略全体が溶融するのは、半導体膜下部に於ける光の
強度が入射光強度の半分程度以上の時である。此の条件
を満たす時には表面と下部との温度差は小さくなる。そ
こで図2には光の強度が表面の半分となる0.5の位置
にも横点線を引いてある。従って硅素を主体とした半導
体膜が効果的に加熱され、且つ半導体膜に損傷が入らず
に膜厚全体で良好な結晶化が進む条件は、図2で0.9
の横点線と0.5の横点線とに挟まれた領域となる。従
来技術のXeClエキシマレーザー光は入射光の殆どが
半導体膜表面にて吸収されるので、レーザー結晶化に適
した半導体膜厚は1nmから4nmと限られて居る事が
分かる。此に対して本願発明の条件では広い膜厚範囲に
て良好な結晶化が行われる事になる。
I (x) / I (0) = exp ( −μpSi · x) (Equation 1) When the absorption coefficient μpSi is 10 −3 nm −1 and 10 −2
In the case of nm- 1, the case of the second harmonic (YAG2ω light) of the Nd: YAG laser beam which is the most excellent pulse laser beam of the present invention, and the case of the XeCl excimer laser beam of the prior art, FIG. 2 shows the relationship. In order for the silicon film to be efficiently heated, at least 10
Since about% needs to be absorbed by the semiconductor film, a horizontal dotted line is drawn at a position of 0.9 which satisfies the condition in FIG. Further, the light intensity means the amount of heat applied to the silicon as it is, and therefore FIG. 2 also shows the temperature distribution in the silicon film during laser light irradiation. According to the research conducted by the applicants, the surface of the semiconductor film is severely damaged by the conventional excimer laser irradiation, while a low-quality semiconductor layer remains under the semiconductor film, thereby obtaining an excellent polycrystalline semiconductor film. The reason for this is due to the large temperature difference existing between the surface and the lower part. The damage to the surface does not occur, and the whole is melted in the thickness direction of the semiconductor film when the light intensity at the lower part of the semiconductor film is about half or more of the incident light intensity. When this condition is satisfied, the temperature difference between the surface and the lower part becomes small. Therefore, in FIG. 2, a horizontal dotted line is also drawn at a position of 0.5 where the light intensity is half of the surface. Therefore, the condition that the semiconductor film mainly composed of silicon is effectively heated, and the favorable crystallization proceeds over the entire film thickness without damaging the semiconductor film is 0.9 in FIG.
And an area between the horizontal dotted line of 0.5 and the horizontal dotted line of 0.5. Since most of the incident light of the conventional XeCl excimer laser light is absorbed on the surface of the semiconductor film, it is understood that the semiconductor film thickness suitable for laser crystallization is limited to 1 nm to 4 nm. On the other hand, under the conditions of the present invention, good crystallization is performed in a wide film thickness range.

【0016】レーザー光を用いた溶融結晶化では、何れ
のレーザー光を用いようとも、温度勾配に沿って結晶は
成長する。一方、薄膜半導体装置で利用される半導体膜
の厚みは、通常30nm程度から100nm程度であ
る。先にも述べた様に、従来のXeClエキシマレーザ
ー光に依る結晶化では半導体膜表面の4nm程度以内で
殆どの光が吸収され、表面近傍のみが加熱される事に起
因して、半導体膜内では上下方向に急峻な温度勾配が生
ずる(図3、a−1)。此の為に結晶は半導体膜の下部
から表面に向かって成長し、レーザー照射後に得られる
多結晶膜は小さな結晶粒から構成される傾向が強かった
(図3、a−2)。(この様に従来技術では下から上に
向かって小さな結晶粒が沢山成長して居たので、半導体
膜中の不純物に起因する結晶核の存在は然程重要な問題
ではなかった。)此に対して本願発明では、溶融結晶化
に最も適した吸収係数を有するレーザー光を照射するの
で、半導体膜が膜厚方向で均一に加熱される。其の結
果、レーザー照射領域の端部に於いては、温度勾配が横
方向に生じ(図3、b−1)、結晶は上下方向よりも寧
ろ横方向に成長し易くなる。即ち、照射領域の端部には
大きな結晶粒が成長する事になる(図3、b−2)。照
射領域内の端部以外の場所でも上下方向の温度差が小さ
い為に、半導体膜下部での結晶核発生確率が従来よりも
著しく低減して、平均的には多結晶半導体膜を構成する
結晶粒は従来よりも大きくなる。横方向への結晶成長が
促進されるのは表面と下部との光強度が其程変わらない
時で、実験に依ると半導体膜下部に於ける光強度が入射
光強度の三分の一程度以上となる場合である。図2には
横成長が生じ易くなる条件の0.667の位置に横点線
を描いてある。従って硅素を主体とした半導体膜が効果
的に加熱され、且つ横成長が生じて大きな結晶粒から成
る多結晶半導体膜が形成される条件は、図2で0.9の
横点線と0.667の横点線とに挟まれた領域となる。
無論、結晶粒を大きくするには温度勾配の他に不純物に
基付く結晶核を抑制せねばならないので、下地保護膜や
第一工程での半導体膜形成等にも前述の配慮が求められ
る。
In melt crystallization using laser light, a crystal grows along a temperature gradient regardless of which laser light is used. On the other hand, the thickness of a semiconductor film used in a thin film semiconductor device is usually about 30 nm to about 100 nm. As described above, in conventional crystallization using XeCl excimer laser light, most light is absorbed within about 4 nm of the semiconductor film surface, and only the vicinity of the surface is heated. In this case, a steep temperature gradient occurs in the vertical direction (FIG. 3, a-1). For this reason, the crystals grew from the lower part of the semiconductor film toward the surface, and the polycrystalline film obtained after laser irradiation had a strong tendency to be composed of small crystal grains (FIG. 3, a-2). (As described above, in the prior art, since a large number of small crystal grains grew from the bottom to the top, the presence of crystal nuclei due to impurities in the semiconductor film was not a very important problem.) On the other hand, in the present invention, the semiconductor film is uniformly heated in the film thickness direction because a laser beam having an absorption coefficient most suitable for melt crystallization is irradiated. As a result, at the end of the laser irradiation area, a temperature gradient is generated in the lateral direction (FIG. 3, b-1), and the crystal grows more easily in the lateral direction than in the vertical direction. That is, large crystal grains grow at the end of the irradiation area (FIG. 3, b-2). Since the temperature difference in the vertical direction is small even at locations other than the ends in the irradiation region, the probability of generating crystal nuclei at the lower portion of the semiconductor film is significantly reduced as compared with the conventional case, and the crystal constituting the polycrystalline semiconductor film on average The grains are larger than before. Lateral crystal growth is promoted when the light intensity between the surface and the lower part does not change so much. According to experiments, the light intensity at the lower part of the semiconductor film is about one third or more of the incident light intensity. This is the case. In FIG. 2, a horizontal dotted line is drawn at a position of 0.667 under the condition that horizontal growth is likely to occur. Therefore, the conditions under which the semiconductor film mainly composed of silicon is effectively heated and the lateral growth occurs to form a polycrystalline semiconductor film composed of large crystal grains are shown in FIG. And the area between the horizontal dotted lines.
Needless to say, in order to enlarge the crystal grains, it is necessary to suppress the crystal nuclei based on impurities in addition to the temperature gradient. Therefore, the above-mentioned consideration is required also for the formation of the base protective film and the semiconductor film in the first step.

【0017】図2を見ると、吸収係数が10−3nm
−1以上で10−2nm−1以下で有っても総ての半導
体膜厚で優良なる多結晶膜が得られるのではない事が分
かる。例えばYAG2ω光(吸収係数μpSi=4.2
6ラ10−3nm−1)では硅素膜が効果的に加熱され
るのは半導体膜の厚みが25nm程度以上の時であり、
表面での損傷が無く膜厚全体が略溶融するのは半導体膜
の厚みが165nm程度以下の時で有る。又、横成長が
生じて結晶粒が大きく成るのは半導体膜厚が95nm程
度以下の時で有る。従って、YAG2ωレーザー光を硅
素を主体とした半導体膜に照射する時に好ましい半導体
膜の厚みは25nm程度以上165nm程度以下で、理
想的には25nm程度以上95nm程度以下となる。此
の様に使用するレーザー光の多結晶硅素中での波長や吸
収係数に応じて最適半導体膜厚は異なって来る。具体的
には硅素膜が効果的に加熱され、且つ表面損傷無く膜厚
全体が略溶融するのは式1でxを半導体膜の厚みdとし
て、I(d)/I(0)が0.5と0.9との間に有る
時だから、 0.5<I(d)/I(0)<0.9 (式2) と表現される。式2を、式1を用いてdに関して解く
と、 0.105・μpSi −1<d<0.693・μpSi −1 (式3) との関係式が得られる。同様に、硅素膜が効果的に加熱
され、且つ横成長が生じて結晶粒が大きく成るのはI
(d)/I(0)が0.667と0.9との間に有る時
だから、 0.405・μpSi −1<d<0.693・μpSi −1 (式4) との関係式が得られる。半導体膜の厚みdと、此の半導
体膜に照射するパルスレーザー光の多結晶硅素中での吸
収係数μpSiとが上述の式3乃至式4を満たして居る
時には必ず優良なる多結晶半導体薄膜が得られ、以て優
れた薄膜半導体装置が製造される訳である。
Referring to FIG. 2, the absorption coefficient is 10 −3 nm.
It can be seen that even if the thickness is not less than -1 and not more than 10 −2 nm −1 , an excellent polycrystalline film cannot be obtained with all semiconductor film thicknesses. For example, YAG2ω light (absorption coefficient μ pSi = 4.2
In the case of 6 × 10 −3 nm −1 ), the silicon film is effectively heated when the thickness of the semiconductor film is about 25 nm or more.
The entire film thickness is substantially melted without any damage on the surface when the thickness of the semiconductor film is about 165 nm or less. Also, the lateral growth occurs and the crystal grains become large when the semiconductor film thickness is about 95 nm or less. Therefore, when the YAG2ω laser beam is applied to the semiconductor film mainly composed of silicon, the preferable thickness of the semiconductor film is about 25 nm to about 165 nm, and ideally about 25 nm to about 95 nm. The optimum semiconductor film thickness varies depending on the wavelength and absorption coefficient of the laser light used in polycrystalline silicon as described above. Specifically, the silicon film is effectively heated, and the entire film thickness is substantially melted without surface damage. In Equation 1, x is defined as the thickness d of the semiconductor film, and I (d) / I (0) is set to 0.1. Since it is between 5 and 0.9, it is expressed as 0.5 <I (d) / I (0) <0.9 (Equation 2). When Equation 2 is solved for d using Equation 1, a relational expression of 0.105 · μ pSi −1 <d <0.693 · μ pSi -1 (Equation 3) is obtained. Similarly, the silicon film is effectively heated and lateral growth occurs to increase the crystal grain size.
(D) Since / I (0) is between 0.667 and 0.9, the relationship with 0.405 · μ pSi −1 <d <0.693 · μ pSi -1 (Equation 4) An expression is obtained. When the thickness d of the semiconductor film and the absorption coefficient μ pSi of the pulsed laser beam applied to the semiconductor film in the polycrystalline silicon satisfy the above-mentioned formulas 3 and 4, an excellent polycrystalline semiconductor thin film must be obtained. As a result, an excellent thin film semiconductor device is manufactured.

【0018】上述の式3及び式4の関係を、図1に示し
た光の波長と吸収係数との関係を考慮して、波長と硅素
を主体とした半導体薄膜の厚みとの関係に描き直した物
が図4で有る。図4の三角印より上の領域で半導体薄膜
は加熱され、丸印より下の領域には表面損傷が生ぜず半
導体膜の厚み方向で全体が溶融する照射エネルギー密度
が存在し得る。又、四角印より下の領域では上下の温度
差が小さく成るので、結晶の横方向への成長が促進され
る。図4では更に丸印や四角印、三角印を其々直線で近
似してある。此の近似直線を用いると、波長λが440
nm以上710nm以下の場合、波長λと膜厚dとが 9.8×10αL2(λ−440)<d<53×10
αH2(λ−440) 但し、αL2=4.9×10−3 nm−1 αH2=5.4×10−3 nm−1 との関係式を満たして居れば、硅素を主体とした半導体
薄膜は効率的に加熱され、且つ表面に損傷が生ぜずに半
導体膜の厚み方向で薄膜の略全体を溶融させ得る事にな
る。例えばレーザー光としてYAG2ω光を用いる場
合、波長が532nmなので、此の条件を満たす半導体
膜厚は28nmから166nmとなる。更に、膜厚dと
波長λとが 9.8×10αL2(λ−440)<d<32×10
αM2(λ−440) 但し、αL2=4.9×10−3 nm−1 αM2=5.2×10−3 nm−1 との関係式を満たして居れば、硅素を主体とした半導体
薄膜は効率的に加熱され、且つ結晶の横方向への成長も
促進されるのでより好ましい。YAG2ω光をレーザー
光として用いるのならば、半導体膜厚が28nmから9
6nmの時に、此の条件は満たされる。
The relationship between the above equations 3 and 4 is redrawn into the relationship between the wavelength and the thickness of the silicon-based semiconductor thin film in consideration of the relationship between the wavelength of light and the absorption coefficient shown in FIG. The thing is in FIG. The semiconductor thin film is heated in a region above the triangle in FIG. 4, and an irradiation energy density can be present in a region below the circle without causing surface damage and melting in the entire thickness of the semiconductor film. Further, in the region below the square mark, the temperature difference between the upper and lower portions becomes smaller, so that the lateral growth of the crystal is promoted. In FIG. 4, circles, squares, and triangles are further approximated by straight lines. Using this approximate straight line, the wavelength λ is 440
In the case of not less than nm and not more than 710 nm, the wavelength λ and the film thickness d are 9.8 × 10 αL2 (λ-440) <d <53 × 10
αH2 (λ-440) where αL2 = 4.9 × 10 −3 nm −1 If the relational expression of αH2 = 5.4 × 10 −3 nm −1 is satisfied, a semiconductor thin film mainly composed of silicon is obtained. It is possible to heat the thin film in the thickness direction of the semiconductor film efficiently without being heated efficiently and without damaging the surface. For example, when YAG2ω light is used as laser light, the wavelength is 532 nm, and the semiconductor film thickness that satisfies this condition is from 28 nm to 166 nm. Further, the film thickness d and the wavelength λ are 9.8 × 10 αL2 (λ-440) <d <32 × 10
αM2 (λ-440) where αL2 = 4.9 × 10 −3 nm −1 If the relational expression of αM2 = 5.2 × 10 −3 nm −1 is satisfied, the semiconductor thin film mainly composed of silicon is This is more preferable because it is efficiently heated and promotes the lateral growth of the crystal. If YAG2ω light is used as the laser light, the semiconductor film thickness should be 9 nm to 9 nm.
At 6 nm, this condition is satisfied.

【0019】同様に波長λが370nm以上440nm
以下の場合には、波長λと膜厚dとが 2.4×10αL1(λ−370)<d<11.2×1
αH1(λ−370) 但し、αL1=8.7×10− nm−1 αH1=9.6×10−3 nm−1 との関係式を満たして居れば、硅素を主体とした半導体
薄膜は効率的に加熱され、且つ表面に損傷が生ぜずに半
導体膜の厚み方向で薄膜の略全体を溶融させ得る事にな
る。波長λと膜厚dとが 2.4×10αL1(λ−370)<d<6.0×10
αM1(λ−370) 但し、αL1=8.7×10−3 nm−1 αM1=1.04×10−2 nm−1 との関係式を満たして居れば、硅素を主体とした半導体
薄膜は効率的に加熱され、且つ結晶の横方向への成長も
促進されるのでより好ましい。
Similarly, the wavelength λ is 370 nm or more and 440 nm.
In the following case, the wavelength λ and the film thickness d are 2.4 × 10αL1 (λ-370)<D <11.2 × 1
0αH1 (λ-370) However, αL1 = 8.7 × 10−3 nm-1 αH1 = 9.6 × 10-3 nm-1 If the relational expression is satisfied, silicon-based semiconductors
The film is heated efficiently and is half-finished without surface damage.
Almost the entire thin film can be melted in the thickness direction of the conductor film.
You. The wavelength λ and the film thickness d are 2.4 × 10αL1 (λ-370)<D <6.0 × 10
αM1 (λ-370)  However, αL1 = 8.7 × 10-3 nm-1 αM1 = 1.04 × 10-2 nm-1 If the relational expression is satisfied, silicon-based semiconductors
The thin film is efficiently heated, and the crystal grows in the lateral direction.
It is more preferable because it is accelerated.

【0020】(実施例1)図5(a)〜(d)はMOS
型電界効果トランジスタを形成する薄膜半導体装置の製
造工程を断面で示した図で有る。本実施例1では基板1
01としてガラスの歪点温度が650℃の無アルカリガ
ラスを用いた。然るに此以外の基板で有っても、薄膜半
導体装置製造工程中の最高温度に耐えられるのならば、
その種類や大きさは無論問われない。まず基板101上
に下地保護膜102と成る酸化硅素膜を堆積する。基板
がセラミックス基板等で半導体膜に取って望ましからざ
る不純物を含んでいる場合、酸化硅素膜堆積前に酸化タ
ンタル膜や窒化硅素膜等の第一の下地保護膜を堆積して
も良い。本実施例1では基板101上にプラズマ化学気
相堆積法(PECVD法)で酸化硅素膜を200nm程
度堆積し、下地保護膜102とした。酸化硅素膜はEC
R−PECVDにて以下の堆積条件で堆積された。
Embodiment 1 FIGS. 5A to 5D show MOS transistors.
FIG. 4 is a cross-sectional view showing a manufacturing process of a thin-film semiconductor device for forming a field-effect transistor. In the first embodiment, the substrate 1
As No. 01, non-alkali glass having a glass strain point of 650 ° C. was used. However, even with other substrates, if they can withstand the maximum temperature during the thin film semiconductor device manufacturing process,
The type and size are of course not questioned. First, a silicon oxide film serving as a base protective film 102 is deposited on a substrate 101. When the substrate is a ceramic substrate or the like and contains undesirable impurities in the semiconductor film, a first underlayer protective film such as a tantalum oxide film or a silicon nitride film may be deposited before the silicon oxide film is deposited. In Example 1, a silicon oxide film having a thickness of about 200 nm was deposited on the substrate 101 by a plasma enhanced chemical vapor deposition (PECVD) method to form a base protective film 102. Silicon oxide film is EC
It was deposited under the following deposition conditions by R-PECVD.

【0021】 モノシラン(SiH)流量・・・60sccm 酸素(O)流量・・・100sccm 圧力・・・2.40mTorr マイクロ波(2.45GHz)出力・・・2250W 印可磁場・・・875Gauss 基板温度・・・100℃ 成膜時間・・・40秒 此の酸化膜の、液温が25℃で濃度が1.67%の沸化
水素酸水溶液に於けるエッチング速度は0.5nm/s
で有った。
Monosilane (SiH 4 ) flow rate: 60 sccm Oxygen (O 2 ) flow rate: 100 sccm Pressure: 2.40 mTorr Microwave (2.45 GHz) output: 2250 W Applied magnetic field: 875 Gauss Substrate temperature ... 100 ° C Film formation time ... 40 seconds The etching rate of this oxide film in a hydrofluoric acid aqueous solution having a solution temperature of 25 ° C and a concentration of 1.67% is 0.5 nm / s.
It was.

【0022】斯様に形成された下地保護膜上に、第一工
程として真性非晶質硅素膜を高真空型LPCVD装置に
て50nm程度の膜厚に堆積した。高真空型LPCVD
装置はホット・ウォール型で容積が184.5l有り、
基板挿入後の堆積可能領域の総面積は約44000cm
で有る。成膜室に於ける最大排気速度は120scc
m/mTorrで有る。堆積温度は425℃で、半導体
膜堆積前には此の温度にて1時間15分間に渡る基板の
加熱乾燥処理が施された。乾燥熱処理の最中、基板が設
置された成膜室には純度が99.9999%以上のヘリ
ウム(He)を200(sccm)と純度が99.99
99%以上の水素(H)を100(sccm)導入
し、成膜室の圧力は約2.5mTorrに保たれた。乾
燥処理が終了し、半導体膜堆積直前の成膜室背景真空度
は、425℃に於ける温度平衡条件にて2.5ラ10
―7Torrで有った。非晶質硅素膜堆積時には成膜室
に純度99.99%以上のジシラン(Si)を2
00sccmの流量で供給し、堆積圧力は凡そ1.1T
orrに保たれた。此の条件下で硅素膜の堆積速度は
0.77nm/minで有る。
As a first step, an intrinsic amorphous silicon film was deposited to a thickness of about 50 nm on the thus formed base protective film by a high vacuum LPCVD apparatus. High vacuum LPCVD
The device is a hot wall type with a capacity of 184.5 l,
Total area of depositable area after substrate insertion is about 44000cm
It is 2 . The maximum pumping speed in the deposition chamber is 120 scc
m / mTorr. The deposition temperature was 425 ° C., and the substrate was heated and dried at this temperature for 1 hour and 15 minutes before depositing the semiconductor film. During the drying heat treatment, helium (He) having a purity of 99.9999% or more was 200 (sccm) and the purity was 99.99 in the film formation chamber in which the substrate was installed.
Hydrogen (H 2 ) of 99% or more was introduced at 100 (sccm), and the pressure in the film formation chamber was maintained at about 2.5 mTorr. After the drying process is completed, the background degree of vacuum in the film forming chamber immediately before the deposition of the semiconductor film is 2.5 l
-7 Torr. When depositing an amorphous silicon film, disilane (Si 2 H 6 ) having a purity of 99.99% or more
At a flow rate of 00 sccm and a deposition pressure of about 1.1 T
kept at orr. Under these conditions, the deposition rate of the silicon film is 0.77 nm / min.

【0023】次に第二工程として第一工程にて得られた
真性非晶質硅素膜にパルス発振するNd:YAGレーザ
ー光の第二高調波を照射して溶融再結晶化を行った。パ
ルスレーザー光の時間半値幅は約60nsで、発信周波
数は200Hzで有った。レーザー光は幅270μmで
長さ5mmの線状に集光され、此の線状の光を各照射毎
に2.5%づつ幅方向にずらして、基板上を走査した。
従って半導体膜上の任意の一点は約40回のレーザー照
射を被って居る。レーザー光の照射エネルギー密度は7
50mJ・cm−2で有る。半導体膜表面に於ける照射
エネルギー密度の平均値に対する変動は約4%で有っ
た。本実施例1にて使用したYAG2ωレーザー光では
50nmの半導体膜の最表面のみを溶融させるエネルギ
ー密度は200mJ・cm−2程度で有り、完全溶融さ
せるエネルギー密度は800mJ・cm−2程度で有っ
たから、半導体膜の約92%が溶融した事に成る。斯様
にして得られた結晶性硅素膜をパターニング加工して半
導体膜の島103を形成した。(図5−a) 次にパターニング加工された半導体膜の島103を被う
様に酸化硅素膜104をECR−PECVD法にて形成
した。此の酸化硅素膜は半導体装置のゲート絶縁膜とし
て機能する。ゲート絶縁膜と成る酸化硅素膜堆積条件は
堆積時間が24秒と短縮された事を除いて、下地保護膜
の酸化硅素膜の堆積条件と同一で有る。但し、酸化硅素
膜堆積の直前にはECR−PECVD装置内で基板に酸
素プラズマを照射して、半導体の表面に低温プラズマ酸
化膜を形成した。プラズマ酸化条件は次の通りで有る。
Next, as a second step, the intrinsic amorphous silicon film obtained in the first step was irradiated with the second harmonic of Nd: YAG laser light that oscillates in a pulsed manner to perform melting and recrystallization. The time half-width of the pulse laser beam was about 60 ns, and the transmission frequency was 200 Hz. The laser light was condensed in a linear form having a width of 270 μm and a length of 5 mm, and the linear light was shifted by 2.5% in the width direction for each irradiation to scan the substrate.
Therefore, any one point on the semiconductor film has been subjected to about 40 laser irradiations. Laser beam irradiation energy density is 7
It is 50 mJ · cm −2 . The variation of the irradiation energy density on the semiconductor film surface with respect to the average value was about 4%. In the YAG2ω laser beam used in the first embodiment, the energy density for melting only the outermost surface of the semiconductor film of 50 nm is about 200 mJ · cm −2 , and the energy density for completely melting the semiconductor film is about 800 mJ · cm −2. Therefore, about 92% of the semiconductor film is melted. The crystalline silicon film thus obtained was patterned to form a semiconductor film island 103. (FIG. 5-a) Next, a silicon oxide film 104 was formed by ECR-PECVD so as to cover the island 103 of the semiconductor film subjected to patterning. This silicon oxide film functions as a gate insulating film of the semiconductor device. The conditions for depositing the silicon oxide film as the gate insulating film are the same as the conditions for depositing the silicon oxide film as the base protective film, except that the deposition time is reduced to 24 seconds. However, immediately before the deposition of the silicon oxide film, the substrate was irradiated with oxygen plasma in an ECR-PECVD apparatus to form a low-temperature plasma oxide film on the surface of the semiconductor. The plasma oxidation conditions are as follows.

【0024】 酸素(O)流量・・・100sccm 圧力・・・1.85mTorr マイクロ波(2.45GHz)出力・・・2000W 印可磁場・・・875Gauss 基板温度・・・100℃ 処理時間・・・24秒 プラズマ酸化に依り凡そ3.5nmの酸化膜が半導体表
面に形成されて居る。酸素プラズマ照射が終了した後、
真空を維持した侭連続で酸化膜を堆積した。従ってゲー
ト絶縁膜と成る酸化硅素膜はプラズマ酸化膜と気相堆積
膜の二者から成り、その膜厚は122nmで有った。斯
様にしてゲート絶縁膜堆積が完了した。(図5−b) 引き続いて金属薄膜に依りゲート電極105をスパッタ
ー法にて形成する。スパッター時の基板温度は150℃
で有った。本実施例1では750nmの膜厚を有するα
構造のタンタル(Ta)にてゲート電極を作成し、この
ゲート電極のシート抵抗は0.8Ω/□で有った。次に
ゲート電極をマスクとして、ドナー又はアクセプターと
なる不純物イオン106を打ち込み、ソース・ドレイン
領域107とチャンネル形成領域108をゲート電極に
対して自己整合的に作成する。本実施例1ではCMOS
半導体装置を作製した。NMOSトランジスタを作製す
る際にはPMOSトランジスタ部をアルミニウム(A
l)薄膜で覆った上で、不純物元素として水素中に5%
の濃度で希釈されたフォスヒィン(PH)を選び、加
速電圧80kVにて水素を含んだ総イオンを7×10
15cm−2の濃度でNMOSトランジスタのソース・
ドレイン領域に打ち込んだ。反対にPMOSトランジス
タを作製する際にはNMOSトランジスタ部をアルミニ
ウム(Al)薄膜で覆った上で、不純物元素として水素
中に5%の濃度で希釈されたジボラン(B)を選
び、加速電圧80kVにて水素を含んだ総イオンを5×
1015cm−2の濃度でPMOSトランジスタのソー
ス・ドレイン領域に打ち込んだ。(図5−c)イオン打
ち込み時の基板温度は300℃で有る。
Oxygen (O 2 ) flow rate: 100 sccm Pressure: 1.85 mTorr Microwave (2.45 GHz) output: 2000 W Applicable magnetic field: 875 Gauss Substrate temperature: 100 ° C. Processing time: An oxide film of about 3.5 nm is formed on the semiconductor surface by plasma oxidation for 24 seconds. After the oxygen plasma irradiation ends,
An oxide film was deposited continuously while maintaining the vacuum. Therefore, the silicon oxide film serving as the gate insulating film was composed of a plasma oxide film and a vapor deposition film, and had a thickness of 122 nm. Thus, the deposition of the gate insulating film was completed. (FIG. 5-b) Subsequently, the gate electrode 105 is formed by a sputtering method using a metal thin film. The substrate temperature during sputter is 150 ° C
It was. In the first embodiment, α having a thickness of 750 nm
A gate electrode was formed from tantalum (Ta) having a structure, and the sheet resistance of the gate electrode was 0.8Ω / □. Next, using the gate electrode as a mask, an impurity ion 106 serving as a donor or an acceptor is implanted, and a source / drain region 107 and a channel formation region 108 are formed in a self-aligned manner with respect to the gate electrode. In the first embodiment, the CMOS
A semiconductor device was manufactured. When fabricating an NMOS transistor, the PMOS transistor portion is made of aluminum (A
l) After covering with a thin film, 5%
Phosphine (PH 3 ) diluted at a concentration of 7 × 10 3
At a concentration of 15 cm -2 , the source of the NMOS transistor
Driven into the drain region. Conversely, when fabricating a PMOS transistor, after covering the NMOS transistor portion with an aluminum (Al) thin film, diborane (B 2 H 6 ) diluted in hydrogen at a concentration of 5% is selected as an impurity element and accelerated. 5x total ions containing hydrogen at a voltage of 80 kV
It was implanted into the source / drain region of the PMOS transistor at a concentration of 10 15 cm −2 . (FIG. 5-c) The substrate temperature at the time of ion implantation is 300 ° C.

【0025】次にPECVD法でTEOS(Si−(O
CHCH)と酸素を原料気体として、基板温度
300℃で層間絶縁膜109を堆積した。層間絶縁膜は
二酸化硅素膜から成り、その膜厚は凡そ500nmで有
った。層間絶縁膜堆積後、層間絶縁膜の焼き締めとソー
ス・ドレイン領域に添加された不純物元素の活性化を兼
ねて、窒素雰囲気下350℃にて2時間の熱処理を施し
た。最後にコンタクト・ホールを開穴し、スパッター法
で基板温度を180℃としてアルミニウムを堆積し、配
線110を作成して薄膜半導体装置が完成した。(図5
−d) この様にして作成した薄膜半導体装置の伝達特性を測定
した。測定した半導体装置のチャンネル形成領域の長さ
及び幅は其々10μmで、測定は室温にて行われた。4
個のNMOSトランジスタのVds=8Vに於ける飽和
領域より求めた平均の移動度は117cm・V−1
−1で有り、平均の閾値電圧は3.41V、平均のサ
ブスレーシュホールド・スイングは0.260V、閾値
電圧とフラットバンド電圧とから求めた平均のアクセプ
ター型捕獲準位密度は2.09×1016cm−3で有
った。又、4個のPMOSトランジスタのVds=−8
Vに於ける飽和領域より求めた平均の移動度は62cm
・V−1・s−1で有り、平均の閾値電圧は−0.8
1V、平均のサブスレーシュホールド・スイングは0.
368V、閾値電圧とフラットバンド電圧とから求めた
平均のドナー型捕獲準位密度は1.66×1016cm
−3で有った。此等の半導体装置は其の特性が基板内で
殆ど変動が無く、高性能半導体装置が均一に製造されて
居た。此に対して従来技術で非晶質硅素膜を堆積してエ
キシマ・レーザーで結晶化した比較例ではNMOSトラ
ンジスタの平均の移動度が33cm・V−1
−1、平均の閾値電圧が3.70V、平均のサブスレ
ーシュホールド・スイングが0.646V、平均のアク
セプター型捕獲準位密度が2.62ラ1016cm−3
で、PMOSトランジスタの平均の移動度が16cm
・V−1・s−1、平均の閾値電圧が−7.06V、平
均のサブスレーシュホールド・スイングが0.617
V、平均のドナー型捕獲準位密度は6.52×1016
cm−3で有った。この例が示す様に本発明に依るとN
型とP型の両半導体装置共に高移動度で低閾値電圧を有
し、且つ急峻なサブスレーシュホールド特性を示す良好
な薄膜半導体装置が汎用ガラス基板を使用し得る低温工
程にて、簡便且つ容易に、又安定的に作成し得る。取り
分け、サブスレーシュホールド・スイング値から分かる
様に禁制帯中央部付近の捕獲準位密度や、ドナー型捕獲
準位密度と云った獲準位密度を著しく低減するとの絶大
なる効果を有し、薄膜半導体装置を用いた回路の低電圧
駆動を可能ならしめている。又、従来技術では移動度が
大きければ閾値電圧や捕獲準位密度も大きく成っていた
が、本願発明に依ると、高移動度と低閾値電圧や低捕獲
準位密度を同時に実現出来るとの優れた効果をも認めら
れる。
Next, TEOS (Si- (O
Using CH 2 CH 3 ) 4 ) and oxygen as source gases, an interlayer insulating film 109 was deposited at a substrate temperature of 300 ° C. The interlayer insulating film was made of a silicon dioxide film, and its thickness was about 500 nm. After the deposition of the interlayer insulating film, a heat treatment was performed at 350 ° C. for 2 hours in a nitrogen atmosphere to bake the interlayer insulating film and activate the impurity element added to the source / drain regions. Finally, a contact hole was opened, aluminum was deposited at a substrate temperature of 180 ° C. by a sputtering method, and a wiring 110 was formed to complete a thin film semiconductor device. (FIG. 5
-D) The transfer characteristics of the thin film semiconductor device thus prepared were measured. The length and width of the channel formation region of the semiconductor device measured were 10 μm each, and the measurement was performed at room temperature. 4
The average mobility of the NMOS transistors obtained from the saturation region at Vds = 8 V is 117 cm 2 · V -1 ·
s −1 , the average threshold voltage is 3.41 V, the average sub-threshold hold swing is 0.260 V, and the average acceptor-type trap state density determined from the threshold voltage and the flat band voltage is 2.09. × 10 16 cm −3 . Also, Vds = −8 of the four PMOS transistors
The average mobility determined from the saturation region at V is 62 cm
2 · V −1 · s −1 and the average threshold voltage is −0.8
1V, average sub-leash hold swing is 0.
368 V, the average donor-type trap state density determined from the threshold voltage and the flat band voltage is 1.66 × 10 16 cm
-3 . The characteristics of these semiconductor devices hardly fluctuated within the substrate, and high-performance semiconductor devices were manufactured uniformly. On the other hand, the average mobility of the NMOS transistor is 33 cm 2 · V -1 · in the comparative example in which an amorphous silicon film is deposited and crystallized by an excimer laser in the prior art.
s −1 , average threshold voltage 3.70 V, average sub-threshold hold swing 0.646 V, average acceptor-type trap level density 2.62 la 10 16 cm −3.
And the average mobility of the PMOS transistor is 16 cm 2
V -1 s -1 , average threshold voltage is -7.06 V, average sub-threshold hold swing is 0.617
V, the average donor-type trap level density is 6.52 × 10 16
cm -3 . As this example shows, according to the present invention, N
Both the P-type and P-type semiconductor devices have a high mobility and a low threshold voltage, and a good thin-film semiconductor device exhibiting a steep sub-threshold hold characteristic can be easily and simply manufactured in a low-temperature process where a general-purpose glass substrate can be used. It can be easily and stably made. In particular, as can be seen from the sub-leash hold swing value, it has a tremendous effect of significantly reducing the trap level density near the center of the forbidden zone and the trap level density called donor type trap level density. Low-voltage driving of a circuit using a semiconductor device is made possible. Further, in the prior art, the threshold voltage and the trap level density are increased when the mobility is high. However, according to the present invention, the high mobility and the low threshold voltage and the low trap level density can be realized at the same time. The effect is also recognized.

【0026】[0026]

【発明の効果】以上詳述してきた様に、従来低品質でば
らつきも大きかった結晶性半導体膜を、本願発明では成
膜方法や結晶化工程を工夫する事に依り、均一で高品質
な結晶性半導体膜とする事が出来る。これに依り薄膜ト
ランジスタに代表される薄膜半導体装置の電気特性を著
しく向上させ、同時に薄膜半導体装置を低電圧にて動作
させ、更には斯様な薄膜半導体装置を安定的に製造し得
るとの効果が認められる。
As described above in detail, a crystalline semiconductor film having a low quality and a large variation in the prior art can be changed to a uniform and high quality crystallographic film by devising a film forming method and a crystallization process in the present invention. Semiconductor film. This has the effect of significantly improving the electrical characteristics of the thin film semiconductor device represented by the thin film transistor, operating the thin film semiconductor device at a low voltage, and stably manufacturing such a thin film semiconductor device. Is recognized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 光の波長と半導体に於ける吸収係数との関係
を説明した図。
FIG. 1 is a view for explaining the relationship between the wavelength of light and the absorption coefficient of a semiconductor.

【図2】 半導体膜厚と膜中での光強度との関係を説明
した図。
FIG. 2 illustrates a relationship between a semiconductor film thickness and light intensity in the film.

【図3】 本願発明の原理を説明した図。FIG. 3 is a diagram illustrating the principle of the present invention.

【図4】 本願発明の範囲を説明する波長と半導体膜厚
との関係を示す図。
FIG. 4 is a diagram illustrating a relationship between wavelength and semiconductor film thickness for explaining the scope of the present invention.

【図5】 本願発明の製造工程を説明した図。FIG. 5 is a diagram illustrating a manufacturing process of the present invention.

【符号の説明】[Explanation of symbols]

101・・・基板 102・・・下地保護膜 103・・・半導体膜の島 104・・・酸化硅素膜 105・・・ゲート電極 106・・・不純物イオン 107・・・ソース・ドレイン領域 108・・・チャネル形成領域 109・・・層間絶縁膜 110・・・配線 DESCRIPTION OF SYMBOLS 101 ... Substrate 102 ... Underlying protective film 103 ... Semiconductor film island 104 ... Silicon oxide film 105 ... Gate electrode 106 ... Impurity ions 107 ... Source / drain region 108 ...・ Channel forming region 109 ・ ・ ・ Interlayer insulating film 110 ・ ・ ・ Wiring

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 21/336 (72)発明者 小川 哲也 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 (72)発明者 時岡 秀忠 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 (72)発明者 佐藤 行雄 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 (72)発明者 井上 満夫 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 (72)発明者 笹川 智広 東京都千代田区丸の内二丁目2番3号 三 菱電機株式会社内 Fターム(参考) 4K030 AA06 AA14 AA16 AA17 BA29 BB12 DA09 FA02 FA10 5F045 AA06 AB03 AB04 AC01 AD08 AE09 AF07 BB07 BB16 BB18 CA15 DA61 DA63 DA67 HA18 5F052 AA02 BA07 BB02 BB03 CA07 DA02 DA10 DB01 DB02 DB03 DB07 EA12 JA01 JA10 5F110 AA08 AA17 BB04 CC02 DD01 DD02 DD07 DD12 DD13 DD14 DD17 DD24 EE04 EE11 EE23 EE44 FF02 FF09 FF25 FF29 GG01 GG02 GG13 GG16 GG25 GG43 GG44 GG45 GG47 GG57 HJ01 HJ04 HJ13 HJ23 HL03 HL23 NN02 NN04 NN23 NN35 NN40 PP03 PP04 PP23 QQ11──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 21/336 (72) Inventor Tetsuya Ogawa 2-3-2 Marunouchi 2-chome, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (72) Inventor Hidetada Tokioka 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Yukio Sato 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric ( 72) Inventor Mitsuo Inoue 2-3-2 Marunouchi, Chiyoda-ku, Tokyo, Japan Mitsui Electric Co., Ltd. (Reference) 4K030 AA06 AA14 AA16 AA17 BA29 BB12 DA09 FA02 FA10 5F045 AA06 AB03 AB04 AC01 AD08 AE09 AF07 BB07 BB16 BB18 CA15 DA61 DA63 DA67 HA18 5F052 AA02 BA07 BB02 BB0 3 CA07 DA02 DA10 DB01 DB02 DB03 DB07 EA12 JA01 JA10 5F110 AA08 AA17 BB04 CC02 DD01 DD02 DD07 DD12 DD13 DD14 DD17 DD24 EE04 EE11 EE23 EE44 FF02 FF09 FF25 FF29 GG01 GG02 GG13 GG16 J04 GG25 GG43 GG43 GG43 GG43 HGG NN23 NN35 NN40 PP03 PP04 PP23 QQ11

Claims (17)

【特許請求の範囲】[Claims] 【請求項1】 基板上に形成された硅素(Si)を主体
とする結晶性半導体膜を能動層として用いて居る薄膜半
導体装置の製造方法に於いて、 基板上に下地保護膜と成る酸化硅素膜を形成する下地保
護膜形成工程と、 該下地保護膜上に硅素(Si)を主体とした半導体膜を
形成する第一工程と、 該半導体膜に370nm以上710nm以下の波長を有
するパルスレーザー光を照射する第二工程とを含む事を
特徴とする薄膜半導体装置の製造方法。
In a method of manufacturing a thin film semiconductor device using a crystalline semiconductor film mainly composed of silicon (Si) formed on a substrate as an active layer, a silicon oxide serving as a base protective film on the substrate is provided. A step of forming a base protective film for forming a film, a first step of forming a semiconductor film mainly composed of silicon (Si) on the base protective film, and a pulsed laser beam having a wavelength of 370 nm or more and 710 nm or less on the semiconductor film. And a second step of irradiating the thin film semiconductor device.
【請求項2】 前記パルスレーザー光の波長が450n
m程度以上650nm程度以下で有る事を特徴とする請
求項1記載の薄膜半導体装置の製造方法。
2. The pulse laser beam has a wavelength of 450 n.
2. The method according to claim 1, wherein the thickness is not less than about m and not more than about 650 nm.
【請求項3】 前記パルスレーザー光が約532nmで
有る事を特徴とする請求項1または2記載の薄膜半導体
装置の製造方法。
3. The method according to claim 1, wherein the pulse laser beam has a wavelength of about 532 nm.
【請求項4】 前記パルスレーザー光が固体発光素子に
て形成される事を特徴とする請求項1乃至3のいずれか
一項に記載の薄膜半導体装置の製造方法。
4. The method for manufacturing a thin film semiconductor device according to claim 1, wherein said pulsed laser light is formed by a solid light emitting element.
【請求項5】 前記パルスレーザー光がNd:YAGレ
ーザー光の第2高調波で有る事を特徴とする請求項4記
載の薄膜半導体装置の製造方法。
5. The method according to claim 4, wherein the pulsed laser light is a second harmonic of Nd: YAG laser light.
【請求項6】 前記パルスレーザー光の前記半導体膜上
に於ける照射エネルギー密度の変動が5%程度未満で有
る事を特徴とする請求項1乃至4のいずれか一項に記載
の薄膜半導体装置の製造方法。
6. The thin-film semiconductor device according to claim 1, wherein a variation in an irradiation energy density of the pulse laser light on the semiconductor film is less than about 5%. Manufacturing method.
【請求項7】 基板上に形成された硅素(Si)を主体
とする結晶性半導体膜を能動層として用いて居る薄膜半
導体装置の製造方法に於いて、 基板上に下地保護膜と成る酸化硅素膜を形成する下地保
護膜形成工程と、 該下地保護膜上に硅素(Si)を主体とした半導体膜を
膜厚d(nm)と成る様に形成する第一工程と、 該半導体膜に440nm以上710nm以下の波長λ
(nm)を有するパルスレーザー光を照射する第二工程
とを含み、 該膜厚dと該波長λとは 9.8×10αL2(λ−440)<d<53×10
αH2(λ−440) 但し、αL2=4.9×10−3 nm−1 αH2=5.4×10−3 nm−1 との関係式を満たして居る事を特徴とする薄膜半導体装
置の製造方法。
7. Mainly silicon (Si) formed on a substrate
Thin film using crystalline semiconductor film as active layer
In a method of manufacturing a conductor device, a silicon oxide film serving as a base protective film is formed on a substrate.
Forming a protective film, and forming a semiconductor film mainly composed of silicon (Si) on the base protective film.
A first step of forming a film having a thickness of d (nm), and a wavelength λ of 440 nm or more and 710 nm or less
Second step of irradiating a pulse laser beam having (nm)
The film thickness d and the wavelength λ are 9.8 × 10αL2 (λ-440)<D <53 × 10
αH2 (λ-440)  However, αL2 = 4.9 × 10-3 nm-1 αH2 = 5.4 × 10-3 nm-1 Thin film semiconductor device characterized by satisfying the relational expression
Manufacturing method of the device.
【請求項8】 基板上に形成された硅素(Si)を主体
とする結晶性半導体膜を能動層として用いて居る薄膜半
導体装置の製造方法に於いて、 基板上に下地保護膜と成る酸化硅素膜を形成する下地保
護膜形成工程と、 該下地保護膜上に硅素(Si)を主体とした半導体膜を
膜厚d(nm)と成る様に形成する第一工程と、 該半導体膜に440nm以上710nm以下の波長λ
(nm)を有するパルスレーザー光を照射する第二工程
とを含み、 該膜厚dと該波長λとは 9.8×10αL2(λ−440)<d<32×10
αM2(λ−440) 但し、αL2=4.9×10−3 nm−1 αM2=5.2×10−3 nm−1 との関係式を満たして居る事を特徴とする薄膜半導体装
置の製造方法。
8. A method for manufacturing a thin-film semiconductor device using a crystalline semiconductor film mainly composed of silicon (Si) formed on a substrate as an active layer, the method comprising the steps of: A first step of forming a semiconductor film mainly composed of silicon (Si) on the base protective film so as to have a thickness of d (nm); and forming a film of 440 nm on the semiconductor film. Wavelength λ not less than 710 nm
(Nm), and the film thickness d and the wavelength λ are 9.8 × 10 αL2 (λ-440) <d <32 × 10
αM2 (λ-440) where αL2 = 4.9 × 10 −3 nm −1 αM2 = 5.2 × 10 −3 nm −1 Method.
【請求項9】 前記パルスレーザー光の波長が450n
m程度以上650nm程度以下で有る事を特徴とする請
求項7または8記載の薄膜半導体装置の製造方法。
9. The pulse laser beam has a wavelength of 450 n.
9. The method for manufacturing a thin film semiconductor device according to claim 7, wherein the thickness is not less than about m and not more than about 650 nm.
【請求項10】 前記パルスレーザー光が約532nm
で有る事を特徴とする請求項7または8記載の薄膜半導
体装置の製造方法。
10. The pulse laser beam has a wavelength of about 532 nm.
9. The method for manufacturing a thin-film semiconductor device according to claim 7, wherein:
【請求項11】 前記パルスレーザー光が固体発光素子
にて形成される事を特徴とする請求項7乃至10のいず
れか一項に記載の薄膜半導体装置の製造方法。
11. The method for manufacturing a thin film semiconductor device according to claim 7, wherein said pulsed laser light is formed by a solid state light emitting device.
【請求項12】 前記パルスレーザー光がNd:YAG
レーザー光の第2高調波で有る事を特徴とする請求項1
1記載の薄膜半導体装置の製造方法。
12. The pulsed laser beam is Nd: YAG.
2. The method according to claim 1, wherein the second harmonic is a laser beam.
2. The method for manufacturing a thin film semiconductor device according to claim 1.
【請求項13】 前記パルスレーザー光の前記半導体膜
上に於ける照射エネルギー密度の変動が5%程度未満で
有る事を特徴とする請求項7乃至12のいずれか一項に
記載の薄膜半導体装置の製造方法。
13. The thin-film semiconductor device according to claim 7, wherein a variation of an irradiation energy density of the pulsed laser beam on the semiconductor film is less than about 5%. Manufacturing method.
【請求項14】 基板上に形成された硅素(Si)を主
体とする結晶性半導体膜を能動層として用いて居る薄膜
半導体装置の製造方法に於いて、 基板上に下地保護膜と成る酸化硅素膜を形成する下地保
護膜形成工程と、 該下地保護膜上に硅素(Si)を主体とした半導体膜を
膜厚d(nm)と成る様に堆積する第一工程と、 該半導体膜に370nm以上440nm以下の波長λ
(nm)を有するパルスレーザー光を照射する第二工程
とを含み、 該膜厚dと該波長λとは 2.4×10αL1(λ−370)<d<11.2×1
αH1(λ−370) 但し、αL1=8.7×10−3 nm−1 αH1=9.6×10−3 nm−1 との関係式を満たして居る事を特徴とする薄膜半導体装
置の製造方法。
14. A method of manufacturing a thin film semiconductor device using a crystalline semiconductor film mainly composed of silicon (Si) formed on a substrate as an active layer, wherein silicon oxide serving as an underlayer protective film on the substrate is provided. A step of forming an underlayer protective film for forming a film; a first step of depositing a semiconductor film mainly composed of silicon (Si) on the underlayer protective film so as to have a thickness of d (nm); Wavelength λ not less than 440 nm
(Nm), and the film thickness d and the wavelength λ are 2.4 × 10 αL1 (λ-370) <d <11.2 × 1
0 αH1 (λ-370) where αL1 = 8.7 × 10 −3 nm −1 αH1 = 9.6 × 10 −3 nm −1 Production method.
【請求項15】 基板上に形成された硅素(Si)を主
体とする結晶性半導体膜を能動層として用いて居る薄膜
半導体装置の製造方法に於いて、 基板上に下地保護膜と成る酸化硅素膜を形成する下地保
護膜形成工程と、 該下地保護膜上に硅素(Si)を主体とした半導体膜を
膜厚d(nm)と成る様に堆積する第一工程と、 該半導体膜に370nm以上440nm以下の波長λ
(nm)を有するパルスレーザー光を照射する第二工程
とを含み、 該膜厚dと該波長λとは 2.4×10αL1(λ−370)<d<6.0×10
αM1(λ−370) 但し、αL1=8.7×10−3 nm−1 αM1=1.04×10−2 nm−1 との関係式を満たして居る事を特徴とする薄膜半導体装
置の製造方法。
15. A method for manufacturing a thin-film semiconductor device using a crystalline semiconductor film mainly composed of silicon (Si) formed on a substrate as an active layer, the method comprising the steps of: A step of forming an underlayer protective film for forming a film; a first step of depositing a semiconductor film mainly composed of silicon (Si) on the underlayer protective film so as to have a thickness of d (nm); Wavelength λ not less than 440 nm
(Nm), and the film thickness d and the wavelength λ are 2.4 × 10 αL1 (λ-370) <d <6.0 × 10
αM1 (λ-370), where αL1 = 8.7 × 10 −3 nm −1 αM1 = 1.04 × 10 −2 nm −1 Method.
【請求項16】 前記パルスレーザー光が固体発光素子
にて形成される事を特徴とする請求項14または15記
載の薄膜半導体装置の製造方法。
16. The method according to claim 14, wherein the pulsed laser light is formed by a solid-state light emitting element.
【請求項17】 前記パルスレーザー光の前記半導体膜
上に於ける照射エネルギー密度の変動が5%程度未満で
有る事を特徴とする請求項1乃至4のいずれか一項に記
載の薄膜半導体装置の製造方法。
17. The thin-film semiconductor device according to claim 1, wherein a variation of an irradiation energy density of the pulse laser beam on the semiconductor film is less than about 5%. Manufacturing method.
JP11070276A 1999-03-16 1999-03-16 Manufacture of thin film semiconductor device Pending JP2000269133A (en)

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