JP2000150901A - Manufacture of thin-film semiconductor device - Google Patents

Manufacture of thin-film semiconductor device

Info

Publication number
JP2000150901A
JP2000150901A JP11070277A JP7027799A JP2000150901A JP 2000150901 A JP2000150901 A JP 2000150901A JP 11070277 A JP11070277 A JP 11070277A JP 7027799 A JP7027799 A JP 7027799A JP 2000150901 A JP2000150901 A JP 2000150901A
Authority
JP
Japan
Prior art keywords
film
semiconductor device
vapor deposition
oxidation
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11070277A
Other languages
Japanese (ja)
Inventor
Mitsutoshi Miyasaka
光敏 宮坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP11070277A priority Critical patent/JP2000150901A/en
Publication of JP2000150901A publication Critical patent/JP2000150901A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To form a silicon oxide film with high quality even when the surface of the semiconductor film is oxidized at a specified temperature below a significant level by depositing an amorphous semiconductor film using a high-order silane as a kind of material gas by the vapor deposition method and crystalizing it so as to form a semiconductor film. SOLUTION: A substrate 501 is made of quartz glass, and a silicon oxide film is deposited to form a base protection film 502 by the plasma chemical vapor deposition method, and then a semiconductor film made mainly of silicon is deposited thereon by using a high-order silane (SinH2n+2: n = integer of 2 or more) as a kind of material gas by the low-pressure chemical vapor deposition method. Next, a silicon oxide film 504 is formed on the surface of an island 503 as a semiconductor film patterned by the thermal oxidation method. In this case, the semiconductor film is oxidized at 1000 deg.C in an atmosphere with oxygen concentration of 5%, and the silicon film is changed into polycrystalline state. Thus, a thin-film semiconductor device excellent in characteristic can be manufactured easily without adding a special step.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本願発明は1070℃程度以
下の比較的低温にて多結晶性若しくは非晶質性半導体膜
表面に高品質な半導体酸化膜を熱酸化法にて形成する技
術に関する。取り分けこの技術を用いて多結晶薄膜半導
体装置に代表される薄膜半導体装置を高性能を維持した
侭、比較的低温にて製造する方法に関する。
The present invention relates to a technique for forming a high-quality semiconductor oxide film on a polycrystalline or amorphous semiconductor film surface at a relatively low temperature of about 1070 ° C. or less by a thermal oxidation method. In particular, the present invention relates to a method for manufacturing a thin film semiconductor device typified by a polycrystalline thin film semiconductor device at a relatively low temperature while maintaining high performance.

【0002】又、本願発明は窮めて高品質な多結晶性半
導体膜を形成する技術に関する。取り分けこの技術を用
いて多結晶薄膜半導体装置に代表される薄膜半導体装置
の性能を著しく向上せしめる製造方法に関する。
[0002] The present invention also relates to a technique for forming a polycrystalline semiconductor film of extremely high quality. In particular, the present invention relates to a manufacturing method for significantly improving the performance of a thin film semiconductor device represented by a polycrystalline thin film semiconductor device by using this technique.

【0003】[0003]

【従来の技術】多結晶硅素薄膜トランジスタ(p−Si
TFT)に代表される薄膜半導体装置は現在、主とし
て1100℃程度以上の高温を利用した所謂高温工程と
呼ばれる手法で製造されて居る。高温工程とは化学気相
堆積法(CVD法)等で基板上に硅素薄膜を形成した後
に、この硅素薄膜表面を前述の1100℃程度以上の高
温で熱酸化するとの方法をその骨格として居る。斯様に
して得られた多結晶硅素膜と酸化硅素膜を金属−酸化膜
−半導体(MOS)電界効果トランジスタ(FET)の
半導体膜とゲート酸化膜として活用するので有る。
2. Description of the Related Art Polycrystalline silicon thin film transistors (p-Si
At present, thin film semiconductor devices represented by TFTs are mainly manufactured by a so-called high-temperature process using a high temperature of about 1100 ° C. or more. The high-temperature process is based on a method of forming a silicon thin film on a substrate by a chemical vapor deposition method (CVD method) and then thermally oxidizing the surface of the silicon thin film at a high temperature of about 1100 ° C. or more. The polycrystalline silicon film and the silicon oxide film thus obtained are used as a semiconductor film and a gate oxide film of a metal-oxide-semiconductor (MOS) field effect transistor (FET).

【0004】[0004]

【発明が解決しようとする課題】斯くした多結晶硅素薄
膜トランジスタの普及に伴い、その生産性の向上と価格
の低減が求められて居る。こうした要求は基板を大きく
して薄膜半導体装置の取れ個数を増す事や、製造装置寿
命を長くする事に依り満たされる訳で有る。然るに従来
の1100℃程度以上の高温過程を利用した技術の侭で
は、基板の大型化に伴い基板の熱に依る歪みや伸縮等の
変形が指数関数的に増大し、事実上基板を大型化し得な
いので有る。又、製造装置も使用温度が高ければ高い
程、著しくその寿命を短縮させるのが一般で有る。斯く
した諸事由に則し、現在薄膜半導体装置製造上の工程最
高温度を低下させる事が強く望まれて居る。
With the widespread use of such polycrystalline silicon thin film transistors, there is a demand for an improvement in productivity and a reduction in cost. These requirements are met by increasing the number of thin film semiconductor devices that can be obtained by enlarging the substrate and extending the life of the manufacturing apparatus. However, if the conventional technology using a high temperature process of about 1100 ° C. or higher is used, the deformation of the substrate due to heat, such as distortion and expansion and contraction, increases exponentially with the increase in the size of the substrate, and the size of the substrate can be increased. There is not. In general, the higher the operating temperature of the manufacturing apparatus is, the shorter its life is remarkably reduced. Under these circumstances, it is now strongly desired to lower the maximum process temperature in manufacturing thin film semiconductor devices.

【0005】さて、多結晶薄膜半導体装置を製造する際
の最高温度は、既に述べた様に半導体膜表面に酸化膜を
形成する熱酸化工程で有る。図1に熱酸化温度を変えた
時に出来上がった薄膜半導体装置が如何なる特性を示す
かを出願人が行った実験結果を以て示す。この実験では
石英基板上に非晶質硅素膜(a−Si)と多結晶硅素膜
(p−Si)を其々低圧化学気相堆積法(LPCVD
法)にて形成し、これらの硅素膜表面を酸素が100%
で1気圧の雰囲気下にて様々な温度で酸化せしめた。そ
れ以後通常の高温工程に従って多結晶性N型MOS薄膜
半導体装置を作製し、その電気特性を測定したので有
る。図1の横軸は熱酸化時の温度を示し、縦軸は完成し
たトランジスタの電子移動度を示して居る。図中の「Ox
dation of a-Si」は堆積直後の(as−deposit
ed)非晶質硅素膜を熱酸化してMOSFETを作製し
た事を意味し、同様に「Oxidation of p-Si」は堆積直
後の多結晶硅素膜を熱酸化してMOSFETを作製した
事を意味して居る。この図から半導体膜の種類に拘わり
なく、酸化温度の低下と共に半導体特性が悪化して行く
事が分かる。この現象は酸化温度が1070℃程度以下
の時に取り分け顕著と化し、これが製造工程の低温化を
阻害する最大要因と成って居る。従来技術では酸化工程
の低温化が即、薄膜半導体装置の特性低下を意味して居
るので有る。
The highest temperature at the time of manufacturing a polycrystalline thin film semiconductor device is the thermal oxidation step of forming an oxide film on the surface of the semiconductor film as described above. FIG. 1 shows what characteristics the thin film semiconductor device obtained when the thermal oxidation temperature is changed is shown by the results of experiments conducted by the applicant. In this experiment, an amorphous silicon film (a-Si) and a polycrystalline silicon film (p-Si) were respectively formed on a quartz substrate by low pressure chemical vapor deposition (LPCVD).
Method), and the surface of these silicon films is
To oxidize at various temperatures under an atmosphere of 1 atm. Thereafter, a polycrystalline N-type MOS thin film semiconductor device was manufactured according to a normal high-temperature process, and its electrical characteristics were measured. The horizontal axis in FIG. 1 indicates the temperature during thermal oxidation, and the vertical axis indicates the electron mobility of the completed transistor. Ox in the figure
“dation of a-Si” means “as-deposited” immediately after deposition.
ed) Oxidation of p-Si means that a MOSFET was fabricated by thermally oxidizing a polycrystalline silicon film immediately after deposition. I'm doing From this figure, it can be understood that the semiconductor characteristics deteriorate as the oxidation temperature decreases regardless of the type of the semiconductor film. This phenomenon becomes particularly noticeable when the oxidation temperature is about 1070 ° C. or lower, and this is the greatest factor that hinders the lowering of the manufacturing process. This is because in the prior art, lowering the temperature of the oxidation process immediately means lowering of the characteristics of the thin film semiconductor device.

【0006】更に従来技術では図1から分かる様に、仮
令酸化温度を1160℃との高温としても、得られる移
動度の最高値は120cm2・V-1・s-1程度であっ
た。現在、多結晶硅素薄膜トランジスタは簡単なシフト
レジスター回路程度にしか利用されてない。これはその
薄膜半導体装置としての性能が単結晶硅素を利用した金
属−酸化物−半導体電界効果トランジスタ(MOSFE
T)に比べて著しく劣って居るが為で有る。
Further, in the prior art, as can be seen from FIG. 1, even when the provisional oxidation temperature is as high as 1160 ° C., the maximum value of the mobility obtained is about 120 cm 2 · V -1 · s -1 . At present, polycrystalline silicon thin film transistors are used only for simple shift register circuits. This is because a metal-oxide-semiconductor field-effect transistor (MOSFE) using single crystal silicon has the performance as a thin film semiconductor device.
This is because it is significantly inferior to T).

【0007】そこで本発明は上述の諸事情を鑑み、その
目的とする所は1070℃程度に現れる特異点温度以下
の温度にて半導体膜表面を酸化させても、良質な酸化硅
素膜や良質な半導体膜酸化膜界面を形成する方法を提供
し、以て1070℃程度以下の比較的低温で優良な薄膜
半導体装置を製造する方法を提供する事に有る。
Accordingly, the present invention has been made in view of the above-mentioned circumstances, and has as its object the purpose of oxidizing a semiconductor film surface at a temperature lower than a singular point temperature which appears at about 1070 ° C. An object of the present invention is to provide a method for forming an interface between a semiconductor film and an oxide film, and to provide a method for manufacturing an excellent thin film semiconductor device at a relatively low temperature of about 1070 ° C. or less.

【0008】又、本発明の別な目的は単結晶硅素を用い
たMOSFETに匹敵し得る窮めて優良な薄膜半導体装
置を製造する方法を提供する事に有る。
It is another object of the present invention to provide a method of manufacturing a thin and excellent semiconductor device comparable to a MOSFET using single crystal silicon.

【0009】[0009]

【課題を解決するための手段】本発明は基板上にシリコ
ン(Si)を主体とした半導体膜を形成する第一工程
と、此の半導体膜の表面を熱酸化する第二工程とを少な
くとも含む薄膜半導体装置の製造方法に関し、第一工程
は気相堆積法(CVD法)にて高次シラン(Sin
2n+2:n=2,3,4)を原料気体の一種として非晶質
半導体膜を堆積した後に、此の非晶質膜を結晶化する事
で先のシリコン(Si)を主体とした半導体膜を形成し
て居る事を以て其の特徴と為す。まず第一工程に先立
ち、下地保護膜である酸化硅素膜が形成された基板や高
純度の石英基板に第一の熱処理を施すのが望ましい。第
一の熱処理の温度は800℃程度から1100℃程度の
間で有る。
The present invention includes at least a first step of forming a semiconductor film mainly composed of silicon (Si) on a substrate, and a second step of thermally oxidizing the surface of the semiconductor film. In a method for manufacturing a thin film semiconductor device, the first step is to use a higher-order silane (Si n H
2n + 2 : n = 2, 3, 4) is used as a source gas to deposit an amorphous semiconductor film, and then the amorphous film is crystallized so that the silicon (Si) is mainly used. The feature is achieved by forming a semiconductor film. First, prior to the first step, it is preferable to perform a first heat treatment on a substrate on which a silicon oxide film as a base protective film is formed or a high-purity quartz substrate. The temperature of the first heat treatment is between about 800 ° C. and 1100 ° C.

【0010】第一工程で半導体膜を形成する際の気相堆
積法は低圧化学気相堆積法(LPCVD法)で行われる
のが好ましく、低圧化学気相堆積法の内でも高真空型低
圧化学気相堆積装置にて行われる事がより望ましい。高
真空型低圧化学気相堆積装置とは、典型的には半導体膜
堆積直前の背景真空度が5×10-7Torr以下と成っ
て居る物を指す。低圧化学気相堆積法にて非晶質半導体
膜を堆積する時には、低圧化学気相堆積装置に於ける漏
洩流量(QL)の高次シラン流量(QSiH)に対する比
(R=QL/QSiH)が10ppm程度以下(R≦1
-5)との状態で行われる。又、低圧化学気相堆積法は
堆積温度が430℃程度未満で、且つ堆積速度が0.5
nm/min程度以上の状態で行われるのが望ましい。
The vapor deposition method for forming a semiconductor film in the first step is preferably performed by a low pressure chemical vapor deposition method (LPCVD method). Among the low pressure chemical vapor deposition methods, a high vacuum type low pressure chemical vapor deposition method is also used. More preferably, it is performed in a vapor deposition apparatus. A high-vacuum low-pressure chemical vapor deposition apparatus typically refers to an apparatus having a background vacuum of 5 × 10 −7 Torr or less immediately before semiconductor film deposition. When depositing an amorphous semiconductor film by a low pressure chemical vapor deposition method, the ratio the higher silane flow rate (Q SiH) of a low pressure chemical vapor deposition apparatus in leak rate (Q L) (R = Q L / Q SiH ) is about 10 ppm or less (R ≦ 1
It is performed in a state with 0 -5). In the low pressure chemical vapor deposition method, the deposition temperature is less than about 430 ° C., and the deposition rate is 0.5
It is desirable to carry out in a state of about nm / min or more.

【0011】第一工程に於ける非晶質半導体膜の結晶化
は固相にて進められると良い。一例としては非晶質半導
体膜を500℃程度から650℃程度の間の所定の温度
で熱処理する事に依り、固相での結晶化は進められる。
より好ましい熱処理温度は550℃程度から600℃程
度の間の所定の温度で有る。
The crystallization of the amorphous semiconductor film in the first step is preferably carried out in a solid phase. As an example, crystallization in a solid phase is promoted by heat-treating an amorphous semiconductor film at a predetermined temperature between about 500 ° C. and 650 ° C.
A more preferable heat treatment temperature is a predetermined temperature between about 550 ° C and about 600 ° C.

【0012】第二工程は酸化性雰囲気下にて1070℃
程度未満の温度で、且つ一原子層酸化時間が酸化膜応力
緩和時間より長い条件にて行う事が、優良なる薄膜半導
体装置を製造する上で重要となる。具体的には、第二工
程を酸素(O2)と不活性気体とを含む雰囲気下にて1
070℃程度未満の温度T(℃)で行い、且つ第二工程
に於ける酸素分圧(PO2)が t1>τ t1=Δx(Δx+2xi+A)/B×60 (s) Δx=0.36 (nm) xi=5 (nm) A=A0exp(α/(k(T+273.15))) A0=0.2026 (nm) α=0.666 (eV) k=8.617×10-5 (eV・K-1) B=B0exp(−β/(k(T+273.15)))・CO20=3.14×108 (nm2・min-1) β=1.620 (eV) k=8.617×10-5 (eV・K-1) CO2=PO2(atm)/1(atm) CO2は酸素濃度に対応する無次元係数 τ=η/μ η=η0exp(γ/(k(T+273.15))) η0=2.3×10-6 (dyn・s・cm-2) γ=4.85 (eV) k=8.617×10-5 (eV・K-1) μ=3.15×1011 (dyn・cm-2) との式を満たす条件にて行われば良い。
The second step is performed at 1070 ° C. in an oxidizing atmosphere.
It is important to manufacture the excellent thin film semiconductor device at a temperature lower than the order and under the condition that the oxidation time of one atomic layer is longer than the stress relaxation time of the oxide film. Specifically, the second step is performed under an atmosphere containing oxygen (O 2 ) and an inert gas.
Carried out at less than about 070 ° C. the temperature T (° C.), and at an oxygen partial pressure in the second step (P O2) is t 1> τ t 1 = Δx (Δx + 2x i + A) / B × 60 (s) Δx = 0.36 (nm) x i = 5 (nm) A = A 0 exp (α / (k (T + 273.15))) A 0 = 0.2026 (nm) α = 0.666 (eV) k = 8 .617 × 10 −5 (eV · K −1 ) B = B 0 exp (−β / (k (T + 273.15))) · C O2 B 0 = 3.14 × 10 8 (nm 2 · min −1) ) Β = 1.620 (eV) k = 8.617 × 10 −5 (eV · K −1 ) C O2 = P O2 (atm) / 1 (atm) C O2 is a dimensionless coefficient τ corresponding to the oxygen concentration. = Η / μ η = η 0 exp (γ / (k (T + 273.15))) η 0 = 2.3 × 10 −6 (dyn · s · cm −2 ) γ = 4.85 (eV) k = 8.61 × 10 -5 (eV · K -1 ) μ = 3.15 × 10 11 may be carried out under conditions satisfying the formula of (dyn · cm -2).

【0013】[0013]

【発明の実施の形態】本発明は石英ガラスや高耐熱性ガ
ラス或いは単結晶硅素基板等の各種基板上に硅素膜(S
i)や硅素ゲルマニウム膜(SixGe1-x:0<x<
1)に代表される半導体膜を形成する第一工程と、この
半導体膜の表面を酸化する第二工程とを少なくとも含む
薄膜半導体装置の製造方法に関する。特に半導体膜は硅
素をその主構成元素(硅素原子構成比が80%程度以
上)とし、それ故表面に形成される酸化膜も酸化硅素を
その主構成元素として居る。半導体膜は物理気相堆積法
(PVD法)や化学気相堆積法(CVD法)等の気相堆
積法等で形成される。PVD法にはスパッター法や蒸着
法等が考えられる。又CVD法には常圧化学気相堆積法
(APCVD法)や低圧化学気相堆積法(LPCVD
法)、プラズマ化学気相堆積法(PECVD法)等が使
用され得る。気相堆積法で形成された半導体膜は堆積直
後には通常多結晶状態か非晶質状態、又はこれらの混合
状態に有る。多結晶状態に有る薄膜は多結晶膜と称さ
れ、薄膜は多くの結晶粒から構成されて居る。結晶粒と
結晶粒の境界には結晶粒界が存在する。同様に非晶質状
態に有る薄膜は非晶質膜と呼ばれ、薄膜は矢張り多くの
非晶質粒から、或いは非晶質粒と僅かな量の結晶粒から
構成されて居る(M. Miyasaka, et al.: Jpn. J. Appl.
Phys.vol.36 (1997) p.2049)。非晶質粒と非晶質粒の
間、或いは非晶質粒と結晶粒の間にも矢張り粒界が存在
する。気相堆積法で形成された半導体薄膜は多かれ少な
かれ、大概の場合此の粒界を有して居る。本発明の一つ
は此等結晶粒や非晶質粒が単独又は混合状態にて薄膜を
構成し、薄膜内に粒界を含む半導体膜の熱酸化に係わ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming a silicon film (S) on various substrates such as quartz glass, high heat resistant glass, and single crystal silicon substrate.
i) and silicon germanium film (Si x Ge 1-x: 0 <x <
The present invention relates to a method for manufacturing a thin film semiconductor device including at least a first step of forming a semiconductor film represented by 1) and a second step of oxidizing the surface of the semiconductor film. In particular, the semiconductor film has silicon as its main constituent element (silicon atom composition ratio is about 80% or more), and therefore, the oxide film formed on the surface also has silicon oxide as its main constituent element. The semiconductor film is formed by a vapor deposition method such as a physical vapor deposition method (PVD method) or a chemical vapor deposition method (CVD method). As the PVD method, a sputtering method, an evaporation method, or the like can be considered. The CVD method includes atmospheric pressure chemical vapor deposition (APCVD) and low pressure chemical vapor deposition (LPCVD).
Method), plasma-enhanced chemical vapor deposition (PECVD) and the like. Immediately after deposition, a semiconductor film formed by a vapor deposition method is usually in a polycrystalline state, an amorphous state, or a mixed state thereof. A thin film in a polycrystalline state is called a polycrystalline film, and the thin film is composed of many crystal grains. A grain boundary exists at the boundary between the crystal grains. Similarly, a thin film in the amorphous state is called an amorphous film, and the thin film is composed of many amorphous grains or a mixture of amorphous grains and a small amount of crystal grains (M. Miyasaka, et al .: Jpn. J. Appl.
Phys. Vol. 36 (1997) p. 2049). An arrowhead grain boundary also exists between the amorphous grains or between the amorphous grains and the crystal grains. Semiconductor thin films formed by vapor deposition have more or less, in most cases, these grain boundaries. One of the aspects of the present invention relates to thermal oxidation of a semiconductor film in which these crystal grains and amorphous grains form a thin film alone or in a mixed state, and include a grain boundary in the thin film.

【0014】第二工程での半導体膜表面の酸化は第一工
程の気相堆積法で得られた多結晶膜や非晶質膜を其の侭
の状態で行う事も出来るし、或いは多結晶膜を再結晶化
したり非晶質膜を結晶化して多結晶状態とした後に行う
事も出来る。結晶化乃至は再結晶化が施された時も多結
晶薄膜は多数の結晶粒から構成され、結晶粒と結晶粒の
間には必ず粒界が認められる。多結晶膜の再結晶化や非
晶質膜の結晶化は、此等半導体膜を500℃程度から1
200℃程度の間の適当な温度にて固相状態の侭行なわ
れても良いし、溶融状態と冷却固化過程を経て行われて
も良い。再結晶化や結晶化を簡便に行う手段としては気
相堆積法等で得られた多結晶膜や非晶質膜にレーザー光
等の高エネルギーを有した電磁波や粒子流を照射するの
が一例として考えられる。
The oxidation of the surface of the semiconductor film in the second step can be performed on the polycrystalline film or the amorphous film obtained by the vapor deposition method in the first step as it is, It can also be performed after the film is recrystallized or the amorphous film is crystallized into a polycrystalline state. Even when crystallization or recrystallization is performed, the polycrystalline thin film is composed of many crystal grains, and a grain boundary is always recognized between the crystal grains. The recrystallization of the polycrystalline film and the crystallization of the amorphous film are performed by changing the temperature of the semiconductor film from about 500 ° C. to 1 °.
It may be carried out in a solid state at an appropriate temperature of about 200 ° C., or may be carried out through a molten state and a cooling and solidifying process. An example of a simple means of performing recrystallization or crystallization is to irradiate a polycrystalline film or an amorphous film obtained by a vapor deposition method or the like with an electromagnetic wave or a particle stream having high energy such as laser light. It is considered as.

【0015】第一工程で斯様にして得られた半導体膜に
対して、本発明では第二工程の熱酸化を酸化性雰囲気下
にて1070℃程度未満の温度で施す。この際に硅素等
の半導体膜構成元素の一原子層が酸化に費やされる時間
(一原子層酸化時間)が酸化の結果として生じた酸化膜
の応力が緩和されるのに費やされる時間(酸化膜応力緩
和時間)より長くなる条件にて酸化を進行させる。酸化
膜応力緩和時間は酸化膜が被る温度のみの関数で有るか
ら、酸化温度を決めると自動的に応力緩和時間が定ま
る。従って本願発明は斯様にして定まる応力緩和時間よ
りも酸化時間が長く成る様に、換言すれば応力緩和速度
よりも酸化速度が遅く成る様に酸化条件を特定する訳で
有る。この酸化条件は従来技術で行われていた酸素分圧
が1気圧(大気圧下で酸素濃度100%)の酸化では満
たし得ず、窒素(N2)やアルゴン(Ar)、ヘリウム
(He)等の不活性気体と酸素(O2)や水(H2O)を
含む雰囲気下や、此等不活性気体と亜酸化窒素(N
2O)を含む雰囲気下、或いは此等不活性気体と二酸化
炭素素(CO2)を含む雰囲気下にて酸化を進行させる
事に依り満たされる。この他、第二工程の酸化を水や亜
酸化窒素、二酸化炭素を単独で含む雰囲気下で進めても
良い。肝心なのは酸化の極初期(酸化膜厚が5nm程度
未満の期間)を除いた酸化進行期間の殆どで、一原子層
酸化時間が応力緩和時間よりも長く成り、その結果酸化
進行界面では酸化膜形成に伴う応力が常に緩和されて居
る状態にて、酸化を行う事で有る。
In the present invention, the semiconductor film thus obtained in the first step is subjected to the second step of thermal oxidation in an oxidizing atmosphere at a temperature of less than about 1070 ° C. At this time, the time spent for oxidizing one atomic layer of a semiconductor film constituent element such as silicon (one atomic layer oxidation time) is spent for relaxing the stress of the oxide film resulting from the oxidation (oxide film). Oxidation proceeds under conditions longer than the stress relaxation time). Since the oxide film stress relaxation time is a function only of the temperature at which the oxide film is exposed, the stress relaxation time is automatically determined when the oxidation temperature is determined. Therefore, the present invention specifies the oxidation conditions so that the oxidation time is longer than the stress relaxation time thus determined, in other words, the oxidation rate is lower than the stress relaxation rate. This oxidation condition cannot be satisfied by the oxidation in which the oxygen partial pressure is 1 atm (the oxygen concentration is 100% under the atmospheric pressure), which has been performed in the prior art, and nitrogen (N 2 ), argon (Ar), helium (He), etc. Under an atmosphere containing an inert gas and oxygen (O 2 ) or water (H 2 O), or an inert gas and nitrous oxide (N
It is satisfied by promoting the oxidation in an atmosphere containing 2 O) or an atmosphere containing such an inert gas and carbon dioxide (CO 2 ). In addition, the oxidation in the second step may be advanced in an atmosphere containing water, nitrous oxide, and carbon dioxide alone. What is important is most of the oxidation progression time except for the very beginning of oxidation (the time when the oxide film thickness is less than about 5 nm), and the oxidation time of one atomic layer becomes longer than the stress relaxation time. Oxidation is performed in a state where the stress accompanying the above is always relaxed.

【0016】1070℃程度未満の温度で行われる熱酸
化工程で一原子層酸化時間を酸化膜応力緩和時間よりも
長くするには、第二工程を酸素(O2)と前述の不活性
気体とを含む雰囲気下或いは酸素を単独で含む低圧下に
て行い、以て酸化速度を遅延せしめる手法も認められ
る。此の時、酸化速度は酸素分圧(PO2)の関数として
一義的に定まるが故、酸素分圧の調整のみで酸化進行界
面での応力緩和が可能と化す。今、酸化温度を1070
℃程度未満の温度T(℃)とする。熱酸化に関するDeal
-Groveの古典理論(B. E. Deal, et al.: J. App. Phy
s. vol.36 (1965)p.3770)に則ると、酸化の極初期に於
ける一原子層酸化時間t1は t1=Δx(Δx+2xi+A)/B×60 (s) と計算される。ここでΔxは半導体一原子層の厚みでそ
の値は略0.36nmで有る。又xiは酸化の極初期に
得られる酸化膜厚で、Deal-Groveの古典理論は酸化膜が
これ以上の厚みを有する時に有効と成る。xiの値は凡
そ5nmで有る。一原子層酸化時間は酸化膜の成長と共
に長く成るので、Deal-Groveの古典理論が成立し始める
酸化の極初期で一原子層酸化時間が酸化膜応力緩和時間
よりも長ければ、以後酸化の全期間でこの条件は常に満
たされる事と成る。即ち Δx=0.36 (nm) xi=5 (nm) との値を上式に代入して得られる一原子層酸化時間t1
が酸化膜応力緩和時間よりも長ければ良いので有る。係
数Bは放物線速度定数と呼ばれ、酸化膜中の酸素の拡散
係数と酸化雰囲気中の酸素濃度の積に比例して居る。
又、係数B/Aは線形速度定数と称され、酸化進行界面
での酸化反応速度に比例する。此等の係数AとBは酸化
温度T(℃)の関数で有り、出願人が行った精密測定に
依ると下記の如く記述される。
In order to make the monoatomic layer oxidation time longer than the oxide film stress relaxation time in the thermal oxidation step performed at a temperature of less than about 1070 ° C., the second step must be performed with oxygen (O 2 ) and the above-mentioned inert gas. There is also recognized a method of performing the reaction in an atmosphere containing oxygen or under a low pressure containing oxygen alone to thereby delay the oxidation rate. At this time, since the oxidation rate is uniquely determined as a function of the oxygen partial pressure (P O2 ), the stress can be relaxed at the oxidation progress interface only by adjusting the oxygen partial pressure. Now, set the oxidation temperature to 1070
The temperature is set to a temperature T (° C.) lower than about ° C. Deal on thermal oxidation
-Grove's classical theory (BE Deal, et al .: J. App. Phy
s. vol. 36 (1965) p. 3770), the atomic layer oxidation time t 1 at the very beginning of oxidation is calculated as t 1 = Δx (Δx + 2x i + A) / B × 60 (s) Is done. Here, Δx is the thickness of the semiconductor atomic layer, and its value is approximately 0.36 nm. The x i in oxide film thickness obtained very early oxidation classical theory of Deal-Grove is effective when the oxide film has more thickness. The value of xi is approximately 5 nm. The monolayer oxidation time increases with the growth of the oxide film. This condition will always be met in the period. That is, the monoatomic layer oxidation time t 1 obtained by substituting the value of Δx = 0.36 (nm) x i = 5 (nm) into the above equation
Should be longer than the oxide film stress relaxation time. The coefficient B is called a parabolic rate constant, and is proportional to the product of the diffusion coefficient of oxygen in the oxide film and the oxygen concentration in the oxidizing atmosphere.
The coefficient B / A is called a linear rate constant, and is proportional to the oxidation reaction rate at the oxidation progress interface. These coefficients A and B are a function of the oxidation temperature T (° C.) and are described as follows, according to precise measurements made by the applicant.

【0017】 A=A0exp(α/(k(T+273.15))) A0=0.2026 (nm) α=0.666 (eV) k=8.617×10-5 (eV・K-1) B=B0exp(−β/(k(T+273.15)))・CO20=3.14×108 (nm2・min-1) β=1.620 (eV) k=8.617×10-5 (eV・K-1) CO2=PO2(atm)/1(atm) 但し此処でPO2は酸化時の酸素分圧を示し、酸化を酸素
濃度100%の低圧下で行う時には熱酸化炉中の圧力を
示す。又、CO2は熱酸化雰囲気下に於ける酸素濃度に対
応する無次元係数で有る。例えば酸素をアルゴン中に5
%の濃度に希釈して大気圧で酸化を行えば、此の無次元
係数の値は0.05と成る。同様に希釈不活性気体を用
いず酸素濃度100%で0.05気圧(38Torr)
の低圧下で酸化を施せば、此の値は矢張り0.05で有
る。一方、酸化硅素膜は温度が700℃程度以上で有れ
ば粘弾性体として振る舞う事が知られて居り、Maxwell
応力緩和モデルを用いると、酸化膜応力緩和時間τは剛
性率ηと粘度μに依り以下の様に表現される(A. Farge
ix, et al.: J. Phys. D: Appl. Phys. vol.17 (1984)
p.2331)。
A = A 0 exp (α / (k (T + 273.15))) A 0 = 0.226 (nm) α = 0.666 (eV) k = 8.617 × 10 −5 (eV · K −1 ) B = B 0 exp (−β / (k (T + 273.15))) · C O2 B 0 = 3.14 × 10 8 (nm 2 · min −1 ) β = 1.620 (eV) k = 8.617 × 10 −5 (eV · K −1 ) C O2 = P O2 (atm) / 1 (atm) Here, P O2 indicates the oxygen partial pressure at the time of oxidation. When performed under low pressure, it indicates the pressure in the thermal oxidation furnace. C O2 is a dimensionless coefficient corresponding to the oxygen concentration in a thermal oxidation atmosphere. For example, oxygen in argon
% And the oxidation at atmospheric pressure, the value of this dimensionless coefficient is 0.05. Similarly, 0.05 atm (38 Torr) at an oxygen concentration of 100% without using a diluted inert gas.
If oxidation is performed under low pressure, this value is 0.05. On the other hand, it is known that a silicon oxide film behaves as a viscoelastic material when the temperature is about 700 ° C. or higher.
Using the stress relaxation model, the oxide film stress relaxation time τ is expressed as follows depending on the rigidity η and the viscosity μ (A. Farge
ix, et al .: J. Phys. D: Appl. Phys. vol.17 (1984)
p.2331).

【0018】 τ=η/μ η=η0exp(γ/(k(T+273.15))) η0=2.3×10-6 (dyn・s・cm-2) γ=4.85 (eV) k=8.617×10-5 (eV・K-1) μ=3.15×1011 (dyn・cm-2) 斯くして一原子層酸化時間t1が酸化膜応力緩和時間τ
よりも長いとの要請は t1>τ との式を満たす様に酸化を行う事と化す。具体的には熱
酸化温度が定められると、上記の不等式を満たす様に酸
素濃度に対応する無次元係数を決め、その酸素分圧にて
酸化を行うので有る。酸化膜が粘弾性体として振舞うと
確認されて居るのが700℃程度以上で有るから前述の
不等式を適応出来るのも酸化温度が700℃程度以上の
時と化す。酸化速度が余りにも遅く成るとDeal-Groveの
酸化理論が成立し始める5nm程度の厚みを有する酸化
膜を得るのでさえ数十時間を費やす事と成り、現実的と
は言えなく成る。本願発明に則して900℃で5nm程
度の酸化膜を得るには14時間30分程度の時間が必要
と成るから、生産性を考慮すると第二工程の温度は90
0℃程度以上が望まれる。
Τ = η / μ η = η 0 exp (γ / (k (T + 273.15))) η 0 = 2.3 × 10 −6 (dyn · s · cm −2 ) γ = 4.85 ( eV) k = 8.617 × 10 −5 (eV · K −1 ) μ = 3.15 × 10 11 (dyn · cm −2 ) Thus, the monoatomic layer oxidation time t 1 is the oxide film stress relaxation time τ.
The requirement that the length be longer than the above is to be oxidized so as to satisfy the equation of t 1 > τ. Specifically, when the thermal oxidation temperature is determined, a dimensionless coefficient corresponding to the oxygen concentration is determined so as to satisfy the above inequality, and oxidation is performed at the oxygen partial pressure. Since it is confirmed that the oxide film behaves as a viscoelastic body at about 700 ° C. or higher, the above inequality can be applied only when the oxidation temperature is about 700 ° C. or higher. If the oxidation rate becomes too slow, it takes several tens of hours to obtain an oxide film having a thickness of about 5 nm, where the theory of Deal-Grove oxidation starts to be established, which is not practical. It takes about 14 hours and 30 minutes to obtain an oxide film of about 5 nm at 900 ° C. in accordance with the present invention.
A temperature of about 0 ° C. or higher is desired.

【0019】酸化温度が低下するに連れて移動度が低下
し、特に1070℃程度以下で急激に悪化する現象は出
願人の研究に依ると以下の如く説明される。半導体(例
えばSi)膜の酸化では酸化膜中(例えばSiO2中)
を酸素等の酸化反応物質(例えばO2)が拡散し、反応
物質が酸化膜と半導体膜の界面に達した後に反応物質が
酸素原子(O)を半導体構成原子間(例えばSi−Si
の間)に供給して、新たな酸化層(例えばSi−O−S
i)を形成する。此の為半導体中の隣り合う半導体原子
間距離(例えばSi−Si間距離)と、酸素原子を中間
に挟む酸化膜中の半導体原子間距離(例えばSi−O−
Si中のSiとSiの距離)は当然異なって来る。此の
原子間距離の相違が半導体膜中では引張り応力を生じ、
酸化膜中では圧縮応力を発生せしめる。酸化温度が10
70℃程度以上で有ると一原子層酸化時間よりも酸化膜
の圧縮応力緩和時間の方が短い為、酸化に依って生じた
応力は直ちに緩和され、酸化進行界面に応力は残らな
い。所が酸化温度が1070℃程度未満では応力緩和時
間が一原子層酸化時間よりも長い為、酸化は常に応力存
在下で進行する事と成る。図2は此等の関係を示した物
で有る。横軸は酸化温度で縦軸は時間で有る。一原子層
酸化時間に三本の線が有り、其々に20nm、60n
m、120nmと有るのは、酸化膜厚が20nmや60
nm、或いは120nmの状態から半導体の一原子層を
更に酸化するのに費やす時間を現して居る訳で有る。酸
化は酸素濃度100%の1気圧下で行われ、従って図2
は従来技術の酸化現象を解析して居る事に成る。酸化温
度が1100℃とか1160℃では一原子層酸化時間の
線が応力緩和時間の線よりも上に有り、酸化時間の方が
応力緩和時間よりも長い事が分かる。一原子層酸化時間
の線と緩和時間の線は1070℃付近で交差し、此より
も低い温度では応力緩和時間の方が長く成る。1070
℃程度未満の温度では半導体の一原子層が酸化される時
間よりも酸化膜の応力が緩和される時間の方が長く、そ
れ故酸化進行界面では酸化応力が常に残存して居るので
有る。
The phenomenon that the mobility decreases as the oxidation temperature lowers, and especially deteriorates sharply at about 1070 ° C. or less, is explained as follows according to the study of the applicant. In the oxidation of a semiconductor (eg, Si) film, in an oxide film (eg, in SiO 2 )
Is diffused by an oxidation reactant (eg, O 2 ) such as oxygen, and after the reactant reaches the interface between the oxide film and the semiconductor film, the reactant converts oxygen atoms (O) between semiconductor constituent atoms (eg, Si—Si).
) And a new oxide layer (e.g., Si-OS)
forming i). For this reason, the distance between adjacent semiconductor atoms (for example, the distance between Si-Si) in the semiconductor and the distance between semiconductor atoms (for example, Si-O-
The distance between Si and Si in Si) naturally differs. This difference in interatomic distance causes tensile stress in the semiconductor film,
A compressive stress is generated in the oxide film. Oxidation temperature is 10
When the temperature is about 70 ° C. or more, the compressive stress relaxation time of the oxide film is shorter than the monoatomic layer oxidation time, so that the stress generated by the oxidation is immediately relaxed and no stress remains at the oxidation progress interface. However, when the oxidation temperature is lower than about 1070 ° C., the stress relaxation time is longer than the one-atomic layer oxidation time, so that the oxidation always proceeds in the presence of stress. FIG. 2 shows these relationships. The horizontal axis is the oxidation temperature and the vertical axis is the time. There are three lines in the monolayer oxidation time, 20nm and 60n respectively.
m, 120 nm means that the oxide film thickness is 20 nm or 60 nm.
This indicates the time required to further oxidize a monolayer of semiconductor from the state of nm or 120 nm. Oxidation is carried out at 100% oxygen and 1 atm.
Is analyzing the oxidation phenomenon of the prior art. When the oxidation temperature is 1100 ° C. or 1160 ° C., the line for the monolayer oxidation time is above the line for the stress relaxation time, and it can be seen that the oxidation time is longer than the stress relaxation time. The line for the monolayer oxidation time and the line for the relaxation time intersect at about 1070 ° C., and at lower temperatures, the stress relaxation time is longer. 1070
At a temperature lower than about ° C., the time during which the stress of the oxide film is relaxed is longer than the time during which the monoatomic layer of the semiconductor is oxidized, and therefore, the oxidative stress always remains at the oxidation progress interface.

【0020】さて本願が取り扱って居る半導体膜は気相
堆積法等で形成され、半導体膜中に必然的に粒界を伴っ
て居る。これは酸化の対象と成る半導体膜が多結晶膜か
非晶質膜かを問わず認められる。斯くした粒界の有る半
導体膜を応力が残存する状態にて酸化を施すと、粒界に
応力が集中して半導体構成原子や酸化膜構成原子を激し
く移動させる。その結果、界面の凹凸が酷くなり、界面
粗れが生ずるので有る。此の界面粗れが移動度の低下や
表面準位の増大をもたらし、薄膜半導体装置の特性を劣
悪な物と化する主因なので有る。酸化に伴う界面粗れは
応力の強弱と半導体膜の平滑度に依存する。先にも述べ
た様に応力は応力緩和時間と酸化時間の関係で定まり、
応力緩和時間が一原子層酸化時間よりも短い時に平滑な
多結晶性半導体膜と酸化膜との界面が得られる。一方、
酸化対象物質としての半導体膜の平滑度は半導体膜の形
成方法で定まる。半導体膜は気相堆積法で形成された非
晶質膜、或いは此の非晶質膜を固相で結晶化させて得ら
れる多結晶膜を酸化対象物質とした方が気相堆積法で直
接得られる多結晶膜を酸化対象物質するより平滑な表面
を得易い傾向に有る。
The semiconductor film dealt with in the present application is formed by a vapor deposition method or the like, and the semiconductor film necessarily has grain boundaries. This is recognized regardless of whether the semiconductor film to be oxidized is a polycrystalline film or an amorphous film. When the semiconductor film having such a grain boundary is oxidized in a state where the stress remains, the stress is concentrated on the grain boundary and the semiconductor constituent atoms and the oxide constituent atoms are violently moved. As a result, the unevenness of the interface becomes severe, and the interface becomes rough. This interface roughness leads to a decrease in mobility and an increase in surface state, which is a main cause of deteriorating the characteristics of the thin film semiconductor device. The roughness of the interface due to oxidation depends on the strength of the stress and the smoothness of the semiconductor film. As mentioned earlier, stress is determined by the relationship between stress relaxation time and oxidation time,
When the stress relaxation time is shorter than the monoatomic layer oxidation time, a smooth interface between the polycrystalline semiconductor film and the oxide film is obtained. on the other hand,
The degree of smoothness of a semiconductor film as an oxidation target substance is determined by a method for forming the semiconductor film. The semiconductor film can be directly formed by vapor deposition if an amorphous film formed by vapor deposition or a polycrystalline film obtained by crystallizing the amorphous film in a solid phase is used as the substance to be oxidized. There is a tendency that a smoother surface can be easily obtained than when the obtained polycrystalline film is oxidized.

【0021】酸化対象物質としての半導体膜が単結晶膜
で有る時には斯様な作用は動作しない。それは単結晶膜
ではその定義より粒界は存在し得ず、故に応力残存下で
の酸化で有っても酸化応力は粒界に集中し得ないからで
有る。酸素濃度100%で1070℃程度以下の処理温
度で単結晶膜を酸化すると、同様に酸化応力は生ずるも
のの応力は界面全体に均一に掛かるので有る。しかも単
結晶半導体膜の表面は平坦で有るから局所的な応力集中
は生じ得ず、酸化時の界面粗れは起こらない事が理解さ
れよう。単結晶膜の低温酸化でも応力だけは発生する
が、此の応力も酸化終了後の不活性気体雰囲気下での熱
処理で完全に解放出来る。単結晶膜の低温酸化では酸化
終了後の不活性雰囲気下の熱処理さえきちんと施せば、
低温酸化の悪影響を総て除去し得る訳で有る。此に対し
て粒界の有る半導体膜の低温酸化では、酸化終了後の熱
処理は単結晶膜の時程効果的には働かない。確かに酸化
終了後に残存して居る応力は酸化後熱処理で解放出来る
が、抑も酸化期間内に粗れて仕舞った界面を平坦化する
事など不可能だからで有る。非単結晶膜の酸化で肝心な
のは酸化期間中に界面に応力が集中しない様な条件とし
て酸化を施す事で有る。
Such a function does not operate when the semiconductor film as the substance to be oxidized is a single crystal film. This is because, by definition, a grain boundary cannot exist in a single crystal film, and therefore, even if the oxidation is performed under residual stress, the oxidative stress cannot concentrate on the grain boundary. When the single crystal film is oxidized at a processing temperature of about 1070 ° C. or less at an oxygen concentration of 100%, an oxidative stress similarly occurs, but the stress is uniformly applied to the entire interface. Moreover, since the surface of the single crystal semiconductor film is flat, local stress concentration cannot occur, and it will be understood that interface roughness during oxidation does not occur. Although only the stress is generated even at the low temperature oxidation of the single crystal film, this stress can be completely released by the heat treatment in an inert gas atmosphere after the oxidation. In low-temperature oxidation of a single crystal film, if heat treatment under an inert atmosphere after oxidation is properly performed,
This means that all the adverse effects of low-temperature oxidation can be eliminated. On the other hand, in low-temperature oxidation of a semiconductor film having grain boundaries, heat treatment after oxidation is not as effective as that of a single crystal film. Certainly, the stress remaining after the completion of the oxidation can be released by the post-oxidation heat treatment, but it is impossible to suppress the roughened and finished interface during the oxidation period. What is important in the oxidation of the non-single-crystal film is to perform the oxidation under such a condition that stress does not concentrate on the interface during the oxidation period.

【0022】酸化期間中に界面に応力が集中しない酸化
の一例(本願発明の一例)を図3に示す。図3の見方は
図2と同様で有る。唯一の相違は図3では酸素濃度が5
%と成る様に酸素を不活性気体で希釈して酸化を施した
点で有る。酸化を大気圧で行って居るので酸素濃度に対
応する無次元係数の値は0.05で有る。図3から分か
る様に酸化進行界面への酸素供給速度を希釈に依り遅く
した事で一原子層酸化時間は上方に移行し、940℃程
度以上の如何なる温度でも一原子層酸化時間よりも応力
緩和時間が短く成って居る。換言すれば940℃程度以
上の温度で有れば、粒界を有する半導体膜を酸化して
も、粒界への応力集中やその結果で有る界面粗れは生ぜ
ず、故に半導体特性も良好な物と化すので有る。無論酸
素濃度に対応する無次元係数の値を更に小さくすれば、
一原子層酸化時間の線と応力緩和時間の線の交点はより
低温側に移行し、以て酸化の一段たる低温化が実現する
事に成る。
FIG. 3 shows an example of oxidation in which stress is not concentrated on the interface during the oxidation period (an example of the present invention). 3 is the same as FIG. The only difference is that in FIG.
% In that oxygen was diluted with an inert gas and oxidized. Since the oxidation is performed at atmospheric pressure, the value of the dimensionless coefficient corresponding to the oxygen concentration is 0.05. As can be seen from FIG. 3, the oxygen supply rate to the oxidation progressing interface was reduced by dilution, so that the monolayer oxidation time shifted upward, and at any temperature above 940 ° C., the stress relaxation was more than that of the monolayer oxidation time. Time is short. In other words, if the temperature is about 940 ° C. or higher, even if the semiconductor film having the grain boundaries is oxidized, stress concentration on the grain boundaries and the resulting interface roughness do not occur, and the semiconductor characteristics are also good. It is a thing. Of course, if the value of the dimensionless coefficient corresponding to the oxygen concentration is further reduced,
The intersection of the line of the monoatomic layer oxidation time and the line of the stress relaxation time shifts to a lower temperature side, thereby achieving a lower temperature of oxidation.

【0023】図3の例が示した如く、界面に応力が集中
せぬ酸化で最も簡便なのは酸化時の酸素分圧(酸素濃度
に対応する無次元係数)を調整する方法で有る。この調
整の仕方を説明する。此処では一例として酸化温度が1
070℃の場合を考える。酸化の係数AとBは前述の式
に従って其々次の数値と計算される。
As shown in the example of FIG. 3, the simplest method of oxidation in which stress is not concentrated on the interface is a method of adjusting the oxygen partial pressure (dimension coefficient corresponding to the oxygen concentration) at the time of oxidation. How to make this adjustment will be described. Here, as an example, the oxidation temperature is 1
Consider the case of 070 ° C. The oxidation coefficients A and B are calculated as the following numerical values according to the above-mentioned equations.

【0024】A=63.930 (nm) B=261.889×CO2 (nm2・min-1) 此を用いると一原子層酸化時間t1は次の様に表現され
る。
A = 63.930 (nm) B = 261.889 × C O2 (nm 2 · min −1 ) Using this, the monoatomic layer oxidation time t 1 is expressed as follows.

【0025】 t1=1604.66/(261.889×CO2) (s) 一方1070℃に於ける酸化膜の剛性率ηと粘度μは η=3.636×1012 (dyn・s・cm-2) μ=3.15×1011 (dyn・cm-2) で有るから、酸化膜応力緩和時間τは τ=3.636×1012/(3.15×1011)=11.543 (s) で有る。此のt1とτを先の不等号で結ぶと、 1604.66/(261.889×CO2)>11.543 が得られ、此をCO2に対して解くと、 CO2<0.53 の条件を得る。結局、酸化温度が1070℃の時には、
酸素濃度に対応する無次元係数が0.53未満と成る様
に酸素濃度や圧力を調整して酸化を行えば良い事が分か
る。こうすれば粒界に応力は集中せず、平滑な多結晶性
半導体膜と酸化膜との界面が形成されるので有る。図4
にはこの様にして計算した各酸化温度での最大酸素濃度
を示す。所望の酸化温度で図4の曲線より下方と成る酸
素分圧で酸化を施せば、常に一原子層酸化時間は酸化膜
応力緩和時間よりも長く成り、以て優良な薄膜半導体装
置が製造されるので有る。
T 1 = 1604.66 / (261.889 × C O2 ) (s) On the other hand, the rigidity η and viscosity μ of the oxide film at 1070 ° C. are η = 3.636 × 10 12 (dyn · s · cm −2 ) μ = 3.15 × 10 11 (dyn · cm −2 ), the oxide film stress relaxation time τ is τ = 3.636 × 10 12 /(3.15×10 11 ) = 111. 543 (s). When connecting the此of t 1 and τ in the preceding inequality, 1604.66 / (261.889 × C O2 )> 11.543 is obtained by solving此against C O2, C O2 <0.53 Is obtained. After all, when the oxidation temperature is 1070 ° C,
It is understood that the oxidation may be performed by adjusting the oxygen concentration and the pressure so that the dimensionless coefficient corresponding to the oxygen concentration is less than 0.53. In this way, stress is not concentrated on the grain boundaries, and a smooth interface between the polycrystalline semiconductor film and the oxide film is formed. FIG.
Shows the maximum oxygen concentration at each oxidation temperature calculated in this way. If oxidation is performed at a desired oxidation temperature at an oxygen partial pressure lower than the curve in FIG. 4, the monoatomic layer oxidation time will always be longer than the oxide film stress relaxation time, thereby producing an excellent thin film semiconductor device. There is.

【0026】多結晶硅素薄膜トランジスタに代表される
薄膜半導体装置を単結晶硅素を用いたMOSFETに匹
敵する程の優良な薄膜半導体装置とする為には、此迄述
べて来た酸化方法は無論の事、第一工程に於ける半導体
膜の形成方法も重要な役割を演ずる。第一工程での半導
体膜形成が熱酸化後の多結晶性半導体膜を構成する結晶
粒の大小と半導体膜の純度を定め、延ては薄膜半導体装
置の移動度や禁制帯中の捕獲状態数に影響を及ぼすが故
で有る。
In order to make a thin film semiconductor device typified by a polycrystalline silicon thin film transistor an excellent thin film semiconductor device comparable to a MOSFET using single crystal silicon, the oxidation method described so far is of course. The method of forming a semiconductor film in the first step also plays an important role. The formation of the semiconductor film in the first step determines the size of the crystal grains constituting the polycrystalline semiconductor film after thermal oxidation and the purity of the semiconductor film. Because it has an effect on

【0027】第一工程では基板上に硅素(Si)を主体
とした半導体膜を形成する。基板としては単結晶硅素等
の半導体基板や石英ガラスやセラミック等の絶縁性基板
が用いられる。此等の基板の表面には半導体膜に対する
下地保護膜として、酸化硅素膜が100nm程度から1
0μm程度堆積されて居る。下地保護膜としての酸化硅
素膜は単に半導体膜と基板との電気的絶縁性を取った
り、或いは基板が含有する不純物の半導体膜への拡散混
入を防ぐにのみならず、下地酸化膜と結晶性半導体膜と
の界面を良質な物として居る。本願発明では薄膜半導体
装置の半導体膜は10nm程度から150nm程度の厚
みを有し、半導体膜の膜厚方向全域に渡ってエネルギー
バンドは曲がって居る場合(SOIの完全空乏化モデル
に相当する)が考えられる。而も本願発明の半導体膜は
膜中に存在する捕獲準位密度が3×1016cm-3程度以
下と非常に少ない。斯様な状況下ではゲート絶縁膜と半
導体膜との界面と共に、下地保護膜と半導体膜との界面
も電気伝導に無視できぬ関与を及ぼす。酸化硅素膜は半
導体膜と界面を成す際に界面捕獲準位を最も低減し得る
物質で有るから下地保護膜として適している訳で有る。
半導体膜は此の下地保護膜上に形成される。従って下地
保護膜としては半導体膜との界面に1012cm-2程度以
下の界面準位を有する酸化硅素膜が望まれる。此の条件
を満たす酸化硅素膜は、液温が25±5℃で濃度が1.
6±0.2%の沸化水素(HF)酸水溶液に於けるエッ
チング速度が1.5nm/s以下となる物である。通
常、下地保護膜はプラズマ化学気相堆積法(PECVD
法)や低圧化学気相堆積法(LPCVD法)、スパッタ
ー法と云った気相堆積法や熱酸化法で形成される。此等
の内でも、特に本願発明に適した下地保護膜を作成する
には、PECVD法の中でも電子サイクロトロン共鳴P
ECVD法(ECR−PECVD法)やヘリコンPEC
VD法、リモートPECVD法を利用する事が好まし
い。又、工業用周波数(13.56MHz)や其の整数
倍の周波数を用いた汎用のPECVD法にて本願発明に
適した酸化硅素膜を得るには、原料物質としてTEOS
(Si−(O−CH2CH34)と酸素(O2)を使用
し、酸素流量をTEOS流量の5倍以上に設定して酸化
硅素膜を堆積すれば良い。或いは原料物質としてモノシ
ラン(SiH4)と亜酸化窒素(N2O)とを用い、希釈
気体としてヘリウム(He)乃至はアルゴン(Ar)と
云った希ガスを用いて、総気体流量中の希ガスの割合を
90%程度以上(即ち総気体流量中の原料物質の割合を
10%程度未満)として酸化硅素膜を堆積すれば良い。
その際に基板温度は280℃以上であることが望まれ
る。基板が高純度の石英から成る時には下地保護膜と石
英基板とが兼用される事も可能で有るが、表面状態を常
に一定として半導体膜品質の変動を最小とするには、上
述の方法にて下地保護膜を形成するのが好ましい。其れ
以外の方法で本願発明に適した下地保護膜を形成する最
も簡単な方法は、気相堆積法や熱酸化法で作成された酸
化膜に熱処理を施す事で有る。窒素やアルゴン等を主成
分とする略不活性な雰囲気下で、800℃程度から11
00℃程度の温度範囲内で10分から2時間程の熱処理
を施せば、界面準位の低い酸化硅素膜を形成する事が可
能となる。こうする事で最終的に薄膜半導体装置の能動
層を構成する半導体膜の厚みが10nm程度から150
nm程度と薄くとも、閾値電圧が低く急峻な閾値下領域
(サブスレーシュホールド)特性を有する優良な薄膜半
導体装置が製造される。此は基板が高純度の石英基板
で、下地保護膜と石英基板が兼用される場合にも適応さ
れる。石英基板も先の条件で熱処理される事で石英基板
製造時に生じた応力が緩和されたり、石英基板内での粘
性流動の発生で、界面準位が低減されるからである。
In the first step, a semiconductor film mainly composed of silicon (Si) is formed on the substrate. As the substrate, a semiconductor substrate such as single crystal silicon or an insulating substrate such as quartz glass or ceramic is used. On the surface of such a substrate, a silicon oxide film as a base protective film for the semiconductor film is formed from about 100 nm to 1 nm.
About 0 μm is deposited. The silicon oxide film as a base protective film not only provides electrical insulation between the semiconductor film and the substrate, or prevents diffusion of impurities contained in the substrate into the semiconductor film, but also prevents the base oxide film from being crystalline. The interface with the semiconductor film is of good quality. In the present invention, the semiconductor film of the thin film semiconductor device has a thickness of about 10 nm to about 150 nm, and the energy band is bent over the entire area of the semiconductor film in the thickness direction (corresponding to a fully depleted model of SOI). Conceivable. In addition, the semiconductor film of the present invention has a very small trap level density of about 3 × 10 16 cm −3 or less. In such a situation, the interface between the underlying protective film and the semiconductor film, as well as the interface between the gate insulating film and the semiconductor film, has a considerable effect on electric conduction. Since a silicon oxide film is a substance that can reduce the interface trap level when forming an interface with a semiconductor film, it is suitable as a base protective film.
The semiconductor film is formed on the underlying protective film. Therefore, a silicon oxide film having an interface state of about 10 12 cm −2 or less at the interface with the semiconductor film is desired as the base protective film. A silicon oxide film satisfying these conditions has a solution temperature of 25 ± 5 ° C. and a concentration of 1.
The etching rate in an aqueous solution of 6 ± 0.2% hydrofluoric acid (HF) is 1.5 nm / s or less. Usually, the underlayer protective film is formed by plasma enhanced chemical vapor deposition (PECVD).
), A low-pressure chemical vapor deposition (LPCVD) method, or a vapor deposition method such as a sputtering method or a thermal oxidation method. Among them, in order to form a base protective film particularly suitable for the present invention, the electron cyclotron resonance P
ECVD (ECR-PECVD) and Helicon PEC
It is preferable to use the VD method and the remote PECVD method. In order to obtain a silicon oxide film suitable for the present invention by a general-purpose PECVD method using an industrial frequency (13.56 MHz) or an integer multiple thereof, TEOS must be used as a raw material.
(Si- (O-CH 2 CH 3) 4) and using oxygen (O 2), the oxygen flow rate is set to more than five times the TEOS flow rate may be deposited silicon oxide film. Alternatively, monosilane (SiH 4 ) and nitrous oxide (N 2 O) are used as raw materials, and a rare gas such as helium (He) or argon (Ar) is used as a diluent gas. The silicon oxide film may be deposited at a gas ratio of about 90% or more (that is, a raw material ratio in the total gas flow rate of less than about 10%).
At that time, the substrate temperature is desired to be 280 ° C. or higher. When the substrate is made of high-purity quartz, the underlying protective film and the quartz substrate can be used in combination. It is preferable to form a base protective film. The simplest method of forming a base protective film suitable for the present invention by any other method is to perform a heat treatment on an oxide film formed by a vapor deposition method or a thermal oxidation method. Under an almost inert atmosphere containing nitrogen, argon, etc. as a main component, from about 800 ° C. to 11
By performing a heat treatment in a temperature range of about 00 ° C. for about 10 minutes to 2 hours, a silicon oxide film having a low interface state can be formed. By doing so, the thickness of the semiconductor film constituting the active layer of the thin film semiconductor device is finally reduced from about 10 nm to 150
Even if the thickness is as thin as about nm, an excellent thin film semiconductor device having a low threshold voltage and a sharp subthreshold region (sub-threshold hold) characteristic is manufactured. This is also applicable to a case where the substrate is a high-purity quartz substrate, and the base protective film and the quartz substrate are also used. This is because the quartz substrate is also subjected to the heat treatment under the above conditions, so that the stress generated during the manufacture of the quartz substrate is relaxed, or the interface state is reduced by viscous flow in the quartz substrate.

【0028】下地保護膜上に非晶質半導体膜が物理気相
堆積法や化学気相堆積法で堆積される。下地保護膜上の
塵や埃は半導体の純度を落とし、更には非晶質膜を堆積
する時に非晶質核と成ったり、或いは非晶質膜を結晶成
長させる時に結晶核ともなるので、半導体膜堆積前に基
板を十分洗浄する必要が有る。此に依り純度が高く、結
晶粒の大きい多結晶性半導体膜が後に得られる事と成
る。下地保護膜の付いた基板は石鹸等の界面活性剤を含
む水溶液や酸を含む水溶液、或いはアルカリを含む水溶
液、更にはエタノール等のアルコールやアセトン等のケ
トンなどの有機溶剤にて洗浄される。酸を含む水溶液と
しては硫酸(H2SO4)や塩酸(HCl)、硝酸(HN
3)、弗酸(HF)等の水溶液、或いは硫酸と過酸化
水素水(H22)と純水(H2O)との混合液(以下本
願明細書中では硫酸過水と略す)、塩酸と過酸化水素水
と純水との混合液(塩酸過水と略す)、硝酸と過酸化水
素水と純水との混合液(硝酸過水と略す)、硫酸と弗酸
と純水(H2O)との混合液、塩酸と弗酸と純水との混
合液、硝酸と弗酸と純水との混合液、アンモニアと弗酸
と純水との混合液等が特に適して居る。アルカリを含む
水溶液としてはアンモニア(NH3)水溶液や、アンモ
ニアと過酸化水素水と純水との混合液(アンモニア過水
と略す)が適して居る。半導体膜堆積前には此等の各種
洗浄を適宜組み合わせ、最終的には純水で十分洗い流す
必要が有る。石英等の基板の好ましい洗浄の一例として
は、次に示す有機溶剤洗浄とアルカリ洗浄、酸洗浄、表
層部除去工程の四種類の洗浄を行う方法が有る。
An amorphous semiconductor film is deposited on the underlying protective film by physical vapor deposition or chemical vapor deposition. Dust and dirt on the underlying protective film reduce the purity of the semiconductor, and further become an amorphous nucleus when depositing an amorphous film, or a crystal nucleus when growing an amorphous film. It is necessary to sufficiently clean the substrate before film deposition. Accordingly, a polycrystalline semiconductor film having high purity and large crystal grains can be obtained later. The substrate provided with the base protective film is washed with an aqueous solution containing a surfactant such as soap, an aqueous solution containing an acid, an aqueous solution containing an alkali, or an organic solvent such as an alcohol such as ethanol or a ketone such as acetone. Examples of the aqueous solution containing an acid include sulfuric acid (H 2 SO 4 ), hydrochloric acid (HCl), and nitric acid (HN
O 3 ), an aqueous solution such as hydrofluoric acid (HF), or a mixed solution of sulfuric acid, hydrogen peroxide (H 2 O 2 ) and pure water (H 2 O) (hereinafter abbreviated as “sulfuric peroxide” in the present specification) ), A mixture of hydrochloric acid, hydrogen peroxide and pure water (abbreviated as hydrochloric / hydrogen peroxide), a mixture of nitric acid, hydrogen peroxide and pure water (abbreviated as nitric peroxide), sulfuric acid, hydrofluoric acid and pure water Particularly suitable are a mixture of water (H 2 O), a mixture of hydrochloric acid, hydrofluoric acid and pure water, a mixture of nitric acid, hydrofluoric acid and pure water, and a mixture of ammonia, hydrofluoric acid and pure water. I have As the aqueous solution containing an alkali, an ammonia (NH 3 ) aqueous solution or a mixed solution of ammonia, hydrogen peroxide and pure water (abbreviated as ammonia peroxide) is suitable. Before the semiconductor film is deposited, it is necessary to appropriately combine these various types of cleaning, and finally to sufficiently wash away with pure water. As an example of preferable cleaning of a substrate made of quartz or the like, there is a method of performing the following four types of cleaning: an organic solvent cleaning, an alkali cleaning, an acid cleaning, and a surface layer removing step.

【0029】(1)有機溶剤洗浄 (1−1)アセトン等のケトン洗浄(有機物除去) (0℃から30℃で1分から10分程度) (1−2)エタノール等のアルコール洗浄(有機物除
去) (0℃から30℃で1分から10分程度) (1−3)純水洗浄(ケトン、アルコール除去) (0℃から30℃で1分から10分程度) (2)アルカリ洗浄 (2−1)アンモニア過水洗浄(金属除去) (50℃から100℃で1分から10分程度) (2−2)純水洗浄(アンモニア除去) (0℃から50℃で1分から10分程度) (3)酸洗浄 (3−1)硫酸過水洗浄(金属除去) (50℃から100℃で1分から10分程度) (3−2)純水洗浄(硫酸除去) (0℃から50℃で1分から10分程度) (3−3)塩酸過水洗浄(金属除去) (50℃から100℃で1分から10分程度) (3−4)純水洗浄(塩酸除去) (0℃から50℃で1分から10分程度) (4)表面部酸化膜除去工程 (4−1)弗酸水溶液洗浄(酸化膜表面除去及び酸化膜
表面の水素終端化) (0℃から30℃で1秒から1分程度) (4−2)純水洗浄(弗酸除去) (0℃から30℃で1分から10分程度) 此等の四工程から成る洗浄の内で最も重要なのは表面部
酸化膜除去工程の洗浄で有る。下地保護膜を成す酸化膜
の表面層を除去すれば表面層に付着していた金属や塵等
も自動的に取り除かれるからで有る。従って工程簡略化
等の要請に依り半導体膜堆積前の洗浄工程を最少とさせ
たい時には、少なくとも表面酸化膜除去の洗浄だけは含
まれる様に洗浄工程を設定すれば良い。弗酸水溶液洗浄
は下地酸化膜の表層部1nm程度から20nm程度が除
去される様に行う。1nm程度以下では均一性の観点よ
り洗浄効果が基板内で同一と成らず、20nm程度以上
では下地酸化膜が薄い場合に下地酸化膜の不純物混入を
防止する機能に障害が生ずる恐れが有るからで有る。弗
酸水溶液洗浄を半導体膜堆積直前に行う事は下地酸化膜
表面を水素原子で終端する事を意味して居る。此の水素
は比較的離脱が容易な為、半導体膜堆積工程の極初期に
シランと化学反応を行い、結果として下地酸化膜と硅素
膜との密着性を向上させる。加えて下地酸化膜と半導体
膜との間の界面準位を減らす効果がある。従って本願が
示す様に能動層半導体膜の厚さが100nm程度未満で
且つ半導体膜のエネルギーバンドが膜厚方向全体に渡っ
て曲がって居る系(SOIの完全空乏化に相当する系)
ではサブスレーシュホールド・スイングの改善や閾値電
圧の低下、及びオフ電流の低減と云ったトランジスタ特
性の改善が見られる。弗酸水溶液は弗酸を純水中に弗酸
濃度が0.1%程度から10%程度と成る様に溶かした
物を基本とするが、此の溶液にアンモニアを追加しても
良い。
(1) Washing of organic solvent (1-1) Washing of ketone such as acetone (removal of organic matter) (0 to 30 ° C. for about 1 to 10 minutes) (1-2) Washing of alcohol such as ethanol (removal of organic matter) (1 to 10 minutes at 0 ° C to 30 ° C) (1-3) Pure water washing (ketone and alcohol removal) (1 to 10 minutes at 0 ° C to 30 ° C) (2) Alkaline washing (2-1) Ammonia peroxide washing (metal removal) (1 to 10 minutes at 50 to 100 ° C) (2-2) Pure water washing (ammonia removal) (1 to 10 minutes at 0 to 50 ° C) (3) Acid Cleaning (3-1) Sulfuric acid peroxide cleaning (metal removal) (1 to 10 minutes at 50 to 100 ° C) (3-2) Pure water cleaning (sulfuric acid removal) (1 to 10 minutes at 0 to 50 ° C) (3-3) Cleaning with hydrochloric acid / hydrogen peroxide (metal removal) (5 (3-4) Pure water washing (removal of hydrochloric acid) (0 to 50 ° C for about 1 to 10 minutes) (4) Surface oxide film removal step (4-1) Hydrofluoric acid aqueous solution cleaning (removal of oxide film surface and hydrogen termination of oxide film surface) (from 0 ° C. to 30 ° C. for about 1 second to 1 minute) (4-2) Pure water cleaning (removal of hydrofluoric acid) (0 ° C. to 30 ° C.) The most important of these four-step cleaning is the cleaning in the surface oxide film removing step. This is because if the surface layer of the oxide film forming the base protective film is removed, metal, dust, and the like adhering to the surface layer are automatically removed. Therefore, when it is desired to minimize the cleaning process before depositing the semiconductor film in response to a request for process simplification or the like, the cleaning process may be set so as to include at least cleaning for removing the surface oxide film. The hydrofluoric acid aqueous solution cleaning is performed so as to remove about 1 nm to about 20 nm of the surface layer portion of the base oxide film. If the thickness is about 1 nm or less, the cleaning effect is not the same in the substrate from the viewpoint of uniformity, and if the thickness is about 20 nm or more, the function of preventing impurities from being mixed in the base oxide film may be impaired when the base oxide film is thin. Yes. Performing the hydrofluoric acid aqueous solution cleaning immediately before depositing the semiconductor film means terminating the surface of the underlying oxide film with hydrogen atoms. Since this hydrogen is relatively easily separated, it reacts chemically with silane at the very beginning of the semiconductor film deposition process, thereby improving the adhesion between the underlying oxide film and the silicon film. In addition, there is an effect of reducing the interface state between the base oxide film and the semiconductor film. Therefore, as shown in the present application, a system in which the thickness of the active layer semiconductor film is less than about 100 nm and the energy band of the semiconductor film is bent over the entire thickness direction (a system corresponding to complete depletion of SOI).
In this case, improvement in transistor characteristics such as improvement of sub-threshold swing, reduction of threshold voltage, and reduction of off-state current are observed. The hydrofluoric acid aqueous solution is basically a solution in which hydrofluoric acid is dissolved in pure water so that the concentration of hydrofluoric acid becomes about 0.1% to about 10%, but ammonia may be added to this solution.

【0030】上述の洗浄と最後の純水に依る洗い流しが
済んだ後に、下地保護膜上に非晶質半導体膜を堆積す
る。半導体膜堆積には各種気相堆積法が可能で有るが、
高純度の半導体膜が容易に堆積されるとの立場からは、
其の内でも特に低圧化学気相堆積法(LPCVD法)が
適して居る。基板は純水に依る洗い流しが終了した後、
直ちに(長くとも2時間程度以内に)気相堆積装置内に
設置されるべきで有る。低圧化学気相堆積法は高真空型
低圧化学気相堆積装置にて行われる。高真空型とは非晶
質半導体膜堆積直前の背景真空度が5×10-7Torr
程度以下とし得る装置で、具体的には成膜室への装置外
部からの漏洩流量が、洗浄した基板からの最大脱ガス総
流量(300mm×300mmのガラス基板17枚で最
大脱ガス総流量は1×10-2(sccm)程度)の十分
の一程度以下(先の例に則ると装置外部からの漏洩流量
は1×10-3(sccm)程度以下)の気密性を有する
装置で有る。装置成膜室の気密性は避け得ない基板から
の脱ガスの最大流量の十分の一程度以下で有れば、仮令
気密性に多少の変動が有ろうとも、総不純物流量(成膜
室への装置外部からの漏洩流量と基板からの脱ガス流量
との和)に対して著しい影響を及ぼさないからで有る。
斯様な高真空型低圧化学気相堆積装置は単に成膜室の気
密性が優れて居るにのみならず、成膜室に於ける排気速
度が100sccm/mTorr(不活性ガスを100
sccm成膜室に流した時に得られる平衡圧力が1mT
orrと成る排気速度)程度以上の排気能力を有して居
る事が更に望まれる。斯うした高排気能力を有する装置
では1時間程度の比較的短時間で、十分な洗浄を施され
た基板からの水等の脱ガス流量を装置の漏洩流量と同程
度の水準迄低下せしめ、生産性を著しく高める事が可能
と成るからで有る。
After the above-described washing and the final washing with pure water, an amorphous semiconductor film is deposited on the underlying protective film. Various vapor deposition methods are possible for semiconductor film deposition,
From the standpoint that high-purity semiconductor films are easily deposited,
Among them, low pressure chemical vapor deposition (LPCVD) is particularly suitable. After the substrate has been rinsed with pure water,
It should be installed immediately (within at most about 2 hours) in the vapor deposition apparatus. The low pressure chemical vapor deposition method is performed in a high vacuum type low pressure chemical vapor deposition apparatus. The high vacuum type means that the background vacuum degree immediately before the deposition of the amorphous semiconductor film is 5 × 10 −7 Torr.
In the apparatus, the leakage flow rate from the outside of the apparatus to the film formation chamber is specifically, the maximum total degassing flow rate from the cleaned substrate (the maximum total degassing flow rate for 17 glass substrates of 300 mm × 300 mm is: The device has airtightness of about one tenth or less (about 1 × 10 −2 (sccm)) (leakage flow from the outside of the apparatus is about 1 × 10 −3 (sccm) or less according to the above example). . If the airtightness of the film formation chamber is less than about one-tenth of the inevitable maximum degassing flow rate from the substrate, the total impurity flow rate (to the The sum of the leakage flow rate from the outside of the apparatus and the degassing flow rate from the substrate is not significantly affected.
Such a high-vacuum type low-pressure chemical vapor deposition apparatus not only has excellent airtightness in the film forming chamber, but also has a pumping speed in the film forming chamber of 100 sccm / mTorr (inert gas of 100 sccm).
The equilibrium pressure obtained when flowing into the sccm deposition chamber is 1 mT
It is further desired to have an evacuation capacity of about (or the evacuation speed of orr). In such a device having a high pumping capacity, in a relatively short time of about one hour, the degassing flow rate of water or the like from the sufficiently cleaned substrate is reduced to the same level as the leak flow rate of the device, This is because productivity can be significantly increased.

【0031】非晶質硅素膜に代表されるシリコンを主体
とする半導体膜は高次シラン(Sin2n+2:nは2以
上の整数)を原料気体の一種として堆積される。価格や
安全性を考慮すると高次シランとしてはジシラン(Si
26)が最も適している。さて、高純度で高品質の半導
体膜を堆積するには、低圧化学気相堆積装置に於ける装
置外部からの漏洩流量(QL)の高次シラン流量
(QSiH)に対する比(R=QL/QSiH)を10ppm
程度以下(R≦10-5)とせねばならない。(先の漏洩
流量が1×10-3(sccm)程度の例の場合、ジシラ
ン流量は100sccm程度以上とする。)前述の如
く、本願発明では高真空型低圧化学気相堆積装置を用い
て基板からの脱ガス流量が外部からの漏洩流量(QL
程度以下に成ってから半導体膜の堆積を試みる。従って
総不純物流量は外部からの漏洩流量(QL)と同程度の
水準で有る。装置外部から成膜室へ漏洩する物質は主と
して空気で有る。空気中の80%を占める窒素は不活性
で有るから、半導体品質に対して大きな問題は生じせし
めず、不純物として問題と成るのは残りの20%を占め
る酸素で有る。一方、成膜室に導入された高次シランの
内で、実際に反応に関与して半導体膜に取り込まれる物
は、成膜条件に依存して多少の変動は有るものの、大凡
20%程度で有る。それ故、仮令成膜室内に存在する酸
素等の不純物が総て半導体膜中に取り込まれるとの現実
には有り得ぬ最悪の状況を想定しても、外部からの漏洩
流量(QL)の高次シラン流量(QSiH)に対する比(R
=QL/QSiH)を10ppm程度以下(R≦10-5)と
すれば、堆積された半導体膜中の硅素原子に対する酸素
原子等の不要な不純物の濃度は多くとも1017cm-3
度以下(実際は1016cm-3程度以下)と成り、高純度
な半導体膜が得られるので有る。高純度な多結晶半導体
膜はそれを薄膜半導体装置の活性層(電界効果トランジ
スタのソース・ドレイン領域やチャンネル形成領域、或
いはバイポーラトランジスタのエミッター・ベース・コ
レクター領域)として用いた時に、半導体膜禁制帯中の
捕獲準位を減らすと共に不純物元素に起因する移動度低
下を最小限に押さえるとの効果を有する。
A semiconductor film mainly composed of silicon typified by an amorphous silicon film is deposited using high-order silane (Si n H 2n + 2 : n is an integer of 2 or more) as a source gas. Considering price and safety, the higher silane is disilane (Si
2 H 6 ) is most suitable. To deposit a high-purity, high-quality semiconductor film, the ratio (R = Q) of the leakage flow rate (Q L ) from the outside of the apparatus to the high-order silane flow rate (Q SiH ) in the low-pressure chemical vapor deposition apparatus. L / Q SiH ) 10ppm
Or less (R ≦ 10 −5 ). (In the case where the leakage flow rate is about 1 × 10 −3 (sccm), the disilane flow rate is about 100 sccm or more.) As described above, in the present invention, the substrate is formed by using a high vacuum type low pressure chemical vapor deposition apparatus. leakage flow rate of de-gas flow rate from the outside from (Q L)
Attempts are made to deposit a semiconductor film when the temperature is less than about the same. Therefore, the total impurities flow rate is at a level comparable with the leakage flow rate (Q L) from the outside. The substance leaking from the outside of the apparatus to the film formation chamber is mainly air. Since nitrogen, which makes up 80% of the air, is inert, no major problem is caused with respect to semiconductor quality, and oxygen which makes up the remaining 20% as an impurity is a problem. On the other hand, among the higher order silanes introduced into the film formation chamber, those actually involved in the reaction and taken into the semiconductor film vary slightly depending on the film formation conditions, but are about 20%. Yes. Thus, even assuming a worst reality, not impossible in the impurity such as oxygen present in the if the film formation chamber is taken all in the semiconductor film, a high leakage rate from the outside (Q L) The ratio (R) to the secondary silane flow rate (Q SiH )
= Q L / Q SiH ) is about 10 ppm or less (R ≦ 10 −5 ), the concentration of unnecessary impurities such as oxygen atoms with respect to silicon atoms in the deposited semiconductor film is at most about 10 17 cm −3. (Actually, about 10 16 cm −3 or less), and a high-purity semiconductor film can be obtained. When a high-purity polycrystalline semiconductor film is used as an active layer of a thin-film semiconductor device (source-drain region or channel formation region of a field-effect transistor, or emitter-base-collector region of a bipolar transistor), a semiconductor film forbidden band is used. This has the effect of reducing the trapping level inside and minimizing the decrease in mobility due to the impurity element.

【0032】上述の諸条件に加え、更に本願発明では4
30℃程度未満との比較的低温で非晶質半導体膜の堆積
を行う。この際に半導体膜の堆積速度が0.5nm/m
in程度以上と成る様に成膜室の圧力や高次シランの流
量、或いは挿入基板枚数が設定される。斯様な低温(4
30℃程度未満)で且つ比較的速い堆積速度を以て非晶
質半導体膜を堆積すると、堆積により得られる非晶質膜
を構成する非晶質粒が総じて大きくなり、斯くして此の
非晶質膜を結晶化させた際に得られる多結晶膜の結晶粒
は著しく増大するに到る。大粒径の結晶粒から構成され
る多結晶膜は高い移動度の値を有し、此を活性層として
用いて居る薄膜半導体装置は優れた性能を示す事と成
る。此の説明から分かる様に高性能薄膜半導体装置を実
現する上での一つの重要要件は非晶質膜の堆積条件に有
る。430℃程度未満との低温で且つ0.5nm/mi
n程度以上の堆積速度で非晶質半導体膜を堆積すると、
非晶質粒の成長元と成る核(非晶質核)の発生速度が非
晶質膜の成長速度に比べて遅く成り、それ故堆積非晶質
膜を構成する非晶質粒が大きく成るので有る。但し、半
導体膜堆積の際に基板洗浄が不十分で有ると、基板上に
付着した不純物が非晶質核として作用する為、非晶質粒
は小さく成って仕舞う。同様に気相堆積装置の機密度が
不十分で有ると(例えばR=QL/QSiH>10-5)、外
部から成膜室に漏洩した不純物気体が基板上に付着して
矢張り非晶質核と成って仕舞い、結果として大粒径の非
晶質粒から成る優れた非晶質膜は得られない。又、成膜
室内での基板乾燥が不十分で有ると(この時には半導体
膜堆積直前の背景真空度が5×10-7Torr程度以下
と成って居ない)、全く同じ原理で非晶質粒は小さく成
る。高性能薄膜半導体装置を得る為には、基板に十分な
洗浄(少なくとも表面酸化膜除去の洗浄工程)を施し、
原料気体流量に対する機密度が十分で有る成膜装置(R
=QL/QSiH≦10-5)を用いて、基板を成膜室で良く
乾燥させた後(半導体膜堆積直前の背景真空度が5×1
-7Torr程度以下とした後)、ジシラン等の高次シ
ランを原料気体として用いて430℃程度未満との堆積
温度で且つ0.5nm/min程度以上の堆積速度で非
晶質半導体膜を堆積する事が肝要なので有る。
In addition to the above conditions, the present invention further provides
The amorphous semiconductor film is deposited at a relatively low temperature of less than about 30 ° C. At this time, the deposition rate of the semiconductor film is 0.5 nm / m.
The pressure in the film forming chamber, the flow rate of the higher order silane, or the number of inserted substrates is set so as to be about in or more. Such low temperature (4
When the amorphous semiconductor film is deposited at a relatively high deposition rate at a temperature lower than about 30 ° C.), the amorphous grains constituting the amorphous film obtained by the deposition generally become large. The crystal grains of the polycrystalline film obtained when crystallizing are significantly increased. A polycrystalline film composed of crystal grains having a large grain size has a high mobility value, and a thin-film semiconductor device using this as an active layer exhibits excellent performance. As can be seen from this description, one important requirement for realizing a high performance thin film semiconductor device is the conditions for depositing an amorphous film. Low temperature of less than about 430 ° C and 0.5 nm / mi
When an amorphous semiconductor film is deposited at a deposition rate of about n or more,
The generation rate of nuclei (amorphous nuclei) from which the amorphous grains grow is slower than the growth rate of the amorphous film, and therefore the amorphous grains constituting the deposited amorphous film become larger. . However, if the cleaning of the substrate is insufficient during the deposition of the semiconductor film, the impurities attached to the substrate act as amorphous nuclei, so that the amorphous grains are reduced to a small size. Similarly, if there is insufficient sensitivity of the vapor deposition apparatus (e.g., R = Q L / Q SiH> 10 -5), adhering impurity gas leaked from outside the film forming chamber is on the substrate arrows clad non As a result, an excellent amorphous film composed of large-sized amorphous grains cannot be obtained. Also, if the substrate is not sufficiently dried in the film forming chamber (at this time, the background vacuum degree immediately before the deposition of the semiconductor film is not lower than about 5 × 10 −7 Torr), the amorphous particles are formed on the same principle. Become smaller. In order to obtain a high performance thin film semiconductor device, the substrate is sufficiently cleaned (at least a cleaning step of removing a surface oxide film),
A film forming apparatus (R
= Q L / Q SiH ≦ 10 −5 ), and after the substrate is thoroughly dried in the film forming chamber (the background vacuum degree immediately before the deposition of the semiconductor film is 5 × 1).
0 -7 Torr or less), and then depositing the amorphous semiconductor film at a deposition temperature of less than about 430 ° C. and at a deposition rate of about 0.5 nm / min or more using a higher-order silane such as disilane as a source gas. It is important to deposit.

【0033】この様にして非晶質半導体膜が得られた後
に此の非晶質半導体膜を結晶化して、多結晶半導体膜を
形成する。非晶質膜の結晶化は、非晶質膜を500℃程
度から650℃程度の間の所定の温度で熱処理して、固
相にて進める事が好ましい。固相結晶化では非晶質膜を
構成する非晶質粒の大小と多結晶膜を構成する結晶粒の
大小との相関が窮めて強いからで有る。換言すれば大き
い非晶質粒から成る非晶質膜を固相にて結晶化すると大
きい結晶粒から成る多結晶膜が得られるので有る。結晶
化を行う際の熱処理温度はそれが低い程結晶核の生成が
押さえられるのでより大きな結晶粒から成る多結晶膜が
得られるが、それに応じて結晶化が完了する時間も長く
成る。熱処理温度は500℃程度から650℃程度の間
で出来る限り低い温度、理想的には550℃程度から6
00℃程度の間の所定の温度に設定される。
After the amorphous semiconductor film is thus obtained, the amorphous semiconductor film is crystallized to form a polycrystalline semiconductor film. It is preferable that the crystallization of the amorphous film be performed in a solid phase by heat-treating the amorphous film at a predetermined temperature between about 500 ° C. and about 650 ° C. This is because in the solid-phase crystallization, the correlation between the size of the amorphous grains constituting the amorphous film and the size of the crystal grains constituting the polycrystalline film is extremely strong. In other words, when an amorphous film composed of large amorphous grains is crystallized in a solid phase, a polycrystalline film composed of large crystal grains is obtained. The lower the heat treatment temperature during crystallization is, the lower the temperature is, the more the generation of crystal nuclei is suppressed, so that a polycrystalline film composed of larger crystal grains can be obtained, but the time required for completing the crystallization is correspondingly longer. The heat treatment temperature is as low as possible between about 500 ° C. and about 650 ° C., ideally about 550 ° C. to 6 ° C.
The temperature is set to a predetermined temperature between about 00 ° C.

【0034】斯うして第一工程で多結晶性半導体膜が形
成された後に、第二工程にて多結晶性半導体膜の表面を
熱酸化して、電界効果型薄膜トランジスタの活性半導体
層と酸化膜を形成する。酸化膜は此の侭ゲート絶縁膜と
して利用されても良いし、一度剥離した後に別の絶縁膜
を何らかの方法で活性層で有る結晶性半導体膜の上に形
成しても良い。第二工程は酸化性雰囲気下にて1070
℃程度未満の温度で、且つ一原子層酸化時間が酸化膜応
力緩和時間より長い条件で行う。酸化膜中の水酸基(−
OH)や水を減少させる為に第二工程を酸素(O2)と
不活性気体とを含む雰囲気下にて1070℃程度未満の
温度T(℃)で行う時には、第二工程に於ける酸素分圧
(PO2)が t1>τ t1=Δx(Δx+2xi+A)/B×60 (s) Δx=0.36 (nm) xi=5 (nm) A=A0exp(α/(k(T+273.15))) A0=0.2026 (nm) α=0.666 (eV) k=8.617×10-5 (eV・K-1) B=B0exp(−β/(k(T+273.15)))・CO20=3.14×108 (nm2・min-1) β=1.620 (eV) k=8.617×10-5 (eV・K-1) CO2=PO2(atm)/1(atm) CO2は酸素濃度に対応する無次元係数 τ=η/μ η=η0exp(γ/(k(T+273.15))) η0=2.3×10-6 (dyn・s・cm-2) γ=4.85 (eV) k=8.617×10-5 (eV・K-1) μ=3.15×1011 (dyn・cm-2) との式を満たす条件にて熱酸化を行う。此等に関しては
先に詳述した通りで有る。
After the polycrystalline semiconductor film is formed in the first step, the surface of the polycrystalline semiconductor film is thermally oxidized in the second step to form an active semiconductor layer and an oxide film of the field-effect thin film transistor. To form The oxide film may be used as it is as a gate insulating film, or another insulating film may be formed on the crystalline semiconductor film which is an active layer by a certain method after being separated once. The second step is 1070 in an oxidizing atmosphere.
It is performed at a temperature of less than about ° C. and under the condition that the oxidation time of one atomic layer is longer than the stress relaxation time of the oxide film. Hydroxyl groups in the oxide film (-
OH) and water, the second step is performed at a temperature T (° C.) of less than about 1070 ° C. in an atmosphere containing oxygen (O 2 ) and an inert gas. partial pressure (P O2) is t 1> τ t 1 = Δx (Δx + 2x i + A) / B × 60 (s) Δx = 0.36 (nm) x i = 5 (nm) A = A 0 exp (α / (K (T + 273.15))) A 0 = 0.226 (nm) α = 0.666 (eV) k = 8.617 × 10 −5 (eV · K −1 ) B = B 0 exp (−β /(K(T+273.15)))·C O2 B 0 = 3.14 × 10 8 (nm 2 · min −1 ) β = 1.620 (eV) k = 8.617 × 10 −5 (eV · K -1) C O2 = P O2 (atm) / 1 (atm) C O2 is the dimensionless coefficient corresponding to the oxygen concentration τ = η / μ η = η 0 exp (γ / (k (T + 273.1 ))) Η 0 = 2.3 × 10 -6 (dyn · s · cm -2) γ = 4.85 (eV) k = 8.617 × 10 -5 (eV · K -1) μ = 3. The thermal oxidation is performed under the condition of 15 × 10 11 (dyn · cm −2 ). These are as described in detail above.

【0035】(実施例1)図5(a)〜(d)はMOS
型電界効果トランジスタを形成する薄膜半導体装置の製
造工程を断面で示した図で有る。本実施例1では基板5
01として石英ガラスを用いた。然るに此以外の基板で
有っても、薄膜半導体装置製造工程中の最高温度に耐え
られれば、その種類や大きさは無論問われない。まず基
板501上にいずれ能動層と成る硅素等の半導体膜を堆
積する。基板が不純物がドープされた単結晶硅素基板等
の導伝性物質の場合や、セラミックス基板等で半導体膜
に取って望ましからざる不純物を含んでいる場合、半導
体膜堆積前に二酸化硅素膜や窒化硅素膜等の下地保護膜
502を堆積するのが好ましい。本実施例1では基板5
01上にプラズマ化学気相堆積法(PECVD法)で酸
化硅素膜を200nm程度堆積し、下地保護膜502と
した。下地保護膜堆積後に基板を窒素中で1000℃、
20分の第一の熱処理を施した。第一の熱処理後の酸化
硅素膜の、液温が25℃で濃度が1.67%の沸化水素
(HF)酸水溶液に於けるエッチング速度は0.2nm
/sであった。此の下地保護膜上に真性非晶質硅素膜を
LPCVD法にて100nm程度の膜厚に堆積した。L
PCVD装置はホット・ウォール型で容積が184.5
lで、基板挿入後の反応総面積は約44000cm2
有る。堆積温度は425℃で原料ガスとして純度99.
99%以上のジシラン(Si26)を用い、200sc
cm反応炉に供給した。堆積圧力は凡そ1.1Torr
で有り、此の条件下で硅素膜の堆積速度は0.77nm
/minで有った。斯様にして得られた非晶質硅素膜を
パターニング加工して半導体膜の島503を形成した。
(図5−a) 次に熱酸化法にてパターニング加工された半導体膜の島
503表面に酸化硅素膜504を形成した。酸化は10
00℃の温度で酸素濃度5%の雰囲気下にて1気圧で1
4時間15分行なわれた。熱酸化炉はホット・ウォール
型で容積が約46lで有る。基板挿入時の熱酸化炉内に
は純度99.999%程度以上の酸素(O2)が250
sccmと純度99.999%程度以上の窒素(N2
が4750sccm導入され、熱酸化炉内部の酸素濃度
を5.0%に保って居る。基板挿入時の炉内温度は80
0℃で有る。大気圧で酸化を行う場合、基板挿入時に空
気(酸素濃度約20.9%)が酸化炉に混入するので、
未調整状態で初期酸化が著しく進行せぬ様に酸化炉温度
を800℃程度以下に保っておくのが好ましい。気相堆
積法等で形成された粒界を有する半導体膜が付いた基板
を700℃程度以上の不活性雰囲気中に挿入すると、急
速に再結晶化や結晶化等の原子移動が生じ、然も此等の
半導体膜は密度が単結晶膜よりも低い為、此の急速な原
子移動の結果として半導体膜に多数の穴が開いて仕舞
う。優良な薄膜半導体装置を作る上では無論これは好ま
しくない。この問題は酸化性雰囲気中に基板を入れる事
で解決される。此は半導体膜表面に酸化膜が形成される
のと半導体原子の移動(結晶化)が同時に進行する為、
半導体膜に穴が開く程の巨大な原子移動が生ずる前の段
階で、半導体原子間に生じた僅かな空隙を酸素原子が補
充するからだと考えられる。いずれにしても半導体膜に
穴が開かない為には基板挿入は酸化性雰囲気でなければ
成らない。しかも酸化膜厚と膜質、及び平滑な界面を得
る様に酸化工程を正確に管理するには酸素濃度が高すぎ
ても問題で有るから、基板挿入時の酸化炉雰囲気は酸化
実行時の雰囲気と略同一で有る事が望まれる。基板挿入
後酸化炉の温度を10℃/minの昇温速度で上げ、約
20分を費やして酸化温度の1000℃とする。酸化温
度に達してから此の状態(酸化過程と称す)を14時間
15分維持して酸化を行なう。基板挿入時から此の酸化
過程の期間中、反応炉には前述の酸素と窒素が導入され
続け、酸化炉内部を所望の一定雰囲気に保って居る。酸
化過程が終了した後直ちに酸素の供給を断ち、反応炉に
は窒素を5000sccm導入する(酸化後処理と称
す)。此の時も酸化炉温度は依然として酸化温度の10
00℃に保ち続ける。単結晶硅素の熱酸化ではこの酸化
後処理は酸化膜の応力解放にその目的を有して居た。本
願では酸化膜の応力は酸化期間中に完全に解放されて居
るので応力解放の目的ではなく、不要な低温酸化を防ぐ
事をその主目的として居る。酸化終了後にいずれ基板を
反応炉から取り出す訳だが、その時に多結晶性半導体膜
と酸化半導体膜との界面品質が悪化せぬ様にするので有
る。酸化後処理は従って反応炉内が半導体膜に対して不
活性状態(酸化過程に導入された気体の残存率が5%程
度未満)と成る迄継続する。流体混合が最も遅い完全混
合系を想定すると、不活性気体流量(本実施例1では窒
素5slm)に酸化後処理時間(本実施例1では30
分)を掛けた不活性気体の総量(本実施例1では窒素5
slm×30分=150l)が反応炉容積(本実施例1
では46l)の3倍程度以上と成る様に酸化後処理の不
活性気体流量や時間を設定するのが好ましい。3倍程度
以上に成れば先の残存率が5%程度未満に成るからで有
る。こうして反応炉内の雰囲気置換が済んだら反応炉の
温度を5℃/min程度の速度で800℃程度迄下げ、
然る後に基板を反応炉から取り出す。基板が空気に触れ
る時の温度は低温酸化を防ぐ為に800℃程度以下が望
まれる。斯様にして半導体膜表面の酸化は終了し、硅素
膜は多結晶状態に変わり、その膜厚は68nm程度へと
薄く成る。又、半導体膜表面に形成された酸化硅素膜5
04の厚みは58nm程度で有る。(図5−b) 次に薄膜半導体装置の閾値電圧を調整する為に11+
20kVの加速電圧で1.2×1012cm-2の濃度で半
導体膜に打ち込んだ。
(Embodiment 1) FIGS. 5A to 5D show MOS transistors.
FIG. 4 is a cross-sectional view showing a manufacturing process of a thin-film semiconductor device for forming a field-effect transistor. In the first embodiment, the substrate 5
01 is quartz glass. However, the type and size of other substrates are not limited as long as they can withstand the maximum temperature during the thin film semiconductor device manufacturing process. First, a semiconductor film of silicon or the like which will eventually become an active layer is deposited on a substrate 501. If the substrate is a conductive material such as a single-crystal silicon substrate doped with impurities, or if a ceramic substrate or the like contains undesired impurities in a semiconductor film, a silicon dioxide film or a silicon dioxide film is deposited before the semiconductor film is deposited. It is preferable to deposit a base protective film 502 such as a silicon nitride film. In the first embodiment, the substrate 5
A silicon oxide film having a thickness of about 200 nm was deposited on the substrate 01 by plasma enhanced chemical vapor deposition (PECVD) to form a base protective film 502. After depositing the base protective film, the substrate is heated at 1000 ° C. in nitrogen.
A first heat treatment of 20 minutes was applied. The etching rate of the silicon oxide film after the first heat treatment in an aqueous solution of hydrofluoric acid (HF) having a liquid temperature of 25 ° C. and a concentration of 1.67% is 0.2 nm.
/ S. On this underlying protective film, an intrinsic amorphous silicon film was deposited to a thickness of about 100 nm by LPCVD. L
The PCVD apparatus is a hot wall type and has a capacity of 184.5.
1, the total reaction area after insertion of the substrate is about 44000 cm 2 . The deposition temperature is 425 ° C. and the purity is 99.
Using disilane (Si 2 H 6 ) of 99% or more, 200 sc
cm reactor. Deposition pressure is about 1.1 Torr
Under these conditions, the deposition rate of the silicon film is 0.77 nm.
/ Min. The amorphous silicon film thus obtained was patterned to form a semiconductor film island 503.
(FIG. 5-a) Next, a silicon oxide film 504 was formed on the surface of the island 503 of the semiconductor film patterned by the thermal oxidation method. Oxidation is 10
1 atmosphere and 1 atmosphere in an atmosphere with an oxygen concentration of 5%
It took 4 hours and 15 minutes. The thermal oxidation furnace is a hot wall type having a volume of about 46 l. In the thermal oxidation furnace when the substrate is inserted, oxygen (O 2 ) having a purity of about 99.999% or more is 250.
Nitrogen (N 2 ) with sccm and purity of about 99.999% or more
Was introduced at 4750 sccm, and the oxygen concentration inside the thermal oxidation furnace was maintained at 5.0%. The furnace temperature when inserting the substrate is 80
0 ° C. When oxidizing at atmospheric pressure, air (oxygen concentration about 20.9%) enters the oxidation furnace when the substrate is inserted.
It is preferable to keep the temperature of the oxidation furnace at about 800 ° C. or lower so that the initial oxidation does not proceed significantly in the unadjusted state. When a substrate provided with a semiconductor film having a grain boundary formed by a vapor deposition method or the like is inserted into an inert atmosphere at about 700 ° C. or higher, atom migration such as recrystallization and crystallization occurs rapidly, and Since these semiconductor films have a lower density than the single crystal film, a large number of holes are formed in the semiconductor film as a result of the rapid atom transfer. Of course, this is not preferable for producing a good thin film semiconductor device. This problem is solved by placing the substrate in an oxidizing atmosphere. This is because an oxide film is formed on the surface of the semiconductor film and the movement (crystallization) of semiconductor atoms proceeds simultaneously.
This is probably because oxygen atoms replenish small voids generated between the semiconductor atoms at the stage before the generation of the huge atom movement that causes a hole in the semiconductor film. In any case, the substrate must be inserted in an oxidizing atmosphere so that no hole is formed in the semiconductor film. Moreover, in order to accurately control the oxidation process so as to obtain an oxide film thickness and film quality and a smooth interface, there is a problem even if the oxygen concentration is too high. It is desirable that they are substantially the same. After the substrate is inserted, the temperature of the oxidation furnace is increased at a rate of 10 ° C./min, and the oxidation temperature is increased to 1000 ° C. in about 20 minutes. After reaching the oxidation temperature, this state (referred to as an oxidation process) is maintained for 14 hours and 15 minutes to perform oxidation. During the period of the oxidation process from the time of substrate insertion, the above-described oxygen and nitrogen are continuously introduced into the reaction furnace, and the inside of the oxidation furnace is maintained at a desired constant atmosphere. Immediately after the completion of the oxidation process, the supply of oxygen is stopped, and 5000 sccm of nitrogen is introduced into the reaction furnace (referred to as post-oxidation treatment). At this time, the oxidation furnace temperature was still 10% of the oxidation temperature.
Keep at 00 ° C. In thermal oxidation of single crystal silicon, this post-oxidation treatment had its purpose in releasing the stress of the oxide film. In the present application, since the stress of the oxide film is completely released during the oxidation period, the main purpose is not to release the stress but to prevent unnecessary low-temperature oxidation. After the oxidation is completed, the substrate is eventually taken out of the reaction furnace. At this time, the quality of the interface between the polycrystalline semiconductor film and the oxide semiconductor film is prevented from deteriorating. The post-oxidation treatment is therefore continued until the inside of the reactor becomes inactive with respect to the semiconductor film (the residual ratio of gas introduced into the oxidation process is less than about 5%). Assuming a complete mixing system in which fluid mixing is the slowest, the post-oxidation treatment time (30 in this embodiment 1) is set to the inert gas flow rate (5 slm of nitrogen in this embodiment 1).
Min) and the total amount of inert gas multiplied by 5 min.
slm × 30 minutes = 150 l) is the reactor volume (Example 1)
In this case, it is preferable to set the flow rate and time of the inert gas in the post-oxidation treatment so as to be about three times or more of 46 l). This is because if the ratio is about three times or more, the remaining ratio becomes less than about 5%. After the atmosphere in the reactor is replaced, the temperature of the reactor is lowered to about 800 ° C. at a rate of about 5 ° C./min.
Thereafter, the substrate is taken out of the reactor. The temperature when the substrate comes into contact with air is desirably about 800 ° C. or less to prevent low-temperature oxidation. In this way, the oxidation of the surface of the semiconductor film is completed, the silicon film changes to a polycrystalline state, and its film thickness is reduced to about 68 nm. The silicon oxide film 5 formed on the surface of the semiconductor film
04 has a thickness of about 58 nm. Next, in order to adjust the threshold voltage of the thin film semiconductor device, 11 B + was implanted into the semiconductor film at an acceleration voltage of 20 kV and a concentration of 1.2 × 10 12 cm −2 .

【0036】引き続いてドナー又はアクセプターを含ん
だ硅素膜に依りゲート電極505を形成する。本実施例
1では燐を含んだ500nmの多結晶硅素にてゲート電
極を作成した。この時のゲート電極のシート抵抗は15
Ω/□で有った。次にゲート電極をマスクとして、ドナ
ー又はアクセプターとなる不純物イオン506を打ち込
み、ソース・ドレイン領域507とチャンネル形成領域
508をゲート電極に対して自己整合的に作成する。本
実施例1ではCMOS薄膜半導体装置を作製した。NM
OSトランジスタを作製する際にはPMOSトランジス
タ部をレジストで覆った上で、不純物元素として燐(31
+)を選び加速電圧50kVにて5×1015cm-2
濃度にNMOSトランジスタのソース・ドレイン領域に
打ち込んだ。反対にPMOSトランジスタを作製する際
にはNMOSトランジスタ部をレジストで覆った上で、
不純物元素として硼素(11+)を選び加速電圧20k
Vにて3×1015cm-2の濃度にPMOSトランジスタ
のソース・ドレイン領域に打ち込んだ。(図5−c) 次にPECVD法等で層間絶縁膜509を堆積した。層
間絶縁膜は二酸化硅素膜から成り、その膜厚は凡そ50
0nmで有った。層間絶縁膜堆積後、層間絶縁膜の焼き
締めとソース・ドレイン領域に添加された不純物元素の
活性化を兼ねて、窒素雰囲気下1000℃にて20分間
の熱処理を施した。最後にコンタクト・ホールを開穴
し、アルミニウム等で配線510を施して薄膜半導体装
置が完成した。(図5−d) この様にして作成した薄膜半導体装置の伝達特性を測定
した。測定した薄膜半導体装置のチャンネル形成領域の
長さ及び幅は其々8μmと10μmで、測定は室温にて
行われた。得られた伝達特性を図6に示す。NMOSト
ランジスタのオン状態(ソース・ドレイン電圧(Vd
s)とゲート電圧(Vgs)が共に3.3V)に於ける
ソース・ドレイン電流(Ids:オン電流と称す)は2
7.6μAと成り、Vds=3.3V、Vgs=0Vで
トランジスタをオフ状態にした時のIds(オフ電流と
称す)は2.26pAで有った。又、このトランジスタ
のVds=5Vに於ける飽和領域より求めた移動度は1
60cm2・V・s-1で有り、閾値電圧は1.07Vで
有った。更にPMOSトランジスタのオン電流(Vds
=Vgs=−3.3V)は1.92μAで、オフ電流
(Vds=−3.3V、Vgs=0V)は0.134p
Aで有った。PMOSトランジスタの移動度と閾値電圧
は其々81cm2・V・s-1と−2.92Vで有った。
N型とP型の両薄膜半導体装置共にゲート電圧3.3V
の変調に対するオン・オフ比が実に7桁以上と成り、然
も高移動度で低閾値電圧を有する窮めて良好な薄膜半導
体装置が得られた。この例が示す様に本発明に依ると工
程最高温度が1000℃程度で有っても、特別な工程を
付加する事なく、単に熱酸化時の工程を厳密に調整する
事のみで非常に優れた特性を有する薄膜半導体装置を簡
便且つ容易に作成し得るので有る。
Subsequently, a gate electrode 505 is formed by a silicon film containing a donor or an acceptor. In the first embodiment, the gate electrode is formed of 500 nm polycrystalline silicon containing phosphorus. The sheet resistance of the gate electrode at this time is 15
Ω / □. Next, using the gate electrode as a mask, an impurity ion 506 serving as a donor or an acceptor is implanted to form a source / drain region 507 and a channel formation region 508 in a self-aligned manner with respect to the gate electrode. In the first embodiment, a CMOS thin film semiconductor device was manufactured. NM
When an OS transistor is manufactured, a PMOS transistor portion is covered with a resist, and phosphorus ( 31) is used as an impurity element.
P + ) was implanted into the source / drain region of the NMOS transistor at an acceleration voltage of 50 kV to a concentration of 5 × 10 15 cm −2 . Conversely, when fabricating a PMOS transistor, cover the NMOS transistor part with resist,
Accelerating voltage 20k select boron (11 B +) as the impurity element
V was implanted into the source / drain region of the PMOS transistor at a concentration of 3 × 10 15 cm −2 . (FIG. 5-c) Next, an interlayer insulating film 509 was deposited by a PECVD method or the like. The interlayer insulating film is composed of a silicon dioxide film, and its film thickness is about 50.
It was 0 nm. After the deposition of the interlayer insulating film, a heat treatment was performed at 1000 ° C. for 20 minutes in a nitrogen atmosphere for the purpose of both baking the interlayer insulating film and activating the impurity element added to the source / drain regions. Finally, a contact hole was opened, and a wiring 510 was formed with aluminum or the like, whereby a thin film semiconductor device was completed. (FIG. 5-d) The transfer characteristics of the thin-film semiconductor device thus prepared were measured. The length and width of the channel forming region of the thin film semiconductor device measured were 8 μm and 10 μm, respectively, and the measurement was performed at room temperature. FIG. 6 shows the obtained transfer characteristics. NMOS transistor ON state (source / drain voltage (Vd
s) and the gate voltage (Vgs) are both 3.3 V), the source / drain current (Ids: referred to as on-current) is 2
7.6 μA, and Ids (referred to as off-state current) when the transistor was turned off at Vds = 3.3 V and Vgs = 0 V was 2.26 pA. The mobility of this transistor obtained from the saturation region at Vds = 5 V is 1
It was 60 cm 2 · V · s -1 and the threshold voltage was 1.07 V. Furthermore, the ON current of the PMOS transistor (Vds
= Vgs = -3.3V) is 1.92 μA, and the off current (Vds = -3.3V, Vgs = 0V) is 0.134p
A. The mobility and threshold voltage of the PMOS transistor were 81 cm 2 · V · s -1 and -2.92 V, respectively.
Gate voltage 3.3V for both N-type and P-type thin film semiconductor devices
The on / off ratio with respect to the modulation was actually 7 digits or more, and a very good thin film semiconductor device having a high mobility and a low threshold voltage was obtained. As shown in this example, according to the present invention, even when the maximum process temperature is about 1000 ° C., it is very excellent only by strictly adjusting the thermal oxidation process without adding a special process. This makes it possible to easily and easily produce a thin film semiconductor device having the above characteristics.

【0037】(比較例1)本願発明が従来技術に比べて
優れて居る事を明示する為に、実施例1に対する従来技
術を此処で披露する。
(Comparative Example 1) In order to clearly show that the present invention is superior to the prior art, the prior art for Example 1 will be described here.

【0038】比較例1では熱酸化工程を除いて他の総て
の工程を実施例1と同一として薄膜半導体装置を作製し
た。酸化は1000℃の温度で酸素濃度100%の雰囲
気下にて1気圧で1時間3分行なわれた。熱酸化炉は実
施例1で使用した物と同じで有る。基板挿入時の熱酸化
炉内には純度99.999%程度以上の酸素(O2)が
5000sccm導入されて居る。基板挿入時の炉内温
度は1000℃で有る。従って基板挿入後直ちに酸化が
始まる。基板挿入時から酸化過程の期間中、反応炉には
常に酸素が5000sccm導入され続ける。1時間3
分の酸化過程が終了した後直ちに酸素の供給を断ち、反
応炉には窒素を5000sccm導入する(酸化後処
理)。酸化後処理時間は15分間で有った。酸化後処理
が終了してから基板は反応炉から取り出される。基板挿
入から基板取り出し迄の全期間を通じて反応炉の温度は
1000℃に保たれて居た。比較例1では斯様にして半
導体膜表面の酸化が終了した。酸化後の多結晶硅素膜は
72nmの厚みを有し、多結晶硅素膜表面に形成された
酸化硅素膜の厚みは60nmで有った。以下実施例1と
同じ工程でCMOS薄膜半導体装置を作製した。
In Comparative Example 1, a thin film semiconductor device was manufactured in the same manner as in Example 1 except for all steps except for the thermal oxidation step. The oxidation was performed at 1000 ° C. in an atmosphere having an oxygen concentration of 100% at 1 atm for 1 hour and 3 minutes. The thermal oxidation furnace is the same as that used in Example 1. Oxygen (O 2 ) having a purity of about 99.999% or more is introduced into the thermal oxidation furnace when the substrate is inserted at 5000 sccm. The furnace temperature at the time of substrate insertion is 1000 ° C. Therefore, oxidation starts immediately after the substrate is inserted. Oxygen is constantly introduced at 5000 sccm into the reactor during the oxidation process from the time of substrate insertion. 1 hour 3
Immediately after the oxidation process for one minute is completed, the supply of oxygen is stopped, and 5000 sccm of nitrogen is introduced into the reaction furnace (post-oxidation treatment). The post-oxidation treatment time was 15 minutes. After the post-oxidation treatment is completed, the substrate is taken out of the reaction furnace. The temperature of the reactor was maintained at 1000 ° C. throughout the period from substrate insertion to substrate removal. In Comparative Example 1, the oxidation of the semiconductor film surface was completed in this manner. The oxidized polycrystalline silicon film had a thickness of 72 nm, and the thickness of the silicon oxide film formed on the surface of the polycrystalline silicon film was 60 nm. Hereinafter, a CMOS thin film semiconductor device was manufactured in the same steps as in Example 1.

【0039】比較例1で得られた薄膜半導体装置の伝達
特性を図7に示す。NMOSトランジスタのオン電流は
17.6μAで、オフ電流は1.59pAで有った。一
方、PMOSトランジスタのオン電流は1.04μA
で、オフ電流は0.359pAで有った。移動度と閾値
電圧は図7中に記入して有る。この比較例1より本願発
明の実施例1の優性が明瞭と化そう。
FIG. 7 shows the transfer characteristics of the thin film semiconductor device obtained in Comparative Example 1. The ON current of the NMOS transistor was 17.6 μA, and the OFF current was 1.59 pA. On the other hand, the ON current of the PMOS transistor is 1.04 μA
And the off-state current was 0.359 pA. The mobility and the threshold voltage are entered in FIG. The superiority of Example 1 of the present invention is likely to be clearer than Comparative Example 1.

【0040】(実施例2)本願発明の別な実施例を此処
で示す。
Embodiment 2 Another embodiment of the present invention is shown here.

【0041】実施例2では酸化対象物質で有る半導体膜
の形成工程を除いて他の総ての工程を実施例1と同一と
して薄膜半導体装置を作製した。半導体膜は下地保護膜
上にLPCVD法にて真性多結晶硅素膜を100nm程
度の膜厚で形成された。LPCVD装置は実施例1で使
用された物と同じで有る。堆積温度は615℃で原料ガ
スとして純度99.99%以上のモノシラン(Si
4)を用い、70sccm反応炉に供給した。堆積圧
力は凡そ70mTorrで有り、此の条件下で多結晶硅
素膜の堆積速度は3.4nm/minで有った。以下実
施例1と同じ工程でCMOS薄膜半導体装置を作製し
た。尚、熱酸化後の多結晶硅素膜は60nmの厚みを有
し、多結晶硅素膜表面に形成された酸化硅素膜の厚みは
68nmで有った。
In Example 2, a thin-film semiconductor device was manufactured in the same manner as in Example 1 except that all the steps were the same except for the step of forming a semiconductor film which was a substance to be oxidized. As the semiconductor film, an intrinsic polycrystalline silicon film having a thickness of about 100 nm was formed on the underlying protective film by the LPCVD method. The LPCVD apparatus is the same as that used in the first embodiment. The deposition temperature is 615 ° C., and monosilane (Si
H 4 ) and fed to a 70 sccm reactor. The deposition pressure was approximately 70 mTorr, and under these conditions, the deposition rate of the polycrystalline silicon film was 3.4 nm / min. Hereinafter, a CMOS thin film semiconductor device was manufactured in the same steps as in Example 1. The polycrystalline silicon film after the thermal oxidation had a thickness of 60 nm, and the thickness of the silicon oxide film formed on the surface of the polycrystalline silicon film was 68 nm.

【0042】実施例2で得られた薄膜半導体装置の伝達
特性を図8に示す。NMOSトランジスタのオン電流は
4.34μAで、オフ電流は0.622pAで有った。
一方、PMOSトランジスタのオン電流は1.02μA
で、オフ電流は2.21pAで有った。移動度と閾値電
圧は図8中に記入して有る。多結晶硅素膜に本願発明に
則する1000℃の熱酸化を施して得られた薄膜半導体
装置の特性は、多結晶硅素膜に従来技術で1200℃の
熱酸化を施して得られる薄膜半導体装置の特性と略同等
と成った。この実施例2が示す通り、本願発明は実質的
に酸化温度を200℃程度以上低下せしめるとの優れた
効果を有して居る。
FIG. 8 shows the transfer characteristics of the thin film semiconductor device obtained in Example 2. The ON current of the NMOS transistor was 4.34 μA, and the OFF current was 0.622 pA.
On the other hand, the ON current of the PMOS transistor is 1.02 μA
The off-state current was 2.21 pA. The mobility and the threshold voltage are entered in FIG. The characteristics of a thin-film semiconductor device obtained by subjecting a polycrystalline silicon film to thermal oxidation at 1000 ° C. according to the present invention are as follows. It was almost equivalent to the characteristics. As shown in Example 2, the present invention has an excellent effect of substantially lowering the oxidation temperature by about 200 ° C. or more.

【0043】(比較例2)実施例2の本願発明が従来技
術に比べて確かに優れて居る事を明示する為に、実施例
2に対する従来技術を比較例2として此処で披露する。
(Comparative Example 2) In order to clearly show that the present invention of Example 2 is superior to the prior art, the prior art for Example 2 will be presented here as Comparative Example 2.

【0044】比較例2では熱酸化工程を除いて他の総て
の工程を実施例2と同一として薄膜半導体装置を作製し
た。酸化対象物質で有る半導体膜を実施例2に記載され
た方法で形成し、熱酸化は比較例1にて示された方法を
以て行われた。即ち、比較例2ではLPCVD法で得ら
れた多結晶硅素膜を1000℃の酸素分圧1気圧の雰囲
気下で熱酸化して薄膜半導体装置を作製するので有る。
熱酸化時間は1時間3分で有った。熱酸化後の多結晶硅
素膜は65nmの厚みを有し、多結晶硅素膜表面に形成
された酸化硅素膜の厚みは56nmで有った。此以外は
実施例2と同じ工程でCMOS薄膜半導体装置を作製し
た。
In Comparative Example 2, a thin film semiconductor device was manufactured in the same manner as in Example 2 except for all the steps except for the thermal oxidation step. A semiconductor film to be oxidized was formed by the method described in Example 2, and thermal oxidation was performed by the method described in Comparative Example 1. That is, in Comparative Example 2, the polycrystalline silicon film obtained by the LPCVD method is thermally oxidized in an atmosphere of 1000 ° C. and an oxygen partial pressure of 1 atm to produce a thin film semiconductor device.
The thermal oxidation time was 1 hour and 3 minutes. The polycrystalline silicon film after the thermal oxidation had a thickness of 65 nm, and the thickness of the silicon oxide film formed on the surface of the polycrystalline silicon film was 56 nm. Except for this, a CMOS thin film semiconductor device was manufactured in the same steps as in Example 2.

【0045】比較例2で得られた薄膜半導体装置の伝達
特性を図9に示す。NMOSトランジスタのオン電流は
0.568μAで、オフ電流は1.14pAで有った。
一方、PMOSトランジスタのオン電流は0.100μ
Aで、オフ電流は0.972pAで有った。移動度と閾
値電圧は図9中に記入して有る。この比較例2を実施例
2と比べれたならば、本願発明の優位は自明で有ろう。
FIG. 9 shows the transfer characteristics of the thin film semiconductor device obtained in Comparative Example 2. The ON current of the NMOS transistor was 0.568 μA, and the OFF current was 1.14 pA.
On the other hand, the ON current of the PMOS transistor is 0.100 μ
At A, the off-state current was 0.972 pA. The mobility and the threshold voltage are entered in FIG. If this Comparative Example 2 is compared with Example 2, the advantage of the present invention will be obvious.

【0046】(実施例3)図10(a)〜(d)はMO
S型電界効果トランジスタを形成する薄膜半導体装置の
製造工程を断面で示した図で有る。本実施例3では基板
1001として石英ガラスを用いた。然るに此以外の基
板で有っても、薄膜半導体装置製造工程中の最高温度に
耐えられれば、その種類や大きさは無論問われない。ま
ず基板1001上に下地保護膜1002と成る酸化硅素
膜を堆積する。基板が高濃度に不純物がドープされた単
結晶硅素基板等の導伝性物質の場合や、セラミックス基
板等で半導体膜に取って望ましからざる不純物を含んで
いる場合、酸化硅素膜堆積前に酸化タンタル膜や窒化硅
素膜等の第一の下地保護膜を堆積しても良い。本実施例
3では基板1001上にプラズマ化学気相堆積法(PE
CVD法)で酸化硅素膜を200nm程度堆積し、下地
保護膜1002とした。
(Embodiment 3) FIGS. 10A to 10D show MOs.
FIG. 5 is a cross-sectional view illustrating a manufacturing process of the thin-film semiconductor device for forming the S-type field-effect transistor. In the third embodiment, quartz glass was used as the substrate 1001. However, the type and size of other substrates are not limited as long as they can withstand the maximum temperature during the thin film semiconductor device manufacturing process. First, a silicon oxide film serving as a base protective film 1002 is deposited on a substrate 1001. If the substrate is made of a conductive material such as a single-crystal silicon substrate doped with impurities at a high concentration, or if a ceramic substrate or the like contains undesired impurities in a semiconductor film, before depositing the silicon oxide film, A first underlying protective film such as a tantalum oxide film or a silicon nitride film may be deposited. In the third embodiment, a plasma enhanced chemical vapor deposition (PE)
A silicon oxide film was deposited to a thickness of about 200 nm by a CVD method to form a base protective film 1002.

【0047】下地保護膜堆積後基板を次の手順で洗浄し
た。
After depositing the underlayer protective film, the substrate was washed in the following procedure.

【0048】(1)超音波照射に依るイソプロピルアル
コール洗浄(27℃、5分間) (2)窒素バブリングされた純水洗浄(27℃、5分
間) (3)アンモニア過水洗浄(80℃、5分間) (4)窒素バブリングされた純水洗浄(27℃、5分
間) (5)硫酸過水洗浄(97℃、5分間) (6)窒素バブリングされた純水洗浄(27℃、5分
間) (7)希釈弗酸水溶液(弗酸濃度1.67%)洗浄(2
7℃、20秒間) (8)窒素バブリングされた純水洗浄(27℃、5分
間) 上記7番目の希釈弗酸水溶液洗浄により、下地酸化膜の
表層部が凡そ10nm除去されて居る。斯うして洗浄さ
れた下地保護膜上に真性非晶質硅素膜をLPCVD法に
て100nm程度の膜厚に堆積した。上記8番目の純水
洗浄が終了してから基板がLPCVD装置の成膜室に設
置される迄の時間は約25分間で有った。
(1) Isopropyl alcohol cleaning by ultrasonic irradiation (27 ° C., 5 minutes) (2) Nitrogen bubbling pure water cleaning (27 ° C., 5 minutes) (3) Ammonia / hydrogen cleaning (80 ° C., 5 minutes) (4) Cleaning with pure water with nitrogen bubbling (27 ° C., 5 minutes) (5) Cleaning with sulfuric acid and peroxide (97 ° C., 5 minutes) (6) Cleaning with nitrogen bubbling and pure water (27 ° C., 5 minutes) (7) Washing with diluted hydrofluoric acid aqueous solution (hydrofluoric acid concentration 1.67%)
(8 ° C., 20 seconds) (8) Nitrogen-bubbled pure water cleaning (27 ° C., 5 minutes) The surface layer portion of the base oxide film is removed by about 10 nm by the seventh diluted hydrofluoric acid aqueous solution cleaning. An intrinsic amorphous silicon film was deposited to a thickness of about 100 nm by LPCVD on the thus-washed base protective film. The time from completion of the eighth pure water cleaning until the substrate was set in the film forming chamber of the LPCVD apparatus was about 25 minutes.

【0049】LPCVD装置はホット・ウォール型で容
積が184.5l有り、基板挿入後の反応総面積は約4
4000cm2で有る。成膜室に於ける最大排気速度は
120sccm/mTorrで有る。堆積温度は425
℃で、此の温度にて1時間15分間に渡る基板の加熱乾
燥処理が施された。乾燥熱処理の最中、基板が設置され
た成膜室には純度が99.9999%以上のヘリウム
(He)を200(sccm)と純度が99.9999
%以上の水素(H2)を100(sccm)導入し、成
膜室の圧力は約2.5mTorrに保たれた。乾燥処理
後に成膜室を孤立させた際の成膜室内圧力上昇は9.7
×10-6Torr/minで有ったから、成膜室への装
置外部からの漏洩流量(QL)と基板からの脱ガス流量
の和で有る総不純物漏洩流量(QTL)はボイル・シャル
ルの法則に則り、 QTL(sccm)=273.15(K)/698.15
(K)×9.7×10-6(Torr/min)/760
(Torr)×184.5×103(cm3)=9.21
×10-4(sccm) で有る。原料ガスで有る純度99.99%以上のジシラ
ン(Si26)は200sccmの流量で成膜室に供給
されたから、総不純物漏洩流量(QTL)に対する高次シ
ランの比(QTL/QSiH)は4.605×10-6と成
る。従って、当然漏洩流量(QL)の高次シラン流量
(QSiH)に対する比(R=QL/QSiH)は4.605
ppm以下で有る。斯うした乾燥処理が終了した半導体
膜堆積直前の成膜室背景真空度は、425℃に於ける温
度平衡条件で2.4×10-7Torrで有った。非晶質
硅素膜堆積時に於ける堆積圧力は凡そ1.1Torrで
有り、此の条件下で硅素膜の堆積速度は0.77nm/
minで有る。
The LPCVD apparatus is a hot wall type, has a volume of 184.5 l, and has a total reaction area of about 4 after the substrate is inserted.
4000 cm 2 . The maximum pumping speed in the film forming chamber is 120 sccm / mTorr. Deposition temperature is 425
The substrate was heated and dried at this temperature for 1 hour and 15 minutes at this temperature. During the drying heat treatment, helium (He) with a purity of 99.9999% or more was set to 200 (sccm) and the purity was 99.99999 in the film formation chamber in which the substrate was installed.
% Or more of hydrogen (H 2 ) was introduced at 100 (sccm), and the pressure in the film forming chamber was maintained at about 2.5 mTorr. The pressure rise in the film formation chamber when the film formation chamber is isolated after the drying treatment is 9.7.
Since it was × 10 −6 Torr / min, the total impurity leakage flow rate (Q TL ), which is the sum of the leakage flow rate (Q L ) from the outside of the apparatus to the film formation chamber and the degassing flow rate from the substrate, was Boyle Charles Q TL (sccm) = 273.15 (K) /698.15
(K) × 9.7 × 10 -6 (Torr / min) / 760
(Torr) × 184.5 × 10 3 (cm 3 ) = 9.21
× 10 -4 (sccm). Disilane (Si 2 H 6 ) having a purity of 99.99% or more, which is a raw material gas, was supplied to the film formation chamber at a flow rate of 200 sccm. Therefore, the ratio of the higher order silane to the total impurity leakage flow rate (Q TL ) (Q TL / Q) SiH ) is 4.605 × 10 -6 . Therefore, naturally the ratio the higher silane flow rate (Q SiH) of leak rate (Q L) (R = Q L / Q SiH) is 4.605
ppm or less. The background vacuum in the film forming chamber immediately before the deposition of the semiconductor film after the completion of the drying process was 2.4 × 10 −7 Torr under the temperature equilibrium condition of 425 ° C. The deposition pressure during the deposition of the amorphous silicon film is about 1.1 Torr, and under these conditions, the deposition rate of the silicon film is 0.77 nm /
min.

【0050】次に斯うして得られた非晶質半導体膜に熱
処理を施して、非晶質膜を固相にて結晶化させた。熱処
理は大気圧の窒素99%と酸素1%の混合気体雰囲気下
にて、600℃の温度で24時間行われた。この熱処理
に依り半導体膜は非晶質状態から多結晶状態へと改質さ
れる。斯様にして得られた結晶性硅素膜をパターニング
加工して半導体膜の島1003を形成した。(図10−
a) 次に熱酸化法にてパターニング加工された半導体膜の島
1003表面に酸化硅素膜1004を形成した。酸化は
1000℃の温度で酸素濃度5%の雰囲気下にて1気圧
で14時間15分行なわれた。熱酸化炉はホット・ウォ
ール型で容積が約46lで有る。基板挿入時の熱酸化炉
内には純度99.999%程度以上の酸素(O2)が2
50sccmと純度99.999%程度以上の窒素(N
2)が4750sccm導入され、熱酸化炉内部の酸素
濃度を5.0%に保って居る。基板挿入時の炉内温度は
800℃で有る。大気圧で酸化を行う場合、基板挿入時
に空気(酸素濃度約20.9%)が酸化炉に混入するの
で、未調整状態で初期酸化が著しく進行せぬ様に酸化炉
温度を800℃程度以下に保っておくのが好ましい。気
相堆積法等で形成された粒界を有する半導体膜が付いた
基板を700℃程度以上の不活性雰囲気中に挿入する
と、急速に再結晶化や結晶化等の原子移動が生じ、然も
此等の半導体膜は密度が単結晶膜よりも低い為、此の急
速な原子移動の結果として半導体膜に多数の穴が開いて
仕舞う。優良な薄膜半導体装置を作る上では無論これは
好ましくない。この問題は酸化性雰囲気中に基板を入れ
る事で解決される。此は半導体膜表面に酸化膜が形成さ
れるのと半導体原子の移動(結晶化)が同時に進行する
為、半導体膜に穴が開く程の巨大な原子移動が生ずる前
の段階で、半導体原子間に生じた僅かな空隙を酸素原子
が補充するからだと考えられる。いずれにしても半導体
膜に穴が開かない為には基板挿入は酸化性雰囲気でなけ
れば成らない。しかも酸化膜厚と膜質、及び平滑な界面
を得る様に酸化工程を正確に管理するには酸素濃度が高
すぎても問題で有るから、基板挿入時の酸化炉雰囲気は
酸化実行時の雰囲気と略同一で有る事が望まれる。基板
挿入後酸化炉の温度を10℃/minの昇温速度で上
げ、約20分を費やして酸化温度の1000℃とする。
酸化温度に達してから此の状態(酸化過程と称す)を1
4時間15分維持して酸化を行なう。基板挿入時から此
の酸化過程の期間中、反応炉には前述の酸素と窒素が導
入され続け、酸化炉内部を所望の一定雰囲気に保って居
る。酸化過程が終了した後直ちに酸素の供給を断ち、反
応炉には窒素を5000sccm導入する(酸化後処理
と称す)。此の時も酸化炉温度は依然として酸化温度の
1000℃に保ち続ける。単結晶硅素の熱酸化ではこの
酸化後処理は酸化膜の応力解放にその目的を有して居
た。本願では酸化膜の応力は酸化期間中に完全に解放さ
れて居るので応力解放の目的ではなく、不要な低温酸化
を防ぐ事をその主目的として居る。酸化終了後にいずれ
基板を反応炉から取り出す訳だが、その時に多結晶性半
導体膜と酸化半導体膜との界面品質が悪化せぬ様にする
ので有る。酸化後処理は従って反応炉内が半導体膜に対
して不活性状態(酸化過程に導入された気体の残存率が
5%程度未満)と成る迄継続する。流体混合が最も遅い
完全混合系を想定すると、不活性気体流量(本実施例3
では窒素5slm)に酸化後処理時間(本実施例3では
30分)を掛けた不活性気体の総量(本実施例3では窒
素5slm×30分=150l)が反応炉容積(本実施
例3では46l)の3倍程度以上と成る様に酸化後処理
の不活性気体流量や時間を設定するのが好ましい。3倍
程度以上に成れば先の残存率が5%程度未満に成るから
で有る。こうして反応炉内の雰囲気置換が済んだら反応
炉の温度を5℃/min程度の速度で800℃程度迄下
げ、然る後に基板を反応炉から取り出す。基板が空気に
触れる時の温度は低温酸化を防ぐ為に800℃程度以下
が望まれる。斯様にして半導体膜表面の酸化は終了し、
その膜厚は71nm程度へと薄く成る。又、半導体膜表
面に形成された酸化硅素膜1004の厚みは57nm程
度で有る。(図10−b) 次に薄膜半導体装置の閾値電圧を調整する為に11+
20kVの加速電圧で1.2×1012cm-2の濃度で半
導体膜に打ち込んだ。
Next, the thus obtained amorphous semiconductor film was subjected to a heat treatment to crystallize the amorphous film in a solid phase. The heat treatment was performed at a temperature of 600 ° C. for 24 hours in a mixed gas atmosphere of 99% nitrogen and 1% oxygen at atmospheric pressure. By this heat treatment, the semiconductor film is modified from an amorphous state to a polycrystalline state. The crystalline silicon film thus obtained was patterned to form a semiconductor film island 1003. (Fig. 10-
a) Next, a silicon oxide film 1004 was formed on the surface of the island 1003 of the semiconductor film patterned by the thermal oxidation method. Oxidation was performed at a temperature of 1000 ° C. in an atmosphere with an oxygen concentration of 5% at 1 atm for 14 hours and 15 minutes. The thermal oxidation furnace is a hot wall type having a volume of about 46 l. Oxygen (O 2 ) with a purity of about 99.999% or more is contained in the thermal oxidation furnace when the substrate is inserted.
Nitrogen (N) having a flow rate of 50 sccm and a purity of about 99.999% or more
2 ) was introduced at 4750 sccm, and the oxygen concentration inside the thermal oxidation furnace was maintained at 5.0%. The furnace temperature at the time of substrate insertion is 800 ° C. When oxidizing at atmospheric pressure, air (oxygen concentration about 20.9%) is mixed into the oxidizing furnace when the substrate is inserted. It is preferable to keep When a substrate provided with a semiconductor film having a grain boundary formed by a vapor deposition method or the like is inserted into an inert atmosphere at about 700 ° C. or higher, atom migration such as recrystallization and crystallization occurs rapidly, and Since these semiconductor films have a lower density than the single crystal film, a large number of holes are formed in the semiconductor film as a result of the rapid atom transfer. Of course, this is not preferable for producing a good thin film semiconductor device. This problem is solved by placing the substrate in an oxidizing atmosphere. This is because the oxide film is formed on the surface of the semiconductor film and the movement (crystallization) of the semiconductor atoms proceeds at the same time. It is presumed that the small voids generated in the above are supplemented by oxygen atoms. In any case, the substrate must be inserted in an oxidizing atmosphere so that no hole is formed in the semiconductor film. Moreover, in order to accurately control the oxidation process so as to obtain an oxide film thickness and film quality and a smooth interface, there is a problem even if the oxygen concentration is too high. It is desirable that they are substantially the same. After the substrate is inserted, the temperature of the oxidation furnace is increased at a rate of 10 ° C./min, and the oxidation temperature is increased to 1000 ° C. in about 20 minutes.
After reaching the oxidation temperature, this state (referred to as oxidation process)
The oxidation is carried out for 4 hours and 15 minutes. During the period of the oxidation process from the time of substrate insertion, the above-described oxygen and nitrogen are continuously introduced into the reaction furnace, and the inside of the oxidation furnace is maintained at a desired constant atmosphere. Immediately after the completion of the oxidation process, the supply of oxygen is stopped, and 5000 sccm of nitrogen is introduced into the reaction furnace (referred to as post-oxidation treatment). At this time, the oxidation furnace temperature is still maintained at the oxidation temperature of 1000 ° C. In thermal oxidation of single crystal silicon, this post-oxidation treatment had its purpose in releasing the stress of the oxide film. In the present application, since the stress of the oxide film is completely released during the oxidation period, the main purpose is not to release the stress but to prevent unnecessary low-temperature oxidation. After the oxidation is completed, the substrate is eventually taken out of the reaction furnace. At this time, the quality of the interface between the polycrystalline semiconductor film and the oxide semiconductor film is prevented from deteriorating. The post-oxidation treatment is therefore continued until the inside of the reactor becomes inactive with respect to the semiconductor film (the residual ratio of gas introduced into the oxidation process is less than about 5%). Assuming a complete mixing system in which fluid mixing is the slowest, an inert gas flow rate (Example 3
5 slm of nitrogen) multiplied by the post-oxidation treatment time (30 minutes in the third embodiment), the total amount of inert gas (5 slm of nitrogen x 30 minutes = 150 l in the third embodiment) is equal to the reactor volume (the third embodiment). It is preferable to set the flow rate and time of the inert gas in the post-oxidation treatment so as to be about 3 times or more of 46 l). This is because if the ratio is about three times or more, the remaining ratio becomes less than about 5%. After the replacement of the atmosphere in the reaction furnace is completed, the temperature of the reaction furnace is lowered to about 800 ° C. at a rate of about 5 ° C./min, and then the substrate is taken out of the reaction furnace. The temperature when the substrate comes into contact with air is desirably about 800 ° C. or less to prevent low-temperature oxidation. In this way, the oxidation of the semiconductor film surface ends,
The film thickness is reduced to about 71 nm. The thickness of the silicon oxide film 1004 formed on the surface of the semiconductor film is about 57 nm. (FIG. 10-b) Next, in order to adjust the threshold voltage of the thin film semiconductor device, 11 B + was implanted into the semiconductor film at an acceleration voltage of 20 kV and a concentration of 1.2 × 10 12 cm −2 .

【0051】引き続いてドナー又はアクセプターを含ん
だ硅素膜に依りゲート電極1005を形成する。本実施
例3では燐を含んだ500nmの多結晶硅素にてゲート
電極を作成した。この時のゲート電極のシート抵抗は1
5Ω/□で有った。次にゲート電極をマスクとして、ド
ナー又はアクセプターとなる不純物イオン1006を打
ち込み、ソース・ドレイン領域1007とチャンネル形
成領域1008をゲート電極に対して自己整合的に作成
する。本実施例3ではCMOS薄膜半導体装置を作製し
た。NMOSトランジスタを作製する際にはPMOSト
ランジスタ部をレジストで覆った上で、不純物元素とし
て燐(31+)を選び加速電圧50kVにて5×1015
cm-2の濃度にNMOSトランジスタのソース・ドレイ
ン領域に打ち込んだ。反対にPMOSトランジスタを作
製する際にはNMOSトランジスタ部をレジストで覆っ
た上で、不純物元素として硼素(11+)を選び加速電
圧20kVにて3×1015cm-2の濃度にPMOSトラ
ンジスタのソース・ドレイン領域に打ち込んだ。(図1
0−c) 次にPECVD法等で層間絶縁膜1009を堆積した。
層間絶縁膜は二酸化硅素膜から成り、その膜厚は凡そ5
00nmで有った。層間絶縁膜堆積後、層間絶縁膜の焼
き締めとソース・ドレイン領域に添加された不純物元素
の活性化を兼ねて、窒素雰囲気下1000℃にて20分
間の熱処理を施した。最後にコンタクト・ホールを開穴
し、アルミニウム等で配線1010を施して薄膜半導体
装置が完成した。(図10−d) この様にして作成した薄膜半導体装置の伝達特性を測定
した。測定した薄膜半導体装置のチャンネル形成領域の
長さ及び幅は其々8μmと10μmで、測定は室温にて
行われた。得られた伝達特性を図11に示す。NMOS
トランジスタのオン状態(ソース・ドレイン電圧(Vd
s)とゲート電圧(Vgs)が共に3.3V)に於ける
ソース・ドレイン電流(Ids:オン電流と称す)は6
8.5μAと成り、Vds=3.3V、Vgs=0Vで
トランジスタをオフ状態にした時のIds(オフ電流と
称す)は0.12pAで有った。又、このトランジスタ
のVds=5Vに於ける飽和領域より求めた移動度は3
95cm2・V・s-1で有り、閾値電圧は1.07Vで
有った。更にPMOSトランジスタのオン電流(Vds
=Vgs=−3.3V)は7.92μAで、オフ電流
(Vds=−3.3V、Vgs=0V)は11.1pA
で有った。PMOSトランジスタの移動度と閾値電圧は
其々102cm2・V・s-1と−1.95Vで有った。
N型とP型の両薄膜半導体装置共にサブスレシュホール
ド・スイングが小さく、且つ高移動度で低閾値電圧を有
する良好な薄膜半導体装置が得られた。取り分けNMO
S薄膜半導体装置は単結晶硅素基板に作られた電界効果
トランジスタに匹敵するとの窮めて優れた特性を示して
居る。
Subsequently, a gate electrode 1005 is formed using a silicon film containing a donor or an acceptor. In the third embodiment, a gate electrode was formed of 500 nm polycrystalline silicon containing phosphorus. At this time, the sheet resistance of the gate electrode is 1
It was 5Ω / □. Next, using the gate electrode as a mask, an impurity ion 1006 serving as a donor or an acceptor is implanted to form a source / drain region 1007 and a channel formation region 1008 in a self-aligned manner with respect to the gate electrode. In the third embodiment, a CMOS thin film semiconductor device was manufactured. When fabricating an NMOS transistor, after covering the PMOS transistor portion with a resist, phosphorus ( 31 P + ) is selected as an impurity element and 5 × 10 15 at an acceleration voltage of 50 kV.
Implanted into the source / drain region of the NMOS transistor at a concentration of cm −2 . On in making the PMOS transistor Contrary to cover the NMOS transistor portion in the resist, as the impurity element, boron (11 B +) to select the acceleration voltage of the PMOS transistor to a concentration of 3 × 10 15 cm -2 at 20kV Implanted in source / drain region. (Figure 1
0-c) Next, an interlayer insulating film 1009 was deposited by a PECVD method or the like.
The interlayer insulating film is composed of a silicon dioxide film, and its film thickness is about 5
00 nm. After the deposition of the interlayer insulating film, a heat treatment was performed at 1000 ° C. for 20 minutes in a nitrogen atmosphere for the purpose of both baking the interlayer insulating film and activating the impurity element added to the source / drain regions. Finally, a contact hole was opened, and a wiring 1010 was formed with aluminum or the like, whereby a thin film semiconductor device was completed. (FIG. 10-d) The transfer characteristics of the thin-film semiconductor device thus manufactured were measured. The length and width of the channel forming region of the thin film semiconductor device measured were 8 μm and 10 μm, respectively, and the measurement was performed at room temperature. FIG. 11 shows the obtained transfer characteristics. NMOS
Transistor ON state (source-drain voltage (Vd
s) and the gate voltage (Vgs) are both 3.3 V), the source / drain current (Ids: referred to as on-current) is 6
8.5 μA, and Ids (referred to as off-state current) when the transistor was turned off at Vds = 3.3 V and Vgs = 0 V was 0.12 pA. The mobility of this transistor obtained from the saturation region at Vds = 5 V is 3
It was 95 cm 2 · V · s -1 and the threshold voltage was 1.07 V. Furthermore, the ON current of the PMOS transistor (Vds
= Vgs = -3.3V) is 7.92 μA, and the off current (Vds = -3.3V, Vgs = 0V) is 11.1 pA
It was. The mobility and threshold voltage of the PMOS transistor were 102 cm 2 · V · s -1 and -1.95 V, respectively.
Both N-type and P-type thin-film semiconductor devices obtained good thin-film semiconductor devices having small sub-threshold swing, high mobility and low threshold voltage. NMO
S thin film semiconductor devices have shown incredibly excellent properties comparable to field effect transistors made on single crystal silicon substrates.

【0052】[0052]

【発明の効果】以上詳述してきた様に、従来低温化し得
なかった薄膜半導体装置の製造工程を本願発明は優れた
特性を維持した侭容易に低温化し得る。これに依り優良
な薄膜半導体装置を高い量産性を以て安定的に製造出来
る様に成った。
As described above in detail, the present invention can easily lower the temperature of a manufacturing process of a thin-film semiconductor device, which could not be lowered conventionally, while maintaining excellent characteristics. As a result, an excellent thin film semiconductor device can be stably manufactured with high mass productivity.

【0053】又、本願発明により単結晶硅素基板に作ら
れる電界効果型薄膜半導体装置に匹敵する性能を有する
薄膜半導体装置を簡便に製造する事が可能と化した。
Further, according to the present invention, it is possible to easily manufacture a thin film semiconductor device having a performance comparable to a field effect type thin film semiconductor device formed on a single crystal silicon substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】従来技術での酸化温度と移動度の関係を示した
図。
FIG. 1 is a diagram showing a relationship between an oxidation temperature and mobility in a conventional technique.

【図2】従来技術での酸化原理を説明した図。FIG. 2 is a view for explaining the principle of oxidation in the prior art.

【図3】本願発明での酸化原理を説明した図。FIG. 3 is a diagram illustrating the principle of oxidation in the present invention.

【図4】本願発明を実施する為の無次元係数の最大値を
示した図。
FIG. 4 is a diagram showing a maximum value of a dimensionless coefficient for implementing the present invention.

【図5】本願発明の製造工程を説明した図。FIG. 5 is a diagram illustrating a manufacturing process of the present invention.

【図6】本願発明の効果を示す図。FIG. 6 is a diagram showing the effect of the present invention.

【図7】比較例が示す図。FIG. 7 is a view showing a comparative example.

【図8】本願発明の効果を示す図。FIG. 8 is a diagram showing the effect of the present invention.

【図9】比較例が示す図。FIG. 9 is a view showing a comparative example.

【図10】本願発明の製造工程を説明した図。FIG. 10 is a diagram illustrating a manufacturing process of the present invention.

【図11】本願発明の効果を示す図。FIG. 11 is a diagram showing the effect of the present invention.

【符号の説明】 501:基板 502:下地保護膜 503:半導体膜 504:ゲート酸化膜 505:ゲート電極 506:不純物イオン 507:ソース・ドレイン領域 508:チャンネル形成領域 509:層間絶縁膜 510:配線 1001:基板 1002:下地保護膜 1003:半導体膜 1004:ゲート酸化膜 1005:ゲート電極 1006:不純物イオン 1007:ソース・ドレイン領域 1008:チャンネル形成領域 1009:層間絶縁膜 1010:配線[Description of Reference Numerals] 501: substrate 502: base protective film 503: semiconductor film 504: gate oxide film 505: gate electrode 506: impurity ion 507: source / drain region 508: channel formation region 509: interlayer insulating film 510: wiring 1001 : Substrate 1002: base protective film 1003: semiconductor film 1004: gate oxide film 1005: gate electrode 1006: impurity ion 1007: source / drain region 1008: channel formation region 1009: interlayer insulating film 1010: wiring

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5F052 AA17 DA02 DA10 DB01 DB02 DB03 DB04 DB07 JA01 5F058 BB04 BB07 BC02 BF55 BF56 BF59 BF62 BJ10 5F110 AA01 AA08 BB04 CC02 DD02 DD03 DD05 DD13 DD24 DD25 EE09 FF02 FF23 GG01 GG02 GG13 GG24 GG32 GG34 GG37 GG42 GG43 GG44 GG45 GG47 HJ01 HJ04 HJ13 HJ23 HL03 NN02 NN23 PP10 PP13  ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) GG34 GG37 GG42 GG43 GG44 GG45 GG47 HJ01 HJ04 HJ13 HJ23 HL03 NN02 NN23 PP10 PP13

Claims (23)

【特許請求の範囲】[Claims] 【請求項1】 基板上にシリコン(Si)を主体とした
半導体膜を形成する第一工程と、該半導体膜の表面を熱
酸化する第二工程とを少なくとも含む薄膜半導体装置の
製造方法に於いて、 該第一工程は気相堆積法(CVD法)にて高次シラン
(Sin2n+2:n=2,3,4)を原料気体の一種と
して非晶質膜を堆積した後に、該非晶質膜を結晶化する
事で半導体膜を形成して居る事を特徴とする薄膜半導体
装置の製造方法。
1. A method for manufacturing a thin film semiconductor device, comprising: a first step of forming a semiconductor film mainly composed of silicon (Si) on a substrate; and a second step of thermally oxidizing a surface of the semiconductor film. In the first step, an amorphous film is deposited by vapor phase deposition (CVD) using higher order silane (Si n H 2n + 2 : n = 2, 3, 4) as a source gas. A method of manufacturing a thin film semiconductor device, wherein a semiconductor film is formed by crystallizing the amorphous film.
【請求項2】 前記気相堆積法は低圧化学気相堆積法
(LPCVD法)で有る事を特徴とする請求項1記載の
薄膜半導体装置の製造方法。
2. The method according to claim 1, wherein the vapor deposition is a low pressure chemical vapor deposition (LPCVD).
【請求項3】 前記低圧化学気相堆積法は高真空型低圧
化学気相堆積装置にて行われる事を特徴とする請求項2
記載の薄膜半導体装置の製造方法。
3. The low-pressure chemical vapor deposition method according to claim 2, wherein the low-pressure chemical vapor deposition method is performed in a high-vacuum type low-pressure chemical vapor deposition apparatus.
A manufacturing method of the thin film semiconductor device according to the above.
【請求項4】 前記高真空型低圧化学気相堆積装置は半
導体膜堆積直前の背景真空度が5×10-7Torr以下
と成って居る事を特徴とする請求項3記載の薄膜半導体
装置の製造方法。
4. The thin film semiconductor device according to claim 3, wherein the high vacuum type low pressure chemical vapor deposition apparatus has a background vacuum of 5 × 10 −7 Torr or less immediately before semiconductor film deposition. Production method.
【請求項5】 前記低圧化学気相堆積法は低圧化学気相
堆積装置に於ける漏洩流量(QL)の高次シラン流量
(QSiH)に対する比(R=QL/QSiH)が10ppm
程度以下(R≦10-5)との状態で行われる事を特徴と
する請求項2記載の薄膜半導体装置の製造方法。
Wherein said low-pressure chemical vapor deposition method ratio higher silane flow rate (Q SiH) (R = Q L / Q SiH) is 10ppm for in leak rate to a low pressure chemical vapor deposition apparatus (Q L)
3. The method for manufacturing a thin film semiconductor device according to claim 2, wherein the method is performed in a state of about (R ≦ 10 −5 ) or less.
【請求項6】 前記低圧化学気相堆積法は堆積温度が4
30℃程度未満で、且つ堆積速度が0.5nm/min
程度以上の状態で行われる事を特徴とする請求項2乃至
5いずれか一項に記載の薄膜半導体装置の製造方法。
6. The low pressure chemical vapor deposition method has a deposition temperature of 4 ° C.
Less than about 30 ° C. and a deposition rate of 0.5 nm / min
6. The method for manufacturing a thin film semiconductor device according to claim 2, wherein the method is performed in a state of about or more.
【請求項7】 前記第一工程に於ける非晶質膜の結晶化
が固相にて進められる事を特徴とする請求項1乃至6い
ずれか一項に記載の薄膜半導体装置の製造方法。
7. The method for manufacturing a thin film semiconductor device according to claim 1, wherein the crystallization of the amorphous film in the first step proceeds in a solid phase.
【請求項8】 前記第一工程に於ける非晶質膜の結晶化
が、該非晶質膜を500℃程度から650℃程度の間の
所定の温度で熱処理する事に依り進められる事を特徴と
する請求項1乃至6いずれか一項に記載の薄膜半導体装
置の製造方法。
8. The crystallization of the amorphous film in the first step is performed by heat-treating the amorphous film at a predetermined temperature between about 500 ° C. and 650 ° C. The method for manufacturing a thin film semiconductor device according to claim 1.
【請求項9】 前記第一工程に於ける非晶質膜の結晶化
が、該非晶質膜を550℃程度から600℃程度の間の
所定の温度で熱処理する事に依り進められる事を特徴と
する請求項1乃至6いずれか一項に記載の薄膜半導体装
置の製造方法。
9. The crystallization of the amorphous film in the first step is performed by heat-treating the amorphous film at a predetermined temperature between about 550 ° C. and about 600 ° C. The method for manufacturing a thin film semiconductor device according to claim 1.
【請求項10】 前記第二工程を酸化性雰囲気下にて1
070℃程度未満の温度で、且つ一原子層酸化時間が酸
化膜応力緩和時間より長い条件にて行う事を特徴とする
請求項1乃至9いずれか一項に記載の薄膜半導体装置の
製造方法。
10. The method according to claim 1, wherein the second step is performed under an oxidizing atmosphere.
The method of manufacturing a thin film semiconductor device according to claim 1, wherein the method is performed at a temperature of less than about 070 ° C. and under a condition that a monoatomic layer oxidation time is longer than an oxide film stress relaxation time.
【請求項11】 前記第二工程を酸素(O2)と不活性
気体とを含む雰囲気下にて1070℃程度未満の温度T
(℃)で行い、且つ該第二工程に於ける酸素分圧
(PO2)が t1>τ t1=Δx(Δx+2xi+A)/B×60 (s) Δx=0.36 (nm) xi=5 (nm) A=A0exp(α/(k(T+273.15))) A0=0.2026 (nm) α=0.666 (eV) k=8.617×10-5 (eV・K-1) B=B0exp(−β/(k(T+273.15)))・CO20=3.14×108 (nm2・min-1) β=1.620 (eV) k=8.617×10-5 (eV・K-1) CO2=PO2(atm)/1(atm) CO2は酸素濃度に対応する無次元係数 τ=η/μ η=η0exp(γ/(k(T+273.15))) η0=2.3×10-6 (dyn・s・cm-2) γ=4.85 (eV) k=8.617×10-5 (eV・K-1) μ=3.15×1011 (dyn・cm-2) との式を満たす条件にて行う事を特徴とする請求項1乃
至8いずれか一項に記載の薄膜半導体装置の製造方法。
11. The method according to claim 1, wherein the second step is performed under an atmosphere containing oxygen (O 2 ) and an inert gas at a temperature T of less than about 1070 ° C.
(℃) carried by, and in the oxygen partial pressure in said second step (P O2) is t 1> τ t 1 = Δx (Δx + 2x i + A) / B × 60 (s) Δx = 0.36 (nm) x i = 5 (nm) A = A 0 exp (α / (k (T + 273.15))) A 0 = 0.226 (nm) α = 0.666 (eV) k = 8.617 × 10 −5 (EV · K −1 ) B = B 0 exp (−β / (k (T + 273.15))) · CO 2 B 0 = 3.14 × 10 8 (nm 2 · min −1 ) β = 1.620 (EV) k = 8.617 × 10 −5 (eV · K −1 ) CO 2 = PO 2 (atm) / 1 (atm) CO 2 is a dimensionless coefficient τ = η / μη = corresponding to the oxygen concentration. η 0 exp (γ / (k (T + 273.15))) η 0 = 2.3 × 10 −6 (dyn · s · cm −2 ) γ = 4.85 (eV) k = 8.617 × 10 − 5 (eV · K -1 method of manufacturing a thin film semiconductor device according to any one of claims 1 to 8, characterized in that performing under conditions satisfying the formula of μ = 3.15 × 10 11 (dyn · cm -2).
【請求項12】 基板上にシリコン(Si)を主体とし
た半導体膜を形成する第一工程と、該半導体膜の表面を
熱酸化する第二工程とを少なくとも含む薄膜半導体装置
の製造方法に於いて、 該第一工程に先立ち該基板に第一の熱処理を施し、 その後該第一工程では気相堆積法(CVD法)にて高次
シラン(Sin2n+2:n=2,3,4)を原料気体の
一種として非晶質膜を堆積した後に、該非晶質膜を結晶
化する事で半導体膜を形成して居る事を特徴とする薄膜
半導体装置の製造方法。
12. A method for manufacturing a thin film semiconductor device, comprising at least a first step of forming a semiconductor film mainly composed of silicon (Si) on a substrate and a second step of thermally oxidizing the surface of the semiconductor film. Prior to the first step, the substrate is subjected to a first heat treatment. Thereafter, in the first step, a higher order silane (Si n H 2n + 2 : n = 2,3) is formed by a vapor deposition method (CVD method). And 4) forming a semiconductor film by depositing an amorphous film as a kind of source gas and crystallizing the amorphous film to form a semiconductor film.
【請求項13】 前記第一の熱処理が800℃程度から
1100℃程度の間の所定の温度にて行われる事を特徴
とする請求項12記載の薄膜半導体装置の製造方法。
13. The method according to claim 12, wherein the first heat treatment is performed at a predetermined temperature between about 800 ° C. and about 1100 ° C.
【請求項14】 前記気相堆積法は低圧化学気相堆積法
(LPCVD法)で有る事を特徴とする請求項12また
は13記載の薄膜半導体装置の製造方法。
14. The method according to claim 12, wherein the vapor deposition is a low pressure chemical vapor deposition (LPCVD).
【請求項15】 前記低圧化学気相堆積法は高真空型低
圧化学気相堆積装置にて行われる事を特徴とする請求項
14記載の薄膜半導体装置の製造方法。
15. The method according to claim 14, wherein the low-pressure chemical vapor deposition is performed by a high-vacuum low-pressure chemical vapor deposition apparatus.
【請求項16】 前記高真空型低圧化学気相堆積装置は
半導体膜堆積直前の背景真空度が5×10-7Torr以
下と成って居る事を特徴とする請求項15記載の薄膜半
導体装置の製造方法。
16. The thin film semiconductor device according to claim 15, wherein said high vacuum type low pressure chemical vapor deposition apparatus has a background vacuum of 5 × 10 −7 Torr or less immediately before semiconductor film deposition. Production method.
【請求項17】 前記低圧化学気相堆積法は低圧化学気
相堆積装置に於ける漏洩流量(QL)の高次シラン流量
(QSiH)に対する比(R=QL/QSiH)が10ppm
程度以下(R≦10-5)との状態で行われる事を特徴と
する請求項14記載の薄膜半導体装置の製造方法。
17. The low-pressure chemical vapor deposition method ratio higher silane flow rate (Q SiH) (R = Q L / Q SiH) is 10ppm for in leak rate to a low pressure chemical vapor deposition apparatus (Q L)
15. The method for manufacturing a thin film semiconductor device according to claim 14, wherein the method is performed in a state where the degree is not more than about (R ≦ 10 −5 ).
【請求項18】 前記低圧化学気相堆積法は堆積温度が
430℃程度未満で、且つ堆積速度が0.5nm/mi
n程度以上の状態で行われる事を特徴とする請求項14
乃至17いずれか一項に記載の薄膜半導体装置の製造方
法。
18. The low pressure chemical vapor deposition method has a deposition temperature of less than about 430 ° C. and a deposition rate of 0.5 nm / mi.
15. The method according to claim 14, wherein the step is performed in a state of about n or more.
18. The method for manufacturing a thin film semiconductor device according to any one of claims 17 to 17.
【請求項19】 前記第一工程に於ける非晶質膜の結晶
化が固相にて進められる事を特徴とする請求項12乃至
18いずれか一項に記載の薄膜半導体装置の製造方法。
19. The method of manufacturing a thin film semiconductor device according to claim 12, wherein the crystallization of the amorphous film in the first step proceeds in a solid phase.
【請求項20】 前記第一工程に於ける非晶質膜の結晶
化が、該非晶質膜を500℃程度から650℃程度の間
の所定の温度で熱処理する事に依り進められる事を特徴
とする請求項12乃至18いずれか一項に記載の薄膜半
導体装置の製造方法。
20. A method according to claim 1, wherein the crystallization of the amorphous film in the first step is performed by heat-treating the amorphous film at a predetermined temperature between about 500 ° C. and 650 ° C. The method for manufacturing a thin-film semiconductor device according to claim 12.
【請求項21】 前記第一工程に於ける非晶質膜の結晶
化が、該非晶質膜を550℃程度から600℃程度の間
の所定の温度で熱処理する事に依り進められる事を特徴
とする請求項12乃至18いずれか一項に記載の薄膜半
導体装置の製造方法。
21. The crystallization of the amorphous film in the first step is performed by subjecting the amorphous film to a heat treatment at a predetermined temperature between about 550 ° C. and about 600 ° C. The method for manufacturing a thin-film semiconductor device according to claim 12.
【請求項22】 前記第二工程を酸化性雰囲気下にて1
070℃程度未満の温度で、且つ一原子層酸化時間が酸
化膜応力緩和時間より長い条件にて行う事を特徴とする
請求項12乃至21記載の薄膜半導体装置の製造方法。
22. The method according to claim 1, wherein the second step is performed under an oxidizing atmosphere.
22. The method of manufacturing a thin film semiconductor device according to claim 12, wherein the temperature is lower than about 070.degree. C. and the time for oxidizing the monoatomic layer is longer than the time for relaxing the oxide film stress.
【請求項23】 前記第二工程を酸素(O2)と不活性
気体とを含む雰囲気下にて1070℃程度未満の温度T
(℃)で行い、且つ該第二工程に於ける酸素分圧
(PO2)が t1>τ t1=Δx(Δx+2xi+A)/B×60 (s) Δx=0.36 (nm) xi=5 (nm) A=A0exp(α/(k(T+273.15))) A0=0.2026 (nm) α=0.666 (eV) k=8.617×10-5 (eV・K-1) B=B0exp(−β/(k(T+273.15)))・CO20=3.14×108 (nm2・min-1) β=1.620 (eV) k=8.617×10-5 (eV・K-1) CO2=PO2(atm)/1(atm) CO2は酸素濃度に対応する無次元係数 τ=η/μ η=η0exp(γ/(k(T+273.15))) η0=2.3×10-6 (dyn・s・cm-2) γ=4.85 (eV) k=8.617×10-5 (eV・K-1) μ=3.15×1011 (dyn・cm-2) との式を満たす条件にて行う事を特徴とする請求項12
乃至20いずれか一項に記載の薄膜半導体装置の製造方
法。
23. The method according to claim 23, wherein the second step is performed under an atmosphere containing oxygen (O 2 ) and an inert gas at a temperature T of less than about 1070 ° C.
(℃) carried by, and in the oxygen partial pressure in said second step (P O2) is t 1> τ t 1 = Δx (Δx + 2x i + A) / B × 60 (s) Δx = 0.36 (nm) x i = 5 (nm) A = A 0 exp (α / (k (T + 273.15))) A 0 = 0.226 (nm) α = 0.666 (eV) k = 8.617 × 10 −5 (EV · K −1 ) B = B 0 exp (−β / (k (T + 273.15))) · CO 2 B 0 = 3.14 × 10 8 (nm 2 · min −1 ) β = 1.620 (EV) k = 8.617 × 10 −5 (eV · K −1 ) CO 2 = PO 2 (atm) / 1 (atm) CO 2 is a dimensionless coefficient τ = η / μη = corresponding to the oxygen concentration. η 0 exp (γ / (k (T + 273.15))) η 0 = 2.3 × 10 −6 (dyn · s · cm −2 ) γ = 4.85 (eV) k = 8.617 × 10 − 5 (eV · K -1 claim, characterized in that performing under conditions satisfying the formula of μ = 3.15 × 10 11 (dyn · cm -2) 12
21. The method for manufacturing a thin-film semiconductor device according to any one of claims 20 to 20.
JP11070277A 1998-09-03 1999-03-16 Manufacture of thin-film semiconductor device Pending JP2000150901A (en)

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* Cited by examiner, † Cited by third party
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CN114457320A (en) * 2021-12-20 2022-05-10 泰州隆基乐叶光伏科技有限公司 Maintenance method of quartz boat

Cited By (2)

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CN114457320A (en) * 2021-12-20 2022-05-10 泰州隆基乐叶光伏科技有限公司 Maintenance method of quartz boat
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