KR100510732B1 - Method of fabricating Poly Silicon Thin Film Transistor - Google Patents

Abstract

The present invention provides a method of manufacturing a polysilicon thin film transistor having no doping damage region by effectively forming an offset or LED structure by a simple process, and applying FEMIC (Field Enhanced Metal Induced Crystalization) technology. The present invention relates to a method for manufacturing a polycrystalline silicon thin film transistor that can completely recover a region damaged by doping.

The polycrystalline silicon thin film transistor according to the present invention has no doping damage region, thereby securing the stability of the hot carrier to improve the characteristics and reliability of the device, and is manufactured by a simple process, thereby reducing the manufacturing cost and excellent in productivity.

Description

Method of manufacturing polycrystalline silicon thin film transistor {Method of fabricating Poly Silicon Thin Film Transistor}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a polysilicon thin film transistor having no regions damaged by doping.

In an active matrix liquid crystal display device using a thin film transistor as a switching element, a pixel driving thin film transistor is formed for each pixel to drive each pixel, and a thin film transistor for driving the pixel driving is used to operate a scan line and a signal line. A thin film transistor for a driving circuit that applies a signal to a data line is formed.

Among the thin film transistors, polycrystalline silicon thin film transistors can be manufactured at a temperature similar to that of amorphous silicon thin film transistors due to the development of laser crystallization technology, and have higher electron or hole mobility than the amorphous silicon thin film transistors. Complementary Metal-Oxide Semiconductor (CMOS) thin film transistors having channels can be implemented, and thus they can be simultaneously formed for driving circuits and pixel driving on large glass substrates.

In such CMOS polycrystalline silicon thin film transistors, the NMOS transistor reduces electron mobility due to Hot Carrier Stress, which has a fatal effect on the stability of circuit operation when driving the panel, and also greatly reduces off current. There is a problem.

Hereinafter, an NMOS polycrystalline silicon thin film transistor and its problems will be described in detail with reference to the accompanying drawings.

1A to 1E are cross-sectional views of a conventional NMOS polycrystalline silicon thin film transistor fabrication process.

First, as shown in FIG. 1A, an insulating material such as silicon oxide (SiO _x ) or silicon nitride (SiN _x ) is deposited on the glass substrate 101 by using chemical vapor deposition (CVD). ), And an amorphous silicon (a-si) 103 layer is formed thereon.

Thereafter, as shown in FIG. 1B, the amorphous silicon layer 103 is polycrystallized by laser annealing while maintaining the temperature of the substrate at about 400 ° C., and then patterned to form a semiconductor layer 103a.

Thereafter, as shown in FIG. 1C, an insulating material layer such as silicon oxide or silicon nitride is formed on the semiconductor layer 103a, and a conductive metal such as aluminum (Al), aluminum alloy, or molybdenum (Mo) -based metal is formed thereon. After the material is formed, the gate insulating film 104 and the gate electrode 105 are formed by patterning.

Thereafter, the semiconductor layer 103a is doped with n + ions using the gate electrode 105 as a mask.

Thereafter, as shown in FIG. 1D, the ions are activated using a laser, heat treatment at about 450 ° C., or instantaneous heat treatment.

The semiconductor layer 103a subjected to the ion implantation and activation process becomes source / drain regions 113 and 123, respectively, and is masked by the gate electrode 105 so that the semiconductor layer into which the ion is not implanted is the channel region 133. )

Thereafter, as shown in FIG. 1E, an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate including the gate electrode 105 to form an interlayer insulating film 106, and then the source / drain 113 and 123. The interlayer insulating layer 106 is etched to expose a predetermined portion of the ()) region to form first contact holes / second contact holes 117 and 127.

Thereafter, source / drain electrodes 118 and 128 connected to the source / drain regions 113 and 123 are formed through the first and second contact holes 117 and 127 to complete an NMOS polycrystalline silicon thin film transistor.

However, since the conventional NMOS polycrystalline silicon thin film transistor generally uses phosphorus (P) as a doping ion, silicon crystals are destroyed because it is relatively larger in terms of mass than boron (B) used as a doping ion in the manufacture of PMOS thin film transistors. The damaged area is generated.

In addition, when the laser is used in the activation process performed after the ion doping, the damaged region remains because the laser irradiation is difficult in the lower end portion 143 of the gate side, and the deformation of the glass substrate used in the low temperature process when thermal activation is applied Applying below 400 ° C makes it difficult to fully recover the damaged area.

As such, the remaining of the damaged region causes hot carrier stress, which in turn degrades transistor characteristics. Hereinafter, the deterioration of transistor characteristics due to hot carrier stress will be described with reference to the accompanying drawings.

FIG. 2 is a cross-sectional view for describing a characteristic deterioration of an element due to ion acceleration in a drain junction region of a conventional NMOS transistor.

As shown in FIG. 2, when the gate voltage + Vg is applied to the gate electrode 205 to reach a threshold voltage (Vth), the conductive channel region 233 is formed between the source region 213 and the drain region 223. do. At this time, electrons are accelerated from the source region 213 to the drain region 223. In the fabrication of the NMOS transistor, the lower region 243 of the gate side damaged by the induction is not activated despite the subsequent process, resulting in crystal damage. As a result, hot carrier stress is generated in which the electrons (IM) flow into the gate insulating layer 204 or the MOS interface due to electron acceleration.

The electron mobility is reduced by such a hot carrier stress, which has a fatal effect on the stability of circuit operation when driving the panel, and has a problem in that the off current is increased.

3 is a graph illustrating a characteristic change of a thin film transistor due to hot carrier stress, and as shown by the arrow of FIG. 3, on current of the transistor due to a characteristic change of a device due to hot carrier stress (On Current) ) Decreases and the off current increases, resulting in a deterioration in the characteristics of the circuit operation, resulting in a deterioration in image quality.

In order to solve this problem, an undoped region is formed in a portion between the gate and the source / drain region to give an offset to reduce the off current by reducing the electric field applied to the junction due to the large resistance of the portion (off-set). Structure), a method of forming a lightly doped drain (LDD) so as to dope a portion of the source / drain region at low concentration to reduce off current and minimize on current reduction (LDD structure), or to recover a damaged region by doping The present invention proposes a sufficient activating method, etc. Hereinafter, a conventional NMOS thin film transistor having an LDD structure will be described.

4A to 4D are cross-sectional views of a manufacturing process of an NMOS thin film transistor having a conventional LDD structure.

First, as shown in FIG. 4A, an insulating material such as silicon oxide or silicon nitride is deposited on the glass substrate 401 by chemical vapor deposition to form a buffer layer 402. Thereafter, an amorphous silicon layer is formed on the buffer layer 402, the amorphous silicon layer is polycrystallized by laser annealing while maintaining the temperature of the substrate 401 at about 400 ° C., and then patterned to form a semiconductor layer 403. do.

Thereafter, an insulating material layer such as silicon oxide or silicon nitride is formed on the semiconductor layer 403, and a conductive metal material such as aluminum (Al), aluminum alloy, or molybdenum (Mo) -based metal is formed thereon. The gate insulating film 404 and the gate electrode 405 are formed by patterning.

Thereafter, the semiconductor layer 403 is doped with n-ion using the gate electrode 405 as a mask.

Thereafter, as shown in FIG. 4B, after the photosensitive film 406 is patterned to cover a predetermined portion of the semiconductor layer 403 and the gate electrode 405, the semiconductor layer 403 using the photosensitive film 406 as a mask. Is doped with n + ions.

Then, as shown in FIG. 4C, when the photoresist layer 406 is removed, the semiconductor layer 403 may be formed of source / drain regions 413 and 423 doped with n + ions, and regions doped with n − ions (LDD doped). 443, and an undoped channel region 433.

Thereafter, as shown in FIG. 4D, an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate including the gate electrode 405 to form an interlayer insulating film 407, and then the source / drain 413 and 423. The interlayer insulating layer 407 is etched to expose a predetermined portion of the ()) region to form first contact holes / second contact holes 417 and 427.

Thereafter, source / drain electrodes 418 and 428 connected to the source / drain regions 413 and 423 through the first and second contact holes 417 and 427 are formed to form an NMOS polycrystalline silicon thin film transistor having an LDD structure. Complete

However, in the LDD NMOS polycrystalline silicon thin film transistor, the process of the photoresist film 406 is added to the process, and the process is complicated. In addition, there is still a doped damage region at the lower side of the gate side, and thus the hot carrier stress is prevented. It is impossible to fundamentally prevent the problem of deterioration of device characteristics.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a polycrystalline silicon thin film transistor in which the manufacturing process is shortened and the occurrence of damaged areas by doping is prevented.

Another object of the present invention is to provide a method of manufacturing a polycrystalline silicon thin film transistor which can completely recover a region damaged by doping.

It is still another object of the present invention to provide a method of manufacturing a polycrystalline silicon thin film transistor having excellent image quality characteristics by preventing the occurrence of hot carrier stress.

In order to achieve the above object, the present invention provides a method of manufacturing a polysilicon thin film transistor having no doped damage region by effectively forming an offset (off-set) or LED (LDD) structure by a simple process.

In addition, the present invention provides a method of manufacturing a polycrystalline silicon thin film transistor which can recover the damaged region by doping by applying FEMIC (Field Enhanced Metal Induced Crystalization) technology.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail. The first and second embodiments are directed to a method of manufacturing a polycrystalline silicon thin film transistor which forms an offset or LED structure by a simple process, and the third embodiment is a method of manufacturing a polycrystalline silicon thin film transistor using FEMIC technology. It is about.

First embodiment

5A to 5D are cross-sectional views illustrating a process of manufacturing a polysilicon thin film transistor according to a first embodiment of the present invention, and a method of forming an offset or LED structure by a simple process.

First, as shown in FIG. 5A, an insulating material such as silicon oxide or silicon nitride is deposited on the glass substrate 501 by chemical vapor deposition to form a buffer layer 502.

Thereafter, an amorphous silicon layer is deposited on the buffer layer 502, and the semiconductor layer 503 is formed by patterning and polycrystallizing the amorphous silicon layer while maintaining the substrate temperature at about 400 ° C.

Thereafter, an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate including the semiconductor layer 503 by using a chemical vapor deposition method to form a gate insulating film 504.

Thereafter, an aluminum, aluminum alloy, or molybdenum-based metal layer is formed on the gate insulating layer 504, and then patterned to form a gate electrode 505. In this case, the gate electrode 505 is preferably patterned to form an angle of 70 to 90 ° with respect to the substrate surface by using an etching process.

Thereafter, as shown in FIG. 5B, an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate including the gate electrode 505 to form an interlayer insulating film 506 by chemical vapor deposition. At this time, the interlayer insulating film is preferably formed to a thickness of less than 2000 kPa.

Thereafter, after the n + doping is performed using the gate insulating film 504 and the interlayer insulating film 506 as a doping target, the doped region is activated. In this case, phosphorus (P) is preferable as the n + doping material, and activation is preferably performed using a laser or a heat treatment method.

By the n + doping and activation process, the semiconductor layer 503 is formed such that the source / drain regions 513 and 523, the offset or LED (LDD) region 543, and the channel region 533 are formed as shown in FIG. 5C. do. That is, due to the difference in thickness between the gate insulating film 504 and the interlayer insulating film 506 used as the doping target, the relatively thin first thickness h1 region is formed of the source / drain region 513 by high concentration n + doping. 523, and the relatively thick second thickness h2 region is an offset or low concentration LDD region 543. As shown in FIG. In the region where the gate electrode 505 is formed, n + ion implantation is shielded by the gate electrode to become the channel region 533.

Thereafter, as shown in FIG. 5D, the interlayer insulating layer 506 and the gate insulating layer 504 are etched to expose predetermined portions of the source / drain regions 513 and 523, thereby forming the first contact hole and the second contact hole. (517, 527). Thereafter, source / drain electrodes 518 and 528 connected to the source / drain regions 513 and 523 are formed through the contact holes 517 and 527 to complete a polysilicon thin film transistor.

Second embodiment

6A to 6D are cross-sectional views illustrating a process of manufacturing a polysilicon thin film transistor according to a second embodiment of the present invention, except that the gate insulating film is patterned to a width corresponding to the gate electrode, and according to the first embodiment of the present invention. Is the same as

First, as shown in FIG. 6A, an insulating material such as silicon oxide or silicon nitride is deposited on the glass substrate 601 by chemical vapor deposition to form a buffer layer 602.

Thereafter, an amorphous silicon layer is deposited on the buffer layer 602, and the semiconductor layer 603 is formed by laser annealing the amorphous silicon layer to polycrystallize while maintaining a substrate temperature of about 400 ° C., and then patterning the semiconductor layer 603.

Thereafter, a gate insulating film made of silicon oxide, silicon nitride, or the like, and a gate metal of aluminum, aluminum alloy, or molybdenum type are deposited and patterned on the semiconductor layer 603 to form a gate insulating film 604 and a gate electrode 605 having a predetermined shape. ).

In this case, the patterned gate insulating film 604 and the gate electrode 605 may be formed by depositing both in order and then patterning. First, the gate insulating film 604 is deposited and patterned, and then the gate electrode layer is formed and patterned. It may be formed by.

In addition, the gate electrode 605 is preferably patterned to form an angle of 70 to 90 degrees with respect to the substrate surface by using an etching process. In the case where the gate electrode 505 is patterned to form an angle of 90 ° with respect to the substrate surface, it is effective to simultaneously deposit and then pattern the gate insulating film 604 and the gate electrode 605 in the process shortening plane.

Thereafter, as shown in FIG. 6B, an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate including the gate electrode 605 to form an interlayer insulating film 606 by chemical vapor deposition. At this time, the interlayer insulating film is preferably formed to a thickness of less than 2000 kPa.

Thereafter, after the n + doping is performed using the interlayer insulating film 606 as a doping target, the doped region is activated. In this case, phosphorus (P) is preferable as the n + doping material, and activation is preferably performed using a laser or a heat treatment method.

By the n + doping and activation process, the semiconductor layer 603 is formed such that the source / drain regions 613 and 623, the offset or LED (LDD) region 643, and the channel region 633 are formed as shown in FIG. 6C. do. That is, due to the difference in thickness of the interlayer insulating film 606 used as the doping target, the relatively thin first thickness h1 region becomes source / drain regions 613 and 623 by high concentration of n + doping, and is relatively Therefore, the thick second thickness h2 region becomes an offset or low density LED region 643. In the region where the gate electrode 605 is formed, n + ion implantation is shielded by the gate electrode to become the channel region 633.

Thereafter, as illustrated in FIG. 6D, the interlayer insulating layer 606 is etched to expose a predetermined portion of the source / drain regions 613 and 623 to form the first contact hole / secondary contact hole 617 and 627. Form. Thereafter, source / drain electrodes 618 and 628 connected to the source / drain regions 613 and 623 are formed through the contact holes 617 and 627 to complete a polysilicon thin film transistor.

As described above, the polysilicon thin film transistor according to the first and second embodiments of the present invention forms an LDD structure or an offset structure using an interlayer insulating film, or an interlayer insulating film and a gate insulating film as a doping target, thereby forming a mask like a conventional photosensitive film. Compared to the method of forming the LDD structure by using the step is shortened, it is possible to prevent the occurrence of the doping damage region.

Third embodiment

7A to 7C are cross-sectional views illustrating a manufacturing process of a polysilicon thin film transistor according to a third embodiment of the present invention, and a method of completely recovering damaged regions by doping by applying FEMIC (Field Enhanced Metal Induced Crystalization) technology.

First, as shown in FIG. 7A, an insulating material such as silicon oxide or silicon nitride is deposited on the glass substrate 701 by chemical vapor deposition to form a buffer layer 702, and then an amorphous silicon layer 703 is formed thereon. Form and pattern.

Thereafter, an insulating material such as silicon oxide or silicon nitride and a conductive metal material such as aluminum (Al), aluminum alloy, or molybdenum (Mo) -based metal are formed and patterned on the amorphous silicon layer 703 to form a gate insulating film 704. ) And the gate electrode 705 are formed.

Thereafter, n + doping is performed on the entire surface of the substrate using the gate electrode 705 as a mask. In this case, the n + doping is preferably doped with phosphorus (P).

The n + doping region of the amorphous silicon layer 703 becomes the source / drain regions 713 and 723 where n + ions are implanted, and is masked by the gate electrode 705 so that the region where no ions are implanted is a channel. Area 733.

Thereafter, as shown in FIG. 7B, an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate to form an interlayer insulating film 706, and the interlayer insulating film is exposed so that predetermined portions of the source / drain regions 713 and 723 are exposed. 706 is etched to form primary contact holes / secondary contact holes 717 and 727.

Thereafter, as shown in FIG. 7C, initial metal films 737 and 747 are formed in the first and second contact holes 717 and 727, and then source / drain electrodes 718 and 728 are formed thereon. . In this case, the initial metal layers 737 and 747 may be made of Ni or Pd, and the source / drain electrodes 718 and 728 may be made of double layers of Ni, Pd, or Ni / Al or Pd / Al. Do.

Thereafter, the amorphous silicon is polycrystallized by applying a field enhanced metal induced crystalization (FEMIC) technique, which is heat-treated to a predetermined temperature and applies an electric field, to complete the polysilicon thin film transistor.

At this time, the heat treatment is preferably performed at 400 ℃, the electric field is preferably applied at 30V / cm.

In this way, by applying the FEMIC technology, the n + doped region is activated and the region damaged by the doping generated at the lower side of the gate electrode is completely recovered. This is because the distance between the contact hole and the gate electrode is generally about 3 μm, so that metal induction crystallization easily occurs to the gate electrode.

As described above, the polycrystalline silicon thin film transistor according to the present invention has no doping damage region, thereby securing stability of the hot carrier, thereby improving the characteristics and reliability of the device.

In addition, the manufacturing cost is reduced because it is manufactured by a simple process is excellent in terms of productivity.

1A to 1E are cross-sectional views of a manufacturing process of an NMOS polycrystalline silicon thin film transistor according to the prior art.

FIG. 2 is a cross-sectional view illustrating a device deterioration due to ion acceleration in a drain junction region of an NMOS polycrystalline silicon thin film transistor manufactured according to the prior art.

3 is a graph illustrating a characteristic change due to hot carrier stress of a polycrystalline silicon thin film transistor manufactured according to the prior art.

4A through 4D are cross-sectional views illustrating a method of manufacturing a polycrystalline silicon thin film transistor having a conventional LDD structure.

5A to 5D are cross-sectional views illustrating a process of manufacturing the polycrystalline silicon thin film transistor according to the first embodiment of the present invention.

6A through 6D are cross-sectional views illustrating a process of manufacturing a polycrystalline silicon thin film transistor according to a second embodiment of the present invention.

7A to 7C are cross-sectional views illustrating a process of manufacturing a polycrystalline silicon thin film transistor according to a third embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

501 glass substrate 502 buffer layer

503: polycrystalline silicon layer (semiconductor layer) 504: gate insulating film

505: gate electrode 506: interlayer insulating film

513: source region 523: drain region

533: channel region 534: offset or LED doped region

517: first contact hole 527: second contact hole

518: source electrode 528: drain electrode

Claims (5)

Forming a buffer layer on the glass substrate; Forming and patterning an amorphous silicon layer on the buffer layer; Forming and patterning a gate insulating film and a gate metal on the amorphous silicon layer; N + doping the entire surface of the glass substrate using the gate metal as a mask to form a source / drain region; Forming an interlayer insulating film on the entire surface of the glass substrate and forming contact holes at predetermined portions to expose the source / drain regions; Forming an initial metal film in the contact hole, and then forming a source / drain electrode thereon; And And heat-treating the glass substrate to a predetermined temperature and applying an electric field to crystallize the amorphous silicon thin film transistor. The method of claim 1, The initial metal film is made of Ni or Pd, the source / drain electrode is a method of manufacturing a polycrystalline silicon thin film transistor, characterized in that consisting of a double layer of Ni, Pd or Ni / Al, Pd / Al. The method according to claim 1 or 2, The heat treatment is a method of manufacturing a polycrystalline silicon thin film transistor, characterized in that carried out at 400 ℃. The method according to claim 1 or 2, The n + doping is a method of manufacturing a polycrystalline silicon thin film transistor, characterized in that the doping (P). The method according to claim 1 or 2, The electric field is a method of manufacturing a polycrystalline silicon thin film transistor, characterized in that applied to 30V / cm.