KR100590265B1 - Method for fabricating TFT using MILC - Google Patents

Abstract

The present invention relates to a method of manufacturing a thin film transistor using a metal induced lateral crystallization method (MILC) capable of forming an offset structure or an LDD structure without an additional mask process.

A method of manufacturing a thin film transistor of the present invention includes the steps of forming a semiconductor layer of an amorphous silicon film using a first mask on an insulating substrate; Forming a gate insulating film on the substrate including the semiconductor layer; Sequentially forming a gate electrode material and a gate capping material on the gate insulating film; Patterning the gate capping material and the gate electrode material using a second mask to form a gate having a gate capping layer; Forming a spacer on a sidewall of the gate and exposing the semiconductor layer; Implanting high concentration impurities into the exposed semiconductor layer to form a high concentration source / drain region; Forming a metal film on the entire surface of the substrate; Crystallizing the semiconductor layer of the amorphous silicon film into the semiconductor layer of the polycrystalline silicon film by using a MILC method; Removing the metal film; And forming a source / drain electrode connected to the source / drain region.

Description

Method for fabricating thin film transistor using metal induced side crystallization method {Method for fabricating TFT using MILC}

1A to 1E are cross-sectional views illustrating a method of manufacturing a thin film transistor using a conventional MILC;

2A through 2E are cross-sectional views illustrating a method of manufacturing a thin film transistor using a MILC method according to an embodiment of the present invention;

<Description of the symbols for the main parts of the drawings>

20: insulating substrate 21: buffer layer

22 semiconductor layer of amorphous silicon film 23 gate insulating film

20a: semiconductor layer 24 of polycrystalline silicon film: gate

25 gate capping layer 26 spacer film for spacer

27-1, 27-2: high concentration source / drain region 28: MILC metal film

22C: Channel Area 22S, 22D: Offset Area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor having an offset or LDD structure using metal induced lateral crystallization (MILC).

In the method of forming a polycrystalline silicon film used as a semiconductor layer of a thin film transistor, an amorphous silicon film is deposited on a substrate and then crystallized at a predetermined temperature to form a polycrystalline silicon film.

Crystallization of the amorphous silicon film includes SPC (Solid Phase Crystallization) by heat treatment, Eximer Laser Anealing (ELA) by laser crystallization, MILC and the like.

The SPC method has a problem of high crystallization temperature and a long process time, and the ELA method has a problem of temporal and spatial nonuniformity due to expensive equipment investment and laser instability.

In contrast, the MILC method has a relatively low process temperature and a short process time using a conventional heat treatment facility. A method of manufacturing a thin film transistor using the MILC method has been disclosed in Korean Patent No. 10-0276378.

1A to 1E are cross-sectional views illustrating a method of manufacturing a thin film transistor using a conventional MILC method.

Referring to FIG. 1A, an amorphous silicon film is deposited on the insulating substrate 10 by using a low pressure chemical vapor deposition (LPCVD) method, and the mask (not shown) is used to form a semiconductor layer. An amorphous silicon film is patterned to form a semiconductor layer 11 made of an amorphous silicon film.

Subsequently, a gate insulating film and a gate electrode material are sequentially formed on the insulating substrate 10 including the semiconductor layer 11. Although not shown in the drawing, the gate electrode material and the gate insulating layer are patterned by using the gate forming mask to form a gate 13 having a gate insulating layer 12 thereunder on the semiconductor layer 11. At this time, the semiconductor layer 11 made of an amorphous silicon film on both sides of the gate 13 is exposed.

Referring to FIG. 1B, a high concentration impurity ion is implanted into the exposed semiconductor layer 11 to form a source region 11S and a drain region 11D which are high concentration impurity regions. In this case, the portion 11c of the semiconductor layer 11 that is not doped with impurities under the gate 13 serves as a channel region of the thin film transistor.

Referring to FIG. 1C, after the photoresist film is coated on the entire surface of the substrate, the photoresist pattern 15 is formed to have a width larger than that of the gate 13. After the photoresist pattern 15 is formed, the metal film 14 is deposited on the entire surface of the substrate by sputtering. At this time, Ni, Pd, Ti, Ag, Au, Al, Sb, or the like is used as the metal film 14.

Referring to FIG. 1D, when the photoresist pattern 15 is removed using a lift-off method, a metal film offset region 17 exposing a portion of the semiconductor layer 11 is formed.

Referring to FIG. 1E, a semiconductor layer 11 made of an amorphous silicon film is crystallized by heat treatment in a furnace to be converted into a semiconductor layer 11a of a polycrystalline silicon film. At this time, the portion 18 of the amorphous silicon film that is in contact with the metal film 14 of the semiconductor layer 11 is crystallized by a metal induced crystallization (MIC) method, and the metal film offset region 17 and the channel region 11C. Is crystallized by the MILC method.

In the conventional method for manufacturing a thin film transistor using the MILC method as described above, the boundary of the MIC region having a different crystal grain structure is located outside the channel region 11c, so that the source / drain junction regions 11S and 11D are separated. The crystal structure was the same. As a result, trapping in the channel region can be prevented, thereby improving device characteristics.

However, in the conventional method of manufacturing a thin film transistor using the MILC method, a separate mask process for forming the metal film offset region 17 is added, thereby lowering productivity and increasing production cost.

In addition, when the offset structure or the LDD structure is formed by using the conventional photoresist pattern, it is difficult to control the doping concentration according to the curing of the photoresist pattern and there is a problem in that the photoresist pattern is not easily removed.

An object of the present invention is to solve the problems of the prior art as described above, an object of the present invention is to provide a method for manufacturing a thin film transistor using a MILC method without an additional mask process.

Another object of the present invention is to provide a method of manufacturing a thin film transistor using a MILC method capable of forming an offset structure or an LDD structure without an additional mask process.

Another object of the present invention is to perform a MILC process using a spacer, and to control the doping concentration by forming an offset or LDD structure, and to simplify the process by eliminating the photoresist pattern removing process. It is an object of the present invention to provide a method for manufacturing a thin film transistor.

In order to achieve the above object of the present invention, the present invention comprises the steps of forming a semiconductor layer of an amorphous silicon film using a first mask on an insulating substrate; Forming a gate insulating film on the substrate including the semiconductor layer; Sequentially forming a gate electrode material and a gate capping material on the gate insulating film; Patterning the gate capping material and the gate electrode material using a second mask to form a gate having a gate capping layer; Forming a spacer on a sidewall of the gate and exposing the semiconductor layer; Implanting high concentration impurities into the exposed semiconductor layer to form a high concentration source / drain region; Forming a metal film on the entire surface of the substrate; Crystallizing the semiconductor layer of the amorphous silicon film into the semiconductor layer of the polycrystalline silicon film by using a MILC method; Removing the metal film; Forming the source / drain electrode; characterized in that it provides a method for manufacturing a thin film transistor comprising a.

A region of the semiconductor layer not doped with impurities under the spacer serves as an offset region, and the offset region of the semiconductor layer serves as a metal film offset region in a crystallization step using a MILC method.

And forming a low concentration source / drain region having the same conductivity type as the high concentration source / drain region in the semiconductor layers on both sides of the gate between forming the gate and forming the spacer. And the low concentration source / drain region serves as a metal film offset region in the crystallization step using the MILC method.

In the method of forming the spacer, an insulating film is formed on the entire surface of the substrate and then etched back to form a spacer on the sidewall of the gate, and the gate insulating film under the insulating film is etched to expose the semiconductor layer.

In the step of crystallizing the semiconductor layer of the amorphous silicon film to the semiconductor layer of the polycrystalline silicon film by using the MILC method, impurities in the high concentration source / drain regions are activated to reduce specific resistance.

An oxide film is used as the spacer insulating film and the gate insulating film, and one of Ni, Pd, Ti, Ag, Au, Al, and Sb is used as the metal film, and the gate capping layer is formed of a nitride film.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention through an embodiment of the present invention.

2A through 2F are cross-sectional views illustrating a method of manufacturing a thin film transistor using a MILC method according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, an oxide film 21 is formed on the insulating substrate 20 such as a corning 1737 370 mm x 400 mm glass substrate to have a thickness of 1000 kV by PECVD. The oxide layer 21 serves as a buffer layer to prevent diffusion of alkali metals such as Na or K into the channel region.

Subsequently, an amorphous silicon film is formed on the buffer layer 21 to a thickness of 500 kV by PECVD, and the semiconductor layer 22 made of an amorphous silicon film is dried by etching the amorphous silicon film using an inductively coupled plasma (ICP) method. Form.

A gate insulating film 23 is formed on the buffer layer 21 including the semiconductor layer 22, and a gate electrode material and a gate capping material are sequentially formed on the gate insulating film 23.

In this case, the gate insulating film 23 is formed by an oxide film or a nitride film with a thickness of 1000 kW by PECVD, and the gate electrode material is deposited with a thickness of 2500 kW by a sputtering method. As the gate electrode material, a single film of Al, Cr, or Mo, or a stacked film of them is used. As a gate capping material, a nitride film is formed to a thickness of 2500 kPa by PECVD.

Although not shown in the drawing, the gate electrode having the gate capping layer 25 is formed by dry etching the gate electrode material and the gate capping material using an ICP method using a gate forming mask.

The spacer insulating film 26a is formed on the gate insulating film 23 having the gate 24. The spacer insulating film 26a forms an oxide film by PECVD.

Referring to FIG. 2B, the spacer insulating layer 26a and the gate insulating layer 23 are etched back to form the spacer 26 on the sidewall of the gate 24 and expose the semiconductor layer 22. High concentration source / drain regions 27-1 and 27-2 are implanted into the exposed semiconductor layer 22 by ion implantation of high concentration impurities having an n-type or p-type conductivity.

In the case where an oxide film is used as the gate insulating film 23, the spacer insulating film 26a and the gate insulating film 23 are dry etched under the same etching conditions to form the spacer 26 and at the same time, the semiconductor layer 22 is formed. To expose it.

In this case, portions 22S and 22D of the semiconductor layer 22 which are not doped with impurities under the spacer 26 serve as offset regions of the thin film transistor, and become metal layer offset regions during the MILC process. A portion 22C below the gate 25 serves as a channel region of the thin film transistor.

Referring to FIG. 2C, the metal film 28 is formed on the entire surface of the substrate by a sputtering method to a thickness of 20 to 100 kPa. As the metal film 28, metals such as Ni, Pd, Ti, Ag, Au, Al, and Sb are used.

Referring to FIG. 2D, when the heat treatment is performed at a temperature of 500 to 600 ° C. in a furnace, activation of a high concentration impurity to reduce specific resistance of the high concentration source / drain regions 27-1 and 27-2 is achieved. At the same time, the amorphous semiconductor layers of the high concentration source / drain regions 27-1 and 27-2 are crystallized by MIC, followed by the metal film offset regions 22S, 22D and the channel region 22C. Crystallization by MILC takes place. As a result, the amorphous semiconductor layer 22 is converted into the semiconductor layer 22a of the polycrystalline silicon film.

At this time, the metal film 28 is in contact with the high concentration source / drain regions 27-1 and 27-2 in the semiconductor layer 22, and the offset regions 22S and 22D under the spacer 26 are formed. ) Is not contacted.

Therefore, since the offset region 22 acts as a metal film offset region, the high concentration source / drain regions 27-1 and 27-2 are crystallized by the MIC method, and the offset regions 22S and 22D. ) And the channel region 22C are crystallized by the MILC method.

Therefore, the trapping of the channel region can be prevented because the MIC boundary and the MILC boundary are located out of the channel region. In addition, the MIC boundary and the MILC boundary may be formed using a spacer without a separate mask process for forming a metal film offset region for positioning the outside of the channel region.

Referring to FIG. 2E, a thin film transistor according to an exemplary embodiment of the present invention is manufactured by removing the remaining metal film 28 and performing a process for forming a subsequent source / drain electrode although not shown in the drawing.

In the embodiment of the present invention, the semiconductor layer 22 has a low concentration having the same conductivity type as that of the high concentration source / drain region after the process of forming the gate 24 of FIG. 2A and before the process of forming the spacer insulating film 26a. When ion is implanted, a low concentration source / drain region may be formed under the spacer 26 to form a source / drain region having an LDD structure. In this case, the low concentration source / drain region serves as a metal film offset region in the MILC process.

The method of manufacturing a thin film transistor according to the embodiment of the present invention as described above is formed by using a spacer when performing a process for forming a metal film offset region for performing the MLIC process and the source / drain region of the offset or LDD structure No additional masking process is required for this.

Therefore, since the thin film transistor can be formed using two masks, the number of masks can be reduced as compared with the conventional method.

 According to the MILC method of the present invention as described above, according to the manufacturing method of the thin film transistor, since the interface between the MILC and the MIC is not located in the channel region, the trap phenomenon in the channel region can be prevented, thereby improving the characteristics of the device.

In addition, since an additional mask process is not required by forming a metal film offset region for performing a MILC process using a spacer, process simplicity and manufacturing cost may be reduced. In addition, since the use of the spacer eliminates the photoresist process, it is easy to control the doping concentration according to the curing of the photoresist film and solves the complexity of the process such as removing the photoresist film.

In addition, the present invention forms a source / drain region of the offset structure or the LDD structure by using the spacer, so that an additional mask process for forming the offset structure or the LDD region is not required, and the off current can be reduced. There is an advantage.

In addition, the process can be simplified by simultaneously activating the high concentration impurity injected into the amorphous semiconductor layer for the high concentration source / drain region and crystallizing the amorphous semiconductor layer.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (10)

Forming a semiconductor layer of an amorphous silicon film using a first mask on the substrate; Forming a gate insulating film on the substrate including the semiconductor layer; Sequentially forming a gate electrode material and a gate capping material on the gate insulating film; Patterning the gate capping material and the gate electrode material using a second mask to form a gate having a gate capping layer; Forming a spacer on a sidewall of the gate and exposing the semiconductor layer; Implanting high concentration impurities into the exposed semiconductor layer to form a high concentration source / drain region; Forming a metal film on the entire surface of the substrate; Crystallizing the semiconductor layer of the amorphous silicon film into the semiconductor layer of the polycrystalline silicon film by using a MILC method; Removing the metal film; And forming a source / drain electrode connected to the source / drain region. The method of claim 1, wherein a region of the semiconductor layer not doped with impurities under the spacer serves as an offset region. The method of claim 2, wherein the offset region of the semiconductor layer serves as a metal film offset region in a crystallization step using a MILC method. 2. The method of claim 1, further comprising forming a low concentration source / drain region having the same conductivity type as the high concentration source / drain region in the semiconductor layers on both sides of the gate between forming the gate and forming the spacer. The method of manufacturing a thin film transistor further comprising forming an LDD structure. 5. The method of claim 4, wherein the low concentration source / drain region acts as a metal film offset region in the crystallization step using the MILC method. The method of claim 1, wherein one of Ni, Pd, Ti, Ag, Au, Al, and Sb is used as the metal film. The method of claim 1, wherein the spacer is formed by forming an insulating film on the entire surface of the substrate and then etching back to form a spacer on the sidewall of the gate, and simultaneously etching the gate insulating film under the insulating film to expose the semiconductor layer. A method of manufacturing a thin film transistor, characterized in that 8. The method of manufacturing a thin film transistor according to claim 7, wherein an oxide film is used as the spacer insulating film and the gate insulating film. The thin film according to claim 1, wherein in the step of crystallizing the semiconductor layer of the amorphous silicon film into the semiconductor layer of the polycrystalline silicon film by using the MILC method, impurities in the high concentration source / drain regions are activated to reduce specific resistance. Method for manufacturing a transistor. The method of claim 1, wherein the gate capping layer is formed of a nitride film.

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