JP2000206569A - Electrooptical device, driving substrate for electrooptical device and their production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for the production of an active matrix substrate housing a high performance driver by uniformly forming a single crystal silicon layer having high electron/hole mobility at a rather low temp., and for the production of an electrooptical device such as a thin film semiconductor device for a display using this active matrix substrate. SOLUTION: A gate part comprising a gate electrode and gate insulating film is formed on one surface of a first substrate 1, and further steps 4 are formed on the surface of the first substrate 1. Then a molten liquid layer 6 of a low melting point metal comprising tin, lead or an alloy of tin and lead containing a semiconductor is formed on the substrate 1 and cooled so as to graphoepitaxially grow a single crystal semiconductor layer 7 from the steps 4 as the seed. Then channel region, source region and drain region are formed in the single crystal semiconductor layer 7. Thus, bottom gate type first thin film transistors which have the gate part under the channel region and constitute a part of peripheral driving circuits are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device, a driving substrate for the electro-optical device, and a method for manufacturing the same. The present invention relates to a structure having a bottom gate type thin film insulated gate field effect transistor (hereinafter, referred to as a bottom gate type MOSTFT) to be used and a method of manufacturing the same.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device has a display portion using amorphous silicon for a TFT and an external driving circuit IC, and a display using a polycrystalline silicon for a TFT by a solid phase growth method. (Japanese Unexamined Patent Publication (Kokai) No. 6-242433), and an integrated type of a display unit and a drive circuit using excimer laser-annealed polycrystalline silicon for a TFT (Japanese Unexamined Patent Publication No. 7-131)
030) is known.

[0003]

However, in the above-mentioned conventional amorphous silicon TFT, although the productivity is good, the electron mobility is as low as about 0.5 to 1.0 cm ² / v · sec. (Hereafter, pM
It is called OSFT. ) Can not be made. Therefore, this pMOST is formed on the same glass substrate as the display unit.
Since a peripheral drive unit using FT cannot be formed, and a driver IC is mounted externally and mounted by a TAB method or the like, cost reduction is difficult, and there is a limit to high definition. is there. Furthermore, electron mobility is 0.5-1.
Since it is as low as about 0 cm ² / v · sec, sufficient on-current cannot be obtained, and the transistor size is inevitably increased when used in a display portion, which is disadvantageous for increasing the pixel aperture ratio. I have.

Further, the conventional polycrystalline silicon TF described above is used.
At T, the electron mobility is 70 to 100 cm ² / v · s
ec, which can cope with high definition. Therefore, recently, an LCD using a polycrystalline silicon TFT integrated with a driving circuit has been developed.
(Liquid crystal display devices) are attracting attention. However, 1
In the case of a large LCD of 5 inches or more, since the electron mobility of polycrystalline silicon is 70 to 100 cm ² / v · sec, the driving capability is insufficient, and eventually, an external driving circuit IC is required. ing.

In a TFT using polycrystalline silicon formed by a solid phase growth method, annealing is performed at a temperature of 600 ° C. or more for more than 10 hours, and a gate Si is formed by thermal oxidation at about 1000 ° C.
Since O ₂ needs to be formed, a dedicated semiconductor manufacturing apparatus must be used. Therefore, the wafer size is 8
Since the diameter is limited to 12 inches φ, high-heat-resistant and expensive quartz glass must be adopted, and it is difficult to reduce the cost. Therefore, the obtained product is currently EV
F and data / AV projector applications.

Further, in the above-described conventional polycrystalline silicon TFT by excimer laser annealing, stability of excimer laser output, increase in apparatus price due to increase in size, increase in yield /
Problems such as quality deterioration are piled up.

[0007] In particular, when a large glass substrate of 1 m square or the like is used, the above-mentioned problems are magnified, and it becomes more difficult to improve performance / quality and reduce costs.

An object of the present invention is to provide an active matrix substrate with a built-in high-performance driver by forming a single-crystal silicon thin film having a high electron / hole mobility at a relatively low temperature and uniformly, particularly in a peripheral driving circuit portion. Enables the manufacture of electro-optical devices such as display thin film semiconductor devices using the same, and has an LDD structure (Li
ghtly doped drain structure) n-channel MOSTF
T (hereinafter referred to as nMOSTFT) or pMOS
TFT or complementary thin-film insulated gate field-effect transistor with high driving capability (hereinafter referred to as cMOSTFT)
And a peripheral drive circuit composed of this cMOSTFT, nMOSTFT, or pMOSTFT, or a mixture of these, enabling a high-quality, high-definition, narrow frame, high-efficiency, large-screen display panel. It can be used even with a large glass substrate having a relatively low strain point, has high productivity, does not require expensive manufacturing equipment, enables cost reduction, and has a threshold adjustment. An object of the present invention is to enable high-speed operation and a large screen by low resistance.

[0009]

According to the present invention, a pixel electrode (for example, a plurality of pixel electrodes arranged in a matrix: the same applies hereinafter) and a peripheral drive circuit portion disposed around the display portion are provided as first components. An electro-optical device in which a predetermined optical material such as a liquid crystal is interposed between the first substrate and the driving substrate for the electro-optical device, and a driving substrate for the electro-optical device. A gate portion including a gate electrode and a gate insulating film is formed on one surface, a step is formed on the one surface of the first substrate, and a semiconductor is formed on the first substrate including the step. Is formed by forming a molten layer of a low-melting-point metal made of tin or lead or an alloy of tin and lead, and further cooling (preferably gradually cooling) the molten-layer of the low-melting-point metal. The semiconductor as a seed A single-crystal semiconductor layer formed by photoepitaxial growth and deposited is provided, and the single-crystal semiconductor layer is used as a channel region, a source region, and a drain region, and a bottom-gate type first having the gate portion below the channel region. The thin film transistor (particularly, MOSTFT: the same applies hereinafter) constitutes at least a part of the peripheral drive circuit section as a means for solving the above problem.

In the present invention, the concept of a single crystal semiconductor includes not only single crystal silicon but also a single crystal compound semiconductor such as single crystal gallium arsenide (Ga.As) and single crystal silicon germanium (Si.Ge). (The same applies hereinafter). Further, in the present invention, a single crystal is a concept including a single crystal containing sub-grain boundaries and dislocations (the same applies hereinafter).

Further, the thin film transistor is
There are a field effect transistor (FET) (there is a MOS type and a junction type, whichever may be used) and a bipolar transistor, and the present invention can be applied to any of the transistors (the same applies hereinafter).

Further, the present invention provides the method for manufacturing the electro-optical device and the driving substrate thereof, wherein a step of forming a gate portion comprising a gate electrode and a gate insulating film on one surface of the first substrate; Forming a step on the one surface of the first substrate; and forming a low melting metal made of tin or lead containing a semiconductor or an alloy of tin and lead on the first substrate including the step. Forming a melt layer, and cooling (preferably slow cooling) the melt layer of the low-melting-point metal so that the semiconductor is graphoepitaxially grown using the step as a seed to deposit a single-crystal semiconductor layer. Forming a channel region, a source region, and a drain region by performing a predetermined process on the single crystal semiconductor layer; and providing the gate portion below the channel region; Forming a first thin film transistor with a bottom gate type which forms at least a part of the drive circuit section, to have a have a solution to the above problems.

According to the present invention, a single-crystal semiconductor layer such as a single-crystal silicon layer is formed from a melt layer of a low-melting metal in which a semiconductor material such as silicon is dissolved by using the step formed on the substrate as a seed. And a bottom gate type MOSTFT of a peripheral drive circuit of a drive substrate such as an active matrix substrate or a peripheral drive circuit in an electro-optical device such as an LCD integrated with a display unit and a peripheral drive circuit. And the like, and at least the active element among passive elements such as resistance, inductance, capacitance, etc., exhibit the following remarkable functions (A) to (G).

(A) A step having a predetermined shape / dimension is formed on a substrate, and the bottom of the step (bottom angle) is used as a seed to perform grapho-epitaxial growth to 540 cm.
^Since a single-crystal semiconductor layer such as a single-crystal silicon layer having a high electron mobility of ² / v · sec or more can be obtained, an electro-optical device such as a display thin-film semiconductor device with a built-in high-performance driver can be manufactured. In this case, in a state viewed in cross section,
The side surface is perpendicular to the bottom surface or desirably 9
It is preferable that the step is formed as a concave portion which is inclined so as to form a base angle of 0 ° or less.

(B) In particular, the single-crystal silicon layer has high electron and hole mobilities comparable to those of a single-crystal silicon substrate as compared with a conventional amorphous silicon layer or polycrystalline silicon layer. Bottom-gate MOSTFTs have high switching characteristics [preferably, LDDs that reduce the electric field strength and reduce the leakage current.
(Lightly doped drain) structure], a display portion comprising an nMOS, pMOSTFT or cMOSTFT;
High drive capability cMOS, nMOS or pMOSTF
It is possible to realize a configuration in which a peripheral drive circuit section composed of T or a mixture thereof is integrated, and a display panel with high image quality, high definition, a narrow frame, high efficiency, and a large screen is realized. In particular, it is difficult to form a pMOSTFT having a high hole mobility as a TFT for LCD in polycrystalline silicon. However, in a single crystal silicon layer according to the present invention, even a hole exhibits a sufficiently high mobility, so that electrons and electrons are positive. A peripheral drive circuit for driving the holes individually or in a combination of both can be manufactured, and a panel in which this is integrated with an nMOS, pMOS, or cMOS LDD structure display TFT can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) The low-melting-point metal melt is prepared at a low temperature (for example, 400 to 600 ° C.), and applied to a substrate heated to a temperature slightly higher than the low-temperature metal by a method such as coating. Since the single crystal silicon layer can be formed, the single crystal silicon layer can be uniformly formed at a relatively low temperature (for example, 450 to 600 ° C.). Therefore, it is easy to obtain a glass substrate or a heat-resistant resin substrate having a relatively low strain point, and it is possible to use a substrate having good physical properties at low cost,
Also, the size of the substrate can be increased.

(D) Since there is no need for annealing at medium temperature for a long time (about 600 ° C., about ten and several hours) or excimer laser annealing as in the case of the solid phase growth method, productivity is high.
Expensive manufacturing equipment is not required, and costs can be reduced.

(E) In this grapho-epitaxial growth, a wide range of P-type or N-type conductivity types can be obtained by adjusting the composition ratio of the low-melting-point metal melt, the melt temperature, the substrate heating temperature and the cooling rate, and the like. Since a single crystal silicon layer having mobility can be easily obtained, Vth (threshold) can be easily adjusted, and high-speed operation can be performed by lowering resistance.

(F) In forming the semiconductor-containing low-melting-point metal melt layer, an appropriate amount of N-type or P-type carrier impurities (boron, phosphorus, antimony, arsenic, bismuth, aluminum, etc.) may be separately doped. In addition, the impurity species and / or the concentration of the single crystal semiconductor layer (single crystal silicon layer) composed of the epitaxial growth layer, that is, the conductivity type such as P type / N type and / or the carrier concentration can be arbitrarily controlled.

(G) Since the low melting point metal is formed of tin or lead or an alloy of tin and lead, tin or lead is mixed in the obtained single crystal silicon layer (single crystal semiconductor layer). However, tin and lead are elements of Group 4 of the periodic table and do not act as carriers in the silicon layer, so that the silicon layer has a high resistance. Therefore, Vth adjustment and resistance adjustment of the TFT by ion doping (implantation) or the like become easy, and a high-performance circuit configuration can be realized. Also,
Since tin and lead remaining in the silicon layer make crystal defects electrically inactive, the obtained silicon layer has reduced junction leakage and increased electron mobility.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail.
In the present invention, the step is formed such that a side surface is perpendicular to the bottom surface or a lower end (preferably) 9
As a concave portion having an inclined shape with a base angle of 0 ° or less,
The step is formed on an insulating substrate or a diffusion barrier thereon, for example, a film such as silicon nitride (SiN) (or both), and this step is used as a seed for crystal growth of the single crystal silicon layer, that is, in the present invention, grapho-epitaxial growth It is good to use it as a seed for time.

Preferably, the step is formed along at least one side of an element region formed by the channel region, the source region and the drain region of the thin film transistor. Further, the passive element, for example, the element may be formed along at least one side of an element region where a resistor is formed. In this case, the first thin film transistor such as the MOSTFT may be provided in the substrate recess due to the step, or may be provided on the substrate outside the recess or both.

Here, an insulating substrate is used as the substrate. In particular, since a molten liquid of a silicon-containing low melting point metal can be formed at a low temperature as described later, a glass substrate having a relatively low strain point is used. A heat-resistant resin substrate can be used. Therefore, a large glass substrate (for example, 1 m
² or more) on which a single-crystal silicon layer can be formed. Such a substrate is inexpensive, easy to make thin,
It can also be manufactured on long rolled substrates. Therefore,
On such a long rolled glass plate or heat-resistant resin substrate, a single-crystal silicon layer formed by grapho-epitaxial growth can be continuously or discontinuously formed by the above-described method.

Since the constituent elements are easily diffused from the inside of the glass into the upper layer of the glass having a low strain point, a diffusion barrier layer such as silicon nitride (SiN) is used for the purpose of suppressing the diffusion. Membrane (thickness eg 50-
(About 200 nm) is preferable. When the diffusion barrier layer is formed as described above, a melt layer made of a silicon-containing low melting point metal is formed on the diffusion barrier layer.

The step is formed by dry etching such as reactive ion etching, and tin containing, for example, 0.03% to 0.0005% by weight (preferably 0.014% to 0.0035% by weight) of silicon. It is preferable to apply the molten liquid of the low melting point metal to the heated insulating substrate, hold the same for a predetermined time (several minutes to several tens of minutes), and then perform the cooling (preferably slow cooling) treatment. Thus, a single-crystal silicon layer having a thickness of several μm to 0.005 μm (for example, 0.1 μm) can be obtained.

In the case where tin or lead is used as the low melting point metal, the insulating substrate is heated to, for example, 600 ° C. or higher than the temperature of the silicon-containing melt, and tin and lead are used as the low melting point metal. When using the alloy of the above, the substrate is heated to, for example, 600 ° C.

In order to form a low-melting-point metal melt containing silicon, when the melt is formed of tin or lead, the tin or lead and silicon are hydrogenated (hydrogen or a nitrogen-hydrogen mixture, or Argon-hydrogen mixture, etc .: The same applies hereinafter)
Under an atmosphere, 350 to 1100 ° C (preferably 400 to 600 ° C for tin / silicon, 50 for lead / silicon)
(0 to 800 ° C.) to form a silicon-containing tin melt. When the low-melting-point metal melt is formed of an alloy of tin and lead, the tin-lead alloy and silicon are mixed in a hydrogen-based atmosphere at 300 to 1100 ° C (preferably 350 to 600 ° C). A heat treatment is performed to form a tin-lead melt containing silicon. Then, the molten liquid thus formed is applied on a substrate that has been heated in advance. The substrate can be heated by a method of uniformly heating the entire substrate using an electric furnace, a lamp, or the like, or by a method of locally heating only a predetermined location using an optical laser, an electron beam, or the like.

It should be noted that a single impurity obtained by previously mixing N-type or P-type carrier impurities (boron, phosphorus, antimony, arsenic, bismuth, etc.) into the molten silicon-containing low-melting-point metal melt. The crystalline silicon layer can be formed to contain any concentration of N-type or P-type carrier impurities. If the single-crystal silicon layer is made N-type or P-type in this way, the nMOS TFT
Alternatively, the fabrication of the pMOSTFT can be facilitated, whereby the fabrication of the cMOSTFT can also be facilitated.

The silicon-containing low melting point metal (tin / silicon or lead / silicon or tin / lead / silicon) thus formed has a high ratio of the low melting point metal (tin or lead or tin / lead). As the melting point decreases. Therefore, by reducing the proportion of silicon, it becomes possible to form a melt of a silicon-containing low melting point metal at a low temperature.

In the above-described method of applying a low-melting-point metal melt, the melt is applied to a substrate for a predetermined time (several minutes to several minutes).
After holding for several tens of minutes, the substrate is gradually cooled. In addition, a dipping method in which the substrate is immersed in the melt and held for a certain period of time (several minutes to several tens of minutes), and then gradually pulled up, or in the melt or A floating method in which the substrate is moved at an appropriate speed on the surface thereof and gradually cooled can be adopted. According to these methods, the thickness of the epitaxially grown layer and the carrier impurity concentration can be controlled by the composition, temperature, pulling rate, and the like of the melt. According to such a coating method, a dipping method, a floating method, or the like, the substrate can be processed continuously or intermittently, so that mass productivity can be improved.

From the low melting point metal in which silicon is melted, the step is seeded by gradually cooling the metal,
That is, the single crystal silicon layer is deposited by grapho-epitaxial growth as a seed for crystal growth. After that, the low melting point metal layer on the single crystal silicon layer is dissolved and removed with hydrochloric acid or the like, and thereafter, the single crystal silicon layer is subjected to a predetermined treatment, whereby an active element and a passive element can be manufactured.

Further, by dissolving and removing a low melting point metal thin film such as tin deposited on the single crystal silicon layer after cooling using hydrochloric acid or the like, tin or lead is prevented from remaining in the silicon layer as an impurity. be able to. Also, even if these tin and lead remain in the silicon layer,
Since these are elements of Group 4 of the periodic table, they do not become carriers in the silicon layer, and thus the silicon layer maintains a high resistance state. Therefore, Vth adjustment and resistance adjustment of the TFT by ion doping (implantation) or the like become easy, and a high-performance circuit configuration can be realized. Further, the single-crystal silicon layer thus formed is used as a formation layer of a channel region, a source region, and a drain region of a bottom gate type MOSTFT constituting at least a part of a peripheral driver circuit, so that impurities in each of these regions can be formed. The species and / or its concentration can be controlled.

The thin film transistors of the peripheral drive circuit section and the display section constitute an n-channel, p-channel or complementary insulated gate field-effect transistor, for example, a set of a complementary type and an n-channel type, and a complementary type. It consists of a set of a p-channel type or a set of a complementary type, an n-channel type and a p-channel type. Further, it is preferable that at least a part of the thin film transistor of the peripheral drive circuit section and / or the display section has an LDD (Lightly doped drain) structure. Note that the LDD structure may be provided not only between the gate and the drain but also between the gate and the source or between the gate and the source and between the gate and the drain (this is referred to as a double LDD).

In particular, regarding the MOSTFT, an nMOS, pMOS or cMOS LD
A D-type TFT is formed, and cM
It is preferable to configure OS, nMOS, pMOSTFT, or a state in which these are mixed.

The first thin film transistor made of the MOSTFT or the like may be provided in the concave portion of the substrate formed by the step, but may be provided outside the concave portion located near the concave portion, or both inside the concave portion and outside the concave portion. Good.

In this case, the step is formed on one surface of the first substrate, and a monocrystalline, polycrystalline, or amorphous silicon layer is formed on the substrate including the step. A top-gate type in which a channel region, a source region, and a drain region of the second thin film transistor are respectively formed from such a silicon layer, and a gate portion is provided above and / or below the channel region;
A bottom-gate or dual-gate thin film transistor may be formed.

Also in this case, the side surface is perpendicular to the bottom surface in a cross-sectional view, or 90 ° (preferably) to the lower end side.
The step similar to that described above may be formed as a concave portion having a slope having the following base angle, and this step may be used as a seed during epitaxial growth (crystal growth) of the single crystal silicon layer.

With respect to the second thin film transistor,
The first substrate and / or a film formed thereon is provided inside and / or outside the concave portion of the substrate formed by the step, and similarly to the first thin film transistor, a single crystal silicon layer formed by grapho-epitaxial growth is used. , Drain and channel regions can be formed.

This second thin film transistor is also
As in the case described above, the N-type or P-type impurity species and / or the concentration thereof can be controlled by mixing N-type or P-type during the formation of the single-crystal, polycrystalline, or amorphous silicon layer. it can. Further, the step may be formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor.

Further, it is preferable that the gate electrode under the single-crystal, polycrystal or amorphous silicon layer has a trapezoidal shape at a side end thereof. Alternatively, it is preferable to provide a diffusion barrier layer between the diffusion barrier layer and the amorphous silicon layer. A source or drain electrode of the first and / or second thin film transistor;
Preferably, it is formed on a region including the step.

The first thin film transistor is at least a bottom gate type of a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region. Further, a switching element for switching a pixel electrode in the display unit is
It is preferable that the second thin film transistor be any of the top gate type, the bottom gate type, and the dual gate type.

In this case, the gate electrode provided below the channel region is formed of a heat-resistant material, or the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor are formed of a common material. can do.

In the peripheral drive circuit section, in addition to the first thin film transistor, a top gate type having a polycrystalline or amorphous silicon layer as a channel region and having a gate portion above and / or below the channel region;
A bottom-gate or dual-gate thin film transistor, or a diode, a resistor, a capacitor, an inductance element, or the like using the single-crystal silicon layer, the polycrystalline silicon layer, or the amorphous silicon layer may be provided.

The peripheral driver circuit section and / or the thin film transistor of the display section may be configured as a single gate or a multi-gate. When the n-channel or p-channel thin film transistor of the peripheral driver circuit portion and / or the display portion is a dual gate type, the upper or lower gate electrode is electrically open or an arbitrary negative voltage (n channel It is preferable to apply a positive voltage (for a p-channel type) or a positive voltage (for a p-channel type) to operate as a bottom-gate or top-gate thin film transistor.

The thin film transistor of the peripheral drive circuit section is an n-channel type, a p-channel type or a complementary type of the first thin film transistor.
Thin film transistor. Further, the thin film transistor of the display portion, a single crystal silicon layer, a polycrystalline silicon layer,
Regardless of which of the amorphous silicon layers is used as the channel region, the channel region is an n-channel type, a p-channel type, or a complementary type.

In the present invention, after the growth of the single crystal silicon layer, an upper gate portion including a gate insulating film and a gate electrode is formed on the single crystal silicon layer, and the upper gate portion is used as a mask to form the single crystal silicon layer. The channel region, the source region, and the drain region may be formed by introducing an impurity element belonging to Group 3 or Group 5 of the periodic table, that is, an N-type or P-type impurity into the layer.

When the second thin film transistor is of a bottom gate type or a dual gate type, a lower gate electrode made of a heat-resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. After forming the lower gate portion, the second thin film transistor can be formed through steps common to the first thin film transistor including the step of forming the step. In this case, the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor may be formed of a common material.

After forming the single-crystal silicon layer on the lower gate portion, an impurity element of Group 3 or 5 of the periodic table is introduced into the single-crystal silicon layer to form source and drain regions. After that, an activation process can be performed.

After the formation of the single crystal silicon layer, the source and drain regions of the first and second thin film transistors are formed by ion-implanting an impurity element using a resist as a mask. After forming the gate insulating film, the upper gate structure of the second thin film transistor may be formed.

When the second thin film transistor is a top gate type, the source and drain of the first and second thin film transistors are formed by ion-implanting an impurity element using the resist as a mask after forming the single crystal silicon layer. A region may be formed, activation treatment may be performed after ion implantation, and then a gate portion including a gate insulating film and a gate electrode of the second thin film transistor may be formed.

Alternatively, when the second thin film transistor is a top gate type, after forming the single crystal silicon layer, a gate insulating film of the second thin film transistor and a gate electrode made of a heat-resistant material are formed. Is formed, and an impurity element is ion-implanted using the gate portion and the resist as a mask.
The source and drain regions of the thin film transistor may be formed, and an activation process may be performed after the ion implantation.

Alternatively, ion implantation for forming a source region and a drain region may be performed using a resist mask that covers the resist mask used for forming the LDD structure. Further, the substrate may be made optically opaque or transparent, and a reflective or transmissive display pixel electrode may be provided.

When the display section has a laminated structure of the pixel electrode and the color filter layer, the color filter is formed on the display array section to improve the aperture ratio and brightness of the display panel. In addition, the cost can be reduced by omitting the color filter substrate and improving the productivity. In this case, when the pixel electrode is a reflective electrode, irregularities are formed on the resin film to obtain optimal reflection characteristics and viewing angle characteristics, and a pixel electrode is provided thereon, and the pixel electrode is a transparent electrode. At times, it is preferable to flatten the surface with a transparent flattening film and to provide a pixel electrode on this flattened surface.

The display section is configured to emit light or modulate light by being driven by the MOSTFT. For example, a liquid crystal display (LCD), an electroluminescence display (E)
L), field emission display (FED), light emitting polymer display (LEPD), light emitting diode display (LE
D) or the like. In this case, a plurality of the pixel electrodes may be arranged in a matrix on the display unit, and the switching element may be connected to each of the pixel electrodes.

A control unit for controlling the operation of the peripheral drive circuit unit and / or the display unit may be provided on the first substrate. The control unit includes a CPU (Central Processing Unit, including a microprocessor), a memory (SR
AM, DRAM, flash ferroelectricity or the like, or a system-on-panel in which a so-called computer system formed by a system LSI or the like in which these are mounted is formed. Further, when such a control unit is provided on the first substrate, a predetermined process is performed on the single crystal semiconductor layer, and elements for forming the control unit, for example, cMOSTFT, nMOSTFT, pMOSTFT,
Active elements such as diodes and passive elements such as resistors, capacitors, and inductances are formed. Note that such a control unit may be formed in the same region as a vertical drive circuit or a horizontal drive circuit serving as a peripheral drive circuit unit, or may be formed in another region.

Next, a preferred embodiment of the present invention will be described in more detail. <First Embodiment> A first embodiment of the present invention will be described with reference to FIGS.

In this embodiment, a single crystal silicon layer is grapho-epitaxially grown from tin / silicon formed on a heat-resistant substrate using the above-described steps (concave portions) provided on the heat-resistant substrate as seeds. Using bottom gate type M
The present invention relates to an active matrix reflective liquid crystal display (LCD) including an OSTFT.

First, the overall layout of the reflection type LCD will be described with reference to FIGS. In this active matrix reflective LCD, as shown in FIG. 11, a main substrate 1 (which constitutes an active matrix substrate, that is, a driving substrate) and a counter substrate 32 are bonded together via a spacer (not shown). It has a flat panel structure, in which liquid crystal (not shown) is sealed between the main substrate 1 and the counter substrate 32. Pixel electrodes 29 (or 41) arranged in a matrix on the surface of the main substrate 1
And a display unit including a switching element for driving the pixel electrode, and a peripheral drive circuit unit connected to the display unit.

The switching element of the display section is an nMOS, pMOS or cMOS according to the present invention, and is formed of a top gate type MOSTFT having an LDD structure. Also, in the peripheral drive circuit section, as a circuit element, a cMOS or nMO of a bottom gate type MOSTFT according to the present invention is used.
The S or p MOSTFTs are each formed as a single type or in a mixed state.

The one peripheral drive circuit section is a horizontal drive circuit that supplies a data signal and drives the TFT of each pixel for each horizontal line. Also, the other peripheral drive circuit section
This is a vertical drive circuit that drives the gate of the TFT of each pixel for each scanning line, and is usually provided on both sides of the display unit. In this example, these drive circuits can be configured in either a dot-sequential analog system or a line-sequential digital system.

As shown in FIG. 12, the above-mentioned TFT is arranged at the intersection of the orthogonal gate bus line and data bus line, and image information is written into a liquid crystal capacitor (C _LC ) via this TFT, and the next information is written. Holds electric charge until comes. In this case, it is not enough to hold only the channel resistance of the TFT. To compensate for this, a storage capacitance (auxiliary capacitance) (C _S ) is added in parallel with the liquid crystal capacitance to compensate for a decrease in the liquid crystal voltage due to leak current. To do.

In such an LCD TFT, the required performance is different between the characteristics of the TFT used for the pixel portion (display portion) and the characteristics of the TFT used for the peripheral driving circuit. Securing current is an important issue. For this reason, as described later, the display unit
By providing a TFT having a D structure, an electric field is hardly applied between the gate and the drain, an effective electric field applied to the channel region is reduced, an off current is reduced, and a change in characteristics is reduced. However, in order to obtain such a configuration, there are problems in that the process becomes complicated, the element size increases, and the off-state current decreases. Therefore, it is necessary to optimize the design according to the intended use. is there.

Usable liquid crystals include TN liquid crystal (nematic liquid crystal used in the TN mode of active matrix drive), STN (super twisted nematic), GH (guest host), PC (phase change). , FLC (ferroelectric liquid crystal), AFL
Liquid crystals for various modes such as C (antiferroelectric liquid crystal) and PDLC (polymer dispersed liquid crystal) can be used.

Next, the circuit system of the peripheral drive circuit unit and the outline of the drive system will be described with reference to FIG. The drive circuit is divided into a gate-side drive circuit and a data-side drive circuit, and it is necessary to form a shift register on both the gate side and the data side. As the shift register, pMOSTF
Although there are those using both T and nMOSTFT (so-called CMOS circuit) and those using only one of the MOSTFTs, cMOSTFT or CMOS circuits are generally used in terms of operation speed, reliability, and low power consumption. It is a target.

The scanning drive circuit is composed of a shift register and a buffer, and sends a pulse synchronized with the horizontal scanning period to each line from the shift register. On the other hand, the data-side driving circuit has two driving methods, a dot sequential method and a line sequential method. The dot sequential system shown in FIG. 13 has a relatively simple circuit configuration, and the display signal is sequentially written directly to each pixel within one horizontal scanning time while the display signal is controlled by a shift register through an analog switch. (R,
G and B schematically show pixels for each color).

Next, an active matrix reflective LCD according to the present embodiment will be described based on a manufacturing method (process) with reference to FIGS. In FIGS. 1 to 7, the left side of each drawing shows a manufacturing method (step) of the display unit, and the right side shows a manufacturing method (step) of the peripheral circuit unit.

First, as shown in FIG. 1A, a sputtered film 71A of a molybdenum / tantalum (Mo.Ta) alloy is formed on one main surface of an insulating substrate 1 such as quartz glass or transparent crystallized glass. It is formed to a thickness of about 300 to 400 nm. Next, as shown in FIG. 1B, a photoresist 70 is formed in a predetermined pattern, and the sputtered film 71A is taper-etched using the photoresist 70 as a mask to form a side end 7A.
1a forms a trapezoidal gate electrode 71 gently inclined at 20 to 45 °.

Next, as shown in FIG. 1C, after removing the photoresist, an SiN film (about 2 nm) is formed on the substrate 1 including the sputtered film 71A by a plasma CVD method or the like.
(Thickness: 00 nm) 72 and SiO ₂ film (about 100 nm thickness) 73
Are formed in this order to form a gate insulating film.

Next, as shown in FIG. 2D, a photoresist 2 is formed in a predetermined pattern on at least a TFT formation region on one main surface of the insulating substrate 1 and, using this as a mask, for example, a CF ₄ plasma F ^A plurality of steps 4 having an appropriate shape and dimensions are formed on the substrate 1 by general-purpose photolithography and etching (photoetching) such as reactive ion etching (RIE) using ⁺ ions 3.

In this case, the insulating substrate 1 is made of quartz glass,
Transparent crystallized glass, ceramics, etc. (However, an opaque ceramic substrate or low-permeability crystallized glass cannot be used in a transmissive LCD described later) (8 to 12 inch φ, 700 to 800 μm) Thickness) can be used. The step 4 serves as a seed at the time of grapho-epitaxial growth of single-crystal silicon described later, and has a depth d of about 0.1 to 0.4 μm, a width w of about 2 to 10 μm, and a length (in a direction perpendicular to the paper surface). ) Is about 10 to 20 μm, and the angle (base angle) between the bottom surface and the side surface is substantially a right angle.

The surface of the substrate 1, especially when the substrate 1 is made of a glass substrate, is exposed to Na from the substrate 1 itself.
In order to prevent diffusion of ions and the like, an SiN film is
It is preferable to form the layer to a thickness of about 0 to 200 nm and, if necessary, to form a silicon oxide film (hereinafter referred to as SiO ₂ film) to a thickness of about 100 nm, for example.

Next, the photoresist 2 is removed, and then, as shown in FIG.
0.0005% by weight (preferably 0.014% by weight
0.0035% by weight) is applied to the entire surface including the step 4 of the substrate 1 heated to 400 to 600 ° C. by spin coating or the like to form a molten liquid layer 6. Instead of this coating method, a dipping method in which the substrate 1 is dipped in the solution, a floating method in which the surface of the melt is gradually moved to float, and a jet method or a contact method under the action of an ultrasonic wave are employed. You can also.

Here, in order to prepare the silicon-tin alloy melt, non-doped silicon or N-type or P-type
Silicon containing an appropriate amount of carrier impurities of the type is added to tin in an amount of 0.1%.
03% by weight to 0.0005% by weight (preferably 0.01%
4% by weight to 0.0035% by weight).
Also, by adding an appropriate amount of N-type or P-type carrier impurities to tin and adjusting the silicon-tin alloy melt to N-type or P-type, the specific resistance of the obtained single crystal silicon layer is controlled. Is also good.

Then, the substrate 1 is held in this state for several minutes to several tens of minutes, and then gradually cooled (in the case of dipping, gradually pulled up) to remove the silicon dissolved in the tin. As shown in FIG. 3 (6), the corner of the bottom surface of the step 4 is used as a seed to grow grapho-epitaxially, thereby depositing single-crystal silicon to a thickness of, for example, about 10 to 100 nm, preferably 40 to 60 nm.
A single crystal silicon layer 7 is formed.

In this case, the single crystal silicon layer 7
The 0) plane is epitaxially grown on the substrate, which is due to a known phenomenon called grapho-epitaxial growth. In this regard, as shown in FIG. 9, when a vertical wall such as the above-described step 4 is formed on an amorphous substrate (glass) 1 and an epitaxy layer is formed thereon, a random wall as shown in FIG. 9B, the (100) plane grows along the plane of the step 4 as shown in FIG. The size of the single crystal grain increases in proportion to the temperature and time. However, when the temperature and time are reduced and shortened, the interval between the steps must be shortened.

The shapes of the steps are shown in FIGS.
By changing variously as in (f), the crystal orientation of the growth layer can be controlled. When fabricating MOS transistors, the (100) plane is most often employed. In short, the cross-sectional shape of the step 4 may be such that the angle of the bottom corner (base angle) may be a right angle, or may be inclined inward or outward from the upper end to the lower end. It is sufficient if it has. Usually, the bottom angle of the step 4 is desirably a right angle or 90 ° or less, and the corner of the bottom surface preferably has a slight curvature.

After the single-crystal silicon layer 7 is deposited on the substrate 1 by grapho-epitaxial growth in this way, as shown in FIG. 3 (7), a film mainly composed of tin is formed on the surface side. 6A (see (6) in FIG. 3) is dissolved and removed with hydrochloric acid, sulfuric acid or the like. Subsequently, a bottom gate type MOSTFT using the single crystal silicon layer 7 as a channel region
To the peripheral drive circuit, and top-gate MOSTFT
Are formed on the display unit as follows.

First, since the impurity concentration of the single crystal silicon layer 7 formed by the above-described grapho-epitaxial growth varies, the entire surface is doped with an appropriate amount of a P-type carrier impurity, for example, boron ions, to adjust the specific resistance. Further, only the pMOSTFT formation region is selectively doped with an N-type carrier impurity to form an N-type well. For example, a p-channel TFT portion is masked with a photoresist (not shown), and P-type impurity ions (for example, B ⁺ ) are
Doping is performed at 0 kV at a dose of 2.7 × 10 ¹¹ atoms / cm ² to adjust the specific resistance.

Further, as shown in FIG.
In order to control the impurity concentration of the STFT formation region, nMOST
The FT portion is masked with a photoresist 60, and N-type impurity ions (for example, P ⁺ ) 65 are applied at 10 kV to 1 × 10 ^{11 at.}
ms / cm ^{2 at} a dose of N-type well 7
Form A.

Next, as shown in FIG. 4 (9), SiO ₂ (about 10 μm) is formed on the entire surface of the single-crystal silicon thin film layer 7 by plasma CVD, high-density plasma CVD, catalytic CVD, or the like.
0 nm thick) and SiN (approximately 200 nm thick) in this order to form a gate insulating film 8, and further, a sputtered film 9 of a molybdenum-tantalum (Mo · Ta) alloy is reduced to a thickness of about 300 to 400 nm. Form.

Next, as shown in (10) of FIG. 4, the TFT in the display area is formed by a general-purpose photolithography technique.
Photoresist pattern 10 in the step region (in the concave portion)
Is formed and is successively etched using this as a mask, so that the gate electrode 11 of Mo.Ta alloy and (Si)
A gate insulating film 12 having a laminated structure of (N / SiO ₂ ) is formed, and the single crystal silicon layer 7 is exposed. Note that M
The sputtered film 9 made of an o-Ta alloy is treated with an acid-based etchant, and SiN is plasma-etched with CF ₄ gas.
SiO ₂ is treated with a hydrofluoric acid-based etchant.

Next, as shown in FIG. 4 (11), all of the nMOS and pMOSTFTs in the peripheral driving region and the gate portion of the nMOSTFT in the display region are formed by photoresist 1
3 and cover the exposed source / drain regions of the nMOS TFT with phosphorus ions 14 at, for example, 20 kV and 5 × 1.
Doping (ion implantation) is performed at a dose of 0 ¹³ atoms / cm ² to form an LDD portion 15 made of an N ⁻ -type layer in a self-aligned manner (self-aligned).

Next, as shown in FIG. 5 (12), all of the pMOS TFTs in the peripheral drive region and n in the peripheral drive region
Gate portion of MOSTFT and nMOSTFT in display area
And the LDD portion are covered with a photoresist 16 and phosphorus or arsenic ions 17
Doping (ion implantation) is performed at 0 kv with a dose of 5 × 10 ¹⁵ atoms / cm ² , and the source 18 and the drain 19 and the LDD 1 made of the N ⁺ type layer of the nMOS TFT are formed.
5 is formed.

Next, as shown in (13) of FIG. 5, the nMOSTFT in the peripheral drive region and the nMOST in the display region are formed.
The entirety of the FT and the gate of the pMOSTFT are covered with a photoresist 20 and boron ions 2
1 at 5 × 10 ¹⁵ atoms / cm ^{2 at} 10 kv, for example.
Doping (ion implantation) at a dose of pMOST
The source part 22 and the drain part 23 of the P ⁺ layer of the FT are formed. This step is unnecessary in the case of the nMOS peripheral drive circuit because there is no pMOSTFT.

Next, as shown in FIG.
A photoresist 24 is formed to make an active element portion such as an FT or a diode or a passive element portion such as a resistor or an inductance into an island. Then, the single crystal silicon layer 7 other than all the active element portions and the passive element portions in the peripheral drive region and the display region is removed by etching using a hydrofluoric acid-based etchant.

Then, as shown in FIG. 6 (15), an SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 200 nm thick) were formed on the entire surface by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. (Thickness of 300 nm) is formed continuously in this order, and the protective film 25 is formed.

Then, in this state, the single crystal silicon layer 7 is activated. For this activation, for example, a lamp of halogen or the like is used, and the annealing condition is set to about 1000.
C. for about 10 seconds. Therefore, a material that can withstand such annealing conditions is required as a gate electrode material, but the above-mentioned Mo / Ta alloy has a high melting point,
The structure can withstand such annealing conditions.
Further, since the gate electrode material made of the Mo.Ta alloy has a high melting point and can withstand annealing conditions, it can be formed not only as a gate portion but also as a wiring over a wide range.

Note that, here, expensive excimer laser annealing is not used, but when this is used, XeC
It is desirable to perform irradiation processing at 1 (308 nm wavelength) over the entire surface or selectively only the active element portion and the passive element portion with 90% or more overlap scanning.

Next, as shown in FIG. 6 (16), contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portion of the display TFT by general-purpose photolithography and etching techniques. .

Then, a sputtered film of aluminum or an aluminum alloy (for example, an aluminum alloy containing 1% Si or an aluminum alloy containing 1 to 2% copper), copper or the like is formed on the entire surface to a thickness of about 500 to 600 nm. By photolithography and etching techniques, the data lines and the gate lines are formed at the same time as the source electrodes 26 of all the TFTs in the peripheral drive circuit and the display section and the drain electrode 27 in the peripheral drive circuit section are formed. Then, about 4 times in forming gas (N ₂ + H ₂ ).
Sinter treatment at 00 ° C / 1h.

Next, as shown in (17) of FIG. 6, an insulating film 36 made of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) is formed by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. Is formed on the entire surface.
Next, a contact window is opened in the drain portion of the display TFT. Note that SiO ₂ , PSG and SiN in the pixel portion are used.
The film does not need to be removed.

Here, as a basic requirement of the reflection type liquid crystal display device, a function of reflecting incident light and a function of scattering incident light must be provided inside the liquid crystal panel. This is because the direction of the observer with respect to the display is substantially determined, but the direction of the incident light cannot be uniquely determined. For this reason, it is necessary to design a reflector assuming that a point light source exists in an arbitrary direction. Therefore, as shown in (18) of FIG.
A photosensitive resin film 28 having a thickness of about 3 μm is formed. Subsequently, as shown in (19) of FIG. 7, an uneven pattern for obtaining optimum reflection characteristics and viewing angle characteristics is formed by general-purpose photolithography and etching technology. It is formed in the pixel portion and is reflowed to form a lower reflective surface made of the roughened surface 28A. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, as shown in FIG. 7 (20), aluminum or 1 nm having a thickness of about 400 to 500 nm is formed on the entire surface.
% Sputtered film such as aluminum alloy containing Si,
Further, the sputtered film other than the pixel portion is removed by a general-purpose photolithography and etching technique, and a reflective film 29 made of a concavo-convex shaped aluminum alloy or the like connected to the drain portion 19 of the display TFT is formed. This reflection film 29
It also functions as a pixel electrode for display. Thereafter, sintering is performed in a forming gas at about 300 ° C. for 1 hour to make the contact sufficient. Note that silver or a silver alloy may be used instead of an aluminum-based material to increase the reflectance.

As described above, the step 4 is used as a seed for the grapho-epitaxial growth to form the single-crystal silicon layer 7, and the display section and the peripheral drive circuit section using the single-crystal silicon layer 7 are each provided with a top gate type. nMOSLD
D-TFT, bottom gate type pMOSTFT and nM
Active matrix substrate 3 incorporating a display section and a peripheral drive circuit section in which a CMOS circuit composed of OSFTs is formed
0 can be produced.

Next, a method of manufacturing a reflection type liquid crystal display (LCD) using the active matrix substrate (drive substrate) 30 will be described with reference to FIG. Hereinafter, this active matrix substrate is referred to as a TFT substrate.

When manufacturing the liquid crystal cell of this LCD by surface assembly suitable for a medium / large liquid crystal panel of 2 inch size or more, first, the TFT substrate 30 and the entire solid IT
Opposite substrate 32 provided with O (Indium tin oxide) electrode 31
The polyimide-based alignment films 33, 3
4 is formed. For these polyimide-based alignment films 33 and 34, polyimide is applied to a thickness of about 50 to 100 nm by roll coating, spin coating, or the like, and thereafter,
It is formed by curing at 180 ° C. for 2 hours.

Next, the TFT substrate 30 and the counter substrate 3
Rubbing or optical alignment processing is performed on each of the polyimide-based alignment films 33 and 34 of No. 2. Rubbing buff materials include cotton and rayon, but cotton is more stable in terms of buff residue (garbage) and retardation. Photoalignment is a technique for aligning liquid crystal molecules by non-contact linearly polarized ultraviolet irradiation. In addition to the rubbing, the polymer alignment film can be formed by obliquely incident polarized light or non-polarized light. As a polymer compound that can form such a polymer alignment film, for example, a polymethyl methacrylate-based polymer having azobenzene can be given.

Next, in order to remove the rubbing buff residue,
After washing with water or IPA (isopropyl alcohol), a common agent is applied to the TFT substrate 30 side, and a sealing agent is applied to the counter substrate 32 side. Acrylic, epoxy acrylate, or epoxy adhesive containing a conductive filler is used as the common agent, and acrylic, epoxy acrylate, or epoxy adhesive is used as the sealant. As the common agent and the sealant, any of a heat curing type, an ultraviolet irradiation curing type, and an ultraviolet irradiation curing + heat curing type can be used. It is preferable to use a radiation curing + heat curing type.

Next, spacers for obtaining a predetermined gap are sprayed on the counter substrate 32 side, and are superposed on the TFT substrate 30 at a predetermined position. After the alignment marks on the counter substrate 32 and the TFT substrate 30 are precisely aligned, the sealant is temporarily cured by irradiating ultraviolet rays, and then heat-cured collectively.

Next, a scribe break is performed to
A single liquid crystal panel in which the substrate 30 and the counter substrate 32 are overlapped is manufactured. Next, the liquid crystal 35 is applied to both substrates 30-32.
It is injected into the gap between them, and after the injection port is sealed with an ultraviolet adhesive, IPA cleaning is performed. Although the type of liquid crystal is not particularly limited as described above, for example, a high-speed TN (twisted nematic) mode using a nematic liquid crystal is generally used.

Next, the liquid crystal 35 is oriented by heating and quenching. Next, a flexible wiring is connected to the panel electrode extraction portion of the TFT substrate 30 by thermocompression bonding of an anisotropic conductive film, and a polarizing plate with a retardation plate is bonded to the counter substrate 32.

In the case where a liquid crystal panel (liquid crystal cell) is manufactured by a single surface assembly suitable for a small liquid crystal panel having a size of 2 inches or less, the TFT substrate 30 and the opposing substrate 32 are formed on the element formation surface in the same manner as described above. Polyimide-based alignment films 33 and 34 are formed, respectively, and the polyimide-based alignment films 33 and 34 are subjected to rubbing or alignment treatment using non-contact linearly polarized ultraviolet light.

Next, the TFT substrate 30 and the counter substrate 3
2 is singly divided by dicing or scribe break, and washed with water or IPA. Subsequently, a common agent is applied to the TFT substrate 30, and a sealing agent containing a spacer is applied to the counter substrate 32. Then, the two substrates are overlapped. Subsequent processes are the same as described above, and a description thereof will be omitted.

In the above-mentioned reflection type LCD, the opposing substrate 32 is a CF (color filter) substrate, and the color filter layer 46 is provided below the ITO electrode 31.
In such a reflection type LCD, incident light from the counter substrate 32 side is efficiently reflected by the reflection film 29 and emitted from the counter substrate 32 side.

When the reflective film 29 is also used as a pixel electrode for display as in the above-described example, and the polyimide-based alignment film 33 is directly formed thereon,
In the case of No. 3, the unevenness of the reflective film 29 serving as a base may cause unevenness in film thickness, rubbing unevenness, and rubbing may cause scratches or peeling and color unevenness.

Therefore, the reflection film 29 is formed so as not to conduct to the drain portion of the TFT so that it does not function as a pixel electrode, and a transparent electrode (I
(A TO electrode). In that case, TF
A thickness of 2 to 3 on the reflection film 29 which does not conduct to the drain portion of T
A transparent resin flattening film of about μm is formed, and a transparent electrode (ITO electrode) having a thickness of about 0.13 to 0.15 μm is formed thereon.
Is formed in a state of being electrically connected to the drain portion of the TFT.

As described above, if the transparent electrode is formed via the transparent resin flattening film, the surface of the transparent electrode is naturally flattened, so that the polyimide alignment film 33 formed thereon is also flattened. Therefore, unevenness in film thickness, rubbing unevenness, scratches and peeling due to rubbing, color unevenness, and the like are prevented from occurring, and quality and yield can be improved.

Further, when the TFT substrate 30 has an on-chip color filter (OCCF) structure in which a color filter is provided on the TFT substrate 30 in addition to the substrate structure shown in FIG. (Or ITO electrode with black mask is solid) and T
The FT substrate 30 is provided with a color filter.

Also in this case, for the TFT substrate 30, the above-described structure in which a transparent electrode (ITO electrode) is provided separately from the reflective film 29 as a pixel electrode can be adopted. That is, a transparent resin flattening film having a thickness of about 2 to 3 μm is formed on the reflection film 29 formed so as not to conduct to the drain portion of the TFT, and a color filter layer having a thickness of about 1 to 2 μm is formed thereon. I do. Then, a transparent resin flattening film having a thickness of about 1 to 2 μm is further formed thereon, and a transparent electrode (I) having a thickness of about 0.13 to 0.15 μm is formed thereon.
TO electrode) is formed in a state of being electrically connected to the drain of the TFT.

As described above, when the color filter and the transparent electrode are formed via the transparent resin flattening film, the surface of the transparent electrode is flattened as described above, and the polyimide alignment film 33 is also flattened. Therefore, it is possible to prevent unevenness in film thickness, uneven rubbing, scratches and peeling due to rubbing, uneven color, and the like, and to improve quality and yield. Incidentally, in the case of incorporating an auxiliary capacitance C _S shown in FIG. 12 in the pixel portion, electrostatic collector layer provided on the substrate 1 described above (not shown) may be connected to the drain region 19 of monocrystalline silicon .

As described above, according to the present embodiment, the following remarkable functions and effects can be obtained. (A) A step 4 having a predetermined shape / dimension is formed on a substrate 1 and is used as a seed for grapho-epitaxial growth (however,
By making the heating temperature during growth relatively low as 400 to 600 ° C.), a single-crystal silicon layer 7 having a high electron mobility of 540 cm ² / v · sec or more can be obtained. Becomes possible.

(B) The single-crystal silicon layer 7 has a smaller thickness than a conventional amorphous silicon layer or polycrystalline silicon layer.
Since it exhibits high electron and hole mobilities comparable to a single crystal silicon substrate, the resulting single crystal silicon bottom gate type MOSTFT has nMOS or pMOS or cMO having an LDD structure with high switching characteristics and low leakage current.
STFT display, high drive capability cMOS, nMO
A structure integrated with a peripheral driver circuit section made of S or pMOSTFT or a mixture of them becomes possible, and a display panel with high image quality, high definition, narrow frame, large screen, and high efficiency is realized. Further, since the single crystal silicon layer 7 has a sufficiently high hole mobility, a peripheral drive circuit for driving electrons and holes individually or in combination of both can be manufactured. Alternatively, a panel integrated with a display TFT having a pMOS or cMOS LDD structure can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) The low-melting-point metal melt is heated to a low temperature (for example, 400 to 600 ° C.).
Can be formed on a substrate heated to a temperature slightly higher than that by coating or other method.
The single crystal silicon layer 7 can be formed uniformly at a relatively low temperature (for example, 450 to 600 ° C.). Therefore, a glass substrate or a heat-resistant resin substrate having a relatively low strain point can be easily obtained, a low-cost substrate having good physical properties can be used, and the substrate can be enlarged.

(D) Since long-time annealing at an intermediate temperature and excimer laser annealing as in the case of the solid phase growth method are not required, productivity is high, and cost reduction is possible without using expensive manufacturing equipment. become.

(E) In this grapho-epitaxial growth, the composition ratio of tin and silicon, the heating temperature and cooling rate of the substrate,
By adjusting the N-type or P-type carrier impurity concentration to be added, a wide range of N-type or P-type conductive type and high-mobility single-crystal silicon layers can be easily obtained. This facilitates high-speed operation by lowering the resistance.

(F) If a color filter is formed on the display array section, the cost reduction can be realized by improving the aperture ratio and brightness of the display panel, omitting the color filter substrate, and improving the productivity.

(G) Since the low melting point metal layer 6 is formed of tin, even if tin is mixed into the obtained single-crystal silicon layer 7, this is an element of Group 4 of the periodic table. Therefore, the single crystal silicon layer 7 does not become a carrier in the silicon layer, so that the single crystal silicon layer 7 has high resistance. Further, tin remaining in the single crystal silicon layer 7 electrically inactivates crystal defects, so that the obtained single crystal silicon layer 7 has reduced junction leakage and improved electron mobility. Become.

<Second Embodiment> A fourth embodiment of the present invention will be described with reference to FIGS. In the embodiment of the present embodiment, the top gate type MOSTFT is provided in the display unit and the bottom gate type MOSTFT is provided in the peripheral drive circuit unit, as in the first embodiment. Unlike the embodiment, the present invention relates to a transmission type LCD. Therefore, the manufacturing process is the same from the process shown in FIG. 1A to the process shown in FIG. Then, in the embodiment of the present example, after these steps, as shown in FIG.
5. At the same time as opening a window for the drain portion contact of the display TFT in the insulating film 36, unnecessary portions of the SiO ₂ , PSG and SiN films in the pixel opening are removed to improve the transmittance. In this example, an opaque ceramic substrate cannot be used.

Next, as shown in (19) of FIG.
On the entire surface, a flattening film 28B of a photosensitive acrylic transparent resin is formed to a thickness of about 2 to 3 μm by spin coating or the like,
TF for display by general-purpose photolithography technology
A window is opened in the flattening film 28B on the drain side of T, and this is cured under predetermined conditions.

Next, as shown in (20) of FIG.
An ITO sputtered film having a thickness of about 130 to 150 nm is formed on the entire surface, and a transparent electrode (pixel electrode) 41 made of ITO in contact with the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology. Then, heat treatment (in forming gas, 200
(250 ° C./1 h), the contact resistance between the drain of the display TFT and ITO is reduced, and the transparency of ITO is improved.

Then, as shown in FIG.
And a transmission type LCD is assembled in the same manner as in the first embodiment. However, a polarizing plate is also attached to the TFT substrate side. In this transmissive LCD, transmitted light is obtained as indicated by a solid arrow, but it may be configured such that transmitted light from the counter substrate 32 side is obtained as indicated by an alternate long and short dashed arrow.

In the case of this transmission type LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.

That is, (1) in FIG. 1 to (16) in FIG.
The steps up to are performed in the same manner as described above. Then, as shown in FIG. 16 (17), PSG / SiO
_After opening the drain portion of the _second insulating film 25 to form an aluminum buried layer 41A for the drain electrode,
An N / PSG insulating film 36 is formed.

Next, as shown in FIG. 16 (18), a photoresist 61 in which each color of R, G, B is dispersed in a pigment for each segment is formed to a predetermined thickness (1 to 1.5 μm). As shown in (19) of FIG. 16, patterning is performed by using a general-purpose photolithography technique, leaving only predetermined positions (each pixel portion), and each color filter layer 61 (R), 61
(G) and 61 (B) are formed (on-chip color filter structure). At this time, the window of the drain part is also opened.

Next, as shown in (19) of FIG.
In a contact hole communicating with the drain of the display TFT, a light shielding layer 43 serving as a black matrix layer is formed by metal patterning over the color filter layer. For example, molybdenum is deposited to a thickness of 200 to 2 by sputtering.
A film is formed to a thickness of about 50 nm, and then patterned into a predetermined shape that covers the display TFT and shields light (on-chip black structure).

Next, as shown in (20) of FIG.
A flattening film 28B made of a transparent resin is formed, and a transparent electrode 41 is buried in a through hole provided in the flattening film so as to be connected to the light shielding layer 43.

As described above, by forming the color filter layer 61 and the light shielding layer 43 on the display array portion, the aperture ratio of the liquid crystal display panel can be improved, and the power consumption of the display module including the backlight can be reduced. Can be realized.

<Third Embodiment> A third embodiment of the present invention will be described. In the embodiment of this example, the above-described steps (concave portions) are formed on a glass substrate having a low strain point, and a single crystal silicon layer is grapho-epitaxially grown from a tin-lead-silicon alloy melt using the steps as a seed. The present invention relates to an active matrix reflective liquid crystal display (LCD) using a bottom gate type MOSTFT.

That is, in the present embodiment, the first
In the process shown in FIG. 1A in the embodiment, the strain point or the maximum use temperature of the substrate 1 is, for example, 60%.
A glass substrate as low as about 0 ° C., for example, a glass substrate such as borosilicate glass or aluminosilicate glass is used. this is,
It is inexpensive and easy to increase the size, and the thickness of the thin plate is increased (for example, 5
(00 × 600 × 0.1 to 1.1 mm thick), it can be rolled / lengthened. Of course, a quartz substrate or a crystallized glass substrate can also be used.

Then, after forming the step 4 in the same manner as described above, as shown in FIG.
Silicon (Si) containing from 0.05% by weight to 0.14% by weight
A tin (Sn) / lead (Pb) melt (at a temperature of 400 to 600 ° C.) is applied to the entire surface including the step 4. At this time, the substrate 1 is heated to 450 to 600C. In preparing the melt, a eutectic solder of, for example, Sn: Pb = 6: 4 can be used as the tin-lead alloy.

Next, the substrate 1 is kept in this state for several minutes to several tens of minutes and then gradually cooled (in the case of dipping, it is gradually pulled up, but in the case of floating, it is gradually moved along the surface of the molten liquid). .), The silicon dissolved in the tin / lead solution is used as a seed for crystal growth at the corners on the bottom surface of the step 4, as shown in FIG. Epitaxial growth is performed to deposit single crystal silicon, thereby forming a single crystal silicon layer 7 having a thickness of about 10 to 100 nm, preferably about 40 to 60 nm. If the dipping method or the floating method is adopted, the composition of the solution, the temperature, the pulling rate, and the like can be easily controlled, and the thickness of the epitaxial growth layer and the impurity concentration can be easily controlled.

In this case, the single crystal silicon layer 7 has the (100) plane epitaxially grown on the substrate as in the above-described embodiment.
By changing variously as in (a) to (f), the crystal orientation of the growth layer can be controlled.

After the single-crystal silicon layer 7 is deposited on the substrate 1 by grapho-epitaxial growth, tin and lead formed on the surface side are mainly used as in the first embodiment. Through a process of dissolving and removing the film to be formed with hydrochloric acid or the like, and further performing a predetermined process on the single crystal silicon layer 7 to form a top gate type MOSTFT on the display portion.
Further, bottom gate type MOSTFTs are formed in the peripheral drive circuit portion. Note that the structure shown in FIG. 8 is also applied to the present embodiment.

According to the present embodiment, in addition to the functions and effects described in the first embodiment, the following remarkable functions and effects can be obtained. (H) The single-crystal silicon layer 7 can be formed uniformly on the glass substrate 1 by grapho-epitaxial growth at a lower temperature of about 400 to 600 ° C.

(I) Therefore, since the single-crystal silicon layer 7 can be formed not only on a glass substrate but also on an insulating substrate such as a heat-resistant resin substrate, the substrate has a low strain point, low cost and good physical properties. The material can be arbitrarily selected, and the size of the substrate can be increased. A glass substrate or a heat-resistant resin substrate can be manufactured at a lower cost than a quartz substrate or a ceramic substrate, and can be made thinner / longer / rolled. It is possible to manufacture a large-sized glass substrate or the like that has been made long or rolled with good productivity and at low cost. When a glass having a low glass strain point (or a maximum operating temperature) (for example, 500 ° C.) is used as the glass substrate, if the constituent elements diffuse from the inside of the glass to the upper layer and affect the transistor characteristics, this is used. For the purpose of control, a barrier layer thin film (for example, silicon nitride: thickness of 50 to 200 nm)
Degree).

(J) In this low-temperature grapho-epitaxial growth, a wide range is adjusted by adjusting the composition ratio of the low melting point metal layer 6 composed of tin and lead, the heating temperature and the cooling rate, and the concentration of N-type or P-type carrier impurities to be added. Since an N-type or P-type conductivity type and a high mobility single crystal silicon layer can be easily obtained, V
Adjustment of th (threshold value) is facilitated, and high-speed operation by lowering the resistance becomes possible.

<Fourth Embodiment> A fourth embodiment of the present invention will be described.

This embodiment is different from the fifth embodiment in that the fifth embodiment is a reflection type LCD.
In the manufacturing process, a single-crystal silicon layer 7 is formed by low-temperature grapho-epitaxial growth using a low-melting-point metal layer 6 made of a tin-lead alloy in the same manner as described in the fourth embodiment. can do.

Then, using this single crystal silicon layer 7,
A transmissive LCD can be manufactured in the same manner as shown in FIGS. 14 to 16 in the fourth embodiment. However, in this example, it is not possible to use an opaque ceramic substrate or an opaque or low transmittance heat resistant resin substrate.

Therefore, in the present embodiment, the fifth
The fourth embodiment and the fourth embodiment can have excellent functions and effects. That is, in addition to the functions and effects of the first embodiment described above, it is possible to use a low-cost and thin and long substrate 1 such as a heat-resistant resin substrate such as borosilicate glass or heat-resistant polyimide. The conductivity type of the single crystal silicon layer 7 and Vth
Is easy to adjust, and by forming the color filter 42 and the black mask 43 on the display array portion,
Also, the aperture ratio of the liquid crystal display panel can be improved, and the power consumption of the display module including the backlight can be reduced.

<Fifth Embodiment> Referring to FIGS. 17 to 25, a fifth embodiment of the present invention will be described.

In the present embodiment, the peripheral drive circuit is provided with a bottom gate type pM similar to that of the first embodiment.
It is composed of a CMOS drive circuit composed of an OSTFT and an nMOSTFT. In addition, although the display section is of a reflective type, the TFTs have various gate structures and various combinations.

That is, in the above-described first embodiment, as shown in FIG. 17A, a top gate type n
While a MOSLDD-TFT is provided, FIG.
In the example shown in (B), the display unit has a bottom gate type nMO.
In the example shown in FIG. 17C, a dual gate type nMOS LD is provided in the display portion.
A D-TFT is provided.

Both the bottom gate type MOSTFT and the dual gate type MOSTFT can be manufactured in the same step as the bottom gate type MOSTFT of the peripheral drive circuit portion as described later. In the case where the gate structure of the TFT of the display portion is changed in this way, especially in the case of a dual gate type, the driving capability is improved by the upper and lower gate portions, which is suitable for high-speed switching. It can be selectively used to operate as a top gate type or a bottom gate type depending on the case.

The bottom gate type MO shown in FIG.
In the STFT, reference numeral 71 in the figure denotes a gate electrode made of Mo, Ta, or the like. Reference numeral 72 denotes an SiN film, 7
Reference numeral 3 denotes an SiO ₂ film, and a gate insulating film is formed by the SiN film and the SiO ₂ film. On this gate insulating film, a channel region using a single crystal silicon layer 7 and the like are formed similarly to the top gate type MOSTFT.

The dual gate type M shown in FIG.
In OSFT, the lower gate is a bottom gate type MOS.
Although the same as the TFT, the upper gate portion has a gate insulating film 73 formed of a SiO ₂ film and a SiO ₂ film, and an upper gate electrode 74 is provided thereon. However, in each case, each gate portion is provided outside the step 4 which is a seed at the time of grapho-epitaxial growth.

Next, the above-mentioned bottom gate type MOSTFT
Will be described with reference to FIGS. 18 to 22, and a method of manufacturing the dual gate type MOSTFT will be described with reference to FIGS. The method of manufacturing the bottom gate type MOSTFT in the peripheral drive circuit section is the same as the steps shown in FIGS. 1 to 6, and therefore, illustration and description thereof are omitted here.

In the display section, a bottom gate type MOST
In order to manufacture the FT, first, in the same manner as in the process shown in FIG. 1A, a molybdenum / tantalum (Mo.Ta) alloy is sputtered on the substrate 1 as shown in FIG. The film 71A is formed to a thickness of about 300 to 400 nm.

Next, in the same manner as in the step shown in FIG. 1B, the photoresist 7 is formed as shown in FIG.
0 is formed in a predetermined pattern, and using this as a mask, the sputtered film 71A is taper-etched so that the side end face 71a is
A gate electrode 71 having a trapezoidal cross section, which is gently inclined at ~ 45 °, is formed.

Next, after the photoresist 70 is removed, plasma CVD is performed on the substrate 1 including the sputtered film 71A as shown in FIG. 18 (3) in the same manner as in the step shown in FIG. 1 (3). The SiN film (about 200 n
m thickness) 72 and a SiO ₂ film (about 100 nm thickness) 73 are laminated in this order to form a gate insulating film.

Next, in the same manner as in the step shown in FIG. 2D, a photoresist 2 is formed in a TFT forming region in a predetermined pattern as shown in FIG. A plurality of steps 4 having an appropriate shape and dimensions are formed on the gate insulating film on 1 (and also on the substrate 1). As described above, the step 4 serves as a seed at the time of grapho-epitaxial growth of single-crystal silicon, and has a depth d of about 0.3 to 0.4 μm, a width w of about 2 to 3 μm, and a length of Perpendicular direction) is about 10 to 20 μm,
The angle (base angle) between the bottom surface and the side surface is substantially a right angle.

Next, the photoresist 2 is removed, and subsequently, in the same manner as in the step shown in FIG. 2 (5), tin containing silicon (or lead or tin. A molten liquid layer 6 made of a lead alloy) is applied on the substrate 1 under the same temperature conditions as in the above-described example.

Next, by gradually cooling in the same manner as in the step shown in FIG. 2 (3), the silicon dissolved in the molten liquid layer 6 is grown as graphite using the bottom surface of the step 4 as a seed. As shown in (6), a single-crystal silicon layer 7 having a thickness of, for example, about 10 to 100 nm, preferably about 40 to 60 nm is deposited. At this time,
Since the side end surface 71a of the underlying gate electrode 71 is a gentle slope, the epitaxial growth due to the step 4 is not hindered on this surface, and the single-crystal silicon layer 7 grows without step disconnection.

Next, as shown in FIG. 19 (7), the film 6A mainly composed of tin (or lead or a tin-lead alloy) formed on the surface side is dissolved and removed with hydrochloric acid or the like, and further necessary. Accordingly, the specific resistance is adjusted by doping an appropriate amount of impurity ions.

Next, after passing through the steps shown in FIGS. 2 (8) to 4 (10), the steps shown in FIG. 19 (8) are performed in the same manner as in the step shown in FIG. 4 (11). NMO of display unit
The gate portion of the STFT is covered with a photoresist 13;
The exposed source / drain regions of the nMOS TFT are doped (ion-implanted) with phosphorus ions 14 to form an LDD portion 15 made of an N ⁻ type layer in a self-aligned manner. At this time, the surface height difference (or pattern) is easily recognized due to the presence of the bottom gate electrode 71. Therefore, the alignment (mask alignment) of the photoresist 13 is easily performed, and alignment deviation hardly occurs.

Next, in the same manner as in the step shown in FIG. 5 (12), the nMOS TFT is formed as shown in FIG.
Is covered with a photoresist 16 and the exposed regions are doped (ion-implanted) with phosphorus or arsenic ions 17 to form a source portion 18 and a drain portion 19 made of the N ⁺ type layer of the nMOS TFT.

Next, in the same manner as in the step shown in FIG. 5 (13), as shown in FIG.
The entirety of T is covered with a photoresist 20 and boron ions 21 are doped (ion-implanted) to form a source portion and a drain portion of the P ⁺ layer of the pMOSTFT of the peripheral drive circuit portion.

Next, in the same manner as in the step shown in FIG. 5 (14), as shown in FIG. 20 (11), the photoresist 2
4 is provided, and the single crystal silicon layer 7 is selectively removed by etching.

Next, in the same manner as in the step shown in FIG. 6 (15), as shown in FIG.
D, a SiO ₂ film 53 (thickness of about 300 nm) and a phosphosilicate glass (PSG) film 54 (thickness of about 300 nm) are continuously formed in this order on the entire surface by high-density plasma CVD, catalytic CVD, or the like. Note that the SiO ₂ film 53 and the PSG film 54 correspond to the above-described protective film 25. Then, in this state, the single crystal silicon layer 7 is activated in the same manner as described above.

Next, in the same manner as in the step shown in FIG. 6 (16), as shown in FIG. 21 (13), a contact window is opened in the source section by general-purpose photolithography and etching techniques. And the thickness of 400 to 5
A sputtered film of an aluminum alloy having a thickness of about 00 nm is formed, and a data line and a gate line are formed simultaneously with the formation of the source electrode 26 of the TFT by general-purpose photolithography and etching techniques. Thereafter, sintering is performed at about 400 ° C./1 h in a forming gas.

Next, in the same manner as in the step shown in (17) of FIG. 6, as shown in (14) of FIG. 21, a PSG film (about 300 μm) is formed by high-density plasma CVD, catalytic CVD, or the like.
An insulating film 36 made of an SiN film (thickness: about 300 nm) and a SiN film (about 300 nm thick) is formed on the entire surface, and a contact window is opened in the drain of the display TFT.

Next, in the same manner as in the step shown in FIG. 7 (18), a photosensitive resin film 28 having a thickness of 2 to 3 μm is formed by spin coating or the like as shown in FIG. 21 (15). By using a general-purpose photolithography and etching technique, an uneven pattern for obtaining optimal reflection characteristics and viewing angle characteristics is formed in a pixel portion, and reflowed to form an uneven rough surface 2.
The lower surface of the reflection surface made of 8A is formed. TF for display at the same time
A resin window for contact of the drain portion of T is opened.

Next, in the same manner as in the step shown in FIG. 7 (20), 40
A sputtered film of an aluminum alloy or the like having a thickness of 0 to 500 nm is formed, and a reflection film 29 having an uneven shape connected to the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology.

As described above, the step 4 was used as a seed for low-temperature grapho-epitaxial growth to form a single-crystal silicon layer 7 from the silicon-containing low-melting-point metal melt layer 6, and this single-crystal silicon layer 7 was used. Bottom-gate type nMOS LDD-TFT (pMOS in peripheral area)
CMOS drive circuit composed of TFT and nMOS TFT)
The active matrix substrate 30 integrated with the display unit and the peripheral drive circuit unit incorporating the above can be manufactured.

FIG. 22 shows an example in which the gate insulating film of the bottom gate type MOSTFT provided in the display portion is formed by an anodic oxidation method of Mo · Ta.

In this example, after the step shown in FIG. 18B, the gate electrode 71 made of a molybdenum-tantalum alloy is subjected to a known anodic oxidation treatment as shown in FIG. A gate insulating film 74 made of Ta ₂ O ₅ is formed on the surface to a thickness of 100 to 200 nm.

Thereafter, (4) in FIG. 18 to (7) in FIG.
Step 4 is formed as shown in FIG. 22 (4) in the same manner as in the step shown in FIG. 22. Subsequently, a molten liquid composed of silicon-containing tin (or lead or a tin-lead alloy) is applied and melted. The liquid layer 6 is formed. Next, (8) in FIG. 19 to (1) in FIG.
In the same manner as in the step 6), the active matrix substrate 30 is manufactured as shown in FIG.

In the display section, a dual gate type MOS
In order to manufacture a TFT, first, (1) to FIG.
A process similar to the process shown in (7) is performed.

Next, as shown in FIG. 23 (8), steps 4 are formed on the insulating films 72 and 73 and the substrate 1, and
The single crystal silicon layer 7 is grown by grapho-epitaxial growth using the step 4 as a seed. Next, in the same manner as in the step shown in FIG.
SiO ₂ film (about 1) by plasma CVD, catalytic CVD, etc.
(Thickness: 00 nm) and SiN (thickness: about 200 nm) are successively formed in this order, an insulating film 80 (which corresponds to the gate insulating film 8 described above) is formed, and a sputtered film made of a Mo.Ta alloy is further formed. 81 (this corresponds to the aforementioned sputtered film 9)
Is formed to a thickness of about 300 to 400 nm.

Next, in the same manner as in the step shown in FIG. 4 (10), a photoresist pattern 10 is formed as shown in FIG.
-Ta alloy top gate electrode 82 and gate insulating layer 8
3 is formed to expose the single crystal silicon layer 7.

Next, in the same manner as in the step shown in FIG. 4 (11), the nMOSTF
T top gate portion is covered with photoresist 13;
Doping (ion implantation) phosphorus ions 14 into the exposed source / drain regions of the display nMOS TFT,
An LDD portion 15 of an N ⁻ type layer is formed.

Then, in the same manner as in the step shown in FIG. 5 (12), the nMOSTF
The gate portion and the LDD portion of T are covered with a photoresist 16 and the exposed region is doped (ion-implanted) with phosphorus or arsenic ions 17 to form a source portion 18 and a drain portion 19 made of an N ⁺ type layer of an nMOS TFT. I do.

Next, in the same manner as in the step shown in FIG. 5 (13), as shown in FIG.
The gate portion of T is covered with a photoresist 20 and the exposed region is doped with boron ions 21 (ion implantation).
Then, the source portion and the drain portion of the P ⁺ layer of the pMOSTFT of the peripheral drive circuit portion are formed.

Then, in the same manner as in the step shown in FIG. 5 (14), a photoresist 24 is provided for islanding the active element section and the passive element section as shown in FIG. The single crystal silicon thin film layer other than the element part and the passive element part is selectively removed by general-purpose photolithography and etching techniques.

Next, in the same manner as in the step shown in FIG. 6 (15), as shown in FIG.
D, S by high density plasma CVD, catalytic CVD, etc.
An iO ₂ film 53 (about 200 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface. These films 53 and 54 correspond to the protective film 25 described above. Then, the single crystal silicon layer 7 is activated.

Next, in the same manner as in the step shown in FIG. 6 (16), a contact window is opened in the source section as shown in FIG. 24 (15). And 400 to 50 on the whole surface
A sputtered film made of an aluminum alloy having a thickness of about 0 nm is formed, and a data line and a gate line are formed at the same time as the source electrode 26 is formed by general-purpose photolithography and etching technology.

Then, in the same manner as in the step shown in FIG. 6 (17), as shown in FIG. 25 (16), an insulating film made of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) 36 is formed on the entire surface, and TF for display is further formed.
A contact window is opened in the drain portion of T.

Next, as shown in (17) of FIG.
A photosensitive resin film 28 having a thickness of about 2 to 3 μm is formed on the entire surface by spin coating or the like. Subsequently, (20) and (2) in FIG.
In the same manner as in the step shown in 1), as shown in FIG. 25 (18), the lower part of the reflection surface composed of the roughened surface 28A is formed in the pixel part, and at the same time, the resin window for contact of the drain part of the display TFT is formed. Opening is performed, and a reflection film 29 made of a concavo-convex shape aluminum alloy or the like for obtaining optimum reflection characteristics and viewing angle characteristics is formed, which is connected to the drain portion 19 of the display TFT.

As described above, the dual gate type nMOS LD is used for the display section using the single crystal silicon layer 7 in which the step 4 is formed as a seed for the grapho-epitaxial growth.
DTFT is used as a bottom gate type pMO
A display-peripheral drive circuit unit integrated type active matrix substrate 30 in which a CMOS drive circuit composed of an STFT and an nMOSTFT is built can be manufactured.

<Sixth Embodiment> A sixth embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, unlike the above-described embodiments, the gate electrode of the top gate portion is formed of a material having relatively low heat resistance such as an aluminum alloy.

First, the top gate type MOSTF
A case where T is provided with a bottom gate type MOSTFT in the peripheral driving circuit portion will be described. In this example, first, the steps are performed in the same manner as the steps shown in FIGS. 1A to 3C in the first embodiment, and then, FIG.
As shown in (8), the pMOSTFT of the peripheral drive circuit section
An N-type well 7A is formed in the portion.

Next, as shown in FIG. 26 (9), all of the nMOS and pMOSTFTs in the peripheral drive region and the gate portion of the nMOSTFT in the display region are formed by photoresist 1
3 and cover the exposed source / drain regions of the nMOS TFT with phosphorus ions 14 at, for example, 20 kV and 5 × 10 5
^By doping (ion implantation) at a dose of ¹³ atoms / cm ² , an LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned manner.

Next, as shown in FIG. 27 (10),
All of the pMOSTFTs in the peripheral drive area, the gates of the nMOSTFTs in the peripheral drive area, and the
The gate of T and the LDD portion are covered with a photoresist 16, and the exposed region is doped (ion-implanted) with phosphorus or arsenic ions 17 at, for example, 20 kV at a dose of 5 × 10 ¹⁵ atoms / cm ² to form an nMOS TFT. N ⁺
LDD with Source 18 and Drain 19 Made of Mold Layer
The part 15 is formed. In this case, the resist 13 is left as shown by a dashed line in FIG.
If the resist 6 is provided, the resist 16 is
The alignment of the mask at the time of formation can be performed, thereby facilitating mask alignment and reducing misalignment.

Next, as shown in FIG. 27 (11),
NMOS TFT in peripheral drive area and nMOS in display area
The entirety of the TFT and the gate of the pMOSTFT are covered with a photoresist 20 and boron ions 2
1 is doped (ion-implanted) at, for example, 10 kV with a dose of 5 × 10 ¹⁵ atoms / cm ² , and pMOSTF
The source part 22 and the drain part 23 of the P ⁺ layer of T are formed.

Next, the resist 20 is removed.
As shown in FIG. 27 (12), the single-crystal silicon layers 7, 7
A is activated in the same manner as described above, and a gate insulating film 12 and a gate electrode material (aluminum or 1%
An aluminum alloy containing Si 11) is formed. The gate electrode material layer 11 can be formed by a vacuum evaporation method or a sputtering method.

[0187] Then, by patterning the respective gate portion in the same manner as described above, then, an island and an active element portion and the passive element portion, further as shown in (13) in FIG. 28, SiO ₂ film on the entire surface (Approximately 200 nm thick) and a phosphosilicate glass (PSG) film (approximately 300 nm thick) are successively formed in this order to form a protective film 25.

Next, as shown in FIG. 28 (14),
By general-purpose photolithography and etching technology, contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFT.

Then, a 500-600 nm-thick sputtered film of aluminum or an aluminum alloy containing 1% Si is formed on the entire surface, and all the TFs of the peripheral drive circuit and the display section are formed by general-purpose photolithography and etching technology.
T source electrode 26 and drain electrode 2 of peripheral drive circuit section
7 and a data line and a gate line are formed at the same time. Then, forming gas (N ₂ +
Sinter in H ₂ ) at about 400 ° C./1 h.

Next, (17) in FIG. 6 to (20) in FIG.
In the same manner as in the process shown in FIG. 1, a top gate type nMOS LDD-type transistor having a gate electrode of aluminum or an aluminum alloy containing 1% Si is provided for the display portion using the single crystal silicon layer 7 and the peripheral drive circuit portion, respectively.
TFT, bottom gate type pMOS TFT and nMOS
It is possible to manufacture an active matrix substrate 30 that integrates a display section and a peripheral drive circuit section and incorporates a CMOS drive circuit formed of TFTs.

In the present embodiment, the gate electrode 11 made of aluminum or an aluminum alloy containing 1% Si is formed after the activation treatment of the single crystal silicon layer 7. Since it is independent of the heat resistance of the electrode material, the heat resistance of the top gate electrode material is relatively low, and low-cost aluminum or an aluminum alloy containing 1% Si can be used. This is because the display unit is a bottom gate type M
The same applies to the case of the OSTFT.

Next, a dual gate type MOST is provided in the display section.
A case in which a bottom gate type MOS TFT is provided in the FT and the peripheral driving circuit will be described. In this example, first, the steps are performed in the same manner as the steps shown in (1) of FIG. 18 to (7) of FIG. 20 in the above-described fifth embodiment.
As shown in (8), the pMOSTF of the peripheral drive circuit section
An N-type well 7A is formed in the T portion.

Next, in the same manner as in the step shown in FIG. 26 (9), as shown in FIG.
The portion is doped with phosphorus ions 14 to form an LDD portion 15.

[0194] Then, similarly to the step illustrated in (10) in FIG. 27, phosphorus ions 17 doped nMOSTFT portion of the display portion and a peripheral driver circuit portion as shown in (10) in FIG. 30, N ⁺ -type Source region 18 and drain region 19
Are formed respectively.

Next, in the same manner as in the step shown in FIG. 27 (11), as shown in FIG. 30 (11), the pMOS TFT portion of the peripheral drive circuit portion is doped with boron ions 21 to form a P ⁺ type source region. 22 and a drain region 23 are respectively formed.

Next, the resist 20 is removed.
As shown in FIG. 30 (12), the single crystal silicon layer 7 is patterned to make the active element portion and the passive element portion into islands. Thereafter, as shown in FIG. 31 (13), the single crystal silicon layers 7, 7A are formed. Is activated in the same manner as described above, and a gate insulating film 80 is formed on the surface of the display portion, while a gate insulating film 12 is formed on the surface of the peripheral drive circuit portion.

Next, as shown in FIG. 31 (14),
An aluminum alloy film formed by a sputtering method is patterned on the entire surface to form each upper gate electrode 83 of the display section and each gate electrode 11 of the peripheral drive circuit section.

Next, as shown in FIG. 31 (15),
An SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 300 nm thick) are successively formed on the entire surface in this order, and a protective film 25 is formed.

Next, the source electrode 26 of all the TFTs in the peripheral driving circuit and the display section and the drain electrode 27 of the peripheral driving circuit section were formed in the same manner as described above, so that the single crystal silicon layer 7 was used. A display part-peripheral drive circuit in which a display part and a peripheral drive circuit part are formed with a CMOS drive circuit composed of a dual gate type nMOS LDD-TFT and a bottom gate type pMOSTFT and an nMOSTFT, respectively, each having a gate electrode made of aluminum alloy or the like. A partially integrated active matrix substrate 30 can be manufactured.

Also in this embodiment, since the gate electrode 83 made of an aluminum alloy or the like is formed after the activation process of the single crystal silicon layer 7, the influence of heat during the activation process depends on the heat resistance of the gate electrode material. Irrelevant, the heat resistance is relatively low as a gate electrode material, a low-cost aluminum alloy or the like can be used, and the choice of the electrode material is widened. The source electrode 26 in the step (14) of FIG.
(And also the drain electrode) can be formed at the same time, which is advantageous in the manufacturing process.

In any of the above-described embodiments, for example, when manufacturing a bottom gate type, a top gate type, or a dual gate type MOSTFT, FIG.
As schematically shown in FIG. 2 (A), when the step 4 is provided, the single crystal silicon film 7 grown on the step 4 may be thin, resulting in step disconnection (poor connection) or thinning (increase in resistance). In order to surely connect with the source electrode 26 (or the drain electrode), it is desirable to dispose the electrode on a region including the step 4, as shown in FIGS.

In the step shown in FIG. 26 (9) or the step shown in FIG. 29 (9), a top gate insulating film is formed on the single crystal silicon layer 7, and ion implantation and activation are performed. After the processing is sequentially performed, the top gate electrode, the source, and the drain electrode may be simultaneously formed using an aluminum alloy.

As described above, the step 4 is formed on the substrate 1 (and also on a film of SiN or the like thereon) as shown in FIG.
As shown in (B), the SiN film 51 on the substrate 1 has a function of stopping diffusion of ions from the glass substrate 1. ) Can also be formed. Instead of this SiN film 51,
Alternatively, the insulating films 72 and 7 are formed on the SiN film 51.
3 may be provided, and a step 4 may be formed on this.

<Seventh Embodiment> A ninth embodiment of the present invention will be described with reference to FIGS.

In this embodiment, various examples in which each TFT is formed outside the above-described step 4 (ie, on the substrate 1 other than the step) will be described. Note that the single-crystal silicon layer 7 and the gate / source / drain electrodes 26 and 27 are schematically illustrated.

First, FIG. 34 shows a top gate type MOSTF.
T is shown. In FIG. 34A, a recess due to the step 4 is formed on one side of the source along the source region, and the gate insulating film 12 and the gate electrode 11 are formed on the single crystal silicon layer 7 on the flat surface of the substrate other than the recess. Is formed. Similarly, in FIG. 34B, the concave portion due to the step 4 is formed not only in the source region but also in the L-shaped pattern along the channel length direction up to the end of the drain region, that is, over two sides. In FIG. 34 (c), the concave portion due to the step 4 is formed in a rectangular shape over four sides so as to surround the TFT active region. In FIG. 34D, a concave portion due to the step 4 is formed over three sides. However, adjacent concave portions are not continuous. In FIG. 34E, the concave portion due to the step 4 is formed in an L-shaped pattern over two sides. However, adjacent concave portions are not continuous.

As described above, it is possible to form recesses due to the steps 4 of various patterns, and since the TFT is provided on a flat surface other than the recesses, the degree of freedom in manufacturing the TFT is increased.
The fabrication itself becomes easier.

Next, FIG. 35 shows a bottom gate type MOSTF.
T is shown. As shown in FIGS. 35A to 35C, the steps 4 (or recesses) of various patterns shown in FIG. 35 can be similarly formed in the bottom gate type MOSTFT. In other words, FIG. 35A is an example corresponding to FIG.
Formed on a flat surface other than the recessed portion. Similarly, FIG. 35B corresponds to FIG.
(C) is an example corresponding to FIGS. 34 (c) and (d).

Next, FIG. 36 shows a dual gate type MOS.
3 shows a TFT. In this dual gate type MOSTFT, steps 4 (or concave portions) of various patterns shown in FIG. 34 can be similarly formed.
A dual-gate MOSTFT can be manufactured on the flat surface inside the step 4 shown in FIG.

<Eighth Embodiment> An eighth embodiment of the present invention will be described with reference to FIGS.

In this embodiment, the example shown in FIG. 37 is a double gate type TFT in which a plurality of TFTs having a self-aligned LDD structure, for example, a plurality of top gate type LDD-TFTs are connected.
It relates to the OSTFT. That is, in this example, as shown in FIG. 37, the gate electrode 11 is branched into two, one of which is the first LDD-TF as the first gate.
A second LDD-TF for T and the other as a second gate
Used for T (however, an N ⁺ -type region 100 is provided between gate electrodes at the center of the single crystal silicon layer to reduce the resistance). In this case, a different voltage may be applied to each gate, and even if one of the gates becomes inoperable for some reason, carriers are transferred between the source and the drain by using the remaining gates. Can be a reliable device.

Further, the first LDD-TFT and the second LDD
Since two thin film transistors for driving each pixel are formed by connecting two D-TFTs in series, the voltage applied between the source and the drain of each thin film transistor in the off state can be greatly reduced. it can. Therefore, the leakage current flowing during the off state can be reduced, and the contrast and the image quality of the liquid crystal display can be improved satisfactorily. Further, since the two LDD-TFTs are connected by using only the same semiconductor layer as that of the low-concentration drain region in the LDD-TFT, the connection distance between the transistors can be reduced, and the LDD-TFT can be reduced. Can be prevented from increasing the required area even if two are connected. The first,
The second gates may be completely separate from each other and operate independently.

In the example shown in FIG. 38A, the bottom gate type MOSTFT has a double gate structure.
The example shown in FIG. 38B is a dual gate type MOST.
The FT has a double gate structure.

These double-gate MOSTFTs have the same advantages as the above-mentioned top-gate type.
In particular, the dual gate type has an advantage that even if one of the upper and lower gate portions becomes inoperable, the other gate portion can be used.

FIG. 39 shows each of the aforementioned double-gate MOSs.
1 shows an equivalent circuit diagram of a TFT. In the above description, the gate is branched into two, but the gate may be branched or divided into three or more. Even in these double-gate or multi-gate structures, it can be configured to have two or more branched gate electrodes of the same potential or divided gate electrodes of different potentials or the same potential in the channel region. .

<Ninth Embodiment> Referring to FIG.
A ninth embodiment of the present invention will be described. In this embodiment mode, one of the upper and lower gate portions is operated as a transistor in the dual gate type TFT of the nMOSTFT, but the other gate portion is operated as follows.

That is, in the example shown in FIG.
In a MOSTFT, an arbitrary negative voltage is always applied to the gate electrode on the top gate side to reduce the leakage current in the back channel. By opening the top gate electrode, it can be used as a bottom gate type. In the example shown in FIG. 40B, an arbitrary negative voltage is always applied to the bottom gate electrode to reduce the leakage current of the back channel. Also in this case, by opening the bottom gate electrode, it can be used as a top gate type. In the case of a pMOSTFT, the back channel leakage current can be reduced by always applying an arbitrary positive voltage to the gate electrode.

In either case, the interface between the single crystal silicon layer 7 and the insulating film has poor crystallinity and a leak current easily flows, but the leak current can be cut off by applying a negative voltage to the electrode as described above. This is advantageous in combination with the effect of the LDD structure. In addition, a leak current may flow due to light incident from the glass substrate 1 side. However, since the light is blocked by the bottom gate electrode, the leak current can be reduced.

<Eleventh Embodiment> A twelfth embodiment of the present invention will be described with reference to FIGS. As described above, each of the top gate type, bottom gate type, and dual gate type TFTs has a difference in structure or function or a feature. Therefore, these TFTs are used in both the display portion and the peripheral drive circuit portion. In some cases, it may be advantageous to provide TFTs in various combinations between these components.

For example, as shown in FIG. 41, when any of a top gate type, a bottom gate type, and a dual gate type MOSTFT is employed for the display portion, a top gate type MOSTFT and a bottom gate type MOSTFT are used for the peripheral driving circuit.
At least a bottom gate type of the TFT and the dual gate type MOSTFT may be employed, or these may be mixed. There are twelve (No. 1 to No. 12) combinations. In particular, when a dual gate structure is used for the MOSTFT of the peripheral drive circuit,
Such a dual gate structure can be easily changed to a top gate type or a bottom gate type by selecting upper and lower gate portions, and a TFT having a large driving capability is required in a part of the peripheral driving circuit. In some cases, a dual gate type may be required. For example, it is considered necessary when the present invention is applied to the organic EL or FED of the present invention as an electro-optical device other than the LCD.

FIGS. 42 and 43 show the MOSTFT of the display section.
44 and FIG. 45 show that the MOST of the display section has the LDD structure when
Reference numeral 7 denotes a TF having an LDD structure in which a MOSTFT in a peripheral drive circuit section has an LDD structure.
48, FIG. 48 and FIG. 49 show respective MOSTs of the peripheral drive circuit unit and the display unit when both the peripheral drive circuit unit and the display unit include the MOSD with the LDD structure.
It is a figure which shows the various examples (No.1-No.216) which showed the combination of FT according to channel conductivity type.

As described above, the combinations according to the gate structure shown in FIG. 41 are specifically as shown in FIGS. 42 to 49. In this case, the same combination is possible even when the peripheral drive circuit portion is formed of a MOSTFT in which a bottom gate type and another gate type are mixed. FIG.
The various combinations of the TFTs shown in FIGS.
The present invention is not limited to the case where the channel region or the like is formed of single-crystal silicon, but is similarly applicable to the case where the channel region is formed of polycrystalline silicon or amorphous silicon (however, only the display portion).

<Eleventh Embodiment> Referring to FIGS. 50 and 51, an eleventh embodiment of the present invention will be described.

In the present embodiment, a TFT using the above-described single crystal silicon layer based on the present invention is provided in the peripheral driving circuit portion of the active matrix driving LCD in order to improve the driving capability. However, this is not limited to the bottom gate type, other gate types may be mixed, the channel conductivity type may be various, and a MOST using a polycrystalline silicon layer other than a single crystal silicon layer may be used.
FT may be included.

On the other hand, although it is desirable to use a single crystal silicon layer for the MOSTFT in the display section,
However, the present invention is not limited thereto, and a polycrystalline silicon or amorphous silicon layer may be used, or a mixture of two of the three types of silicon layers may be used. However, when the display portion is formed of an nMOS TFT, a practical switching speed can be obtained even if the display portion is formed using an amorphous silicon layer, but the TFT area can be reduced in single crystal silicon or polycrystalline silicon, and the pixel area can be reduced. It is more advantageous than amorphous silicon in reducing defects. During the grapho-epitaxial growth described above,
Polycrystalline silicon as well as monocrystalline silicon is produced at the same time, and may include a so-called CGS (Continuous Grain Silicon) structure, which can also be used for forming active elements and passive elements.

FIG. 51 shows examples (A), (B), and (C) of various combinations of MOSTFTs between respective parts, and FIG. 52 shows specific examples. When single crystal silicon is used, the current capability is improved, so that the element can be made smaller, a large screen can be obtained and the aperture ratio can be improved in the display portion.

In the peripheral drive circuit section, the above-described MOS is used.
It goes without saying that not only the TFT but also an electronic circuit in which a diode, a capacitance, a resistance, an inductance and the like are integrated may be integrally formed on an insulating substrate (a glass substrate or the like).

<Twelfth Embodiment> A twelfth embodiment of the present invention will be described with reference to FIG.

In this embodiment, the present invention is applied to passive matrix driving, while each of the above-described embodiments relates to an example of active matrix driving.

That is, in the present embodiment, the display section does not include a switching element such as the above-described MOSTFT, and receives light incident on the display section only by a potential difference caused by a voltage applied between a pair of electrodes formed on the opposing substrate. Alternatively, the reflected light is dimmed. Such dimming elements include reflective and transmissive LCDs, as well as organic or inorganic E-lights.
L (electroluminescence display element), FED (field emission display element), LEPD (light emitting polymer display element), LED (light emitting diode display element) and the like are also included.

<Thirteenth Embodiment> A thirteenth embodiment of the present invention will be described with reference to FIG.

In the embodiment of the present invention, the present invention is applied to an electro-optical device other than an LCD, such as an organic or inorganic EL (electroluminescence element), an FED (field emission display element),
It is applied to LEPD (light emitting polymer display element), LED (light emitting diode display element) and the like.

FIG. 53A shows an active matrix driven EL element. This EL element is, for example, an organic EL layer (or ZnS: M) using an amorphous organic compound.
An inorganic EL layer using n) 90 is provided on the substrate 1, the transparent electrode (ITO) 41 described above is formed below the substrate 1, and the cathode 91 is formed above the same. Thus, light of a predetermined color can be obtained through the color filter layer 61.

In this EL element, a MOSTFT is formed on the substrate 1 to apply a data voltage to the transparent electrode 41 by active matrix driving. Single-crystal silicon MOS according to the present invention using a single-crystal silicon layer obtained by epitaxial growth
It is a TFT (that is, an nMOSLDD-TFT).
Further, a similar TFT is provided in a peripheral driving circuit. Since the EL element having such a configuration is driven by a MOSLDD-TFT using a single crystal silicon layer, the switching speed is high and the leakage current is small.

It should be noted that the above filter 61
If the L layer 90 emits a specific color, it can be omitted. In the case of an EL element, since a driving voltage is high, it is advantageous to provide a high-withstand-voltage driver element (such as a high-withstand-voltage cMOSTFT and a bipolar element) in addition to the MOSTFT in the peripheral drive circuit portion.

FIG. 53B shows an FED driven by passive matrix. In this FED, electrons emitted from the cold cathode 94 by the voltage applied between the electrodes 92 and 93 are incident on the opposing phosphor layer 96 by selecting the gate line 95 in a vacuum portion between the opposing glass substrates 1-32. Thus, light emission of a predetermined color is obtained.

Here, the emitter line 92 is guided to a peripheral drive circuit and driven by a data voltage. The peripheral drive circuit is provided with a MOSTFT made of a single crystal silicon layer formed according to the present invention. , Emitter line 9
2 which contributes to high-speed driving. The FED can be driven in an active matrix by connecting the MOSTFT to each pixel.

In the device shown in FIG.
If a known light emitting polymer is used instead of the layer 90, a passive matrix or active matrix driven light emitting polymer display device (LEPD) can be formed. In addition, a device similar to the FED using the diamond thin film on the cathode side in the element of FIG. 53B can also be configured. Further, in the light emitting diode, the film of the light emitting portion can be grown by single crystal by the epitaxial growth method of the present invention.

The embodiments of the present invention described above can be variously modified based on the technical idea of the present invention. For example, at the time of forming the above-mentioned molten layer 6 of the low-melting-point metal, an element of Group 3 or Group 5 of the periodic table having high solubility, for example, boron, phosphorus, antimony, arsenic, aluminum, gallium, indium, bismuth, etc. By doping the melt of the low melting point metal in an appropriate amount, the P-type or N-type channel conductivity type of the silicon epitaxial growth layer 7 to be grown and the carrier concentration thereof can be arbitrarily controlled.

In order to prevent diffusion of ions from the glass substrate, a SiN film (for example, 50 to 200 nm) is formed on the substrate surface.
Thickness) and, if necessary, a SiO ₂ film (for example, 100
nm thick), and the step 4 described above may be formed in these films. The above-described step can be formed by an ion milling method or the like in addition to RIE.

Although the present invention is suitable for the TFTs in the peripheral drive circuit portion and the display portion, the present invention also provides an active region of an element such as a diode and a passive region such as a resistor, a capacitance, and an inductance. It is also possible to form a single-crystal silicon layer by using the method described above.

[0242]

As described above, according to the present invention, a single-crystal silicon layer or other single-crystal silicon layer is formed by using a step formed on a substrate as a seed from a low-melting-point metal melt layer in which a semiconductor material such as silicon is dissolved. The semiconductor layer is subjected to grapho-epitaxial growth to form a single-crystal semiconductor layer such as a single-crystal silicon layer. LC with integrated circuit
Since it is used for a bottom gate type MOSTFT of a peripheral drive circuit in an electro-optical device such as D, it has the following remarkable effects (A) to (G).

(A) A step having a predetermined shape / dimension is formed on a substrate, and the corner of the bottom of the step (bottom angle) is used as a seed for grapho-epitaxial growth to obtain a step of 540 cm.
^Since a single-crystal semiconductor layer such as a single-crystal silicon layer having a high electron mobility of ² / v · sec or more can be obtained, an electro-optical device such as a display thin-film semiconductor device with a built-in high-performance driver can be manufactured.

(B) In particular, since this single crystal silicon layer has high electron and hole mobilities comparable to those of a single crystal silicon substrate as compared with a conventional amorphous silicon layer or a polycrystalline silicon layer, a single crystal silicon layer obtained therefrom is obtained. Bottom-gate MOSTFTs have high switching characteristics [preferably, LDDs that reduce the electric field strength to reduce the leakage current.
(Lightly doped drain) structure], a display portion comprising an nMOS, pMOSTFT or cMOSTFT;
High drive capability cMOS, nMOS or pMOSTF
It is possible to realize a configuration in which a peripheral drive circuit section composed of T or a mixture thereof is integrated, and a display panel with high image quality, high definition, a narrow frame, high efficiency, and a large screen is realized.

(C) The above-mentioned low-melting-point metal melt is prepared at a low temperature (for example, 400 to 600 ° C.).
The single crystal silicon layer can be formed uniformly at a relatively low temperature (for example, 450 to 600 ° C.) because it can be formed on a substrate heated to a temperature slightly higher than that by a method such as coating. Therefore, a glass substrate having a relatively low strain point, a heat-resistant organic substrate, or the like can be easily obtained, a low-cost substrate having good physical properties can be used, and the substrate can be enlarged.

(D) Long-term annealing (about 600 ° C., about ten and several hours) at medium temperature as in the case of the solid phase growth method and excimer laser annealing are unnecessary, so that high productivity and expensive manufacturing equipment are required. Is unnecessary and cost can be reduced.

(E) In this grapho-epitaxial growth, a wide range of P is adjusted by adjusting the composition ratio of tin / silicon, the composition ratio of lead / silicon, the composition ratio of tin / lead / silicon, and the heating temperature and cooling rate of the substrate. Type or N-type conductivity and a high mobility single crystal silicon layer can be easily obtained.
(Threshold value) adjustment becomes easy, and high-speed operation by lowering the resistance becomes possible.

(F) When forming a semiconductor (amorphous silicon or polycrystalline silicon) film or a semiconductor-containing low melting point metal, an N-type or P-type carrier impurity (boron, phosphorus, antimony, arsenic, bismuth, aluminum) ) Is mixed (introduced) in an appropriate amount, the impurity type and / or its concentration of the single crystal semiconductor layer (single crystal silicon layer) composed of the grapho-epitaxial growth layer, that is, the conductivity type such as P-type / N-type and / or the like. Alternatively, the carrier concentration can be arbitrarily controlled.

(G) Since tin or lead or an alloy of tin and lead, or tin or lead or an alloy of tin and lead containing a semiconductor is used as the low melting point metal,
Even if tin or lead is mixed in the obtained single crystal silicon layer (single crystal semiconductor layer), these are elements of Group 4 of the periodic table and do not become carriers in the silicon layer. The layer becomes highly resistive. Therefore, Vth adjustment and resistance adjustment of the TFT by ion doping (implantation) or the like become easy, and a high-performance circuit configuration can be realized. In addition, tin and lead remaining in the silicon layer electrically inactivate crystal defects, so that the obtained silicon layer has a reduced junction leak and an increased electron mobility.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of an LCD (Liquid Crystal Display) according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 3 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 4 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 5 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 6 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 7 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 8 is a sectional view of a main part of the LCD.

FIG. 9 is a schematic perspective view for explaining the state of silicon crystal growth on an amorphous substrate.

FIG. 10 shows grapho-epitaxial growth technology.
It is a schematic sectional drawing which shows various step shapes and a silicon growth crystal orientation.

FIG. 11 is a perspective view showing an overall schematic layout of the LCD according to the first embodiment of the present invention.

FIG. 12 is an equivalent circuit diagram of the LCD.

FIG. 13 is a schematic configuration diagram of the same LCD.

FIG. 14 is a cross-sectional view showing a manufacturing process of the LCD according to the second embodiment of the present invention in the order of steps.

FIG. 15 is a sectional view of a main part of the LCD.

FIG. 16 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 17 is a sectional view of a main part of an LCD according to a fifth embodiment of the present invention.

FIG. 18 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 19 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 20 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 21 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 22 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 23 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 24 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 25 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 26 is a sectional view illustrating the manufacturing process of the LCD according to the sixth embodiment of the present invention in the order of steps.

FIG. 27 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 28 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 29 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 30 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 31 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 32 is a fragmentary cross-sectional view of the same at the time of manufacturing the LCD;

FIG. 33 is a fragmentary cross-sectional view of the same at the time of manufacturing the LCD;

FIG. 34 is a plan view or a sectional view showing various TFTs of an LCD according to a seventh embodiment of the present invention.

FIG. 35 is a cross-sectional view showing various TFTs at the time of manufacturing the LCD.

FIG. 36 is a cross-sectional view of a principal part of the LCD.

FIG. 37 is a cross-sectional view of a main part of an LCD according to an eighth embodiment of the present invention.

FIG. 38 is a cross-sectional view of a principal part of various TFTs of the LCD.

FIG. 39 is an equivalent circuit diagram of a TFT of the LCD.

FIG. 40 shows T of the LCD according to the ninth embodiment of the present invention.
It is principal part sectional drawing of FT.

FIG. 41 is a diagram showing a combination of TFTs of each part of the LCD according to the tenth embodiment of the present invention.

FIG. 42 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 43 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 44 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 45 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 46 is a view showing a combination of TFTs of each part of the LCD.

FIG. 47 is a view showing a combination of TFTs of each part of the LCD.

FIG. 48 is a view showing a combination of TFTs in each part of the LCD.

FIG. 49 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 50 is a schematic layout diagram of an LCD according to an eleventh embodiment of the present invention.

FIG. 51 is a diagram showing a combination of TFTs of each part of the LCD.

FIG. 52 is a schematic layout diagram of a device according to a twelfth embodiment of the present invention.

FIG. 53 is a sectional view of a main part of an EL and FED according to a thirteenth embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 4 ... Step, 6 ... Low melting metal layer, 7 ...
Single-crystal silicon layer, 9: sputtered film, 11: gate electrode, 12: gate oxide film, 14, 17: N-type impurity ion, 15: LDD portion, 18, 19: N ⁺ type source or drain region, 21: P Type impurity ions, 22, 23 ... P
⁺ Source or drain region, 25, 36 ... insulating film, 2
6, 27, 31, 41: electrode, 29: reflective film, 30: L
CD (TFT) substrate

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/336 H01L 29/78 612B H04N 5/66 102 613A 616A 626C 627G (72) Inventor Yuichi Sato Tokyo 6-35 Kita Shinagawa, Shinagawa-ku Sony Corporation (72) Inventor Hajime Yagi 6-35 Kita Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F-term (reference) 2H091 FA14Y FB04 FB08 FC02 FC22 FC23 GA06 GA13 HA07 HA08 HA10 HA11 HA12 LA03 LA15 LA17 LA19 2H092 GA59 HA28 JA23 JA25 JA26 JA35 JA36 JA38 JA39 JB43 JB52 JB58 JB62 KA03 KA04 KA05 KA10 KA12 KA19 KB05 KB13 MA03 MA05 MA07 MA08 MA10 NA15 MA19 PA01 PA02 PA06 PA08 PA09 PA12 QA07 QA08 QA10 QA11 QA13 QA14 QA15 2H093 NA16 NA42 NA43 NA53 NA64 NC09 NC11 NC33 NC34 NC40 NC50 ND06 ND17 ND22 ND42 NE01 NE02 NE03 NE06 NF05 NF06 NF11 NF13 NF19 NF20 5C058 AA09 AA11 AA12 AA13 AB01 BA35 5F110 AA06 AA08 AA09 AA18 AA30 BB02 BB04 CC02 CC08 DD03 DD02 DD03 DD02 DD03 DD03 DD02 DD FF29 FF30 GG02 GG12 GG13 GG15 GG16 GG33 HJ01 HJ04 HJ13 HJ23 HL03 HL06 HM15 HM18 NN03 NN04 NN23 NN24 NN25 NN35 NN44 NN46 NN47 NN54 NN73 PP23 PP24 PP34 PP36 QQ09 QQ11 Q

Claims (146)

[Claims] 1. A display device comprising: a display portion on which a pixel electrode is disposed; and a peripheral driver circuit portion disposed around the display portion on a first substrate. An electro-optical device including a predetermined optical material interposed therebetween, wherein a gate portion including a gate electrode and a gate insulating film is formed on one surface of the first substrate, A step is formed on one surface, and on the first substrate including the step, a molten liquid layer of a low-melting metal made of tin or lead containing a semiconductor or an alloy of tin and lead is formed. The semiconductor layer is grapho-epitaxially grown using the steps as seeds by cooling the melt layer of the low-melting-point metal, and a single-crystal semiconductor layer formed by deposition is provided. Source area and drain And down region, the electro-optical device characterized by bottom-gate type first thin film transistor constitutes at least a part of the peripheral driving circuit portion having the gate portion to the lower portion of the channel region. 2. The electro-optical device according to claim 1, wherein the semiconductor is a silicon material such as amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 3. The electro-optical device according to claim 2, wherein the step is formed as a concave portion such that a side surface of the bottom surface is perpendicular to the bottom surface or inclined toward a lower end. 4. The semiconductor device according to claim 1, wherein the single crystal semiconductor layer is N-type or P-type.
3. The electro-optical device according to claim 2, wherein the specific resistance is adjusted by mixing a type of carrier impurity. 5. The electro-optical device according to claim 2, wherein the gate electrode under the single-crystal silicon layer has a trapezoidal shape at a side end thereof. 6. The electro-optical device according to claim 2, wherein a diffusion barrier layer is provided between the first substrate and the single crystal semiconductor layer. 7. The electric device according to claim 2, wherein the first thin film transistor is provided in and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Optical device. 8. The electro-optical device according to claim 2, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the first thin film transistor. 9. The peripheral driving circuit section, wherein
A thin film transistor of a top gate type, a bottom gate type or a dual gate type having a polycrystalline or amorphous silicon layer as a channel region and a gate portion above and / or below the channel region, or the single crystal silicon The electro-optical device according to claim 2, wherein a diode, a resistor, a capacitance, an inductance element, or the like using a layer, a polycrystalline silicon layer, or an amorphous silicon layer is provided. 10. The electro-optical device according to claim 2, wherein in the display unit, a switching element for switching the pixel electrode is provided on the first substrate. 11. The switching element may be of a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region.
The electro-optical device according to claim 10, wherein the thin film transistor is a thin film transistor. 12. The gate electrode provided below the channel region is made of a heat-resistant material.
2. The electro-optical device according to 1. 13. The thin film transistor of the peripheral driver circuit portion and / or the display portion is configured as a single gate or a multi-gate, and in the case of a multi-gate, two or more branches of the same potential or in a channel region. The electro-optical device according to claim 11, further comprising divided gate electrodes having different potentials or the same potential. 14. The electro-optical device according to claim 11, wherein the thin film transistors of the peripheral driver circuit portion and the display portion form an n-channel, p-channel, or complementary insulated gate field-effect transistor. 15. The thin film transistor of the peripheral drive circuit section comprises a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. The electro-optical device according to claim 14. 16. A single type in which at least a part of the thin film transistor of the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure has an LDD portion between a gate and a source or a drain, or The electro-optical device according to claim 11, wherein the electro-optical device is a double type having an LDD portion between the gate, the source, and the drain. 17. A single crystal, polycrystal, or amorphous silicon layer is formed on the first substrate having the step formed thereon, and the second thin film transistor forms a channel on the single crystal, polycrystal, or amorphous silicon layer. 12. The semiconductor device according to claim 11, further comprising a gate portion at an upper portion and / or a lower portion of the channel region as a region, a source region, and a drain region.
An electro-optical device according to claim 1. 18. The method according to claim 1, wherein the thin film transistor of the peripheral driver circuit portion is the n-channel, p-channel, or complementary first thin film transistor, and the thin film transistor of the display portion has a single crystal silicon layer as a channel region. an n-channel type, a p-channel type, or a complementary type; an n-channel type, a p-channel type, or a complementary type when a polycrystalline silicon layer is used as a channel region; and an n-channel type when an amorphous silicon layer is used as a channel region. The electro-optical device according to claim 17, which is a p-channel type or a complementary type. 19. The electro-optical device according to claim 17, wherein a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step. 20. The electric device according to claim 17, wherein the second thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Optical device. 21. The electric device according to claim 17, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Optical device. 22. The electro-optical device according to claim 17, wherein the gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 23. The electro-optical device according to claim 17, wherein a diffusion barrier layer is provided between the first substrate and the single crystal, polycrystal, or amorphous silicon layer. 24. The electro-optical device according to claim 2, wherein the first substrate is made of a glass substrate or a heat-resistant resin substrate. 25. The electro-optical device according to claim 2, wherein the first substrate is optically opaque or transparent. 26. The electro-optical device according to claim 2, wherein the pixel electrode is provided for a reflective or transmissive display unit. 27. The electro-optical device according to claim 2, wherein a laminated structure of the pixel electrode and a color filter layer is provided in the display unit. 28. When the pixel electrode is a reflective electrode, irregularities are formed on the resin film, and the pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is formed by a transparent flattening film. The electro-optical device according to claim 2, wherein the pixel electrode is planarized, and the pixel electrode is provided on the planarized surface. 29. The display device according to claim 29, wherein the display unit emits light or modulates light when driven by the switching element.
The electro-optical device according to claim 10. 30. The electro-optical device according to claim 10, wherein a plurality of the pixel electrodes are arranged in a matrix on the display unit, and the switching element is connected to each of the pixel electrodes. 31. The electro-optical device according to claim 2, configured as a liquid crystal display, an electroluminescence display, a field emission display, a light emitting polymer display, a light emitting diode display, or the like. 32. The electro-optical device according to claim 1, wherein a control unit that controls an operation of the peripheral drive circuit unit and / or the display unit is provided on the first substrate. 33. The electro-optical device according to claim 32, wherein the control unit is a system-on-panel integrally formed with a so-called computer system, which is configured by a CPU, a memory, or a system LSI in which these are mounted. 34. A driving substrate for an electro-optical device, comprising a display portion on which a pixel electrode is disposed, and a peripheral driving circuit portion disposed around the display portion on a substrate, wherein one surface of the substrate is provided. A gate portion including a gate electrode and a gate insulating film is formed thereon, a step is formed on the one surface of the substrate, and tin or lead or tin containing a semiconductor is formed on the substrate including the step. A low-melting-point metal melt layer made of an alloy with lead is formed, and the low-melting-point metal melt layer is further subjected to cooling treatment so that the semiconductor is graphoepitaxially grown and deposited using the steps as seeds, and is deposited. A bottom gate having the single crystal semiconductor layer as a channel region, a source region, and a drain region, and the gate portion below the channel region. First driving substrate for an electro-optical device, wherein a thin film transistor constitutes at least a part of the peripheral driving circuit portion. 35. The driving substrate for an electro-optical device according to claim 34, wherein the semiconductor is a silicon material such as amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 36. The driving substrate for an electro-optical device according to claim 35, wherein the step is formed as a concave portion on the bottom surface such that a side surface is perpendicular to the bottom surface or inclined toward the lower end. 37. The driving substrate for an electro-optical device according to claim 35, wherein the specific resistance of the single crystal semiconductor layer is adjusted by mixing an N-type or P-type carrier impurity. 38. The gate electrode under the single-crystal silicon layer has a trapezoidal shape at a side end thereof.
A driving substrate for an electro-optical device according to claim 5. 39. The driving substrate for an electro-optical device according to claim 35, wherein a diffusion barrier layer is provided between the substrate and the single crystal semiconductor layer. 40. The method according to claim 35, wherein the first thin film transistor is provided inside and / or outside a concave portion of the substrate due to the step formed on the substrate and / or a film thereon.
A driving substrate for the electro-optical device according to the above. 41. The electro-optical device according to claim 35, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the first thin film transistor. Drive board. 42. In the peripheral driver circuit section, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type and a bottom type having a gate portion above and / or below the channel region. The electro-optic according to claim 35, wherein a gate, a dual-gate thin film transistor, or a diode, a resistor, a capacitance, an inductance element, or the like using the single crystal silicon layer, the polycrystal silicon layer, or the amorphous silicon layer is provided. Driving board for equipment. 43. The driving substrate for an electro-optical device according to claim 35, wherein in the display section, a switching element for switching the pixel electrode is provided on the substrate. 44. A switching device comprising a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region.
44. The driving substrate for an electro-optical device according to claim 43, wherein the driving substrate is a thin film transistor. 45. The gate electrode provided below the channel region is made of a heat-resistant material.
5. A drive substrate for an electro-optical device according to claim 4. 46. The thin film transistor of the peripheral driver circuit portion and / or the display portion is configured as a single gate or a multi-gate, and in the case of a multi-gate, two or more branched equal potential or The drive substrate for an electro-optical device according to claim 44, further comprising divided gate electrodes having different potentials or the same potential. 47. The electro-optical device according to claim 44, wherein the thin film transistors of the peripheral driver circuit portion and the display portion constitute an n-channel, p-channel, or complementary insulated gate field-effect transistor. Drive board. 48. The thin film transistor of the peripheral drive circuit portion is formed of a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. A drive substrate for an electro-optical device according to claim 47. 49. A single type in which at least a part of the thin film transistor of the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure has an LDD portion between a gate and a source or a drain, or The drive substrate for an electro-optical device according to claim 44, wherein the drive substrate is of a double type having an LDD portion between the gate and the source and the drain. 50. A single crystal on the substrate having the step,
A polycrystalline or amorphous silicon layer is formed, and the second thin film transistor forms the single crystal, polycrystalline, or amorphous silicon layer as a channel region, a source region, and a drain region, and an upper portion and / or a lower portion of the channel region. The drive substrate for an electro-optical device according to claim 44, further comprising a gate portion. 51. When the thin film transistor of the peripheral driver circuit portion is the n-channel, p-channel, or complementary first thin film transistor, and the thin film transistor of the display portion uses a single crystal silicon layer as a channel region an n-channel type, a p-channel type, or a complementary type; an n-channel type, a p-channel type, or a complementary type when a polycrystalline silicon layer is used as a channel region; and an n-channel type when an amorphous silicon layer is used as a channel region. The driving substrate for an electro-optical device according to claim 50, wherein the driving substrate is a p-channel type or a complementary type. 52. The driving substrate for an electro-optical device according to claim 50, wherein a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step. 53. The substrate according to claim 50, wherein the second thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon.
A driving substrate for the electro-optical device according to the above. 54. The electric device according to claim 50, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Driving substrate for optical devices. 55. The driving substrate for an electro-optical device according to claim 50, wherein the gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 56. The driving substrate for an electro-optical device according to claim 50, wherein a diffusion barrier layer is provided between the substrate and the single crystal, polycrystal, or amorphous silicon layer. 57. The driving substrate for an electro-optical device according to claim 35, wherein the substrate is a glass substrate or a heat-resistant resin substrate. 58. The driving substrate for an electro-optical device according to claim 35, wherein the substrate is optically opaque or transparent. 59. The driving substrate for an electro-optical device according to claim 35, wherein the pixel electrode is provided for a reflective or transmissive display unit. 60. The driving substrate for an electro-optical device according to claim 35, wherein a laminated structure of the pixel electrode and a color filter layer is provided in the display unit. 61. When the pixel electrode is a reflective electrode, irregularities are formed on the resin film, and the pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is formed by a transparent flattening film. 36. The driving substrate for an electro-optical device according to claim 35, wherein the driving substrate is planarized and the pixel electrode is provided on the planarized surface. 62. The display section, wherein the display section is configured to perform light emission or dimming by driving by the switching element.
A driving substrate for an electro-optical device according to claim 43. 63. The driving substrate for an electro-optical device according to claim 43, wherein a plurality of the pixel electrodes are arranged in a matrix on the display section, and the switching element is connected to each of the pixel electrodes. 64. The driving substrate for an electro-optical device according to claim 35, configured as a liquid crystal display, an electroluminescence display, a field emission display, a light emitting polymer display, a light emitting diode display, or the like. 65. The driving substrate for an electro-optical device according to claim 34, wherein a control unit for controlling an operation of the peripheral driving circuit unit and / or the display unit is provided on the substrate. 66. The electro-optical device according to claim 65, wherein the control unit is a system-on-panel integrally formed with a so-called computer system, which is configured by a CPU, a memory, or a system LSI in which these are mounted. Drive board. 67. A display device having a display portion on which a pixel electrode is provided, and a peripheral drive circuit portion provided around the display portion on a first substrate, wherein the first substrate, the second substrate, A method of manufacturing an electro-optical device having a predetermined optical material interposed therebetween, wherein a step of forming a gate portion comprising a gate electrode and a gate insulating film on one surface of the first substrate; Forming a step on the one surface of the first substrate; melting a low melting metal made of tin or lead containing a semiconductor or an alloy of tin and lead on the first substrate including the step; A step of forming a liquid layer; and a step of cooling the molten liquid layer of the low melting point metal to cause the semiconductor to undergo grapho-epitaxial growth using the step as a seed to deposit a single crystal semiconductor layer. To the specified processing Forming a tunnel region, a source region, and a drain region; and forming a first bottom-gate thin film transistor having the gate portion below the channel region and forming at least a part of the peripheral driver circuit portion. And a method for manufacturing an electro-optical device. 68. The method according to claim 67, wherein said semiconductor is a silicon material such as amorphous silicon or polycrystalline silicon, and said single crystal semiconductor layer is a single crystal silicon layer. 69. The method of manufacturing an electro-optical device according to claim 68, wherein the step is formed as a concave portion such that a side surface is perpendicular to the bottom surface or inclined toward the lower end side. 70. An impurity type and / or a concentration of an obtained single crystal semiconductor layer by mixing an N-type or P-type carrier impurity into the low-melting-point metal melt layer. Of manufacturing an electro-optical device. 71. The specific resistance of the single crystal semiconductor layer is adjusted by mixing an N-type or P-type carrier impurity into the single crystal semiconductor layer prior to performing the predetermined treatment on the single crystal semiconductor layer. A method for manufacturing an electro-optical device. 72. The method of manufacturing an electro-optical device according to claim 68, wherein the gate electrode under the single-crystal silicon layer is formed such that a side end thereof has a trapezoidal shape. 73. A diffusion barrier layer is formed on the first substrate, and a low-melting-point metal melt layer is formed thereon.
A method for manufacturing an electro-optical device according to claim 68. 74. The method of manufacturing an electro-optical device according to claim 68, wherein the cooling treatment is performed after applying the molten liquid of the low melting point metal to the heated first substrate, and holding the molten liquid for a predetermined time. 75. The electro-optical device according to claim 68, wherein the first thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Production method. 76. The method according to claim 68, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the first thin film transistor. . 77. After depositing the single-crystal silicon layer, an N-type or P-type carrier impurity is introduced into the single-crystal silicon layer to form the channel region, the source region, and the drain region. The manufacturing method of the electro-optical device according to the above. 78. In the peripheral driver circuit portion, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type and a bottom portion having a gate portion above and / or below the channel region. 70. The manufacturing of the electro-optical device according to claim 68, wherein a gate, a dual-gate thin film transistor, or a diode, a resistor, a capacitance, an inductance element, or the like using the single crystal silicon layer, the polycrystal silicon layer, or the amorphous silicon layer is provided. Method. 79. The method of manufacturing an electro-optical device according to claim 68, wherein a switching element for switching the pixel electrode is provided on the first substrate in the display section. 80. The electric device according to claim 79, wherein a second thin film transistor of a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region is formed as the switching element. A method for manufacturing an optical device. 81. When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat-resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. 81. The method of manufacturing an electro-optical device according to claim 80, wherein after forming the lower gate portion, the second thin film transistor is formed through steps common to the first thin film transistor including the step of forming the step. 82. After the single-crystal semiconductor layer is formed on the lower gate portion, an N-type or P-type carrier impurity is introduced into the single-crystal semiconductor layer to form source and drain regions, and then activated. The method for manufacturing an electro-optical device according to claim 81, wherein the process is performed. 83. After the formation of the single crystal semiconductor layer, the source and drain regions of the first and second thin film transistors are formed by ion implantation of the impurity using a resist as a mask, and the activation is performed after the ion implantation. The method for manufacturing an electro-optical device according to claim 82, wherein after forming the gate insulating film, an upper gate electrode of the second thin film transistor is formed. 84. When the second thin film transistor is of a top gate type, the source and drain regions of the first and second thin film transistors are ion-implanted using a resist as a mask after the formation of the single crystal semiconductor layer. 81. The method of manufacturing an electro-optical device according to claim 80, wherein an activation process is performed after the ion implantation, and then a gate portion including a gate insulating film and a gate electrode of the second thin film transistor is formed. 85. When the second thin film transistor is a top-gate type, a gate insulating film of the second thin film transistor and a gate electrode made of a heat-resistant material are formed after forming the single crystal semiconductor layer to form a gate portion. 81. The method according to claim 80, wherein the source and drain regions of the first and second thin film transistors are formed by ion implantation of an impurity element using the gate portion and the resist as a mask, and an activation process is performed after the ion implantation. Of manufacturing an electro-optical device. 86. The method of manufacturing an electro-optical device according to claim 80, wherein an n-channel type, a p-channel type, or a complementary type insulated gate field effect transistor is configured as the thin film transistor of the peripheral driver circuit portion and the display portion. . 87. The thin film transistor of the peripheral drive circuit portion is formed by a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. 89. The method for manufacturing an electro-optical device according to claim 86, wherein 88. At least a part of the thin film transistor in the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure is a single type having an LDD portion between a gate and a source or a drain, or a single type having an LDD portion. The method of manufacturing an electro-optical device according to claim 81, wherein the device is of a double type having an LDD portion between the source and the drain. 89. The electro-optical device according to claim 88, wherein a resist mask used for forming the LDD structure is left, and ion implantation for forming a source region and a drain region is performed using a resist mask covering the resist mask. Manufacturing method. 90. forming a single crystal, polycrystal, or amorphous silicon layer on the first substrate having the step formed thereon,
9. The second thin film transistor having a gate portion above and / or below the channel region, wherein the single crystal, polycrystalline, or amorphous silicon layer is used as a channel region, a source region, and a drain region.
0. A method for manufacturing an electro-optical device according to item 0. 91. When the thin film transistor of the peripheral driver circuit portion is the n-channel, p-channel, or complementary first thin film transistor, and the thin film transistor of the display portion is a single crystal silicon layer in a channel region, n A channel type, a p-channel type, or a complementary type; when a polycrystalline silicon layer is used as a channel region, an n-channel type, a p-channel type, or a complementary type;
The method of manufacturing an electro-optical device according to claim 90, wherein when the amorphous silicon layer is used as a channel region, the channel region is an n-channel type, a p-channel type, or a complementary type. 92. The method according to claim 90, wherein a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step. 93. The electro-optical device according to claim 90, wherein the second thin film transistor is provided in and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Production method. 94. The electro-optical device according to claim 90, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Manufacturing method. 95. The method of manufacturing an electro-optical device according to claim 90, wherein the gate electrode under the single crystal, polycrystal or amorphous silicon layer has a trapezoidal shape at a side end thereof. 96. The method according to claim 90, wherein a diffusion barrier layer is provided between the first substrate and the single crystal, polycrystal, or amorphous silicon layer. 97. The method according to claim 68, wherein the first substrate is a glass substrate or a heat-resistant resin substrate. 98. The method according to claim 68, wherein the first substrate is optically opaque or transparent. 99. The method according to claim 68, wherein the pixel electrode is provided for a reflective or transmissive display unit. 100. The method of manufacturing an electro-optical device according to claim 68, wherein a laminated structure of the pixel electrode and a color filter layer is provided in the display unit. 101. When the pixel electrode is a reflective electrode, an unevenness is formed on a resin film, and a pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is flattened by a transparent flattening film. The method for manufacturing an electro-optical device according to claim 68, wherein the pixel electrode is provided on the flattened surface. 102. The method of manufacturing an electro-optical device according to claim 79, wherein said display unit is configured to emit light or adjust light by being driven by said switching element. 103. The method of manufacturing an electro-optical device according to claim 79, wherein the plurality of pixel electrodes are arranged in a matrix on the display section, and the switching element is connected to each of the pixel electrodes. 104. The method for manufacturing an electro-optical device according to claim 68, wherein the method is configured as a liquid crystal display, an electroluminescence display, a field emission display, a light emitting polymer display, a light emitting diode display, or the like. 105. A step of performing a predetermined process on the single crystal semiconductor layer to form an element for constituting a control unit for controlling an operation of the peripheral driver circuit unit and / or the display unit. The manufacturing method of the electro-optical device according to the above. 106. An element for constituting the control unit may be a cMOSTFT, an nMOSTFT, or a pMOSTF.
106. The method of manufacturing an electro-optical device according to claim 105, comprising an active element such as T and a diode, and a passive element such as a resistor, a capacitor, and an inductance. 107. A display unit on which pixel electrodes are arranged, and a peripheral drive circuit unit arranged around the display unit are provided on a substrate, and a predetermined optical system is provided between the substrate and the second substrate. In a method of manufacturing a drive substrate for an electro-optical device having a material interposed, a step of forming a gate portion including a gate electrode and a gate insulating film on one surface of the substrate; and the one surface of the substrate. Forming a step on the substrate; forming, on the substrate including the step, a low-melting-point metal melt layer made of tin or lead containing a semiconductor or an alloy of tin and lead; and A step of subjecting the semiconductor to grapho-epitaxial growth using the step as a seed by cooling the molten metal layer to deposit a single-crystal semiconductor layer; Forming a region and a drain region; and forming a bottom-gate first thin film transistor having the gate portion below the channel region and constituting at least a part of the peripheral driver circuit portion. A method for manufacturing a drive substrate for an electro-optical device, comprising: 108. The method according to claim 107, wherein said semiconductor is a silicon material such as amorphous silicon or polycrystalline silicon, and said single crystal semiconductor layer is a single crystal silicon layer. 109. The method of manufacturing a driving substrate for an electro-optical device according to claim 108, wherein the step is formed as a concave portion such that a side surface of the bottom surface is perpendicular to the bottom surface or inclined toward a lower end. 110. An impurity type and / or concentration of an obtained single crystal semiconductor layer is controlled by mixing an N-type or P-type carrier impurity in the low-melting-point metal melt layer. A method for manufacturing a drive substrate for an electro-optical device. 111. An N-type or P-type semiconductor layer is formed on the single crystal semiconductor layer before the predetermined treatment is performed on the single crystal semiconductor layer.
Adjust the specific resistance by mixing the carrier impurities of the mold,
A method for manufacturing a drive substrate for an electro-optical device according to claim 108. 112. The gate electrode under the single crystal silicon layer is formed such that a side end portion has a trapezoidal shape.
A method for manufacturing a drive substrate for an electro-optical device according to claim 108. 113. The method for manufacturing a driving substrate for an electro-optical device according to claim 108, wherein a diffusion barrier layer is formed on the substrate, and a melted layer of the low melting point metal is formed thereon. 114. The method for manufacturing a driving substrate for an electro-optical device according to claim 108, wherein the cooling treatment is performed after applying the molten liquid of the low melting point metal to the heated substrate and holding the molten liquid for a predetermined time. 115. The driving substrate for an electro-optical device according to claim 108, wherein the first thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon. Manufacturing method. 116. The driving device for an electro-optical device according to claim 108, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the first thin film transistor. Substrate manufacturing method. 117. After depositing the single-crystal silicon layer, an N-type or P-type carrier impurity is introduced into the single-crystal silicon layer to form the channel region, the source region, and the drain region. 13. A method for manufacturing a drive substrate for an electro-optical device according to claim 1. 118. In the peripheral driver circuit portion, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type and a bottom portion having a gate portion above and / or below the channel region. A gate type or dual gate type thin film transistor, or a diode using the single crystal silicon layer or the polycrystalline silicon layer or the amorphous silicon layer, a resistor, a capacitance, an inductance element, or the like, is provided. A method for manufacturing a drive substrate. 119. The method of manufacturing a driving substrate for an electro-optical device according to claim 108, wherein a switching element for switching the pixel electrode is provided on the substrate in the display unit. 120. The electricity according to claim 119, wherein a second thin film transistor of a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region is formed as the switching element. A method for manufacturing a drive substrate for an optical device. 121. When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat-resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. 121. The driving substrate for an electro-optical device according to claim 120, wherein after forming the lower gate portion, the second thin film transistor is formed through steps common to the first thin film transistor including the step of forming the step. Production method. 122. After forming the single-crystal semiconductor layer on the lower gate portion, an N-type or P-type carrier impurity is introduced into the single-crystal semiconductor layer to form source and drain regions, and then activated. 121. Perform processing.
A method for manufacturing a driving substrate for an electro-optical device according to the above. 123. After forming the single crystal semiconductor layer, each source and drain region of the first and second thin film transistors is formed by ion implantation of the impurity using a resist as a mask, and the activation is performed after the ion implantation. The method for manufacturing a driving substrate for an electro-optical device according to claim 122, wherein after forming the gate insulating film, an upper gate electrode of the second thin film transistor is formed. 124. In the case where the second thin film transistor is a top gate type, after forming the single crystal semiconductor layer, each source and drain region of the first and second thin film transistors is ion-implanted using a resist as a mask. After this ion implantation, an activation process is performed.
120. Thereafter, a gate portion including a gate insulating film and a gate electrode of the second thin film transistor is formed.
A method for manufacturing a driving substrate for an electro-optical device according to the above. 125. In the case where the second thin film transistor is a top-gate type, after forming the single crystal semiconductor layer, a gate insulating film of the second thin film transistor and a gate electrode made of a heat-resistant material are formed. To form
121. The electro-optical device according to claim 120, wherein the source and drain regions of the first and second thin film transistors are formed by ion implantation of an impurity element using the gate portion and the resist as a mask, and an activation process is performed after the ion implantation. Of manufacturing a driving substrate for a semiconductor device. 126. An electro-optical device drive according to claim 120, wherein an n-channel, p-channel, or complementary insulated gate field effect transistor is formed as the thin film transistor of the peripheral driver circuit portion and the display portion. Substrate manufacturing method. 127. The thin film transistor of the peripheral drive circuit section is a set of a complementary type and an n-channel type, and
A pair of channel type, or complementary type, n-channel type and p
127. The method of manufacturing a driving substrate for an electro-optical device according to claim 126, wherein the driving substrate is formed as a pair with a channel type. 128. At least a part of the thin film transistor of the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure is a single type having an LDD portion between a gate and a source or a drain, or a gate type. 122. The method of manufacturing a driving substrate for an electro-optical device according to claim 121, wherein the driving substrate is of a double type having an LDD portion between the source and the drain. 129. The electro-optical device according to claim 128, wherein a resist mask used for forming the LDD structure is left, and ion implantation for forming a source region and a drain region is performed using a resist mask covering the resist mask. Of manufacturing a driving substrate for a semiconductor device. 130. A single crystal, polycrystal, or amorphous silicon layer is formed on the substrate having the step formed thereon, and the single crystal, polycrystal, or amorphous silicon layer is used as a channel region, a source region, and a drain region. 13. The second thin film transistor having a gate portion above and / or below the channel region.
0. A method for manufacturing a drive substrate for an electro-optical device according to 0. 131. When the thin film transistor of the peripheral driver circuit portion is the first thin film transistor of an n-channel type, a p-channel type, or a complementary type, and the thin film transistor of the display portion is a single crystal silicon layer in a channel region, n A channel type, a p-channel type, or a complementary type; an n-channel type, a p-channel type, or a complementary type when a polycrystalline silicon layer is used as a channel region; and an n-channel type or a p-channel when an amorphous silicon layer is used as a channel region. 130. The method of manufacturing a driving substrate for an electro-optical device according to claim 130, wherein the driving substrate is a mold or a complementary mold. 132. The method of manufacturing a driving substrate for an electro-optical device according to claim 130, wherein a source or drain electrode of said first and / or second thin film transistor is formed on a region including said step. 133. The driving substrate for an electro-optical device according to claim 130, wherein the second thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon. Manufacturing method. 134. The electro-optical device according to claim 130, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Of manufacturing a driving substrate for a semiconductor device. 135. The method of manufacturing a driving substrate for an electro-optical device according to claim 130, wherein the gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 136. The method for manufacturing a driving substrate for an electro-optical device according to claim 130, wherein a diffusion barrier layer is provided between said substrate and said single crystal, polycrystal or amorphous silicon layer. 137. The method of manufacturing a driving substrate for an electro-optical device according to claim 108, wherein said substrate is a glass substrate or a heat-resistant resin substrate. 138. The method according to claim 108, wherein said substrate is optically opaque or transparent. 139. The method for manufacturing a driving substrate for an electro-optical device according to claim 108, wherein said pixel electrode is provided for a reflective or transmissive display portion. 140. The method of manufacturing a driving substrate for an electro-optical device according to claim 108, wherein a laminated structure of the pixel electrode and a color filter layer is provided in the display unit. 141. When the pixel electrode is a reflective electrode, an unevenness is formed on a resin film, and a pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is flattened by a transparent flattening film. The method for manufacturing a driving substrate for an electro-optical device according to claim 108, wherein the pixel electrode is provided on the flattened surface. 142. The method of manufacturing a driving substrate for an electro-optical device according to claim 119, wherein the display section emits light or modulates light by driving the switching element. 143. The method for manufacturing a driving substrate for an electro-optical device according to claim 119, wherein a plurality of said pixel electrodes are arranged in a matrix on said display section, and said switching element is connected to each of said pixel electrodes. . 144. The method of manufacturing a driving substrate for an electro-optical device according to claim 108, wherein the driving substrate is configured as a liquid crystal display, an electroluminescence display, a field emission display, a light emitting polymer display, a light emitting diode display, or the like. . 145. A step of performing a predetermined process on the single crystal semiconductor layer to form an element for constituting a control unit for controlling an operation of the peripheral driver circuit unit and / or the display unit. A method for manufacturing a driving substrate for an electro-optical device according to the above. 146. An element for constituting the control unit is a cMOSTFT, an nMOSTFT, or a pMOSTF.
146. The method for manufacturing a drive substrate for an electro-optical device according to claim 145, comprising an active element such as T or a diode, or a passive element such as a resistor, a capacitor, or an inductance.