JP2000231124A - Electrooptical device, driving board for electrooptical device, and production of these - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for the production of an active matrix substrate housing high-performance drivers and for the production of an electrooptical device such as a display thin film semiconductor device using the substrate by uniformly forming a single crystal silicon layer having a high electron/hole mobility at a rather low temp. SOLUTION: A gate part consisting of gate electrodes 11 and a gate insulating film is formed on one surface of a first substrate 1, and further, steps 4 are formed on the surface of the first substrate 1. A semiconductor film is formed on the first substrate 1 including the steps. Then the semiconductor film is irradiated with laser beam to graphoepitaxially grow a single crystal semiconductor layer 7 with using the steps 4 as the seed. Then the single crystal semiconductor layer 7 is subjected to specified treatment to form channel regions, source regions and drain regions. Thus, dual gate type first thin film transistors which have the gate part in each of the upper and lower part of the channel region and which constitute at least a part of peripheral driving circuits are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device, a driving substrate for the electro-optical device, and a method for manufacturing the same. The dual-gate thin-film insulated gate field-effect transistor used
It is called a dual gate type MOSTFT. ) And a method of manufacturing the same.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device has a display portion using amorphous silicon for a TFT and an external driving circuit IC, and a display using a polycrystalline silicon for a TFT by a solid phase growth method. (Japanese Unexamined Patent Publication (Kokai) No. 6-242433), and an integrated type of a display unit and a drive circuit using excimer laser-annealed polycrystalline silicon for a TFT (Japanese Unexamined Patent Publication No. 7-131)
030) is known.

[0003]

However, in the above-mentioned conventional amorphous silicon TFT, although the productivity is good, the electron mobility is as low as about 0.5 to 1.0 cm ² / v · sec. (Hereafter, pM
It is called OSFT. ) Can not be made. Therefore, this pMOST is formed on the same glass substrate as the display unit.
Since a peripheral drive unit using FT cannot be formed, and a driver IC is mounted externally and mounted by a TAB method or the like, cost reduction is difficult, and there is a limit to high definition. is there. Furthermore, electron mobility is 0.5-1.
Since it is as low as about 0 cm ² / v · sec, sufficient on-current cannot be obtained, and the transistor size is inevitably increased when used in a display portion, which is disadvantageous for increasing the pixel aperture ratio. I have.

Further, the conventional polycrystalline silicon TF described above is used.
At T, the electron mobility is 70 to 100 cm ² / v · s
ec, which can cope with high definition. Therefore, recently, an LCD using a polycrystalline silicon TFT integrated with a driving circuit has been developed.
(Liquid crystal display devices) are attracting attention. However, 1
In the case of a large LCD of 5 inches or more, since the electron mobility of polycrystalline silicon is 70 to 100 cm ² / v · sec, the driving capability is insufficient, and eventually, an external driving circuit IC is required. ing.

In a TFT using polycrystalline silicon formed by a solid phase growth method, annealing is performed at a temperature of 600 ° C. or more for more than 10 hours, and a gate Si is formed by thermal oxidation at about 1000 ° C.
Since O ₂ needs to be formed, a dedicated semiconductor manufacturing apparatus must be used. Therefore, the wafer size is 8
Since the diameter is limited to 12 inches φ, high-heat-resistant and expensive quartz glass must be adopted, and it is difficult to reduce the cost. Therefore, the obtained product is currently EV
F and data / AV projector applications.

Further, in the above-described conventional polycrystalline silicon TFT by excimer laser annealing, stability of excimer laser output, increase in apparatus price due to increase in size, increase in yield /
Problems such as quality deterioration are piled up.

[0007] In particular, when a large glass substrate of 1 m square or the like is used, the above-mentioned problems are magnified, and it becomes more difficult to improve performance / quality and reduce costs.

An object of the present invention is to provide an active matrix substrate with a built-in high-performance driver by forming a single-crystal silicon thin film having a high electron / hole mobility at a relatively low temperature and uniformly, particularly in a peripheral driving circuit portion. Enables the manufacture of electro-optical devices such as display thin film semiconductor devices using the same, and has an LDD structure (Li
ghtly doped drain structure) n-channel MOSTF
T (hereinafter referred to as nMOSTFT) or pMOS
TFT or complementary thin-film insulated gate field-effect transistor with high driving capability (hereinafter referred to as cMOSTFT)
And a peripheral drive circuit composed of this cMOSTFT, nMOSTFT, or pMOSTFT, or a mixture of these, enabling a high-quality, high-definition, narrow frame, high-efficiency, large-screen display panel. It can be used even with a large glass substrate having a relatively low strain point, has high productivity, does not require expensive manufacturing equipment, enables cost reduction, and has a threshold adjustment. An object of the present invention is to enable high-speed operation and a large screen by low resistance.

[0009]

According to the present invention, a pixel electrode (for example, a plurality of pixel electrodes arranged in a matrix: the same applies hereinafter) and a peripheral drive circuit portion disposed around the display portion are provided as first components. An electro-optical device in which a predetermined optical material such as a liquid crystal is interposed between the first substrate and the driving substrate for the electro-optical device, and a driving substrate for the electro-optical device. A gate portion including a gate electrode and a gate insulating film is formed on one surface, a step is formed on one surface of the first substrate, and a step is formed on the first substrate including the step and the gate portion. Then, a film made of a semiconductor (for example, silicon) formed on the step is heated and melted by laser irradiation treatment, and then cooled (preferably gradually cooled) to be solidified. A single-crystal semiconductor layer (for example, a single-crystal silicon layer) is formed by growth, and the single-crystal semiconductor layer is used as a channel region, a source region, and a drain region, and the gate portion is provided above and below the channel region, respectively. The first of dual gate type
Thin film transistor (especially MOSTFT: the same applies hereinafter)
Constitute at least a part of the peripheral drive circuit section as a means for solving the problem.

In the present invention, the concept of a single crystal semiconductor includes not only single crystal silicon but also a single crystal compound semiconductor such as single crystal gallium arsenide (Ga.As) and single crystal silicon germanium (Si.Ge). (The same applies hereinafter). Further, in the present invention, a single crystal is a concept including a single crystal containing sub-grain boundaries and dislocations (the same applies hereinafter).

Further, the thin film transistor is
There are a field effect transistor (FET) (there is a MOS type and a junction type, whichever may be used) and a bipolar transistor, and the present invention can be applied to any of the transistors (the same applies hereinafter).

The present invention also relates to a method of effectively manufacturing the electro-optical device and its driving substrate, wherein a display section provided with pixel electrodes (for example, a plurality of pixel electrodes arranged in a matrix: the same applies hereinafter) is provided. And a peripheral driving circuit portion disposed around the display portion and a first substrate (that is, a driving substrate: the same applies hereinafter) by interposing a predetermined optical material such as liquid crystal between the first and second substrates. Forming a gate portion including a gate electrode and a gate insulating film on one surface of the first substrate; and a method of manufacturing the driving substrate for the electro-optical device. Forming a step on one surface, forming a semiconductor (for example, silicon) on the first substrate including the step and the gate portion, and performing a laser irradiation process on the film made of the semiconductor. Heat and melt the film Solidification by cooling (preferably slowly cooling) to form a single crystal semiconductor layer (for example, a single crystal silicon layer) by grapho-epitaxial growth using the step as a seed, and performing a predetermined treatment on the single crystal semiconductor layer to form a channel. Forming a region, a source region, and a drain region; and forming a dual-gate first thin film transistor having the gate portion above and below the channel region, and forming at least a part of the peripheral driver circuit portion. And a forming step.

According to the present invention, a semiconductor film formed on a substrate including a step is heated and melted by laser irradiation treatment and solidified by cooling by using the step as a seed, thereby growing the single crystal silicon layer by grapho-epitaxial growth. Such a single crystal semiconductor layer, this epitaxial growth layer,
Since it is used for a dual gate type MOSTFT of a peripheral driving circuit of a driving substrate such as an active matrix substrate and a dual gate type MOSTFT of a peripheral driving circuit in an electro-optical device such as an LCD integrated with a display unit and a peripheral driving circuit, (A) to (G).

(A) A step having a predetermined shape / dimension is formed on a substrate, and the bottom of the step (bottom angle) is used as a seed to perform grapho-epitaxial growth to 540 cm.
^{Since a} single-crystal semiconductor layer such as a single-crystal silicon layer having a high electron mobility of ² / v · sec or more can be obtained, an electro-optical device such as a display thin-film semiconductor device with a built-in high-performance driver can be manufactured. In this case, in a state viewed in cross section,
The side surface is perpendicular to the bottom surface or desirably 9
It is preferable that the step is formed as a concave portion which is inclined so as to form a base angle of 0 ° or less.

(B) In particular, the single-crystal silicon layer has high electron and hole mobilities comparable to those of a single-crystal silicon substrate as compared with a conventional amorphous silicon layer or polycrystalline silicon layer. The dual gate type MOSTFT has a high switching characteristic [preferably, an LD which reduces the electric field strength to reduce the leakage current.
D (Lightly doped drain) structure], a display unit composed of an nMOS, pMOSTFT, or cMOSTFT, and a cMOS, nMOS, or pMOS with high driving capability
A configuration in which a TFT or a peripheral drive circuit portion composed of a mixture of TFTs is integrated becomes possible, and a high-quality, high-definition, narrow frame, high-efficiency, large-screen display panel is realized. In particular,
In polycrystalline silicon, it is difficult to form a pMOSTFT having a high hole mobility as a TFT for an LCD. However, in a single crystal silicon layer according to the present invention, even a hole shows a sufficiently high mobility. Can be manufactured individually or in combination with each other, and this can be manufactured by using nMOS, pMOS, or cMOS.
A panel integrated with the TFT for a display portion having the LDD structure can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) In particular, since a dual gate type MOSTFT is used for the peripheral driving circuit, a cMO having a driving capability 1.5 to 2 times higher than that of a single gate type TFT is used.
An S, nMOS or pMOS TFT can be formed, and it becomes a TFT with higher performance and a large driving capability. This is particularly suitable when a TFT having a large driving capability is required in a part of the peripheral driving circuit. For example, not only one of the pair of peripheral vertical driving circuits can be omitted, but also it is considered to be advantageous when the present invention is applied to an organic EL or FED as an electro-optical device other than the LCD. Further, the dual gate structure can be easily changed to a top gate type or a bottom gate type by selecting the upper and lower gate portions, and even if one of the upper and lower gate portions becomes inoperable, one of the upper and lower gate portions becomes inoperable. A gate section can be used.

(D) A single crystal semiconductor layer such as a single crystal silicon layer can be formed by using the above-described step as a seed for grapho-epitaxial growth and subjecting the semiconductor film to laser irradiation on the step. A single-crystal silicon film or the like can be uniformly formed on a substrate at a low temperature. Accordingly, a glass substrate or a heat-resistant resin substrate having a relatively low strain point can be easily obtained, a low-cost substrate with good physical properties can be used, and the size of the substrate can be increased.

(E) Since annealing at a medium temperature for a long time (about 600 ° C., about ten and several hours) as in the case of the solid phase growth method is not required, productivity is high, and expensive manufacturing equipment is not required and cost is reduced. Becomes possible.

(F) In this grapho-epitaxial growth, a wide range of P-type or N-type is adjusted by adjusting the irradiation energy and irradiation time of the laser, the shape and dimensions of the step, and the heating temperature and cooling rate of the substrate. Since a single-crystal silicon layer of conductivity type and high mobility can be easily obtained, Vth (threshold) adjustment becomes easy, and high-speed operation by lowering the resistance becomes possible.

(G) A semiconductor (amorphous silicon or polycrystalline silicon) film, or a single crystal semiconductor layer (single crystal silicon layer) obtained by subjecting the film to laser irradiation, contains N-type or P-type carrier impurities. (Boron, phosphorus, antimony, arsenic, bismuth, aluminum, etc.), the impurity species and / or concentration of the single crystal semiconductor layer (single crystal silicon layer)
That is, the conductivity type such as P-type / N-type and / or the carrier concentration can be arbitrarily controlled.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail.
In the present invention, the step is formed such that a side surface is perpendicular to the bottom surface or a lower end (preferably) 9
As a concave portion having an inclined shape with a base angle of 0 ° or less,
It is preferable to form the insulating substrate or a diffusion barrier thereon, for example, a film of silicon nitride (SiN) or the like (or both of them), and use this step as a seed during the grapho-epitaxial growth of the single-crystal silicon layer.

Preferably, the step is formed along at least one side of an element region formed by the channel region, the source region and the drain region of the thin film transistor. Further, when a passive element, for example, a resistor is formed of the single crystal silicon layer, the step is preferably formed along at least one side of an element region where the resistor is formed. In this case, the first thin film transistor such as the MOSTFT may be provided in the substrate recess due to the step, or may be provided on the substrate outside the recess or both.

The step is formed by dry etching such as reactive ion etching, and the step is used as a seed to irradiate a silicon film (semiconductor film) made of amorphous silicon or polycrystalline silicon with a laser, thereby obtaining the single crystal silicon. Layers can be formed. In other words, the semiconductor film is irradiated with a laser such as an argon laser or an excimer laser, heated and melted, and further cooled (preferably gradually cooled), so that the semiconductor (silicon) is graphed with the step as a seed. Mono-crystalline silicon layer (5-100 n
m thickness, preferably 30 to 50 nm thickness). As a laser beam used for the laser irradiation process, a line beam (for example, 275 × 0.3 to 0.3 mm) is used.
4 mm ² ) and an area beam (for example, 100 × 100)
mm ² ) can be used.

When a short-wavelength pal laser beam (for example, an excimer laser) is used for the laser irradiation process, the laser wavelength is 100 to 400 (nm), and the practical range is 150 to 350.
(Nm) (e.g., XeCl; 308 nm wavelength), and a pulse width of 100 nsec or less (preferably 10 to 50 nsec)
c), the peak intensity of the pulse is 10 ⁶ W / cm ² to 10 ⁸
W / cm ² , fluence (energy of one pulse) is 1 J / cm ² or less (preferably 50 mJ / cm 2
^{2 to} 500 mJ / cm ² , more preferably 200 mJ / cm ²
cm ^{2 to} 500 mJ / cm ² ). Then, it is preferable to irradiate such a short-wavelength pulsed laser beam with an overlap scanning of 95% or more.

As for the formation of the single crystal silicon layer by such laser irradiation, a method of locally irradiating the laser with only a predetermined place, that is, only a TFT forming region, and performing epitaxial growth, instead of the whole, is also adopted. It is possible. Further, when forming a single crystal silicon layer by such a laser irradiation process, the substrate temperature is set at 2 ° C.
It is preferable to heat to 00 to 500 ° C.

In such laser irradiation processing, irradiation energy, irradiation time, irradiation and scanning method,
The melting state and the cooling state are affected by conditions such as the presence or absence of a low reflection film and the atmosphere (in a vacuum or an inert gas) at the time of irradiation, and silicon crystallinity (eg, electron / hole mobility, leak current, etc.) is affected. Therefore, it is necessary to determine conditions for obtaining the desired silicon crystallinity in advance by experiments and the like.

Further, by mixing an N-type or P-type carrier impurity into a semiconductor film made of amorphous silicon or polycrystalline silicon in advance, the obtained single-crystal silicon layer can be made to have an arbitrary concentration of N-type or P-type carrier impurity. Can be formed.

As the first substrate on which the first thin film transistor is formed, an insulating substrate, particularly a glass substrate having a low strain point or a heat-resistant resin substrate is used. Therefore, a single crystal silicon layer can be formed over a large glass substrate (for example, 1 m ² or more), and the substrate temperature at the time of forming the single crystal silicon layer by laser irradiation treatment is set to 20 as described above.
Since the temperature can be lowered to about 0 to 500 ° C., glass having a low strain point of 470 to 670 ° C. can be used as the glass substrate. Such a substrate is inexpensive, easily thinned, and can be manufactured on a long rolled substrate. Therefore, a single-crystal silicon layer formed by grapho-epitaxial growth can be continuously or discontinuously formed on such a long rolled glass plate or heat-resistant resin substrate by the above method.

Since the constituent elements are easily diffused from the inside of the glass into the upper layer of the glass having a low strain point, a diffusion barrier layer such as silicon nitride (SiN) is used for the purpose of suppressing the diffusion. Membrane (thickness eg 50-
(About 200 nm) is preferable.

As a method of forming a semiconductor (for example, amorphous silicon or polycrystalline silicon) on a substrate including a step, a known method such as a sputtering method or a plasma CVD method can be adopted. If an N-type or P-type carrier impurity such as B or B is added, or if a doping gas such as PH ₃ or B ₂ H ₆ is mixed in the supply gas, the N-type or P-type
Can be typed. If the single crystal silicon layer is made N-type or P-type in this way, the nMOSTF
The fabrication of T or pMOS TFTs can be facilitated,
Thereby, fabrication of the cMOSTFT can be facilitated.

As described above, the single-crystal silicon layer formed by the grapho-epitaxial growth on the substrate is replaced with the dual-gate type MO constituting at least a part of the peripheral drive circuit.
By forming the channel region, the source region, and the drain region of the STFT as the formation layer, the impurity species and / or the concentration of each of these regions can be controlled.

The thin film transistors of the peripheral drive circuit section and the display section constitute an n-channel, p-channel or complementary insulated gate field-effect transistor, for example, a set of a complementary type and an n-channel type, and a complementary type. It consists of a set of a p-channel type or a set of a complementary type, an n-channel type and a p-channel type. Further, it is preferable that at least a part of the thin film transistor of the peripheral drive circuit section and / or the display section has an LDD (Lightly doped drain) structure. Note that the LDD structure may be provided not only between the gate and the drain but also between the gate and the source or between the gate and the source and between the gate and the drain (this is referred to as a double LDD).

In particular, regarding the MOSTFT, an nMOS, pMOS or cMOS LD
A D-type TFT is formed, and cM
It is preferable to configure OS, nMOS, pMOSTFT, or a state in which these are mixed. The MOSTFT
May be provided in the concave portion of the substrate formed by the step, but may be provided outside the concave portion located near the concave portion, or both inside the concave portion and outside the concave portion.

In this case, the step is formed on one surface of the first substrate, and a single-crystal silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer is formed on the substrate including the step. . A channel region, a source region, and a drain region of the second thin film transistor are formed from such a silicon layer, respectively, and a gate portion is provided above and / or below the channel region. A dual-gate thin film transistor may be formed.

In this case as well, the side surface is at right angles to the bottom surface or 90 ° (preferably) 90 ° toward the lower end when viewed in cross section.
The step similar to the above may be formed as a concave part having a slope having the following base angle, and the step may be used as a seed during the grapho-epitaxial growth of the single crystal silicon layer.

Regarding the second thin film transistor,
The first substrate and / or a film formed thereon is provided inside and / or outside the concave portion of the substrate formed by the step, and similarly to the first thin film transistor, a single crystal silicon layer formed by grapho-epitaxial growth is used. , Drain and channel regions can be formed.

This second thin film transistor is also
As in the case described above, the N-type or P-type impurity species and / or the concentration thereof can be controlled by mixing N-type or P-type during the formation of the single-crystal, polycrystalline, or amorphous silicon layer. it can. Further, the step may be formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor.

Further, it is preferable that a gate electrode under the single crystal, polycrystal or amorphous silicon layer is trapezoidal at a side end thereof, and that the first substrate and the single crystal or polycrystal are formed. Alternatively, it is preferable to provide a diffusion barrier layer between the diffusion barrier layer and the amorphous silicon layer. A source or drain electrode of the first and / or second thin film transistor;
Preferably, it is formed on a region including the step.

The first thin film transistor is at least a dual gate type of a top gate type, a bottom gate type or a dual gate type having a gate portion above and / or below a channel region. Further, it is preferable that a switching element for switching a pixel electrode in the display portion is a second thin film transistor formed of any one of the top gate type, the bottom gate type, and the dual gate type.

In this case, the gate electrode provided below the channel region is formed of a heat-resistant material, or the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor are formed of a common material. can do.

In the peripheral driver circuit section, in addition to the first thin film transistor, a top gate type having a polycrystalline or amorphous silicon layer as a channel region and having a gate portion above and / or below the channel region;
A bottom-gate or dual-gate thin film transistor, or a diode, a resistor, a capacitor, an inductance element, or the like using the single-crystal silicon layer, the polycrystalline silicon layer, or the amorphous silicon layer may be provided.

The peripheral drive circuit section and / or the thin film transistor of the display section may be configured as a single gate or a multi-gate. When the n-channel or p-channel thin film transistor of the peripheral driver circuit portion and / or the display portion is a dual gate type, the upper or lower gate electrode is electrically open or an arbitrary negative voltage (n channel It is preferable to apply a positive voltage (for a p-channel type) or a positive voltage (for a p-channel type) to operate as a bottom-gate or top-gate thin film transistor.

The thin film transistor of the peripheral drive circuit section is an n-channel type, a p-channel type or a complementary type of the first thin film transistor.
Thin film transistor. Further, the thin film transistor of the display portion, a single crystal silicon layer, a polycrystalline silicon layer,
Whichever of the amorphous silicon layers is used as the channel region, the channel region can be an n-channel type, a p-channel type, or a complementary type.

In the present invention, after the growth of the single-crystal silicon layer, an upper gate portion including a gate insulating film and a gate electrode is formed on the single-crystal silicon layer, and the single-crystal silicon layer is formed using the upper gate portion as a mask. The channel region, the source region, and the drain region may be formed by introducing an impurity element belonging to Group 3 or Group 5 of the periodic table, that is, an N-type or P-type impurity into the layer.

When the second thin film transistor is of a bottom gate type or a dual gate type, a lower gate electrode made of a heat resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. After forming the lower gate portion, the second thin film transistor can be formed through steps common to the first thin film transistor including the step of forming the step. In this case, the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor may be formed of a common material.

After forming the single-crystal silicon layer on the lower gate portion, an impurity element of Group 3 or 5 of the periodic table is introduced into the single-crystal silicon layer to form source and drain regions. After that, an activation process can be performed.

After the formation of the single crystal silicon layer, the source and drain regions of the first and second thin film transistors are formed by ion-implanting an impurity element using a resist as a mask. After forming the gate insulating film, the upper gate electrode of the first thin film transistor and the second gate electrode
And the upper gate electrode of the thin film transistor described above.

When the second thin film transistor is of a top gate type, after forming the single crystal silicon layer, each source and drain of the first and second thin film transistors are implanted by ion-implanting an impurity element using a resist as a mask. A region may be formed, activation treatment may be performed after ion implantation, and thereafter, each gate portion including a gate insulating film and a gate electrode of the first and second thin film transistors may be formed.

Alternatively, when the second thin film transistor is a top gate type, after forming the single crystal silicon layer, each gate insulating film of the first and second thin film transistors and a gate electrode made of a heat resistant material are formed. Then, the source and drain regions may be formed by ion-implanting an impurity element using the gate and the resist as a mask, and an activation process may be performed after the ion implantation.

Alternatively, ion implantation for forming a source region and a drain region may be performed using a resist mask covering the resist mask used for forming the LDD structure. Further, the substrate may be made optically opaque or transparent, and a reflective or transmissive display pixel electrode may be provided.

When the display section has a laminated structure of the pixel electrode and the color filter layer, the color filter is formed on the display array section to improve the aperture ratio and brightness of the display panel. In addition, the cost can be reduced by omitting the color filter substrate and improving the productivity. In this case, when the pixel electrode is a reflective electrode, irregularities are formed on the resin film to obtain optimal reflection characteristics and viewing angle characteristics, and a pixel electrode is provided thereon, and the pixel electrode is a transparent electrode. At times, it is preferable to flatten the surface with a transparent flattening film and to provide a pixel electrode on this flattened surface.

The display section is configured to emit light or control light by being driven by the MOSTFT. For example, a liquid crystal display (LCD), an electroluminescence display (E)
L), field emission display (FED), light emitting polymer display (LEPD), light emitting diode display (LE
D) or the like. In this case, a plurality of the pixel electrodes may be arranged in a matrix on the display unit, and the switching element may be connected to each of the pixel electrodes.

A control section for controlling the operation of the peripheral drive circuit section and / or the display section may be provided on the first substrate. The control unit includes a CPU (Central Processing Unit, including a microprocessor), a memory (SR
A system-on-panel formed integrally with a so-called computer system formed by a system LSI or the like in which AM, DRAM, flash, ferroelectricity or the like are mixed.

In the case where such a control unit is provided on the first substrate, a predetermined process is performed on the single crystal semiconductor layer,
An element for constituting the control unit, for example, a cMOSTFT;
Active elements such as nMOSTFTs, pMOSTFTs, and diodes, and passive elements such as resistors, capacitors, and inductances are formed. Note that such a control unit may be formed in the same region as a vertical drive circuit or a horizontal drive circuit serving as a peripheral drive circuit unit, or may be formed in another region.

Next, a preferred embodiment of the present invention will be described in more detail. <First Embodiment> A first embodiment of the present invention will be described with reference to FIGS.

In the embodiment of the present invention, the silicon film (semiconductor film) formed on the heat-resistant substrate is heated and melted by laser irradiation using the above-mentioned step (recess) provided on the substrate as a seed, and then cooled. An active matrix reflective liquid crystal display device (LC) in which a single-crystal silicon layer (single-crystal semiconductor layer) is grapho-epitaxially grown by solidification and a dual-gate MOSTFT is formed using the single-crystal silicon layer.
D).

First, the overall layout of this reflective LCD will be described with reference to FIGS. In this active matrix reflective LCD, as shown in FIG. 10, a main substrate 1 (which constitutes an active matrix substrate, that is, a driving substrate) and a counter substrate 32 are bonded together via a spacer (not shown). It has a flat panel structure, in which liquid crystal (not shown) is sealed between the main substrate 1 and the counter substrate 32. Pixel electrodes 29 (or 41) arranged in a matrix on the surface of the main substrate 1
And a display unit including a switching element for driving the pixel electrode, and a peripheral drive circuit unit connected to the display unit.

The switching element of the display section is an nMOS, pMOS or cMOS according to the present invention, and is constituted by a top gate type MOSTFT having an LDD structure. In the peripheral drive circuit section, as a circuit element, a cMOS or nM of a dual gate type MOSTFT according to the present invention is used.
The OS or the pMOSTFT is formed as a single type or as a mixture.

The one peripheral drive circuit section is a horizontal drive circuit that supplies a data signal and drives the TFT of each pixel for each horizontal line. Also, the other peripheral drive circuit section
This is a vertical drive circuit that drives the gate of the TFT of each pixel for each scanning line, and is usually provided on both sides of the display unit. In this example, these drive circuits can be configured in either a dot-sequential analog system or a line-sequential digital system.

As shown in FIG. 11, the above-mentioned TFT is arranged at the intersection of the orthogonal gate bus line and data bus line, and image information is written into a liquid crystal capacitor (C _LC ) via this TFT, and the next information is written. Holds electric charge until comes. In this case, it is not enough to hold only the channel resistance of the TFT. To compensate for this, a storage capacitance (auxiliary capacitance) (C _S ) is added in parallel with the liquid crystal capacitance to compensate for a decrease in the liquid crystal voltage due to leak current. To do.

In such an LCD TFT, the required performance is different between the characteristics of the TFT used for the pixel portion (display portion) and the characteristics of the TFT used for the peripheral driving circuit. Securing current is an important issue. For this reason, as described later, the display unit
By providing a TFT having a D structure, an electric field is hardly applied between the gate and the drain, an effective electric field applied to the channel region is reduced, an off current is reduced, and a change in characteristics is reduced. However, in order to obtain such a configuration, there are problems in that the process becomes complicated, the element size increases, and the off-state current decreases. Therefore, it is necessary to optimize the design according to the intended use. is there.

Usable liquid crystals include TN liquid crystal (nematic liquid crystal used for TN mode of active matrix driving), STN (super twisted nematic), GH (guest / host), PC (phase change). , FLC (ferroelectric liquid crystal), AFL
Liquid crystals for various modes such as C (antiferroelectric liquid crystal) and PDLC (polymer dispersed liquid crystal) can be used.

Next, the circuit system of the peripheral drive circuit unit and the outline of the drive system will be described with reference to FIG. The drive circuit is divided into a gate-side drive circuit and a data-side drive circuit, and it is necessary to form a shift register on both the gate side and the data side. As the shift register, pMOSTF
Although there are those using both T and nMOSTFT (so-called CMOS circuit) and those using only one of the MOSTFTs, cMOSTFT or CMOS circuits are generally used in terms of operation speed, reliability, and low power consumption. It is a target.

The scanning drive circuit is composed of a shift register and a buffer, and sends a pulse synchronized with the horizontal scanning period from the shift register to each line. On the other hand, the data-side driving circuit has two driving methods, a dot sequential method and a line sequential method. The dot sequential method shown in FIG. 12 has a relatively simple circuit configuration, and the display signal is sequentially written to each pixel sequentially within one horizontal scanning time while controlling the display signal through an analog switch by a shift register. (R,
G and B schematically show pixels for each color).

Next, an active matrix reflective LCD according to the present embodiment will be described based on the manufacturing method (process) with reference to FIGS. In FIGS. 1 to 6, the left side of each drawing shows the manufacturing method (step) of the display unit, and the right side shows the manufacturing method (step) of the peripheral circuit unit.

First, as shown in FIG. 1A, on one main surface of an insulating substrate 1 such as borosilicate glass, quartz glass, or transparent crystallized glass, molybdenum / tantalum (M
o · Ta) Sputtered film 71A of alloy is formed to a thickness of 500 to 60
It is formed to about 0 nm. Next, as shown in FIG. 1B, a photoresist 70 is formed in a predetermined pattern.
Using this as a mask, the sputtered film 71A is taper-etched to form a gate electrode 71 whose side end 71a is gently inclined in a trapezoidal shape at 20 to 45 °.

Next, as shown in FIG. 1C, after removing the photoresist, an SiN film (about 2 nm) is formed on the substrate 1 including the sputtered film 71A by a plasma CVD method or the like.
A gate insulating film is formed by laminating a (thickness: 00 nm) 72 and an SiO ₂ film (about 100 nm) 73 in this order.

Next, as shown in FIG. 2D, a photoresist 2 is formed in a predetermined pattern on at least one TFT forming region on one main surface of the insulating substrate 1 and, using this as a mask, for example, F _{4 of} CF ₄ plasma is used. ^A plurality of steps 4 having an appropriate shape and dimensions are formed on the substrate 1 by general-purpose photolithography and etching (photoetching) such as reactive ion etching (RIE) using ⁺ ions 3.

In this case, the insulating substrate 1 is made of quartz glass,
Transparent crystal glass, ceramics, etc. (However, an opaque ceramic substrate or a low-transparency crystallized glass cannot be used in a transmission type LCD described later) (8).
１２12 inches φ, 700-800 μm thick) can be used. The step 4 serves as a seed during the later-described single-crystal silicon grapho-epitaxial growth and has a depth d of 0.
The width is about 1 to 0.4 μm, the width w is about 2 to 10 μm, and the length (in the direction perpendicular to the paper surface) is about 10 to 20 μm.
The angle (base angle) between the bottom surface and the side surface is substantially a right angle.

The surface of the substrate 1, especially when the substrate 1 is made of a glass substrate, is exposed to Na from the substrate 1 itself.
In order to prevent diffusion of ions and the like, an SiN film is
It is preferable to form the layer to a thickness of about 0 to 200 nm and, if necessary, to form a silicon oxide film (hereinafter referred to as SiO ₂ film) to a thickness of about 100 nm, for example.

Next, the photoresist 2 is removed, and then amorphous silicon or polycrystalline silicon is formed on the surface of the insulating substrate 1 on which the step 4 is formed by sputtering, plasma CVD or the like by about 10 to 100 nm, preferably 30 to 70 nm.
A silicon film (not shown) is formed to a thickness of about nm. At this time, an N-type or P-type carrier impurity, for example, phosphorus or boron is added in an appropriate amount (for example, 0.1 to 1.0 pp).
m) Targeting doped single crystal silicon,
Sputtering using this may form a silicon film in which the type and / or concentration of carrier impurities are adjusted.

In plasma CVD, an appropriate amount (for example, 0.1 to 1.0 ppm) of N ₃ type PH ₃ or AsH ₃ is mixed into monosilane or disilane gas or the like.
Appropriate amount of B ₂ H ₆ for mold (for example, 0.1 to 1.0 ppm)
By mixing, a silicon film in which the type and / or the concentration of the carrier impurity is adjusted may be formed.

Subsequently, the silicon film is irradiated with a laser beam to heat and melt the film, and then solidified by cooling (preferably gradually cooling), whereby silicon is grapho-epitaxially grown using the step 4 as a seed. As shown in (5), a single-crystal silicon layer 7 is formed on the entire surface including the step 4 to a thickness of about 5 to 100 nm, preferably 30 to 50 nm.
It is formed to a thickness of about nm. At this time, the side edge 71a of the underlying gate electrode 71 has a gentle slope, so that the epitaxial growth due to the step 4 is not hindered on this surface, and the single-crystal silicon layer 7 grows without step disconnection. Will do. When the substrate 1 is made of borosilicate glass or aluminosilicate glass, the substrate temperature is set to 200 to 500 ° C.
In the case of a quartz substrate, crystallized glass, or a ceramic substrate, the substrate temperature is set to 600 to 800 ° C.

As the laser irradiation processing, the short-wavelength pulse laser light (for example, excimer laser; XeC
1 (308 nm wavelength)) is preferably used, and in that case, it is preferable to perform irradiation with 95% or more overlap scanning. Incidentally, regarding the formation of the single crystal silicon layer 7 by such a laser irradiation process, as described above, not a whole but only a predetermined place, that is, a TFT
It is also possible to adopt a method in which only the formation region is locally irradiated with a laser to perform grapho-epitaxial growth. When forming the single crystal silicon layer 7 by such a laser irradiation process, the substrate temperature is set to 200 to 500.
It is preferable to adjust the heating to ℃. The heating of the substrate 1
In addition to the method of uniformly heating the entire substrate using an electric furnace,
Only at predetermined places by light laser, electron beam, etc.
For example, a method of locally heating only the TFT formation region is also possible.

In such laser irradiation processing, irradiation energy, irradiation time, irradiation and scanning method,
The melting state and the cooling state are affected by conditions such as the presence or absence of a low reflection film and the atmosphere (in a vacuum or an inert gas) at the time of irradiation, and silicon crystallinity (eg, electron / hole mobility, leak current, etc.) is affected. Therefore, it is necessary to determine conditions for obtaining the desired silicon crystallinity in advance by experiments and the like. Further, by mixing an N-type or P-type carrier impurity into a semiconductor film made of amorphous silicon or polycrystalline silicon in advance, the obtained single-crystal silicon film 4 contains an arbitrary concentration of N-type or P-type carrier impurity. Can be formed.

The single-crystal silicon layer 7 deposited as described above has a (100) plane epitaxially grown on a substrate, which is due to a known phenomenon called grapho-epitaxial growth. In this regard, as shown in FIG. 8, when a vertical wall such as the above-described step 4 is formed on an amorphous substrate (glass) 1 and an epitaxy layer is formed thereon, a random wall as shown in FIG. 8B, the (100) plane grows along the plane of the step 4 as shown in FIG. The size of the single crystal grain increases in proportion to the temperature and time. However, when the temperature and time are reduced and shortened, the interval between the steps must be shortened.

The shapes of the steps are shown in FIGS.
By changing variously as in (f), the crystal orientation of the growth layer can be controlled. When fabricating MOS transistors, the (100) plane is most often employed. In short, the cross-sectional shape of the step 4 may be such that the angle of the bottom corner (base angle) may be a right angle, or may be inclined inward or outward from the upper end to the lower end. It is sufficient if it has. Usually, the bottom angle of the step 4 is desirably a right angle or 90 ° or less, and the corner of the bottom surface preferably has a slight curvature.

After the single-crystal silicon layer 7 is deposited on the substrate 1 by grapho-epitaxial growth by laser irradiation in this manner, a dual-gate MOSTFT having the single-crystal silicon layer 7 as a channel region is then connected to a peripheral drive circuit. A top gate type MOSTFT is formed on the display unit as follows.

First, since the impurity concentration of the single crystal silicon layer 7 formed by the above-mentioned grapho-epitaxial growth varies, the entire surface is doped with an appropriate amount of a P-type carrier impurity, for example, boron ions to adjust the specific resistance. Further, only the pMOSTFT formation region is selectively doped with an N-type carrier impurity to form an N-type well. For example, the pMOSTFT portion is masked with a photoresist (not shown), and P-type impurity ions (for example, B ⁺ ) are
At a dose of 2.7 × 10 ¹¹ atoms / cm ² to adjust the specific resistance.

As shown in FIG. 2 (6), the pMO
In order to control the impurity concentration of the STFT formation region, nMOST
The FT portion is masked with a photoresist 60, and N-type impurity ions (for example, P ⁺ ) 65 are applied at 10 kV to 1 × 10 ^{11 at.}
ms / cm ^{2 at} a dose of N-type well 7
Form A.

Then, as shown in FIG. 3 (7), SiO ₂ (about 100 n) is formed on the entire surface of the single crystal silicon layer 7 by plasma CVD, high density plasma CVD, catalytic CVD or the like.
m thickness) and SiN (approximately 200 nm thickness) are successively formed in this order to form a gate insulating film 8.
A sputtered film 9 of a tantalum (Mo.Ta) alloy having a thickness of 50
It is formed to a thickness of about 0 to 600 nm.

Next, as shown in FIG. 3 (8), a photoresist pattern 10 is formed in a step region (in the concave portion) of the TFT portion of the display region by a general-purpose photolithography technique, and this is used as a mask. By performing continuous etching, a gate electrode 11 of a Mo.Ta alloy and a gate insulating film 12 having a laminated structure of (SiN / SiO ₂ ) are formed, and the single crystal silicon layer 7 is exposed. The sputtered film 9 made of the Mo.Ta alloy is treated with an acid-based etching solution, SiN is treated with plasma etching of CF ₄ gas, and SiO ₂ is treated with a hydrofluoric acid-based etching solution.

Next, as shown in FIG. 3 (9), all of the nMOS and pMOSTFTs in the peripheral drive region and the gate portion of the nMOSTFT in the display region are formed by photoresist 13
Then, phosphorus ions 14 are applied to the exposed source / drain regions of the nMOS TFT at, for example, 1 × 10 kV at 10 kV.
Doping (ion implantation) is performed at a dose of ¹³ atoms / cm ² to form an LDD portion 15 made of an N ⁻ -type layer in a self-aligned (self-aligned) manner.

Next, as shown in FIG. 4 (10), all of the pMOS TFTs in the peripheral drive region and n in the peripheral drive region
Gate portion of MOSTFT and nMOSTFT in display area
And the LDD portion are covered with a photoresist 16 and phosphorus or arsenic ions 17
Doping (ion implantation) is performed at 0 kv with a dose of 5 × 10 ¹⁵ atoms / cm ² , and the source 18 and the drain 19 and the LDD 1 made of the N ⁺ type layer of the nMOS TFT are formed.
5 is formed.

Next, as shown in FIG. 4 (11), the nMOSTFT in the peripheral drive region and the nMOSTT in the display region
The entirety of the FT and the gate of the pMOSTFT are covered with a photoresist 20 and boron ions 2
1 at 5 × 10 ¹⁵ atoms / cm ^{2 at} 10 kv, for example.
Doping (ion implantation) at a dose of pMOST
The source part 22 and the drain part 23 of the P ⁺ layer of the FT are formed. This step is unnecessary in the case of the nMOS peripheral drive circuit because there is no pMOSTFT.

Next, as shown in FIG.
A photoresist 24 is formed to make an active element portion such as an FT or a diode or a passive element portion such as a resistor or an inductance into an island. Then, the single crystal silicon layer 7 other than all the active element portions and the passive element portions in the peripheral drive region and the display region is removed by etching using a hydrofluoric acid-based etchant.

Next, as shown in FIG. 5 (13), an SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 200 nm thick) were formed on the entire surface by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. (Thickness of 300 nm) is formed continuously in this order, and the protective film 25 is formed.

Then, in this state, the single crystal silicon layer 7 is activated. For this activation, for example, a lamp of halogen or the like is used, and the annealing condition is set to about 1000.
C. for about 10 seconds. Therefore, a material that can withstand such annealing conditions is required as a gate electrode material, but the above-mentioned Mo / Ta alloy has a high melting point,
The structure can withstand such annealing conditions.
Further, since the gate electrode material made of the Mo.Ta alloy has a high melting point and can withstand annealing conditions, it can be formed not only as a gate portion but also as a wiring over a wide range. When annealing is performed using an excimer laser, XeCl (wavelength of 308 nm) is used.
It is desirable to perform irradiation processing on the entire surface or selectively only the active element portion and the passive element portion with 90% or more overlap scanning.

Next, as shown in FIG. 5 (14), contact windows for the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFTs are opened by general-purpose photolithography and etching techniques. .

Then, a sputtered film of aluminum or an aluminum alloy (for example, an aluminum alloy containing 1% Si or an aluminum alloy containing 1 to 2% copper), copper or the like is formed on the entire surface to a thickness of about 500 to 600 nm. By photolithography and etching techniques, the data lines and the gate lines are formed at the same time as the source electrodes 26 of all the TFTs in the peripheral drive circuit and the display section and the drain electrode 27 in the peripheral drive circuit section are formed. Then, about 4 times in forming gas (N ₂ + H ₂ ).
Sinter treatment at 00 ° C / 1h.

Next, as shown in FIG. 5 (15), an insulating film 36 made of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) is formed by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. Is formed on the entire surface.
Next, a contact window is opened in the drain portion of the display TFT. Note that SiO ₂ , PSG and SiN in the pixel portion are used.
The film does not need to be removed.

Here, as a basic requirement of the reflection type liquid crystal display device, a function of reflecting incident light and a function of scattering incident light must be provided inside the liquid crystal panel. This is because the direction of the observer with respect to the display is substantially determined, but the direction of the incident light cannot be uniquely determined. For this reason, it is necessary to design a reflector assuming that a point light source exists in an arbitrary direction. Therefore, as shown in (16) of FIG.
A photosensitive resin film 28 having a thickness of about 3 μm is formed. Subsequently, as shown in FIG. 6 (17), a concavo-convex pattern for obtaining optimum reflection characteristics and viewing angle characteristics is formed by general-purpose photolithography and etching technology. It is formed in the pixel portion and is reflowed to form a lower reflective surface made of the roughened surface 28A. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, as shown in (18) of FIG. 6, aluminum or 1 nm having a thickness of about 400 to 500 nm is formed on the entire surface.
% Sputtered film such as aluminum alloy containing Si,
Further, the sputtered film other than the pixel portion is removed by a general-purpose photolithography and etching technique, and a reflective film 29 made of a concavo-convex shaped aluminum alloy or the like connected to the drain portion 19 of the display TFT is formed. This reflection film 29
It also functions as a pixel electrode for display. Thereafter, sintering is performed in a forming gas at about 300 ° C. for 1 hour to make the contact sufficient. Note that silver or a silver alloy may be used instead of an aluminum-based material to increase the reflectance.

As described above, a single crystal silicon layer 7 is formed by laser irradiation using the step 4 as a seed for grapho-epitaxial growth, and a top gate type nMOSLDD-TF
T is a dual gate type pMOST in the peripheral drive circuit section.
The display-peripheral drive circuit unit integrated type active matrix substrate 30 incorporating the CMOS circuit constituted by the FT and the nMOSTFT can be manufactured.

Next, a method of manufacturing a reflective liquid crystal display (LCD) using the active matrix substrate (drive substrate) 30 will be described with reference to FIG. Hereinafter, this active matrix substrate is referred to as a TFT substrate.

When manufacturing the liquid crystal cell of this LCD by surface assembly suitable for a medium / large liquid crystal panel of 2 inch size or more, first, the TFT substrate 30 and the entire solid IT
Opposite substrate 32 provided with O (Indium tin oxide) electrode 31
The polyimide-based alignment films 33, 3
4 is formed. For these polyimide-based alignment films 33 and 34, polyimide is applied to a thickness of about 50 to 100 nm by roll coating, spin coating, or the like, and thereafter,
It is formed by curing at 180 ° C. for 2 hours.

Next, the TFT substrate 30 and the counter substrate 3
Rubbing or optical alignment processing is performed on each of the polyimide-based alignment films 33 and 34 of No. 2. Rubbing buff materials include cotton and rayon, but cotton is more stable in terms of buff residue (garbage) and retardation. Photoalignment is a technique for aligning liquid crystal molecules by non-contact linearly polarized ultraviolet irradiation. In addition to the rubbing, the polymer alignment film can be formed by obliquely incident polarized light or non-polarized light. As a polymer compound that can form such a polymer alignment film, for example, a polymethyl methacrylate-based polymer having azobenzene can be given.

Next, in order to remove the rubbing buff residue,
After washing with water or IPA (isopropyl alcohol), a common agent is applied to the TFT substrate 30 side, and a sealing agent is applied to the counter substrate 32 side. Acrylic, epoxy acrylate, or epoxy adhesive containing a conductive filler is used as the common agent, and acrylic, epoxy acrylate, or epoxy adhesive is used as the sealant. As the common agent and the sealant, any of a heat curing type, an ultraviolet irradiation curing type, and an ultraviolet irradiation curing + heat curing type can be used. It is preferable to use a radiation curing + heat curing type.

Next, spacers for obtaining a predetermined gap are sprayed on the counter substrate 32 side, and are superposed on the TFT substrate 30 at a predetermined position. After the alignment marks on the counter substrate 32 and the TFT substrate 30 are precisely aligned, the sealant is temporarily cured by irradiating ultraviolet rays, and then heat-cured collectively.

Next, a scribe break is performed to
A single liquid crystal panel in which the substrate 30 and the counter substrate 32 are overlapped is manufactured. Next, the liquid crystal 35 is applied to both substrates 30-32.
It is injected into the gap between them, and after the injection port is sealed with an ultraviolet adhesive, IPA cleaning is performed. Although the type of liquid crystal is not particularly limited as described above, for example, a high-speed TN (twisted nematic) mode using a nematic liquid crystal is generally used. Next, the liquid crystal 35 is oriented by heating and quenching. Next, a flexible wiring is connected to the panel electrode take-out portion of the TFT substrate 30 by thermocompression bonding of an anisotropic conductive film, and a polarizing plate with a retardation plate is bonded to the counter substrate 32.

When a liquid crystal panel (liquid crystal cell) is manufactured by a single surface assembly suitable for a small liquid crystal panel having a size of 2 inches or less, the TFT substrate 30 and the counter substrate 32 are formed on the element formation surface in the same manner as described above. Polyimide-based alignment films 33 and 34 are formed, respectively, and the polyimide-based alignment films 33 and 34 are subjected to rubbing or alignment treatment using non-contact linearly polarized ultraviolet light.

Next, the TFT substrate 30 and the counter substrate 3
2 is singly divided by dicing or scribe break, and washed with water or IPA. Subsequently, a common agent is applied to the TFT substrate 30, and a sealing agent containing a spacer is applied to the counter substrate 32. Then, the two substrates are overlapped. Subsequent processes are the same as described above, and a description thereof will be omitted.

In the reflection type LCD described above, the opposing substrate 32 is a CF (color filter) substrate, and the color filter layer 46 is provided below the ITO electrode 31.
In such a reflection type LCD, incident light from the counter substrate 32 side is efficiently reflected by the reflection film 29 and emitted from the counter substrate 32 side.

When the reflective film 29 is also used as a pixel electrode for display as in the above-described example, and the polyimide-based alignment film 33 is directly formed thereon,
In the case of No. 3, the unevenness of the reflective film 29 serving as a base may cause unevenness in film thickness, rubbing unevenness, and rubbing may cause scratches or peeling and color unevenness.

Therefore, the reflection film 29 is formed so as not to conduct to the drain portion of the TFT so that it does not function as a pixel electrode, and a transparent electrode (I
(A TO electrode). In that case, TF
A thickness of 2 to 3 on the reflection film 29 which does not conduct to the drain portion of T
A transparent resin flattening film of about μm is formed, and a transparent electrode (ITO electrode) having a thickness of about 0.13 to 0.15 μm is formed thereon.
Is formed in a state of being electrically connected to the drain portion of the TFT.

As described above, if the transparent electrode is formed via the transparent resin flattening film, the surface of the transparent electrode is naturally flattened, so that the polyimide alignment film 33 formed thereon is also flattened. Therefore, unevenness in film thickness, rubbing unevenness, scratches and peeling due to rubbing, color unevenness, and the like are prevented from occurring, and quality and yield can be improved.

Further, when the TFT substrate 30 has an on-chip color filter (OCCF) structure in which a color filter is provided on the TFT substrate 30 in addition to the substrate structure shown in FIG. (Or ITO electrode with black mask is solid) and T
The FT substrate 30 is provided with a color filter.

Also in this case, for the TFT substrate 30, the above-described structure in which a transparent electrode (ITO electrode) is provided separately from the reflective film 29 as a pixel electrode can be adopted. That is, a transparent resin flattening film having a thickness of about 2 to 3 μm is formed on the reflection film 29 formed so as not to conduct to the drain portion of the TFT, and a color filter layer having a thickness of about 1 to 2 μm is formed thereon. I do. Then, a transparent resin flattening film having a thickness of about 1 to 2 μm is further formed thereon, and a transparent electrode (I) having a thickness of about 0.13 to 0.15 μm is formed thereon.
TO electrode) is formed in a state of being electrically connected to the drain of the TFT.

As described above, when the color filter and the transparent electrode are formed via the transparent resin flattening film, the surface of the transparent electrode becomes flat as described above, and the polyimide alignment film 33 becomes flat. Therefore, it is possible to prevent unevenness in film thickness, uneven rubbing, scratches and peeling due to rubbing, uneven color, and the like, and to improve quality and yield. Incidentally, in the case of incorporating an auxiliary capacitance C _S of FIG. 11 in the pixel portion, electrostatic collector layer provided on the substrate 1 described above (not shown) may be connected to the drain region 19 of monocrystalline silicon .

As described above, according to the present embodiment, the following remarkable effects can be obtained. (A) A step 4 having a predetermined shape / dimension is formed on a substrate 1 and this is used as a seed to perform grapho-epitaxial growth by a laser irradiation process (however, a heating temperature during growth is 200 to 8).
By setting the temperature to 00 ° C., preferably 300 to 400 ° C., a single crystal silicon layer 7 having a high electron mobility of 540 cm ² / v · sec or more can be obtained. It becomes possible.

(B) The single-crystal silicon layer 7 has a smaller thickness than a conventional amorphous silicon layer or polycrystalline silicon layer.
Since it exhibits high electron and hole mobilities comparable to those of a single crystal silicon substrate, a single crystal silicon dual gate MOSTFT obtained therefrom has an nMOS or pMOS or cM having an LDD structure with high switching characteristics and low leakage current.
The display section of OSTFT, cMOS and nM of high drive capability
A configuration integrated with a peripheral drive circuit section composed of an OS, a pMOSTFT, or a mixture thereof becomes possible, and a display panel with high image quality, high definition, a narrow frame, a large screen, and high efficiency is realized. Further, since the single crystal silicon layer 7 has a sufficiently high hole mobility, a peripheral drive circuit for driving electrons and holes individually or in combination of both can be manufactured. Alternatively, a panel integrated with a display TFT having a pMOS or cMOS LDD structure can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) In particular, since a dual gate type MOSTFT is used for the peripheral driving circuit, a cMO having a driving capability 1.5 to 2 times higher than that of a single gate type TFT is used.
An S, nMOS or pMOS TFT can be formed, and it becomes a TFT with higher performance and a large driving capability. This is particularly suitable when a TFT having a large driving capability is required in a part of the peripheral driving circuit. In addition, the dual gate structure can be easily changed to a top gate type or a bottom gate type by selecting the upper and lower gate portions. A gate section can be used.

(D) Since the heat treatment temperature during the silicon epitaxial growth can be made 800 ° C. or less by employing the laser irradiation method, the heat treatment can be performed at a relatively low temperature (for example, 200 to 600 ° C. or less) on the insulating substrate. The single crystal silicon layer 7 can be formed uniformly. Substrates such as quartz glass, crystallized glass, and ceramic substrates, as well as borosilicate glass, aluminosilicate glass, and heat-resistant resin substrates, have low strain points, low cost, and good physical properties. The material can be arbitrarily selected, and the size of the substrate can be increased.

(E) Since long-time annealing is not required at a medium temperature as in the case of the solid phase growth method, the productivity is high,
In addition, expensive manufacturing equipment is not required and cost can be reduced.

(F) In this grapho-epitaxial growth, by adjusting the irradiation energy and irradiation time of the laser, the shape and size of the step, the heating temperature and cooling rate of the substrate, the concentration of N-type or P-type carrier impurities to be added, and the like. It is easy to obtain a single crystal silicon layer having a wide range of conductivity type such as N-type or P-type and high mobility, so that Vth (threshold) can be easily adjusted and high-speed operation can be performed by lowering resistance. Become.

(G) If a color filter is formed on the display array section, cost reduction can be realized by improving the aperture ratio and luminance of the display panel, omitting the color filter substrate, improving productivity, and the like.

<Second Embodiment> A second embodiment of the present invention will be described with reference to FIGS.

Although the present embodiment has a top gate type MOSTFT in the display unit and a dual gate type MOSTFT in the peripheral drive circuit unit, the first embodiment is similar to the first embodiment. Different from the form of the transmission type L
It is about CD. Accordingly, the manufacturing process is changed from the process shown in FIG. 1A to the process shown in FIG.
This is the same up to the step shown in FIG. Then, in the embodiment of this example, after these steps, as shown in FIG. 13 (16), a window for a drain portion contact of the display TFT is opened in the protective film 25 and the insulating film 36. , for improving the transmittance, unwanted SiO ₂ of the pixel opening, PSG and S
The iN film is removed.

Next, as shown in FIG. 13 (17),
On the entire surface, a flattening film 28B of a photosensitive acrylic transparent resin is formed to a thickness of about 2 to 3 μm by spin coating or the like,
TF for display by general-purpose photolithography technology
A window is opened in the flattening film 28B on the drain side of T, and this is cured under predetermined conditions.

Next, as shown in (18) of FIG.
An ITO sputtered film having a thickness of about 130 to 150 nm is formed on the entire surface, and a transparent electrode (pixel electrode) 41 made of ITO in contact with the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology. Then, heat treatment (in forming gas, 200
(250 ° C./1 h), the contact resistance between the drain of the display TFT and ITO is reduced, and the transparency of ITO is improved.

Then, as shown in FIG.
And a transmission type LCD is assembled in the same manner as in the first embodiment. However, a polarizing plate is also attached to the TFT substrate side. In this transmissive LCD, transmitted light is obtained as indicated by a solid arrow, but it may be configured such that transmitted light from the counter substrate 32 side is obtained as indicated by an alternate long and short dashed arrow.

In the case of this transmission type LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows. That is, the steps from (1) in FIG. 1 to (14) in FIG. 5 are performed in the same manner as described above. Then, as shown in FIG. 15 (15), the insulating film 25 of PSG / SiO ₂ is formed.
The drain portion is also opened to form an aluminum buried layer 41A for a drain electrode, and then a SiN / PSG insulating film 36 is formed.

Next, as shown in FIG. 15 (16), a photoresist 61 in which each color of R, G and B is dispersed in a pigment for each segment is formed to a predetermined thickness (1 to 1.5 μm). As shown in (17) of FIG. 15, patterning is performed by using a general-purpose photolithography technique while leaving only predetermined positions (each pixel portion), and each color filter layer 61 (R), 61
(G) and 61 (B) are formed (on-chip color filter structure). At this time, the window of the drain part is also opened. In this example, an opaque ceramic substrate, glass having low transmittance, and a heat-resistant resin substrate cannot be used.

Next, as shown in FIG. 15 (17),
In a contact hole communicating with the drain of the display TFT, a light shielding layer 43 serving as a black mask layer of the display TFT is formed by metal patterning over the color filter layer. For example, a film of titanium or molybdenum is formed to a thickness of about 200 to 250 nm by a sputtering method, and is then patterned into a predetermined shape that covers the display TFT and shields light (on-chip black structure).

Next, as shown in (18) of FIG.
A flattening film 28B made of a transparent resin is formed, and a transparent electrode 41 is buried in a through hole provided in the flattening film so as to be connected to the light shielding layer 43.

As described above, by forming the color filter layer 61 and the light shielding layer 43 on the display array portion, the aperture ratio of the liquid crystal display panel can be improved, and the power consumption of the display module including the backlight can be reduced. Can be realized.

<Third Embodiment> A third embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, the peripheral drive circuit is provided with a dual gate type p-type transistor similar to that of the first embodiment.
It is composed of a CMOS drive circuit composed of a MOSTFT and an nMOSTFT. In addition, although the display section is of a reflective type, the TFTs have various gate structures and various combinations.

That is, in the above-described first embodiment, as shown in FIG.
While the MOSLDD-TFT is provided, FIG.
In the example shown in (B), the display unit has a bottom gate type nMO.
An SLDD-TFT is provided. In the example shown in FIG.
A D-TFT is provided.

Both the bottom gate type MOSTFT and the dual gate type MOSTFT can be manufactured in the same step as the dual gate type MOSTFT of the peripheral drive circuit section as described later. In the case where the gate structure of the TFT of the display portion is changed in this way, especially in the case of a dual gate type, the driving capability is improved by the upper and lower gate portions, which is suitable for high-speed switching. It can be selectively used to operate as a top gate type or a bottom gate type depending on the case.

The bottom gate type MO shown in FIG.
In the STFT, reference numeral 71 in the figure denotes a gate electrode made of Mo, Ta, or the like. Reference numeral 72 denotes an SiN film, 7
Reference numeral 3 denotes an SiO ₂ film, and a gate insulating film is formed by the SiN film and the SiO ₂ film. On this gate insulating film, a dual gate type MOS of a peripheral driving circuit portion is provided.
Similar to the TFT, a channel region and the like using the single crystal silicon layer 7 are formed.

The dual gate type M shown in FIG.
In OSFT, the lower gate is a bottom gate type MOS.
Although the same as the TFT, the upper gate portion has a gate insulating film 82 formed of a SiO ₂ film and a SiO ₂ film, and an upper gate electrode 83 is provided thereon. However, in each case, each gate portion is provided outside the step 4 which is a seed at the time of grapho-epitaxial growth.

Next, the above-mentioned bottom gate type MOSTFT
17 will be described with reference to FIGS. 17 to 21. Further, a method of manufacturing the dual gate type MOSTFT will be described with reference to FIGS. The method of manufacturing the dual-gate type MOSTFT in the peripheral drive circuit section is the same as the steps shown in FIGS. 1 to 6, and therefore, illustration and description thereof are omitted here.

In the display section, a bottom gate type MOST
In order to manufacture the FT, first, a molybdenum / tantalum (Mo.Ta) alloy is sputtered on the substrate 1 as shown in FIG. The film 71A is formed to a thickness of about 300 to 400 nm.

Next, in the same manner as in the step shown in FIG. 1B, a photoresist 70 is formed in a predetermined pattern as shown in FIG. 17B and the sputtered film 71A is Taper etching, and the side end surface 71a is 2
A gate electrode 71 having a trapezoidal cross section that is gently inclined at 0 to 45 ° is formed.

Next, after the photoresist 70 is removed, plasma CVD is performed on the substrate 1 including the sputtered film 71A as shown in FIG. 17 (3) in the same manner as in the step shown in FIG. 1 (3). The SiN film (about 200 n
m thickness) 72 and a SiO ₂ film (about 100 nm thickness) 73 are laminated in this order to form a gate insulating film.

Next, in the same manner as in the step shown in FIG. 2D, a photoresist 2 is formed in a predetermined pattern in the TFT forming region as shown in FIG. A plurality of steps 4 having an appropriate shape and dimensions are formed on the gate insulating film on 1 (and also on the substrate 1). As described above, the step 4 serves as a seed during the later-described monocrystalline silicon grapho-epitaxial growth.
The depth d is about 0.3 to 0.4 μm, the width w is about 2 to 3 μm, the length (in the direction perpendicular to the paper surface) is about 10 to 20 μm, and the angle (base angle) between the bottom surface and the side surface is It is almost right angle.

Next, the photoresist 2 is removed, and then amorphous silicon or polycrystalline silicon is formed to a thickness of about 10 to 100 nm on the surface of the insulating substrate 1 on which the step 4 is formed by sputtering, plasma CVD, or the like. Then, a silicon film (not shown) is formed. Next, in the same manner as in the step shown in FIG. 2 (5), the silicon film is irradiated with a laser beam, and the film is heated and melted, and further cooled (preferably gradually cooled) to be solidified. FIG. 18 shows a grapho-epitaxial growth of silicon as a seed.
As shown in (5), a single-crystal silicon layer 7 is formed on the entire surface including the step 4 to a thickness of about 5 to 100 nm, preferably 30 to 50 nm.
It is formed to a thickness of about nm. At this time, the underlying gate electrode 71
Side end surface 71a is a gentle slope,
On this surface, the grapho-epitaxial growth due to the steps 4 is not hindered, and the single-crystal silicon layer 7 grows without any steps.

Then, after going through the steps shown in FIGS. 2 (6) to 3 (8), the steps shown in FIG. 18 (6) are performed in the same manner as the steps shown in FIG. 3 (9). NMOST of the display section
The gate portion of the FT is covered with a photoresist 13, and the exposed source / drain regions of the nMOS TFT are doped (ion-implanted) with phosphorus ions 14 to form an LDD portion 15 made of an N ⁻ -type layer in a self-aligned manner. At this time, the surface height difference (or pattern) is easily recognized due to the presence of the bottom gate electrode 71. Therefore, the alignment (mask alignment) of the photoresist 13 is easily performed, and alignment deviation hardly occurs.

Next, in the same manner as in the step shown in FIG. 4 (10), as shown in FIG.
Is covered with a photoresist 16 and the exposed regions are doped (ion-implanted) with phosphorus or arsenic ions 17 to form a source portion 18 and a drain portion 19 made of the N ⁺ type layer of the nMOS TFT.

Next, in the same manner as in the step shown in FIG. 4 (11), as shown in FIG.
Is covered with a photoresist 20, and boron ions 21 are doped (ion-implanted) to form a source portion and a drain portion of a P ⁺ layer of a pMOS TFT of a peripheral drive circuit portion.

Next, in the same manner as in the step shown in FIG. 4 (12), a photoresist 24 is formed to make the active element section and the passive element section into islands as shown in FIG. 19 (9).
Is provided, and the single crystal silicon layer 7 is selectively removed by etching.

Next, in the same manner as in the step shown in FIG. 5 (13), as shown in FIG.
D, a SiO ₂ film 53 (thickness of about 300 nm) and a phosphosilicate glass (PSG) film 54 (thickness of about 300 nm) are continuously formed in this order on the entire surface by high-density plasma CVD, catalytic CVD, or the like. Note that the SiO ₂ film 53 and the PSG film 54 correspond to the above-described protective film 25. Then, in this state, the single crystal silicon layer 7 is activated in the same manner as described above.

Next, in the same manner as in the step shown in FIG. 5 (14), a contact window of the source portion is opened by general-purpose photolithography and etching as shown in FIG. 20 (11). And the thickness of 400 to 5
A sputtered film of an aluminum alloy or the like having a thickness of about 00 nm is formed, and a data line and a gate line are formed at the same time when the source electrode 26 of the TFT is formed by general-purpose photolithography and etching technology. Thereafter, sintering is performed at about 400 ° C./1 h in a forming gas.

Next, in the same manner as in the step shown in FIG. 5 (15), the PSG film (about 300 μm) is formed by high-density plasma CVD, catalytic CVD, etc. as shown in FIG. 20 (12).
An insulating film 36 made of an SiN film (thickness: about 300 nm) and a SiN film (about 300 nm thick) is formed on the entire surface, and a contact window is opened in the drain of the display TFT.

Next, in the same manner as in the step shown in FIG. 6 (16), a photosensitive resin film 28 having a thickness of 2 to 3 μm is formed by spin coating or the like as shown in FIG. 20 (13). As shown in (14) of FIG. 20, an uneven pattern for obtaining optimum reflection characteristics and viewing angle characteristics is formed in the pixel portion by general-purpose photolithography and etching technology, and is formed by reflow to form an uneven rough surface 28A. The lower part of the reflecting surface is formed. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, in the same manner as in the step shown in FIG. 6 (18), the entire surface is formed as shown in FIG. 20 (14).
A sputtered film of an aluminum alloy or the like having a thickness of 0 to 500 nm is formed, and a reflection film 29 having an uneven shape connected to the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology.

As described above, the single crystal silicon layer 7 is formed by laser irradiation using the step 4 as a seed for low-temperature grapho-epitaxial growth, and the bottom gate type nMOS LDD-
TFT (dual gate type pMOS TFT in the peripheral area)
And an active matrix substrate 30 integrated with a display unit-peripheral drive circuit unit incorporating a CMOS drive circuit comprising an nMOS TFT).

FIG. 21 shows an example in which the gate insulating film of the bottom gate type MOSTFT provided in the display portion is formed by an anodic oxidation method of Mo · Ta.

In this example, after the step shown in FIG. 17B, the molybdenum-tantalum alloy film 71 is subjected to a known anodic oxidation treatment as shown in FIG. _A gate insulating film 74 of ₂ O ₅ is formed to a thickness of 100 to 200 nm.

Thereafter, in the same manner as in the step shown in FIG. 18D, a step 4 is formed as shown in FIG. 21D, and then amorphous silicon or polycrystalline silicon is deposited to form a silicon layer. Form a film. Next, the silicon film is heated and melted by a laser irradiation method, and further cooled (slowly cooled) and solidified, whereby the step 4 is used as a seed for grapho-epitaxial growth to form a single-crystal silicon layer 7. Next, (6) in FIG. 18 to (1) in FIG.
In the same manner as in the step shown in 4), the active matrix substrate 30 is manufactured as shown in FIG.

In the display section, a dual gate type MOS
In order to manufacture a TFT, first, FIG.
The same processing as the step (5) is performed.

Next, as shown in (6) of FIG. 22, a step 4 is formed on the insulating films 72 and 73 and the substrate 1, and furthermore,
Amorphous silicon or polycrystalline silicon is formed on the step 4 to form a silicon film (not shown). Then
The silicon film is heated and melted by laser irradiation treatment, and further cooled (preferably gradually cooled) to be solidified, whereby the single crystal silicon layer 7 is grown by grapho-epitaxial growth using the step 4 as a seed.

Next, in the same manner as in the step shown in FIG.
D, SiO ₂ film (about 100 nm thick) by catalytic CVD, etc.
And SiN (about 200 nm thick) are successively formed in this order, and an insulating film 80 (this corresponds to the gate insulating film 8 described above)
And a sputtered film 81 (which corresponds to the above-described sputtered film 9) made of a Mo.Ta alloy
It is formed to a thickness of about 00 nm.

Next, a photoresist pattern 10 is formed as shown in FIG. 22 (7) in the same manner as in the step shown in FIG. 3 (8), and Mo.multidot.
Top gate electrode 82 of Ta alloy and gate insulating layer 83
Is formed to expose the single crystal silicon layer 7.

Next, in the same manner as in the step shown in FIG. 3 (9), the top gate portion of the nMOS TFT is covered with the photoresist 13 as shown in FIG. The source / drain regions are doped with phosphorus ions 14 (ion implantation) to form N ⁻
The LDD part 15 of the mold layer is formed.

Next, in the same manner as in the step shown in FIG. 4 (10), the gate portion and the LDD portion of the nMOS TFT are covered with the photoresist 16 as shown in FIG. Arsenic ions 17 are doped (ion-implanted) to form a source portion 18 and a drain portion 19 made of an N ⁺ type layer of the nMOS TFT.

Next, in the same manner as in the step shown in FIG. 4 (11), as shown in FIG.
The gate portion of T is covered with a photoresist 20 and the exposed region is doped with boron ions 21 (ion implantation).
Then, the source portion and the drain portion of the P ⁺ layer of the pMOSTFT of the peripheral drive circuit portion are formed.

Next, in the same manner as in the step shown in FIG. 4 (12), a photoresist 24 is provided for islanding the active element section and the passive element section as shown in FIG. The single crystal silicon layer other than the element portion and the passive element portion is selectively removed by general-purpose photolithography and etching techniques.

Next, in the same manner as in the step shown in FIG. 5 (13), as shown in FIG.
D, S by high density plasma CVD, catalytic CVD, etc.
An iO ₂ film 53 (about 200 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface. These films 53 and 54 correspond to the protective film 25 described above. Then, the single crystal silicon layer 7 is activated.

Next, in the same manner as in the step shown in FIG. 5 (14), a contact window is opened in the source section as shown in FIG. 23 (13). And 400 to 50 on the whole surface
A sputtered film made of an aluminum alloy or the like having a thickness of about 0 nm is formed, and the data line and the gate line are formed at the same time as the source electrode 26 is formed by general-purpose photolithography and etching technology.

Next, in the same manner as in the step shown in FIG. 5 (15), as shown in FIG. 24 (14), an insulating film made of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) 36 is formed on the entire surface, and TF for display is further formed.
A contact window is opened in the drain portion of T.

Next, as shown in FIG. 24 (15),
A photosensitive resin film 28 having a thickness of about 2 to 3 μm is formed on the entire surface by spin coating or the like. Subsequently, (17) and (1) in FIG.
In the same manner as in the process shown in 8), as shown in FIG. 24 (16), the lower portion of the reflection surface composed of the roughened surface 28A is formed in the pixel portion, and at the same time, the contact resin window of the drain portion of the display TFT is formed. Opening is performed, and a reflection film 29 made of a concavo-convex shape aluminum alloy or the like for obtaining optimum reflection characteristics and viewing angle characteristics is formed, which is connected to the drain portion 19 of the display TFT.

As described above, a single crystal silicon layer 7 is formed by laser irradiation using the step 4 as a seed for grapho-epitaxial growth, and a dual gate type nMOS LDDTF is formed on the display using the single crystal silicon layer 7.
T is a dual gate type pMOST in the peripheral drive circuit section.
The display-peripheral drive circuit unit integrated type active matrix substrate 30 in which CMOS drive circuits each composed of an FT and an nMOS TFT are manufactured can be manufactured.

<Fourth Embodiment> The fourth embodiment of the present invention will be described with reference to FIGS.

In this embodiment, unlike the above-described embodiment, the gate electrode of the top gate portion is formed of a material having relatively low heat resistance such as an aluminum alloy.

First, the top gate type MOSTF
T is a dual gate MOSTFT in the peripheral drive circuit
Will be described. In this example, first, the steps are performed in the same manner as the steps shown in FIGS. 1 (1) to 2 (5) in the above-described first embodiment, and subsequently, FIG.
As shown in (6), the pMOSTFT of the peripheral drive circuit section
An N-type well 7A is formed in the portion.

Next, as shown in FIG. 25 (7), all of the nMOS and pMOSTFTs in the peripheral drive region and the gate portion of the nMOSTFT in the display region are formed by photoresist 1
3, phosphorus ions 14 are applied to the exposed source / drain regions of the nMOS TFT at, for example, 1 × 10 kV at 10 kV.
^By doping (ion implantation) at a dose of ¹³ atoms / cm ² , an LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned manner.

Next, as shown in FIG. 26 (8), all the pMOS TFTs in the peripheral drive region and n in the peripheral drive region
Gate portion of MOSTFT and nMOSTFT in display area
And the LDD portion are covered with a photoresist 16 and phosphorus or arsenic ions 17
By doping (ion implantation) at 0 kV and a dose of 5 × 10 ¹⁵ atoms / cm ² , the source 18 and the drain 19 and the LDD 15 made of the N ⁺ type layer of the nMOS TFT are formed. In this case, the resist 13 is left as shown by a dashed line in FIG.
Is provided, it is possible to perform the mask alignment at the time of forming the resist 16 using the resist 13 as a guide, thereby facilitating the mask alignment and reducing the misalignment.

Next, as shown in FIG. 26 (9), the nMOSTFT in the peripheral drive region and the nMOSTT in the display region
The entirety of the FT and the gate of the pMOSTFT are covered with a photoresist 20 and boron ions 21
(Ion implantation) at a dose of 5 × 10 ¹⁵ atoms / cm ^{2 at} 10 kV, for example,
The source part 22 and the drain part 23 of the P ⁺ layer are formed.

Next, the resist 20 is removed.
As shown in FIG. 26 (10), the single-crystal silicon layers 7, 7
A is activated in the same manner as described above, and a gate insulating film 12 and a gate electrode material (aluminum or 1%
An aluminum alloy containing Si 11) is formed. The gate electrode material layer 11 can be formed by a vacuum evaporation method or a sputtering method.

[0172] Then, by patterning the respective gate portion in the same manner as described above, then, an island and an active element portion and the passive element portion, further as shown in (11) in FIG. 27, SiO ₂ film on the entire surface (Approximately 200 nm thick) and a phosphosilicate glass (PSG) film (approximately 300 nm thick) are successively formed in this order to form a protective film 25.

Next, as shown in (12) of FIG.
By general-purpose photolithography and etching technology, contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFT.

Then, a 500-600 nm thick sputtered film of aluminum or an aluminum alloy containing 1% Si is formed on the entire surface, and all the TFs of the peripheral drive circuit and the display unit are formed by general-purpose photolithography and etching technology.
T source electrode 26 and drain electrode 2 of peripheral drive circuit section
7 and a data line and a gate line are formed at the same time. Then, forming gas (N ₂ +
Sinter in H ₂ ) at about 400 ° C./1 h.

Next, (15) in FIG. 5 to (18) in FIG.
In the same manner as in the process shown in FIG. 1, a top gate type nMOS LDD-type transistor having a gate electrode of aluminum or an aluminum alloy containing 1% Si is provided for the display portion using the single crystal silicon layer 7 and the peripheral drive circuit portion, respectively.
TFT, dual gate type pMOS TFT and nMO
It is possible to manufacture an active matrix substrate 30 incorporating a display section and a peripheral drive circuit section, in which a CMOS drive circuit constituted by an STFT is built.

In the present embodiment, the gate electrode 11 made of aluminum or an aluminum alloy containing 1% Si is formed after the activation treatment of the single crystal silicon layer 7, so that the influence of heat during the activation treatment is not affected by the gate. Since it is independent of the heat resistance of the electrode material, the heat resistance of the top gate electrode material is relatively low, and low-cost aluminum or an aluminum alloy containing 1% Si can be used. This is because the display unit is a bottom gate type M
The same applies to the case of OSTFT.

Next, a dual gate type MOST is provided in the display section.
Dual gate type MOS TFT for FT and peripheral drive circuit
Will be described. In this example, first, (1) to (1) of FIG. 17 in the third embodiment described above.
8 (5), and then, as shown in FIG. 28 (5), the pMOS of the peripheral drive circuit section.
An N-type well 7A is formed in the TFT section.

Next, in the same manner as in the step shown in FIG. 25 (7), as shown in FIG.
The portion is doped with phosphorus ions 14 to form an LDD portion 15.

[0179] Next, in the same manner as the step shown in (8) in FIG. 26, doped with phosphorus ions 17 to nMOSTFT portion of the display portion and a peripheral driver circuit portion as shown in (7) in FIG. 29, N ⁺ -type A source region 18 and a drain region 19 are formed.

Next, in the same manner as in the step shown in FIG. 26 (9), as shown in FIG. 29 (8), the pMOSTFT part of the peripheral drive circuit section is doped with boron ions 21,
^{A +} type source region 22 and a drain region 23 are respectively formed.

Next, the resist 20 is removed.
As shown in FIG. 29 (9), the single crystal silicon layer 7 is patterned to make the active element portion and the passive element portion into islands. Thereafter, as shown in FIG. 30 (10), the single crystal silicon layers 7, 7A are formed. Is activated in the same manner as described above, and a gate insulating film 80 is formed on the surface, and a gate insulating film 12 is formed on the surface in the peripheral driver circuit portion.

Next, as shown in FIG. 30 (11),
By patterning an aluminum alloy or the like formed on the entire surface by sputtering, each upper gate electrode 83 of the display unit and each upper gate electrode 11 of the peripheral drive circuit unit are formed.

Next, as shown in FIG. 30 (12),
An SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 300 nm thick) are successively formed on the entire surface in this order, and a protective film 25 is formed.

Then, the source electrode 26 of all the TFTs in the peripheral drive circuit portion and the display portion and the drain electrode 27 of the peripheral drive circuit portion are formed in the same manner as described above, so that the single crystal silicon layer 7 is used. Display-peripheral drive incorporating a dual-gate nMOS LDD-TFT, a dual-gate pMOSTFT and an nMOSTFT each having a gate electrode of an aluminum alloy or the like in the display unit and the peripheral drive circuit unit. An active matrix substrate 30 integrated with a circuit portion can be manufactured.

Also in the present embodiment, since the gate electrode 83 made of an aluminum alloy or the like is formed after the activation process of the single crystal silicon layer 7, the influence of heat during the activation process depends on the heat resistance of the gate electrode material. Irrelevant, the heat resistance is relatively low as the material of the top gate electrode, a low-cost aluminum alloy or the like can be used, and the choice of the electrode material is widened. The source electrode 26 (and also the drain electrode) can be formed at the same time in the step (11) of FIG. 30, but this is advantageous in the manufacturing process.

In any of the above-described embodiments, for example, when manufacturing a bottom gate type, a top gate type, or a dual gate type MOSTFT, FIG.
As schematically shown in FIG. 1A, when the step 4 is provided, the single crystal silicon film 7 grown on the step 4 may be thin, resulting in step disconnection (poor connection) or thinning (increase in resistance). In order to ensure connection with the source electrode 26 (or the drain electrode), it is desirable to dispose the electrode on a region including the step 4, as shown in FIGS.

In the step shown in FIG. 25 (7) or the step shown in FIG. 28 (6), a top gate insulating film is formed on the single crystal silicon layer 7, and ion implantation and activation are performed. After the processing is sequentially performed, the top gate electrode, the source, and the drain electrode may be simultaneously formed using an aluminum alloy or the like.

As described above, the step 4 is formed on the substrate 1 (and also on a film of SiN or the like thereon) as shown in FIG.
As shown in (B), the SiN film 51 on the substrate 1 (this has a function of stopping diffusion of ions from the glass substrate 1).
Can also be formed.

<Fifth Embodiment> A fifth embodiment of the present invention will be described with reference to FIGS.

In this embodiment, various examples will be described in which each TFT is formed outside the above-described step 4 (ie, on the substrate 1 other than the step). Note that the single-crystal silicon layer 7 and the gate / source / drain electrodes 26 and 27 are schematically illustrated.

First, FIG. 33 shows a top gate type MOSTF.
T is shown. 33A, a recess due to the step 4 is formed on one side of the source side along the source region, and the gate insulating film 12 and the gate electrode 11 are formed on the single crystal silicon layer 7 on the flat surface of the substrate other than the recess. Is formed. Similarly, in FIG. 33B, the concave portion due to the step 4 is formed in an L-shaped pattern not only in the source region but also up to the end of the drain region along the channel length direction, that is, over two sides. In FIG. 33 (c), the concave portion due to the step 4 is formed in a rectangular shape over four sides so as to surround the TFT active region. In FIG. 33 (d), a concave portion due to the step 4 is formed over three sides. However, adjacent concave portions are not continuous. In FIG. 33 (e), the concave portion due to the step 4 is formed in an L-shaped pattern over two sides. However, adjacent concave portions are not continuous.

As described above, it is possible to form the concave portion due to the step 4 of the various patterns, and since the TFT is provided on the flat surface other than the concave portion, the degree of freedom in manufacturing the TFT increases.
The fabrication itself becomes easier.

Next, FIG. 34 shows a bottom gate type MOSTF.
T is shown. As shown in FIGS. 34 (a) to 34 (c), the steps 4 (or recesses) of various patterns shown in FIG. 33 can be similarly formed in the bottom gate type MOSTFT. That is, FIG. 34A is an example corresponding to FIG. 33A,
Formed on a flat surface other than the recessed portion. Similarly, FIG. 34B corresponds to FIG.
(C) is an example corresponding to FIGS. 33 (c) and (d).

Next, FIG. 35 shows a dual gate type MOS.
3 shows a TFT. As shown in FIG. 35, the steps 4 (or recesses) of various patterns shown in FIG. 33 can be similarly formed in the dual gate type MOSTFT.
For example, a dual-gate MOSTFT can be manufactured on a flat surface in an area inside the step 4 shown in FIGS. 33 (c) and 33 (d).

<Sixth Embodiment> Referring to FIGS. 36 to 38, a sixth embodiment of the present invention will be described.

In this embodiment, the example shown in FIG. 36 is a double gate type TFT in which a plurality of TFTs having a self-aligned LDD structure, for example, a plurality of top gate type LDD-TFTs are connected.
It relates to the OSTFT. That is, in this example, as shown in FIG. 36, the gate electrode 11 is branched into two, one of which is a first LDD-TF as a first gate.
A second LDD-TF for T and the other as a second gate
Used for T (however, an N ⁺ -type region 100 is provided between gate electrodes at the center of the single crystal silicon layer to reduce the resistance). In this case, a different voltage may be applied to each gate, and even if one of the gates becomes inoperable for some reason, carriers are transferred between the source and the drain by using the remaining gates. Can be a reliable device.

Further, the first LDD-TFT and the second LDD-TFT
Since two thin film transistors for driving each pixel are formed by connecting two D-TFTs in series, the voltage applied between the source and the drain of each thin film transistor in the off state can be greatly reduced. it can. Therefore, the leakage current flowing during the off state can be reduced, and the contrast and the image quality of the liquid crystal display can be improved satisfactorily. Further, since the two LDD-TFTs are connected by using only the same semiconductor layer as that of the low-concentration drain region in the LDD-TFT, the connection distance between the transistors can be reduced, and the LDD-TFT can be reduced. Can be prevented from increasing the required area even if two are connected. The first,
The second gates may be completely separate from each other and operate independently.

In the example shown in FIG. 37A, the bottom gate type MOSTFT has a double gate structure.
The example shown in FIG. 37B is a dual gate type MOST.
The FT has a double gate structure.

These double-gate MOSTFTs have the same advantages as the above-described top-gate type.
In particular, the dual gate type has an advantage that even if one of the upper and lower gate portions becomes inoperable, the other gate portion can be used.

FIG. 38 shows the above-mentioned double gate type MOS.
1 shows an equivalent circuit diagram of a TFT. In the above description, the gate is branched into two, but the gate may be branched or divided into three or more. Even in these double-gate or multi-gate structures, it can be configured to have two or more branched gate electrodes of the same potential or divided gate electrodes of different potentials or the same potential in the channel region. .

<Seventh Embodiment> Referring to FIG.
A seventh embodiment of the present invention will be described. In this embodiment mode, one of the upper and lower gate portions is operated as a transistor in the dual gate type TFT of the nMOSTFT, but the other gate portion is operated as follows.

That is, in the example shown in FIG.
In a MOSTFT, an arbitrary negative voltage is always applied to the gate electrode on the top gate side to reduce the leakage current in the back channel. By opening the top gate electrode, it can be used as a bottom gate type. In the example shown in FIG. 39B, an arbitrary negative voltage is always applied to the bottom gate electrode to reduce the leakage current of the back channel. Also in this case, by opening the bottom gate electrode, it can be used as a top gate type. In the case of a pMOSTFT, the back channel leakage current can be reduced by always applying an arbitrary positive voltage to the gate electrode.

In any case, the interface between the single-crystal silicon layer 7 and the insulating film has poor crystallinity and a leak current easily flows, but the leak current can be cut off by applying a negative voltage to the electrode as described above. This is advantageous in combination with the effect of the LDD structure. In addition, a leak current may flow due to light incident from the glass substrate 1 side. However, since the light is blocked by the bottom gate electrode, the leak current can be reduced.

<Eighth Embodiment> Referring to FIGS. 40 to 48, an eighth embodiment of the present invention will be described. As described above, each of the top gate type, bottom gate type, and dual gate type TFTs has a difference in structure or function or a feature. Therefore, these TFTs are used in both the display portion and the peripheral drive circuit portion. When providing, TF is required between these units.
It may be advantageous to provide T in various combinations.

For example, as shown in FIG. 40, when any of a top gate type, a bottom gate type, and a dual gate type MOSTFT is used for the display unit, the top gate type MOSTFT and the bottom gate type MOSTFT are used for the peripheral driving circuit.
It is also possible to employ at least a dual gate type of the TFT and the dual gate type MOS TFT, or to mix them. There are twelve (No. 1 to No. 12) combinations. In particular, when a dual gate structure is used for the MOSTFT of the peripheral driver circuit, such a dual gate structure can be easily changed to a top gate type or a bottom gate type by selecting upper and lower gate portions. When a TFT having a large driving capability is required for a part of the peripheral driving circuit, a dual gate type may be required. For example, it is considered necessary when the present invention is applied to the organic EL or FED of the present invention as an electro-optical device other than the LCD.

FIGS. 41 and 42 show the MOSTFT of the display section.
43 and FIG. 44 show the case where the MOSTFT of the display section has the LDD structure, when FIG.
Reference numeral 6 denotes a TF having an LDD structure in which a MOSTFT in a peripheral drive circuit section has an LDD structure.
47 and FIG. 48, when both the peripheral drive circuit section and the display section include the LDD-structured MOSTFT, the MOSTs of the peripheral drive circuit section and the display section are respectively shown.
It is a figure which shows the various examples (No.1-No.216) which showed the combination of FT according to channel conductivity type.

As described above, the combinations for each gate structure shown in FIG. 40 are specifically as shown in FIGS. In this case, the same combination is possible even when the peripheral drive circuit section is made of a MOS TFT mixed with other gate types of the top gate type. FIG.
The various combinations of the TFTs shown in FIGS.
The present invention is not limited to the case where the channel region or the like is formed of single-crystal silicon, but is similarly applicable to the case where the channel region is formed of polycrystalline silicon or amorphous silicon (however, only the display portion).

<Ninth Embodiment> Referring to FIGS. 49 and 50, a ninth embodiment of the present invention will be described.

In the present embodiment, in the active matrix drive LCD, a TFT using the above-mentioned single crystal silicon layer based on the present invention is provided in the peripheral drive circuit portion thereof in order to improve the drive capability. However, this is not limited to the dual gate type, and other gate types may be mixed, the channel conductivity type may be various, and a MOS using a polycrystalline silicon layer other than the single crystal silicon layer may be used.
A TFT may be included.

On the other hand, although it is desirable to use a single crystal silicon layer for the MOSTFT in the display section,
However, the present invention is not limited thereto, and a polycrystalline silicon or amorphous silicon layer may be used, or a mixture of two of the three types of silicon layers may be used. However, when the display portion is formed of an nMOS TFT, a practical switching speed can be obtained even if the display portion is formed using an amorphous silicon layer, but the TFT area can be reduced in single crystal silicon or polycrystalline silicon, and the pixel area can be reduced. It is more advantageous than amorphous silicon in reducing defects. During the grapho-epitaxial growth described above,
Polycrystalline silicon as well as monocrystalline silicon is produced at the same time, and may include a so-called CGS (Continuous Grain Silicon) structure, which can also be used for forming active elements and passive elements.

FIG. 49 shows examples (A), (B) and (C) of various combinations of MOSTFTs between respective parts, and FIG. 50 shows specific examples. When single crystal silicon is used, the current capability is improved, so that the element can be made smaller, high definition and a large screen can be achieved, and the aperture ratio and the luminance of the display portion can be improved.

In the peripheral drive circuit section, the above-described MOS is used.
It goes without saying that not only the TFT but also an electronic circuit in which a diode, a capacitance, a resistance, an inductance and the like are integrated may be integrally formed on an insulating substrate (a glass substrate or the like).

<Tenth Embodiment> Referring to FIG. 51, a tenth embodiment of the present invention will be described.

In this embodiment, the embodiments described above are applied to passive matrix driving, while the above-described embodiments relate to the example of active matrix driving.

That is, in the present embodiment, the display section does not include the switching element such as the MOSTFT described above, and the incident light of the display section is determined only by the potential difference caused by the voltage applied between the pair of electrodes formed on the opposing substrate. Alternatively, the reflected light is dimmed. Such dimming elements include reflective and transmissive LCDs, ELs (electroluminescent display elements), FEDs (field emission display elements), LEPDs (light emitting polymer display elements), and LEDs (light emitting diode display elements). Also included.

<Eleventh Embodiment> Referring to FIG. 52, an eleventh embodiment of the present invention will be described.

In this embodiment, the present invention is applied to an electro-optical device other than an LCD, such as an organic or inorganic EL (electroluminescence element), FED (field emission display element), or the like.
It is applied to LEPD (light emitting polymer display element), LED (light emitting diode display element) and the like.

FIG. 52A shows an active matrix driven EL element. This EL element is, for example, an organic EL layer (or ZnS: M) using an amorphous organic compound.
An inorganic EL layer using n) 90 is provided on the substrate 1, the transparent electrode (ITO) 41 described above is formed below the substrate 1, and the cathode 91 is formed above the same. Thus, light of a predetermined color can be obtained through the color filter layer 61.

In this EL element, a MOSTFT is formed on the substrate 1 in order to apply a data voltage to the transparent electrode 41 by active matrix driving. This MOSTFT uses a laser beam with the step 4 on the substrate 1 as a seed. A single-crystal silicon MOSTFT (ie, nMOSL) according to the present invention using a single-crystal silicon layer obtained by grapho-epitaxial growth by an irradiation treatment method.
DD-TFT). Further, a similar TFT is provided in a peripheral driving circuit. Since the EL element having such a configuration is driven by a MOSLDD-TFT using a single crystal silicon layer, the switching speed is high and the leakage current is small.

[0220] Note that the filter 61
If the L layer 90 emits a specific color, it can be omitted. In the case of an EL element, since a driving voltage is high, it is advantageous to provide a high-withstand-voltage driver element (such as a high-withstand-voltage cMOSTFT and a bipolar element) in addition to the MOSTFT in the peripheral drive circuit portion.

FIG. 52B shows an FED driven by passive matrix. In this FED, electrons emitted from the cold cathode 94 by the voltage applied between the electrodes 92 and 93 are incident on the opposing phosphor layer 96 by selecting the gate line 95 in a vacuum portion between the opposing glass substrates 1-32. Thus, light emission of a predetermined color is obtained.

Here, the emitter line 92 is led to a peripheral drive circuit and driven by a data voltage. The peripheral drive circuit is provided with a MOSTFT made of a single crystal silicon layer formed according to the present invention. , Emitter line 9
2 which contributes to high-speed driving. The FED can be driven in an active matrix by connecting the MOSTFT to each pixel.

In the device shown in FIG.
If a known light emitting polymer is used instead of the layer 90, a passive matrix or active matrix driven light emitting polymer display device (LEPD) can be formed. In addition, a device similar to the FED using the diamond thin film on the cathode side in the element of FIG. 52B can also be configured. Further, in a light emitting diode, for example, a gallium-based (gallium.
A light-emitting portion made of a film of aluminum, arsenic, etc.) can be driven. Alternatively, it is conceivable to grow the film of the light emitting portion by single crystal by the epitaxial growth method of the present invention.

The embodiments of the present invention described above can be variously modified based on the technical concept of the present invention.

For example, to prevent diffusion of ions from a glass substrate, a SiN film (for example, 50 to 200 nm) is formed on the substrate surface.
m thick) and, if necessary, a SiO ₂ film (for example, 10
(Thickness of 0 nm), or the step 4 described above may be formed in these films. The above-described steps can be formed by an ion milling method or the like in addition to RIE.

Although the present invention is suitable for the TFTs of the peripheral drive circuit section and the display section, the present invention also provides an active area of an element such as a diode and a passive area such as a resistor, a capacitor, and an inductance. It is also possible to form a single-crystal silicon layer by using the method described above.

[0227]

As described above, according to the present invention, a step is used as a seed, and a semiconductor film formed on a substrate including the step is heated and melted by a laser irradiation process, and then cooled and solidified to form a graphograph. A single-crystal semiconductor layer such as a single-crystal silicon layer is formed by epitaxial growth, and this epitaxially-grown layer is used as a dual-gate MOSTF for a peripheral driving circuit of a driving substrate such as an active matrix substrate.
Dual gate type MO for peripheral drive circuit in electro-optical devices such as T and display unit-peripheral drive circuit integrated LCD
The following (A) to (F)
Has the remarkable effect shown in FIG.

(A) A step having a predetermined shape / dimension is formed on a substrate, and the bottom (corner) of the bottom of the step is used as a seed for grapho-epitaxial growth to obtain 540 cm.
^{Since a} single-crystal semiconductor layer such as a single-crystal silicon layer having a high electron mobility of ² / v · sec or more can be obtained, an electro-optical device such as a display thin-film semiconductor device with a built-in high-performance driver can be manufactured.

(B) In particular, since this single crystal silicon layer has higher electron and hole mobilities comparable to those of a single crystal silicon substrate as compared with a conventional amorphous silicon layer or polycrystalline silicon layer, a single crystal silicon layer obtained therefrom is obtained. The dual gate type MOSTFT has a high switching characteristic [preferably, an LD which reduces the electric field strength to reduce the leakage current.
D (Lightly doped drain) structure], a display unit composed of an nMOS, pMOSTFT, or cMOSTFT, and a cMOS, nMOS, or pMOS with high driving capability
A configuration in which a TFT or a peripheral drive circuit portion composed of a mixture of TFTs is integrated becomes possible, and a high-quality, high-definition, narrow frame, high-efficiency, large-screen display panel is realized. In particular,
In polycrystalline silicon, it is difficult to form a pMOSTFT having a high hole mobility as a TFT for an LCD. However, in a single crystal silicon layer according to the present invention, even a hole shows a sufficiently high mobility. Can be manufactured individually or in combination with each other, and this can be manufactured by using nMOS, pMOS, or cMOS.
A panel integrated with the TFT for a display portion having the LDD structure can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) In particular, since a dual gate type MOSTFT is used in the peripheral drive circuit, a cM having a driving capability 1.5 to 2 times higher than that of a single gate type TFT is used.
An OS, an nMOS or a pMOS TFT can be formed, and it becomes a TFT with higher performance and a large driving capability. This is particularly preferable when a TFT having a large driving capability is required in a part of the peripheral driving circuit. For example, not only one of the pair of peripheral vertical driving circuits can be omitted, but also it is considered to be advantageous when the present invention is applied to an organic EL or FED as an electro-optical device other than the LCD. In addition, the dual gate structure can be easily changed to a top gate type or a bottom gate type by selecting the upper and lower gate portions, and if one of the upper and lower gate portions becomes inoperable, one of the upper and lower gate portions becomes inoperable. A gate section can be used.

(D) Since a single crystal semiconductor layer such as a single crystal silicon layer can be formed by using the above-mentioned material layer as a seed for heteroepitaxial growth and subjecting the semiconductor film to laser irradiation treatment on this material layer. In addition, a single-crystal silicon film or the like can be uniformly formed on a substrate at a low temperature. Therefore, a glass substrate having a relatively low strain point, a heat-resistant organic substrate, or the like can be easily obtained, a low-cost substrate having good physical properties can be used, and the substrate can be enlarged.

(E) Since annealing at a medium temperature for a long time (about 600 ° C., about ten and several hours) as in the case of the solid phase growth method is not required, productivity is high, expensive manufacturing equipment is not required, and cost is reduced. Becomes possible.

(F) In this grapho-epitaxial growth, a wide range of P-type or N-type is adjusted by adjusting the irradiation energy and irradiation time of the laser, the shape and size of the step, and the heating temperature and cooling rate of the substrate. Since a single-crystal silicon layer of conductivity type and high mobility can be easily obtained, Vth (threshold) adjustment becomes easy, and high-speed operation by lowering the resistance becomes possible.

(G) A semiconductor (amorphous silicon or polycrystalline silicon) film, or a single crystal semiconductor layer (single crystal silicon layer) obtained by subjecting the film to laser irradiation, contains N-type or P-type carrier impurities. (Boron, phosphorus, antimony, arsenic, bismuth, aluminum, etc.), the impurity species and / or concentration of the single crystal semiconductor layer (single crystal silicon layer)
That is, the conductivity type such as P-type / N-type and / or the carrier concentration can be arbitrarily controlled.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of an LCD (Liquid Crystal Display) according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 3 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 4 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 5 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 6 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 7 is a sectional view of a main part of the LCD.

FIG. 8 is a schematic perspective view for explaining the state of silicon crystal growth on an amorphous substrate.

FIG. 9 is a schematic cross-sectional view showing various step shapes and a silicon growth crystal orientation in the grapho-epitaxial growth technique.

FIG. 10 is a perspective view showing an overall schematic layout of the LCD according to the first embodiment of the present invention.

FIG. 11 is an equivalent circuit diagram of the LCD.

FIG. 12 is a schematic configuration diagram of the same LCD.

FIG. 13 is a cross-sectional view showing a process of manufacturing an LCD according to the second embodiment of the present invention in the order of steps.

FIG. 14 is a sectional view of an essential part of the LCD.

FIG. 15 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 16 is a sectional view of a main part of an LCD according to a third embodiment of the present invention.

FIG. 17 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 18 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 19 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 20 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 21 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 22 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 23 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 24 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 25 is a cross-sectional view showing a manufacturing process of the LCD according to the fourth embodiment of the present invention in the order of steps.

FIG. 26 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 27 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 28 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 29 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 30 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 31 is a fragmentary cross-sectional view of the same at the time of manufacturing the LCD;

FIG. 32 is a fragmentary cross-sectional view of the same at the time of manufacturing the LCD;

FIG. 33 is a plan view or a sectional view showing various TFTs of an LCD according to a fifth embodiment of the present invention.

FIG. 34 is a cross-sectional view showing various TFTs at the time of manufacturing the LCD.

FIG. 35 is a cross-sectional view of a main part of the LCD.

FIG. 36 is a sectional view or a plan view of a main part of an LCD according to a sixth embodiment of the present invention.

FIG. 37 is a cross-sectional view of a principal part of various TFTs of the LCD.

FIG. 38 is an equivalent circuit diagram of a TFT of the LCD.

FIG. 39 shows T of the LCD according to the seventh embodiment of the present invention.
It is principal part sectional drawing of FT.

FIG. 40 is a diagram showing a combination of TFTs of each part of the LCD according to the eighth embodiment of the present invention.

FIG. 41 is a diagram showing a combination of TFTs of each part of the LCD.

FIG. 42 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 43 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 44 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 45 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 46 is a view showing a combination of TFTs of each part of the LCD.

FIG. 47 is a view showing a combination of TFTs of each part of the LCD.

FIG. 48 is a view showing a combination of TFTs in each part of the LCD.

FIG. 49 is a schematic layout diagram of an LCD according to a ninth embodiment of the present invention.

FIG. 50 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 51 is a schematic layout diagram of a device according to a tenth embodiment of the present invention;

FIG. 52 is a sectional view of a main part of an EL and FED according to an eleventh embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 4 ... Step, 7 ... Single crystal silicon layer, 9 ... Sputtered film, 11 ... Gate electrode, 12 ... Gate oxide film, 1
4, 17 ... N-type impurity ions, 15 ... LDD part, 18,
19 ... N ⁺ type source or drain region, 21 ... P type impurity ion, 22, 23 ... P ⁺ source or drain region,
25, 36 ... insulating films, 26, 27, 31, 41 ... electrodes,
29: reflective film, 30: LCD (TFT) substrate

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 29/78 627G F-term (Reference) 2H092 GA48 GA50 GA59 HA15 HA25 HA28 JA25 JA26 JA33 JA35 JA36 JA38 JA39 JA43 JB07 JB52 JB57 JB58 KA03 KA04 KA05 KA10 KA12 KA18 KA19 KB14 KB24 MA04 MA05 MA08 MA10 MA19 MA22 MA24 MA27 MA30 MA32 MA37 MA41 NA19 NA25 NA27 PA01 PA02 PA04 PA06 PA08 PA09 PA12 QA07 QA08 QA10 QA14 QA15 5C058 AA06 AB06 BA35 5C09A A1BA13 BA13 AA06 AA08 AA17 BB01 BB02 BB04 CC02 CC07 CC08 DD01 DD02 DD03 DD07 DD12 DD13 DD14 DD21 EE03 EE04 EE06 EE23 EE28 EE30 EE44 FF02 FF03 FF09 FF10 FF29 FF30 GG02 GG13 GG15 J03 GG17 GG17 GG17 GG25 GG17 NN25 NN27 NN35 NN36 NN46 NN54 NN55 NN71 NN72 NN73 PP03 PP04 PP10 PP27 PP36 PP38 PP40 QQ09 QQ11 QQ12 QQ19

Claims (146)

[Claims] 1. A display device comprising: a display portion on which a pixel electrode is disposed; and a peripheral drive circuit portion disposed around the display portion on a first substrate. An electro-optical device having a predetermined optical material interposed therebetween, wherein a gate portion including a gate electrode and a gate insulating film is formed on one surface of the first substrate, and one of the first substrates A step is formed on the surface of the first substrate including the step and the gate portion;
A film of a semiconductor formed on the step is heated and melted by laser irradiation treatment, and further cooled and solidified, thereby forming a single crystal semiconductor layer formed by grapho-epitaxial growth using the step as a seed. A crystalline semiconductor layer serving as a channel region, a source region, and a drain region, and a dual-gate first thin film transistor having the gate portion above and below the channel region respectively forms at least a part of the peripheral driver circuit portion; An electro-optical device, comprising: 2. The electro-optical device according to claim 1, wherein the film made of the semiconductor is amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 3. The electro-optical device according to claim 2, wherein the step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section. 4. The electric device according to claim 2, wherein the first thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Optical device. 5. The semiconductor device according to claim 1, wherein the single crystal semiconductor layer is N-type or P-type.
3. The electro-optical device according to claim 2, wherein the specific resistance is adjusted by mixing the type of carrier impurity. 6. The electro-optical device according to claim 2, wherein the gate electrode under the single-crystal silicon layer has a trapezoidal shape at a side end thereof. 7. The electro-optical device according to claim 2, wherein a diffusion barrier layer is provided between the first substrate and the single crystal semiconductor layer. 8. The method according to claim 1, wherein the peripheral driving circuit section includes the first driving circuit.
A thin film transistor of a top gate type, a bottom gate type or a dual gate type having a polycrystalline or amorphous silicon layer as a channel region and a gate portion above and / or below the channel region, or the single crystal silicon The electro-optical device according to claim 2, wherein a diode, a resistor, a capacitance, an inductance element, or the like using a layer, a polycrystalline silicon layer, or an amorphous silicon layer is provided. 9. The electro-optical device according to claim 2, wherein in the display unit, a switching element for switching the pixel electrode is provided on the first substrate. 10. A top gate type, a bottom gate type, or a dual gate type, wherein the switching element has a gate portion above and / or below a channel region.
The electro-optical device according to claim 9, wherein the thin film transistor is a thin film transistor. 11. The gate electrode provided below the channel region is made of a heat-resistant material.
0 electro-optical device. 12. The thin film transistor of the peripheral driver circuit section and the display section has an n-channel type, a p-channel type,
The electro-optical device according to claim 10, wherein the electro-optical device forms a complementary insulated gate field effect transistor. 13. The thin film transistor of the peripheral drive circuit section comprises a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. The electro-optical device according to claim 12, wherein: 14. A single type in which at least a part of the thin film transistor of the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure has an LDD portion between a gate and a source or a drain, or The electro-optical device according to claim 10, wherein the electro-optical device is of a double type having an LDD portion between a gate, a source, and a drain. 15. A single crystal, polycrystalline or amorphous silicon layer is formed on the first substrate including the step,
The electro-optical device according to claim 10, wherein the second thin film transistor uses the single crystal, polycrystalline, or amorphous silicon layer as a channel region, a source region, and a drain region, and has a gate portion above and / or below the channel region. apparatus. 16. The electro-optical device according to claim 15, wherein a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step. 17. The electric device according to claim 15, wherein the second thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Optical device. 18. The electric device according to claim 15, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Optical device. 19. The electro-optical device according to claim 15, wherein the gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 20. The electro-optical device according to claim 15, wherein a diffusion barrier layer is provided between the first substrate and the single crystal, polycrystal, or amorphous silicon layer. 21. The thin film transistor of the peripheral driver circuit portion and / or the display portion is configured as a single gate or a multi-gate, and in the case of a multi-gate, two or more branched same potentials in a channel region, or The electro-optical device according to claim 10, further comprising divided gate electrodes having different potentials or the same potential. 22. When the peripheral driver circuit portion and / or the n-channel or p-channel thin film transistor of the display portion is a dual gate type, an upper or lower gate electrode is electrically opened or an arbitrary negative electrode is provided. The electro-optical device according to claim 10, wherein a voltage (in the case of an n-channel type) or a positive voltage (in the case of a p-channel type) is applied to operate as a bottom-gate or top-gate thin film transistor. 23. When the thin film transistor in the peripheral driver circuit portion is the first n-channel, p-channel, or complementary thin film transistor, and the thin film transistor in the display portion has a single crystal silicon layer as a channel region. n-channel type, p-channel type, or complementary type; n-channel type, p-channel type, or complementary type when a polycrystalline silicon layer is used as a channel region; and n-channel type when an amorphous silicon layer is used as a channel region. The electro-optical device according to claim 12, which is of a p-channel type or a complementary type. 24. The electro-optical device according to claim 2, wherein the first substrate is a glass substrate or a heat-resistant resin substrate. 25. The electro-optical device according to claim 2, wherein the first substrate is optically opaque or transparent. 26. The electro-optical device according to claim 2, wherein the pixel electrode is provided for a reflective or transmissive display unit. 27. The electro-optical device according to claim 2, wherein the display section has a laminated structure of the pixel electrode and a color filter layer. 28. When the pixel electrode is a reflective electrode, irregularities are formed on the resin film, and the pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is formed by a transparent flattening film. The electro-optical device according to claim 2, wherein the pixel electrode is planarized, and the pixel electrode is provided on the planarized surface. 29. The electro-optical device according to claim 9, wherein the display section emits light or modulates light when driven by the switching element. 30. The electro-optical device according to claim 9, wherein a plurality of the pixel electrodes are arranged in a matrix on the display section, and the switching element is connected to each of the pixel electrodes. 31. The electro-optical device according to claim 2, configured as a liquid crystal display, an electroluminescence display, a field emission display, a light emitting polymer display, a light emitting diode display, or the like. 32. The electro-optical device according to claim 1, wherein a control unit that controls an operation of the peripheral drive circuit unit and / or the display unit is provided on the first substrate. 33. The electro-optical device according to claim 32, wherein the control unit is a system-on-panel integrally formed with a so-called computer system, which is configured by a CPU, a memory, or a system LSI in which these are mounted. 34. A driving substrate for an electro-optical device, comprising a display portion on which a pixel electrode is disposed, and a peripheral driving circuit portion disposed around the display portion on a substrate, wherein one surface of the substrate is provided. A gate portion including a gate electrode and a gate insulating film is formed thereon; a step is formed on one surface of the substrate; and the step is formed on the substrate including the step and the gate portion. A semiconductor film is heated and melted by laser irradiation treatment and further cooled and solidified to form a single-crystal semiconductor layer formed by grapho-epitaxial growth using the step as a seed. A dual-gate first thin-film transistor having a source region and a drain region, and the gate portion above and below the channel region, respectively; Drive substrate for an electro-optical device characterized in that the data constitutes at least part of the peripheral driving circuit portion. 35. The driving substrate for an electro-optical device according to claim 34, wherein the film made of the semiconductor is amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 36. The driving substrate for an electro-optical device according to claim 35, wherein the step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section. 37. The first thin film transistor is provided inside and / or outside a substrate recess due to the step formed on the substrate and / or a film thereon.
A driving substrate for the electro-optical device according to the above. 38. The driving substrate for an electro-optical device according to claim 35, wherein the specific resistance of the single crystal semiconductor layer is adjusted by mixing N-type or P-type carrier impurities. 39. The gate electrode under the single-crystal silicon layer has a trapezoidal shape at a side end thereof.
A driving substrate for an electro-optical device according to claim 5. 40. The driving substrate for an electro-optical device according to claim 35, wherein a diffusion barrier layer is provided between the substrate and the single crystal semiconductor layer. 41. In the peripheral driver circuit section, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type and a bottom type having a gate portion above and / or below the channel region. The electro-optic according to claim 35, wherein a gate, a dual-gate thin film transistor, or a diode, a resistor, a capacitance, an inductance element, or the like using the single crystal silicon layer, the polycrystal silicon layer, or the amorphous silicon layer is provided. Driving board for equipment. 42. The driving substrate for an electro-optical device according to claim 35, wherein a switching element for switching the pixel electrode is provided on the substrate in the display unit. 43. The switching element of a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region.
43. The driving substrate for an electro-optical device according to claim 42, wherein the driving substrate is a thin film transistor. 44. The gate electrode provided below the channel region is made of a heat-resistant material.
4. A drive substrate for an electro-optical device according to claim 3. 45. The thin film transistor of the peripheral driver circuit section and the display section has an n-channel type, a p-channel type,
44. The driving substrate for an electro-optical device according to claim 43, wherein the driving substrate comprises a complementary insulated gate field effect transistor. 46. The thin film transistor of the peripheral drive circuit section comprises a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. A driving substrate for an electro-optical device according to claim 45. 47. A single type in which at least a part of the thin film transistor of the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure has an LDD portion between a gate and a source or a drain. 44. The driving substrate for an electro-optical device according to claim 43, wherein the driving substrate is a double type having an LDD portion between the gate and the source and the drain. 48. A single crystal on the substrate including the step,
A polycrystalline or amorphous silicon layer is formed, and the second thin film transistor uses the single crystal, polycrystalline or amorphous silicon layer as a channel region, a source region and a drain region, and a gate portion above and / or below the channel region. The drive substrate for an electro-optical device according to claim 43, comprising: 49. The driving substrate for an electro-optical device according to claim 48, wherein a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step. 50. The device according to claim 48, wherein the second thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon.
A driving substrate for the electro-optical device according to the above. 51. The electric device according to claim 48, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Driving substrate for optical devices. 52. The driving substrate for an electro-optical device according to claim 48, wherein the gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 53. The driving substrate for an electro-optical device according to claim 48, wherein a diffusion barrier layer is provided between the substrate and the single crystal, polycrystal, or amorphous silicon layer. 54. The thin film transistor of the peripheral driver circuit portion and / or the display portion is configured as a single gate or a multi-gate, and in the case of a multi-gate, two or more branched same potentials in a channel region, or 44. The driving substrate for an electro-optical device according to claim 43, further comprising divided gate electrodes having different potentials or the same potential. 55. When the n-type or p-channel type thin film transistor of the peripheral driver circuit portion and / or the display portion is a dual gate type, an upper or lower gate electrode is electrically opened or an arbitrary negative electrode is provided. 44. The driving substrate for an electro-optical device according to claim 43, wherein a voltage (for an n-channel type) or a positive voltage (for a p-channel type) is applied to operate as a bottom-gate or top-gate thin film transistor. 56. When the thin film transistor of the peripheral driver circuit portion is the n-channel, p-channel, or complementary first thin film transistor, and the thin film transistor of the display portion uses a single crystal silicon layer as a channel region n-channel type, p-channel type, or complementary type; n-channel type, p-channel type, or complementary type when a polycrystalline silicon layer is used as a channel region; and n-channel type when an amorphous silicon layer is used as a channel region. 46. The driving substrate for an electro-optical device according to claim 45, wherein the driving substrate is a p-channel type or a complementary type. 57. The driving substrate for an electro-optical device according to claim 35, wherein the substrate is a glass substrate or a heat-resistant resin substrate. 58. The driving substrate for an electro-optical device according to claim 35, wherein the substrate is optically opaque or transparent. 59. The driving substrate for an electro-optical device according to claim 35, wherein the pixel electrode is provided for a reflective or transmissive display unit. 60. The driving substrate for an electro-optical device according to claim 35, wherein the display section has a laminated structure of the pixel electrode and a color filter layer. 61. When the pixel electrode is a reflective electrode, irregularities are formed on the resin film, and the pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is formed by a transparent flattening film. 36. The driving substrate for an electro-optical device according to claim 35, wherein the driving substrate is planarized and the pixel electrode is provided on the planarized surface. 62. The driving substrate for an electro-optical device according to claim 42, wherein the display section emits light or modulates light when driven by the switching element. 63. The driving substrate for an electro-optical device according to claim 42, wherein the plurality of pixel electrodes are arranged in a matrix on the display section, and the switching element is connected to each of the pixel electrodes. 64. The driving substrate for an electro-optical device according to claim 35, configured as a liquid crystal display, an electroluminescence display, a field emission display, a light emitting polymer display, a light emitting diode display, or the like. 65. The driving substrate for an electro-optical device according to claim 34, wherein a control unit for controlling an operation of the peripheral driving circuit unit and / or the display unit is provided on the substrate. 66. The electro-optical device according to claim 65, wherein the control unit is a system-on-panel integrally formed with a so-called computer system, which is configured by a CPU, a memory, or a system LSI in which these are mounted. Drive board. 67. A display device having a display portion on which a pixel electrode is provided, and a peripheral drive circuit portion provided around the display portion on a first substrate, wherein the first substrate, the second substrate, A method of manufacturing an electro-optical device having a predetermined optical material interposed therebetween, wherein a step of forming a gate portion comprising a gate electrode and a gate insulating film on one surface of the first substrate; Forming a step on the one surface of the one substrate, forming a semiconductor on the first substrate including the step and the gate portion, and performing a laser irradiation process on the film made of the semiconductor. A step of subjecting the single crystal semiconductor layer to grapho-epitaxial growth by using the step as a seed by heating and melting and further solidifying the film by cooling; a channel region, a source region, and a drain region by performing predetermined processing on the single crystal semiconductor layer; Form Forming a dual-gate first thin film transistor that has the gate portions above and below the channel region, respectively, and forms at least a part of the peripheral driver circuit portion. A method for manufacturing an electro-optical device. 68. The method according to claim 67, wherein the semiconductor film is amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 69. The temperature of the first substrate when the single crystal semiconductor layer is subjected to grapho-epitaxial growth by 200 to
The method for manufacturing an electro-optical device according to claim 68, wherein the temperature is set to 500 ° C. 70. The method of manufacturing an electro-optical device according to claim 68, wherein the step is formed as a concave portion such that a side surface of the bottom surface is perpendicular to the bottom surface or inclined toward a lower end. 71. The method according to claim 68, wherein a diffusion barrier layer is formed on the first substrate, and the single crystal semiconductor layer is formed thereon. 72. The electro-optical device according to claim 68, wherein an impurity type and / or a concentration of the semiconductor film obtained by mixing an N-type or P-type carrier impurity during the film formation of the semiconductor are controlled. Production method. 73. The method according to claim 68, wherein prior to performing said predetermined treatment on said single crystal semiconductor layer, an N-type or P-type carrier impurity is mixed into said single crystal semiconductor layer to adjust its specific resistance. A method for manufacturing an electro-optical device. 74. The electro-optical device according to claim 68, wherein the first thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Production method. 75. The method of manufacturing an electro-optical device according to claim 68, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the first thin film transistor. . 76. The method of manufacturing an electro-optical device according to claim 68, wherein the gate electrode under the single crystal semiconductor layer has a trapezoidal shape at a side end thereof. 77. In the peripheral driver circuit section, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type and a bottom type having a gate portion above and / or below the channel region. 69. The manufacturing of the electro-optical device according to claim 68, wherein a gate, a dual-gate thin film transistor, or a diode, a resistor, a capacitance, an inductance element using the single crystal silicon layer, the polycrystal silicon layer, or the amorphous silicon layer is provided. Method. 78. The method according to claim 68, wherein a switching element for switching the pixel electrode is provided on the first substrate in the display section. 79. The electricity according to claim 78, wherein a second thin film transistor of a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region is formed as the switching element. A method for manufacturing an optical device. 80. The method according to claim 79, wherein the gate electrode provided below the channel region is formed of a heat-resistant material. 81. When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat-resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. 80. The method of manufacturing an electro-optical device according to claim 79, wherein the second thin film transistor is formed through a process common to the first thin film transistor including a step of forming the step after forming the lower gate portion. 82. After the single-crystal semiconductor layer is formed on the lower gate portion, an N-type or P-type carrier impurity is introduced into the single-crystal semiconductor layer to form source and drain regions, and then activated. The method for manufacturing an electro-optical device according to claim 81, wherein the process is performed. 83. After the formation of the single crystal semiconductor layer, the source and drain regions of the first and second thin film transistors are formed by ion implantation of the impurity using a resist as a mask, and the activation is performed after the ion implantation. 83. The method of manufacturing an electro-optical device according to claim 82, wherein after forming the gate insulating film, an upper gate electrode of the first thin film transistor and, if necessary, an upper gate electrode of the second thin film transistor are formed. 84. When the second thin film transistor is of a top gate type, the source and drain regions of the first and second thin film transistors are ion-implanted using a resist as a mask after the formation of the single crystal semiconductor layer. 80. The manufacturing of the electro-optical device according to claim 79, wherein an activation process is performed after the ion implantation, and thereafter, each gate portion including a gate insulating film and a gate electrode of the first and second thin film transistors is formed. Method. 85. In the case where the second thin film transistor is a top-gate type, after forming the single crystal semiconductor layer, a gate insulating film of the first and second thin film transistors and a gate electrode made of a heat-resistant material are formed. Then, using the gate portion and the resist as a mask, the source and drain regions of the first and second thin film transistors are formed by ion implantation of impurity elements, and an activation process is performed after the ion implantation. A method for manufacturing an electro-optical device according to claim 79. 86. The method of manufacturing an electro-optical device according to claim 79, wherein an n-channel type, a p-channel type, or a complementary type insulated gate field effect transistor is configured as the thin film transistor of the peripheral driver circuit portion and the display portion. . 87. The thin film transistor of the peripheral drive circuit portion is formed by a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. 89. The method for manufacturing an electro-optical device according to claim 86, wherein 88. At least a part of the thin film transistor in the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure is a single type having an LDD portion between a gate and a source or a drain, or a single type having an LDD portion. 80. The method of manufacturing an electro-optical device according to claim 79, wherein the device is of a double type having an LDD portion between the source and the drain. 89. The electro-optical device according to claim 88, wherein a resist mask used for forming the LDD structure is left, and ion implantation for forming a source region and a drain region is performed using a resist mask covering the resist mask. Manufacturing method. 90. A single crystal, polycrystal, or amorphous silicon layer is formed on one surface of the first substrate, and the single crystal, polycrystal, or amorphous silicon layer is used as a channel region, a source region, and a drain region. 89. The method of manufacturing an electro-optical device according to claim 86, wherein the second thin film transistor having a gate portion at an upper portion and / or a lower portion thereof is formed. 91. The method of manufacturing an electro-optical device according to claim 90, wherein the step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section. 92. The method of manufacturing an electro-optical device according to claim 91, wherein a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step. 93. The electro-optical device according to claim 91, wherein the second thin film transistor is provided in and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Production method. 94. The electro-optical device according to claim 91, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Manufacturing method. 95. The method of manufacturing an electro-optical device according to claim 91, wherein the gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 96. The method of manufacturing an electro-optical device according to claim 91, wherein a diffusion barrier layer is provided between said first substrate and said single crystal, polycrystal or amorphous silicon layer. 97. The method according to claim 68, wherein the first substrate is a glass substrate or a heat-resistant resin substrate. 98. The method according to claim 68, wherein the first substrate is optically opaque or transparent. 99. The method according to claim 68, wherein the pixel electrode is provided for a reflective or transmissive display unit. 100. The method of manufacturing an electro-optical device according to claim 68, wherein a laminated structure of the pixel electrode and a color filter layer is provided in the display unit. 101. When the pixel electrode is a reflective electrode, an unevenness is formed on a resin film, and a pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is flattened by a transparent flattening film. The method for manufacturing an electro-optical device according to claim 68, wherein the pixel electrode is provided on the flattened surface. 102. The method of manufacturing an electro-optical device according to claim 78, wherein the display unit is configured to emit light or adjust light when driven by the switching element. 103. The method of manufacturing an electro-optical device according to claim 78, wherein the plurality of pixel electrodes are arranged in a matrix on the display section, and the switching element is connected to each of the pixel electrodes. 104. The method for manufacturing an electro-optical device according to claim 68, wherein the method is configured as a liquid crystal display, an electroluminescence display, a field emission display, a light emitting polymer display, a light emitting diode display, or the like. 105. A step of performing a predetermined process on the single crystal semiconductor layer to form an element for constituting a control unit for controlling an operation of the peripheral driver circuit unit and / or the display unit. The manufacturing method of the electro-optical device according to the above. 106. An element for constituting the control unit may be a cMOSTFT, an nMOSTFT, or a pMOSTF.
106. The method of manufacturing an electro-optical device according to claim 105, comprising an active element such as T and a diode, and a passive element such as a resistor, a capacitor, and an inductance. 107. A method of manufacturing a drive substrate for an electro-optical device, comprising: a display portion on which a pixel electrode is disposed; and a peripheral drive circuit portion disposed around the display portion on the substrate. Forming a gate portion comprising a gate electrode and a gate insulating film on one surface; forming a step on the one surface of the substrate; and forming a semiconductor on the substrate including the step and the gate portion. Forming a single crystal semiconductor layer by a laser irradiation treatment on the film made of the semiconductor, heating and melting the film, and further cooling and solidifying the film; Performing a predetermined process on the crystalline semiconductor layer to form a channel region, a source region, and a drain region; and having the gate portions above and below the channel region, respectively. Forming a dual-gate first thin-film transistor that forms at least a part of the peripheral drive circuit unit. 108. The method according to claim 107, wherein the film made of the semiconductor is amorphous silicon or polycrystalline silicon, and the single crystal semiconductor layer is a single crystal silicon layer. 109. The temperature of the substrate when the single crystal semiconductor layer is grown by grapho-epitaxial growth is 200 to 50.
The method for producing a drive substrate for an electro-optical device according to claim 108, wherein the temperature is set to 0 ° C. 110. The method of manufacturing a driving substrate for an electro-optical device according to claim 108, wherein the step is formed as a concave portion such that a side surface of the bottom surface is perpendicular to the bottom surface or inclined toward a lower end. 111. A diffusion barrier layer is formed on the substrate, and the single crystal semiconductor layer is formed thereon.
08. A method for manufacturing a drive substrate for an electro-optical device according to 08. 112. controlling the impurity species and / or concentration of the semiconductor film obtained by mixing an N-type or P-type carrier impurity during the formation of the semiconductor;
A method for manufacturing a drive substrate for an electro-optical device according to claim 108. 113. An N-type or P-type semiconductor layer is formed on the single crystal semiconductor layer before the predetermined treatment is performed on the single crystal semiconductor layer.
Adjust the specific resistance by mixing the carrier impurities of the mold,
A method for manufacturing a drive substrate for an electro-optical device according to claim 108. 114. The driving substrate for an electro-optical device according to claim 108, wherein the first thin film transistor is provided in and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon. Manufacturing method. 115. The driving device for an electro-optical device according to claim 108, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the first thin film transistor. Substrate manufacturing method. 116. The method of manufacturing a driving substrate for an electro-optical device according to claim 108, wherein the gate electrode under the single crystal semiconductor layer has a trapezoidal shape at a side end thereof. 117. In the peripheral driver circuit portion, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type and a bottom portion having a gate portion above and / or below the channel region. A gate type or dual gate type thin film transistor, or a diode using the single crystal silicon layer or the polycrystalline silicon layer or the amorphous silicon layer, a resistor, a capacitance, an inductance element, or the like, is provided. A method for manufacturing a drive substrate. 118. The method of manufacturing a driving substrate for an electro-optical device according to claim 108, wherein a switching element for switching the pixel electrode is provided on the substrate in the display unit. 119. The electricity according to claim 118, wherein a second thin film transistor of a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region is formed as the switching element. A method for manufacturing a drive substrate for an optical device. 120. A gate electrode provided below the channel region is formed of a heat-resistant material.
A method for manufacturing a driving substrate for an electro-optical device according to the above. 121. When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat-resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. 120. The driving substrate for an electro-optical device according to claim 119, wherein, after forming the lower gate portion, the second thin film transistor is formed through steps common to the first thin film transistor including the step of forming the step. Production method. 122. After forming the single-crystal semiconductor layer on the lower gate portion, an N-type or P-type carrier impurity is introduced into the single-crystal semiconductor layer to form source and drain regions, and then activated. 121. Perform processing.
A method for manufacturing a driving substrate for an electro-optical device according to the above. 123. After forming the single crystal semiconductor layer, each source and drain region of the first and second thin film transistors is formed by ion implantation of the impurity using a resist as a mask, and the activation is performed after the ion implantation. 123. The driving substrate for an electro-optical device according to claim 122, wherein after forming the gate insulating film, an upper gate electrode of the first thin film transistor and, if necessary, an upper gate electrode of the second thin film transistor are formed. Production method. 124. In the case where the second thin film transistor is a top gate type, after forming the single crystal semiconductor layer, each source and drain region of the first and second thin film transistors is ion-implanted using a resist as a mask. After this ion implantation, an activation process is performed.
120. The method of manufacturing a driving substrate for an electro-optical device according to claim 119, further comprising forming a gate portion including a gate insulating film and a gate electrode of the first and second thin film transistors. 125. In the case where the second thin film transistor is a top gate type, after forming the single crystal semiconductor layer, a gate insulating film of the first and second thin film transistors and a gate electrode made of a heat-resistant material are formed. A source portion and a drain region of the first and second thin film transistors are formed by ion implantation of an impurity element using the gate portion and the resist as a mask, and an activation process is performed after the ion implantation. 120. A method for manufacturing a drive substrate for an electro-optical device according to claim 119. 126. An electro-optical device drive according to claim 119, wherein an n-channel type, a p-channel type, or a complementary type insulated gate field effect transistor is formed as the thin film transistor of the peripheral driver circuit portion and the display portion. Substrate manufacturing method. 127. The thin film transistor of the peripheral drive circuit section is a set of a complementary type and an n-channel type, and
A pair of channel type, or complementary type, n-channel type and p
89. The method for manufacturing a drive substrate for an electro-optical device according to claim 86, wherein the drive substrate is formed as a set with a channel type. 128. At least a part of the thin film transistor of the peripheral driver circuit portion and / or the display portion has an LDD structure, and the LDD structure is a single type having an LDD portion between a gate and a source or a drain, or a gate type. 120. The method of manufacturing a driving substrate for an electro-optical device according to claim 119, wherein the driving substrate is of a double type having an LDD portion between the source and the drain. 129. The electro-optical device according to claim 128, wherein a resist mask used for forming the LDD structure is left, and ion implantation for forming a source region and a drain region is performed using a resist mask covering the resist mask. Of manufacturing a driving substrate for a semiconductor device. 130. A single crystal, polycrystalline, or amorphous silicon layer is formed on one surface of the substrate, and the single crystal, polycrystalline, or amorphous silicon layer is used as a channel region, a source region, and a drain region. 127. The method of manufacturing a driving substrate for an electro-optical device according to claim 126, wherein the second thin film transistor having a gate portion at a lower portion is formed. 131. The manufacturing of a drive substrate for an electro-optical device according to claim 130, wherein the step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in a cross section. Method. 132. The method for manufacturing a driving substrate for an electro-optical device according to claim 131, wherein a source or drain electrode of said first and / or second thin film transistor is formed on a region including said step. 133. The driving substrate for an electro-optical device according to claim 131, wherein the second thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon. Manufacturing method. 134. The electro-optical device according to claim 131, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Of manufacturing a driving substrate for a semiconductor device. 135. The method for manufacturing a driving substrate for an electro-optical device according to claim 131, wherein the gate electrode under the single crystal, polycrystal, or amorphous silicon layer has a trapezoidal shape at a side end thereof. 136. The method for manufacturing a driving substrate for an electro-optical device according to claim 131, wherein a diffusion barrier layer is provided between said substrate and said single crystal, polycrystalline or amorphous silicon layer. 137. The method of manufacturing a driving substrate for an electro-optical device according to claim 108, wherein said substrate is a glass substrate or a heat-resistant resin substrate. 138. The method according to claim 108, wherein said substrate is optically opaque or transparent. 139. The method for manufacturing a driving substrate for an electro-optical device according to claim 108, wherein said pixel electrode is provided for a reflective or transmissive display portion. 140. The method of manufacturing a driving substrate for an electro-optical device according to claim 108, wherein a laminated structure of the pixel electrode and a color filter layer is provided in the display unit. 141. When the pixel electrode is a reflective electrode, an unevenness is formed on a resin film, and a pixel electrode is provided thereon. When the pixel electrode is a transparent electrode, the surface is flattened by a transparent flattening film. The method for manufacturing a driving substrate for an electro-optical device according to claim 108, wherein the pixel electrode is provided on the flattened surface. 142. The method of manufacturing a driving substrate for an electro-optical device according to claim 118, wherein said display unit is configured to emit light or adjust light when driven by said switching element. 143. The method for manufacturing a driving substrate for an electro-optical device according to claim 118, wherein a plurality of said pixel electrodes are arranged in a matrix on said display section, and said switching element is connected to each of said pixel electrodes. . 144. The method of manufacturing a driving substrate for an electro-optical device according to claim 108, wherein the driving substrate is configured as a liquid crystal display, an electroluminescence display, a field emission display, a light emitting polymer display, a light emitting diode display, or the like. . 145. A step of performing a predetermined process on the single crystal semiconductor layer to form an element for constituting a control unit for controlling an operation of the peripheral driver circuit unit and / or the display unit. A method for manufacturing a driving substrate for an electro-optical device according to the above. 146. An element for constituting the control unit is a cMOSTFT, an nMOSTFT, or a pMOSTF.
146. The method for manufacturing a drive substrate for an electro-optical device according to claim 145, comprising an active element such as T or a diode, or a passive element such as a resistor, a capacitor, or an inductance.