JP2000122087A - Production of electrooptical device and production of driving substrate for electrooptical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a display panel having high image quality, high definition a narrow frame, high efficiency and a large screen, to attain high productivity and easy adjustment of threshold value and to enable high-speed action and the enlargement of the screen due to reduced resistance by depositing a single crystal silicon layer by the hetero-epitaxial growth of silicon in a layer of a low melting point metal with a seed. SOLUTION: A single crystal silicon layer 7 is formed by hetero-epitaxial growth from a layer 6 of a low melting point metal containing molten polycrystal silicon with a crystalline sapphire film 50 formed on a substrate 1 as a seed. The single crystal silicon layer 7 is used as the bottom gate type MOSTFT of an electrooptical device such as display part-peripheral driving circuit integration type LCD. Since the single crystal silicon layer 7 exhibits sufficiently high mobility even to holes, a peripheral driving circuit which attains driving with electrons, holes or a combination of these is manufactured and a panel is obtained by integrating the circuit with TFT for a display part having an LDD structure such as nMOS or pMOS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electro-optical device and a method for manufacturing a driving substrate for an electro-optical device, and more particularly to a bottom gate using a single crystal silicon layer heteroepitaxially grown on an insulating substrate as an active region. Type thin film insulated gate field effect transistor (hereinafter referred to as a bottom gate type MOSTFT. The bottom gate type includes an inverted staggered NSI type and an inverted staggered ISI type) and a liquid crystal display device having a passive region. It relates to a preferred structure and method.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device has a display portion using amorphous silicon for a TFT and an external driving circuit IC, and a display using a polycrystalline silicon for a TFT by a solid phase growth method. Unit and driving circuit integrated (Japanese Patent Laid-Open No. 6-242433), excimer laser-annealed polycrystalline silicon TFT
(Japanese Patent Laid-Open No. 7-13)
No. 1030).

[0003]

However, the above-mentioned conventional amorphous silicon TFT has good productivity, but has a low electron mobility of about 0.5 to 1.0 cm ² / v · sec. MOSTFT (hereinafter pMO
Called STFT. ) Can not be made. Therefore, p
Since the peripheral driver using the MOSTFT cannot be formed on the same glass substrate as the display, the driver IC is externally mounted and mounted by the TAB method or the like, so that cost reduction is difficult. For this reason, there is a limit to high definition. Further, the electron mobility is 0.5 to 1.0 cm ² / v · s
Since it is as low as around ec, sufficient on-current cannot be obtained, and when used in a display portion, the transistor size is inevitably increased, which is disadvantageous for a high aperture ratio of a pixel.

In addition, the above-described conventional polycrystalline silicon TF
Since the electron mobility of T is 70 to 100 cm ² / v · sec, which can cope with high definition, an LCD (liquid crystal display) using a polycrystalline silicon TFT integrated with a driving circuit has recently attracted attention. However, a large LCD of 15 inches or more
, The electron mobility of polycrystalline silicon is 70-100.
Because of cm ² / v · sec, the driving ability is insufficient, and eventually, an external driving circuit IC is required.

In a TFT using polycrystalline silicon formed by a solid phase growth method, annealing is performed at a temperature of 600 ° C. or more for more than 10 hours, and a gate Si is formed by thermal oxidation at about 1000 ° C.
Since the formation of O ₂ is necessary, a semiconductor manufacturing apparatus has to be adopted. For this reason, a wafer size of 8 to 12 inches φ is a limit, and it is inevitable to use expensive quartz glass having high heat resistance, and it is difficult to reduce the cost. Therefore, EV
F and data / AV projector applications.

Further, in the above-described conventional polycrystalline silicon TFT by excimer laser annealing, there are many problems such as stability of excimer laser output, productivity, increase in apparatus price due to increase in size, reduction in yield / quality, and the like. .

[0007] In particular, when a large glass substrate of 1 m square or the like is used, the above-mentioned problems are magnified, and it becomes more difficult to improve performance / quality and reduce costs.

An object of the present invention is to provide an active matrix substrate with a built-in high-performance driver by forming a single-crystal silicon layer having a high electron / hole mobility at a relatively low temperature and uniformly, particularly in a peripheral driving circuit portion. Enables the manufacture of electro-optical devices such as display thin-film semiconductor devices using the same, and has an LDD structure (Ligh
n-channel MOS TFT with tly doped drain structure)
(Hereinafter referred to as nMOSTFT) or pMOSTFT
Alternatively, a display portion of a complementary thin film insulated gate field effect transistor (hereinafter, referred to as a cMOSTFT) having a high driving capability, and the cMOSTFT, the nMOSTFT, or the pMOT
It is possible to integrate the STFT or a peripheral drive circuit composed of a mixture of them, and realize a high-quality, high-definition, narrow-frame, high-efficiency, large-screen display panel. It can be used even for large glass substrates with low cost, high productivity, no expensive manufacturing equipment is required, cost can be reduced, and threshold adjustment is easy and high speed operation due to low resistance And to enable a large screen.

[0009]

That is, the present invention relates to a pixel electrode (for example, a plurality of pixel electrodes arranged in a matrix):
The same applies to the following. A display unit provided with the same) and a peripheral drive circuit unit provided around the display unit are provided on a first substrate (that is, a driving substrate: the same applies hereinafter). 1st substrate and 2nd
An electro-optical device in which a predetermined optical material such as a liquid crystal is interposed between the substrate and the substrate (that is, a counter substrate; the same applies hereinafter), and a method of manufacturing a driving substrate for the electro-optical device. Forming a gate portion comprising a gate electrode and a gate insulating film on one surface of the first substrate; and forming a material layer having good lattice matching with single crystal silicon on the one surface of the first substrate. Forming a polycrystalline or amorphous silicon layer to a predetermined thickness on the first substrate including the material layer and the gate portion.
Forming a low melting point metal layer on or below the polycrystalline or amorphous silicon layer, or forming a low melting point metal layer containing silicon on the first substrate including the material layer Performing a heat treatment, dissolving the polycrystalline or amorphous silicon layer or the silicon in the low melting point metal layer by a heat treatment, and then performing a cooling treatment (preferably a gradual cooling treatment) on the silicon of the polycrystalline or amorphous silicon layer. Or the step of heteroepitaxially growing silicon of the low melting point metal layer using the material layer as a seed, and depositing a single crystal silicon layer,
Performing a predetermined process on the single crystal silicon layer to form a channel region, a source region, and a drain region;
Forming a bottom gate type first thin film transistor (especially, MOSTFT: the same applies hereinafter) having the gate portion below the channel region and forming at least a part of the peripheral driver circuit portion. The present invention relates to a method of manufacturing an electro-optical device and a method of manufacturing a driving substrate thereof, which are characterized. In the present invention, the thin film transistor is a field effect transistor (FET)
(There are a MOS type and a junction type, whichever may be used.) And a bipolar transistor. The present invention can be applied to any of the transistors (the same applies hereinafter).

According to the present invention, the above-mentioned material layer (for example, a crystalline sapphire film) having a good lattice matching with single crystal silicon
A single crystal silicon layer is formed by heteroepitaxial growth from a polycrystalline silicon or amorphous silicon or a low melting point metal layer in which silicon is dissolved, and this epitaxial growth layer is used as a bottom of a peripheral driving circuit of a driving substrate such as an active matrix substrate. Gate type MOSTF
Since it is used for a bottom gate type MOSTFT of a peripheral drive circuit of an electro-optical device such as an LCD integrated with a T or a display unit-peripheral drive circuit, the following remarkable operational effects (A) to (G) are obtained. be able to.

(A) forming a material layer (for example, a crystalline sapphire film) having good lattice matching with single crystal silicon on a substrate;
By heteroepitaxially growing the material layer as a seed, a single-crystal silicon layer having a high electron mobility of 540 cm ² / v · sec or more can be obtained. Manufacturing becomes possible.

(B) In particular, since the single-crystal silicon layer exhibits high electron and hole mobilities comparable to those of a single-crystal silicon substrate as compared with a conventional amorphous silicon layer or polycrystalline silicon layer, Bottom gate type M
The OSTFT has a high switching characteristic [preferably, an LDD (Lig
htly doped drain) structure]
It is possible to integrate a display unit composed of an STFT or cMOSTFT and a peripheral driving circuit unit composed of a cMOS having a high driving capability, or an nMOS, a pMOSTFT, or a mixture of these, thereby achieving high image quality, high definition, a narrow frame, and high efficiency. Thus, a large-screen display panel is realized. In particular, polycrystalline silicon has a high hole mobility pMOST as a TFT for LCD.
Although it is difficult to form an FT, the single crystal silicon layer according to the present invention exhibits sufficiently high mobility even with holes, so that a peripheral drive circuit for driving electrons and holes alone or in combination of both can be manufactured. A panel in which this is integrated with a TFT for a display portion having an LDD structure of nMOS, pMOS or cMOS can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) Then, the above-mentioned material layer is used as a seed for heteroepitaxial growth, and the above-mentioned polycrystalline or amorphous silicon layer is formed on this material layer by plasma or low pressure CVD (chemical vapor deposition: substrate temperature 1).
(400 ° C. to 400 ° C.), and the low melting point metal layer can be formed by a method such as a vacuum evaporation method or a sputtering method. Further, the heat treatment temperature during the silicon epitaxial growth can be 930 ° C. or less. Therefore, a single-crystal silicon layer can be uniformly formed on an insulating substrate at a relatively low temperature (for example, 400 to 450 ° C.).

(D) Since annealing at medium temperature for a long time (about 600 ° C., ten and several hours) and excimer laser annealing as in the case of the solid phase growth method are not required, high productivity and expensive manufacturing equipment are required. Is unnecessary and cost can be reduced.

(E) In this heteroepitaxial growth, the crystallinity of a material layer such as a crystalline sapphire film, the composition ratio between polycrystalline or amorphous silicon and a low melting point metal, the heating temperature of the substrate, the cooling rate, etc. are adjusted to cover a wide range. Since a single-crystal silicon layer having a P-type impurity concentration and high mobility can be easily obtained, Vth (threshold) can be easily adjusted, and high-speed operation can be performed by lowering the resistance.

(F) When forming a polycrystalline or amorphous silicon or silicon-containing low-melting metal layer, an appropriate amount of an impurity element of group 3 or 5 (boron, phosphorus, antimony, arsenic, bismuth, aluminum, etc.) is separately added. By doping, it is possible to arbitrarily control the impurity species and / or the concentration thereof, that is, the conductivity type such as P-type / N-type and / or the carrier concentration of the single crystal silicon layer formed by heteroepitaxial growth.

(G) The material layer such as a crystalline sapphire film serves as a diffusion barrier for various atoms, so that diffusion of impurities from the glass substrate can be suppressed.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, an insulating substrate is used as the first substrate, and the material layer is made of sapphire (Al ₂ O ₃ ), a spinel structure (for example, MgO.Al).
₂ O ₃ ), calcium fluoride (CaF ₂ ), strontium fluoride (SrF ₂ ), barium fluoride (Ba)
F ₂ ), boron phosphide (BP), yttrium oxide ((Y ₂ O ₃ ) _m ) and zirconium oxide ((Zr
It is preferably formed of a substance selected from the group consisting of O ₂ ) _{1 -m} ) and the like.

On such a material layer, the polycrystalline or amorphous silicon layer is formed by a low pressure CVD method, a catalytic CVD method,
Substrate temperature of 100 ~ such as plasma CVD method and sputtering method
For example, several μm to 0.005 μm by a low temperature film forming technique of 400 ° C.
m, and the low-melting-point metal layer is, for example, several tens to several hundreds of the polycrystalline or amorphous silicon layer.
The heat treatment is preferably performed after depositing twice the thickness by a vacuum evaporation method or a sputtering method.

In this case, a polycrystalline or amorphous silicon layer may be formed by the low-temperature film forming technique described above, and the low melting point metal layer may be deposited above or below this. Alternatively, the heat treatment may be performed by depositing the silicon-containing low melting point metal layer.

Further, an insulating substrate such as a glass substrate or a heat-resistant organic substrate is used as the substrate, and the low melting point metal layer is formed of indium, gallium, tin, bismuth, lead, zinc, or the like.
It can be formed of at least one selected from the group consisting of antimony and aluminum.

In this case, when the low melting point metal layer is formed of indium, the heat treatment is performed at 850 to 1100 ° C. in a hydrogen-based (hydrogen, nitrogen-hydrogen mixture, or argon-hydrogen mixture, etc.) atmosphere. (Preferably 900 to 950 ° C.) to form an indium / silicon melt, and when the low melting point metal layer is formed of indium / gallium or gallium, the heat treatment is performed in a hydrogen-based atmosphere at 300 to 1100 ° C. (preferably). 350-60
0 ° C) or 400 to 1100 ° C (preferably 420 to 6)
(00 ° C.) to form an indium gallium silicon melt or a gallium silicon melt.
The substrate can be heated by a method of uniformly heating the entire substrate using an electric furnace, a lamp, or the like, or a method of locally heating only a predetermined location by an optical laser, an electron beam, or the like.

As is clear from the state diagram shown in FIG. 11, the melting point of the low melting point metal containing silicon decreases in accordance with the proportion of the low melting point metal. When using indium, forming an indium melt layer containing silicon (for example, containing 1% by weight) at a substrate temperature of 850 to 1100 ° C. can use a quartz plate glass as a substrate up to about 1000 ° C. Up to 850 ° C., glass having lower heat resistance, for example, crystallized glass can be used. When gallium is used, a gallium melt layer containing silicon (for example, containing 1% by weight) can be formed at a substrate temperature of 400 to 1100 ° C. for the same reason as described above.

In the latter case (in the case of indium gallium silicon or gallium silicon), a glass substrate having a relatively low strain point or a heat-resistant organic substrate can be used as the substrate, so that a large glass substrate (for example, 1 m ² or more) is used. Although a semiconductor crystal layer can be formed thereon, such a substrate is inexpensive, easily thinned, and a long rolled glass plate can be manufactured. Using this, a single-crystal silicon layer formed by heteroepitaxial growth can be continuously or discontinuously formed on a long rolled glass plate or a heat-resistant organic substrate by the above method.

As described above, since the constituent elements are easily diffused from the inside of the glass to the upper layer of the glass having a low strain point, a thin film of the diffusion barrier layer (for example, silicon nitride (SiN)) is used for the purpose of suppressing the diffusion. : 50-200n thickness
m) is preferably formed. Therefore, in this case, the polycrystalline or amorphous silicon layer or the silicon-containing low melting point metal layer is formed on the diffusion barrier layer.

After the single crystal silicon layer is deposited from the low melting point metal in which silicon is melted by heteroepitaxial growth using the above material layer as a seed by slow cooling, the low melting point metal layer is formed on the single crystal silicon layer. Then, a predetermined process is performed on the single crystal silicon layer to produce an active element and a passive element.

As described above, the low melting point metal thin film such as indium deposited on the single crystal silicon layer after the slow cooling is dissolved and removed using hydrochloric acid or the like, but a small amount of indium (10 ¹⁶ atoms / s) is contained in the silicon layer. (approximately cc) so that a P-type single-crystal silicon layer semiconductor is formed immediately after the formation. Therefore, this is nMOSTF
It is convenient for the production of T. However, an N-type single crystal silicon layer can be entirely or selectively formed by ion-implanting an appropriate amount of N-type impurities such as phosphorus atoms over the entire surface or selectively. Therefore, a pMOSTFT can also be formed. . For this reason, a cMOSTFT can also be produced. High solubility when forming polycrystalline or amorphous silicon or silicon-containing low melting point metal layer
Group 5 or group 5 impurity elements (boron, phosphorus, antimony,
Arsenic, bismuth, etc.) can be separately doped in an appropriate amount, so that the impurity species and / or
Alternatively, the concentration thereof, that is, the P-type / N-type and / or carrier concentration can be arbitrarily controlled.

As described above, the single crystal silicon layer heteroepitaxially grown on the substrate is applied to a channel region, a source region and a drain region of a top gate type MOSTFT constituting at least a part of a peripheral driving circuit.
The impurity species in each of these regions and / or the concentration thereof can be controlled.

The peripheral driver circuit section and the thin film transistor of the display section constitute an n-channel, p-channel or complementary insulated gate field-effect transistor, for example, a set of complementary and n-channel transistors and a complementary and p-channel transistor. It may be composed of a set of a channel type or a set of a complementary type, an n-channel type and a p-channel type. Further, it is preferable that at least a part of the thin film transistor of the peripheral drive circuit section and / or the display section has an LDD (Lightly doped drain) structure. Note that the LDD structure may be provided not only between the gate and the drain, but also between the gate and the source, or between the gate and the source and between the gate and the drain (this is called a double LDD).

In particular, the MOSTFT has n
A MOS or pMOS or cMOS LDD type TFT is formed, and a cMOS or nMOS
Alternatively, a pMOS TFT or a mixture of these may be formed.

In the present invention, a step is provided in the substrate and / or the film thereon, and the step is formed so that the side surface is perpendicular to the bottom surface or a bottom angle of preferably 90 ° or less in the cross section. As a concave part that becomes inclined,
It is preferable that the material layer is formed on an insulating substrate or a film of SiN or the like (or both) on the insulating substrate, and the material layer is formed on the substrate including the step, and used as a seed for epitaxial growth of the single crystal silicon layer. . The step is preferably formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the thin film transistor. When a passive element, for example, a resistor is formed of the single-crystal silicon layer, the step is preferably formed along at least one side of an element region where the resistor is formed.

In this case, a step having a predetermined shape as described above serving as a seed for the epitaxial growth is formed at a predetermined position on the insulating substrate as the substrate, and the material layer is formed on the insulating substrate including the step. be able to.

Alternatively, a step having a predetermined shape similar to the above may be formed in the material layer, and the single crystal silicon layer may be formed on the material layer including the step.

In these cases, the step also acts as a seed in addition to the material layer, so that a single crystal silicon layer having higher crystallinity can be formed.

The first thin film transistor such as the MOSTFT may be provided in the substrate concave portion due to the step, but may be provided on the substrate near the concave portion outside the concave portion or both of them. The step may be formed by dry etching such as reactive ion etching.

In this case, the step is formed on one surface of the first substrate, and a monocrystalline, polycrystalline or amorphous silicon layer is formed on the substrate including the step, and the second thin film transistor is formed. Using the single crystal, polycrystalline or amorphous silicon layer as a channel region, a source region and a drain region,
Alternatively, a top gate type, a bottom gate type, or a dual gate type having a gate portion at a lower portion may be used.

Also in this case, the step similar to the above is formed as a concave portion in which the side surface is perpendicular to the bottom surface in the cross section or inclined so as to form a bottom angle of preferably 90 ° or less toward the lower end side. This step is used as a seed during epitaxial growth of the single crystal silicon layer.

The second thin film transistor includes the first thin film transistor.
The source, the drain, and the like are provided inside and / or outside of the substrate concave portion due to the step formed on the substrate and / or the film formed on the substrate and using a single crystal silicon layer formed by grapho-epitaxial growth similarly to the first thin film transistor. Each region of the channel may be formed.

Also in the second thin film transistor, similarly to the above, the impurity species of Group 3 or Group 5 of the single crystal, polycrystalline or amorphous silicon layer and / or the concentration thereof can be controlled, and the level difference can be reduced. The thin film transistor may be formed along at least one side of an element region formed by the channel region, the source region, and the drain region. Further, it is preferable that the gate electrode under the single crystal, polycrystal or amorphous silicon layer has a trapezoidal shape at its side end. A diffusion barrier layer may be provided between the first substrate and the single crystal, polycrystalline or amorphous silicon layer.

It is preferable that a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step.

The first thin film transistor is at least a bottom gate type selected from a top gate type, a bottom gate type or a dual gate type having a gate portion above and / or below a channel region; , The switching element for switching the pixel electrode may be the top gate type, the bottom gate type, or the dual gate type second thin film transistor.

In this case, the gate electrode provided below the channel region is formed of a heat-resistant material, or the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor are formed of a common material. May do it.

In the peripheral drive circuit section, in addition to the first thin film transistor, a top gate type having a polycrystalline or amorphous silicon layer as a channel region and having a gate portion above and / or below the channel region;
A bottom-gate or dual-gate thin film transistor, or a diode, a resistor, a capacitor, an inductance element, or the like using the single-crystal silicon layer, the polycrystalline silicon layer, or the amorphous silicon layer may be provided.

The peripheral driver circuit section and / or the thin film transistor of the display section may be configured as a single gate or a multi-gate.

When the n-type or p-channel type thin film transistor of the peripheral driver circuit portion and / or the display portion is a dual gate type, the upper or lower gate electrode is electrically open or an arbitrary negative voltage (n It is preferable that a thin film transistor be operated as a bottom-gate or top-gate thin film transistor by applying a channel-type or positive voltage (in the case of a p-channel type).

The thin film transistor of the peripheral drive circuit section is an n-channel type, a p-channel type or a complementary type of the first thin film transistor.
When the single-crystal silicon layer is used as a channel region, the thin-film transistor of the display portion is an n-channel type, a p-channel type, or a complementary type. When an amorphous silicon layer is used as a channel region, an n-channel type, a p-channel type, or a complementary type may be used.

In the present invention, after the growth of the single crystal silicon layer, an upper gate portion including a gate insulating film and a gate electrode is formed on the single crystal silicon layer, and the upper gate portion is used as a mask to form the single crystal silicon layer. Group 3 or 5 in layer
The channel region, the source region, and the drain region may be formed by introducing a group III impurity element.

When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. After forming the lower gate portion, the second thin film transistor can be formed through a process common to the first thin film transistor including the step of forming the step. In this case, the upper gate electrode of the second thin film transistor and the gate electrode of the first thin film transistor can be formed of a common material.

After forming the single-crystal silicon layer on the lower gate portion, an impurity element of group 3 or 5 is introduced into the single-crystal silicon layer to form source and drain regions, and then activated. Processing can be performed.

After the formation of the single crystal silicon layer, the source and drain regions of the first and second thin film transistors are formed by ion implantation of the impurity element using a resist as a mask. After forming the gate insulating film, the upper gate electrode of the second thin film transistor may be formed.

When the second thin film transistor is a top gate type, after forming the single crystal silicon layer, each source and drain region of the first and second thin film transistors is formed by ion implantation of the impurity element using a resist as a mask. Then, an activation process is performed after the ion implantation, and thereafter, a gate portion including the gate insulating film and the gate electrode of the second thin film transistor can be formed.

Alternatively, when the second thin film transistor is a top gate type, after forming the single crystal silicon layer, a gate insulating film of the second thin film transistor and a gate electrode made of a heat resistant material are formed to form a gate portion. Forming
The source and drain regions of the first and second thin film transistors may be formed by ion implantation of the impurity element using the gate portion and the resist as a mask, and an activation process may be performed after the ion implantation.

In addition, ion implantation for forming a source region and a drain region can be performed using a resist mask covering the resist mask used in forming the LDD structure.

The substrate may be optically opaque or transparent, and a reflective or transmissive pixel electrode for display may be provided.

When the display section has a laminated structure of the pixel electrode and the color filter layer, the color filter is formed on the display array section to improve the aperture ratio and brightness of the display panel. In addition, the cost can be reduced by omitting the color filter substrate and improving the productivity.

In this case, when the pixel electrode is a reflective electrode, irregularities are formed on the resin film to obtain optimum reflection characteristics and viewing angle characteristics, and the pixel electrode is provided thereon, and the pixel electrode is In the case of a transparent electrode, the surface is preferably flattened by a transparent flattening film, and a pixel electrode is preferably provided on this flattened surface.

The display section is configured to emit light or control light by being driven by the MOSTFT. For example, a liquid crystal display (LCD), an electroluminescence display (E)
L) or field emission display (FED), light emitting polymer display (LEPD), light emitting diode display (LE
D) or the like. In this case, a plurality of the pixel electrodes may be arranged in a matrix on the display unit, and the switching element may be connected to each of the pixel electrodes.

Next, the present invention will be described in more detail with reference to preferred embodiments.

<First Embodiment> FIGS. 1 to 13 show a first embodiment of the present invention.

In the present embodiment, the above-mentioned material layer (for example, a crystalline sapphire film) is formed on the surface including the above-mentioned steps (concave portions) provided on the heat-resistant substrate, and this material layer is used as a seed to form indium. The present invention relates to an active matrix reflective liquid crystal display device (LCD) in which a single-crystal silicon layer is hetero-epitaxially grown from silicon at a high temperature and a bottom gate type MOSTFT is used as a peripheral drive circuit using the single-crystal silicon layer. First, the overall layout of this reflective LCD will be described with reference to FIGS.

As shown in FIG. 12, in this active matrix reflective LCD, a main substrate 1 (which constitutes an active matrix substrate) and a counter substrate 32 are bonded together via a spacer (not shown). It has a flat panel structure, and liquid crystal (not shown here) is sealed between both substrates 1-32. On the surface of the main substrate 1, a display unit including pixel electrodes 29 (or 41) arranged in a matrix, a switching element for driving the pixel electrodes, and a peripheral drive circuit unit connected to the display unit are provided. Is provided.

The switching element of the display unit is formed of an nMOS, pMOS or cMOS and a top gate type MOSTFT having an LDD structure according to the present invention. In the peripheral drive circuit section, cMOS or nMOS or pMOS of the bottom gate type MOSTFT according to the present invention is also used as a circuit element.
MOSTFTs or a mixture thereof are formed. Note that one of the peripheral drive circuit units is a horizontal drive circuit that supplies a data signal to drive the TFT of each pixel for each horizontal line, and the other peripheral drive circuit unit connects the gate of the TFT of each pixel for each scan line. , And are usually provided on both sides of the display unit. These drive circuits can be configured in either a dot-sequential analog system or a line-sequential digital system.

As shown in FIG. 13, the above-mentioned TFT is arranged at the intersection of the gate bus line and the data bus line which are orthogonal to each other, and image information is written into the liquid crystal capacitance (C _LC ) via this TFT, and the next information is written. Holds electric charge until comes. In this case, it is not enough to hold the TFT channel resistance alone. To compensate for this, a storage capacitor (auxiliary capacitor) (C _S ) is added in parallel with the liquid crystal capacitor to compensate for a decrease in the liquid crystal voltage due to leak current. May be. Such TF for LCD
In T, the required performance differs between the characteristics of the TFT used for the pixel portion (display portion) and the characteristics of the TFT used for the peripheral drive circuit. In the TFT of the pixel portion, it is important to control the off current and secure the on current. It becomes a problem. For this reason, the display unit
By providing a TFT having an LDD structure as described below,
As a structure in which an electric field is hardly applied between the gate and the drain, an effective electric field applied to the channel region can be reduced, an off current can be reduced, and a change in characteristics can be reduced. However, the process becomes complicated, the element size becomes large, and problems such as a decrease in on-current occur. Therefore, an optimum design is required for each purpose of use.

Usable liquid crystals include TN liquid crystal (nematic liquid crystal used in the TN mode of active matrix driving), STN (super twisted nematic), GH (guest host), PC (phase change). , FLC (ferroelectric liquid crystal), AFL
Liquid crystals for various modes such as C (antiferroelectric liquid crystal) and PDLC (polymer dispersed liquid crystal) may be employed.

Referring to FIG. 14, an outline of a circuit system of a peripheral driving circuit and a driving method thereof will be described. The driving circuit is divided into a gate side driving circuit and a data side driving circuit.
It is necessary to configure a shift register on both the data side.
Shift registers are generally pMOSTFT and nMOS
Using both TFTs (so-called CMOS circuit)
Some use only one of the MOSTFTs. However, in terms of operating speed, reliability, and low power consumption, cMOST
FT or CMOS circuits are common.

The scanning drive circuit is composed of a shift register and a buffer, and sends a pulse synchronized with the horizontal scanning period from the shift register to each line. On the other hand, there are two driving methods for the data side driving circuit, a dot sequential method and a line sequential method. In the dot sequential method shown in the figure, the circuit configuration is relatively simple, and the display signal is controlled by a shift register through an analog switch. While writing to each pixel directly. Write sequentially to each pixel within one horizontal scanning time (R, G,
B schematically shows a pixel for each color).

Next, an active matrix reflective LCD according to the present embodiment will be described with reference to FIGS. However, in FIGS. 1 to 7, the left side of each figure shows the manufacturing process of the display unit, and the right side shows the manufacturing process of the peripheral drive circuit unit.

First, as shown in FIG. 1A, a sputtered film 71 (500) of a molybdenum / tantalum (Mo.Ta) alloy is formed on one main surface of an insulating substrate 1 such as quartz glass or transparent crystallized glass.厚 600 nm thick).

Next, as shown in FIG. 1B, a photoresist 70 is formed in a predetermined pattern, and using this as a mask, the Mo / Ta film 71 is taper-etched so that the side end 71a has a trapezoidal shape. A gate electrode 71 that is gently inclined at an angle of about 45 degrees is formed.

Next, as shown in FIG. 1C, after removing the photoresist 70, the substrate 1 including the molybdenum-tantalum alloy film 71 is formed on the substrate 1 by a plasma CVD method or the like.
SiN film (about 100 nm thick) 72 and SiO ₂ film (about 20 nm thick)
(Thickness of 0 nm) 73 is formed in this order to form a gate insulating film.

Next, as shown in (4) of FIG. 2, a photoresist 2 is formed in a predetermined pattern at least in a TFT formation region, and using this as a mask, for example, F ⁺ ions 3 of CF ₄ plasma are irradiated, and A plurality of steps 4 are formed in the gate insulating film (and also on the substrate 1) in appropriate shapes and dimensions by general-purpose photolithography such as active ion etching (RIE) and etching (photoetching).

In this case, quartz glass is used as the insulating substrate 1,
High heat-resistant substrates (8 to 1) made of transparent crystallized glass, ceramics, and the like (however, an opaque ceramic substrate or low-transparency crystallized glass cannot be used in a transmission type LCD described later).
2 inch φ, 700 to 800 μm thick) can be used. The step 4 serves as a seed for heteroepitaxial growth of single-crystal silicon, which will be described later, together with the crystalline sapphire film, and has a depth d of 0.1 to 0.4 μm, a width w of 2 to 10 μm, and a length (in the direction perpendicular to the paper surface). ) 10-20 μm
The angle between the base and the side (base angle) is a right angle. Note that a SiN film (for example, 50 to 2) is formed on the surface of the substrate 1 to prevent diffusion of Na ions and the like from the glass substrate.
00 nm thick) and a silicon oxide film (hereinafter referred to as Si
It is called an O ₂ film. ) (For example, about 100 nm thick) may be continuously formed in advance.

Then, as shown in FIG. 2 (5), after removing the photoresist 2, a crystalline sapphire film (thickness 20 μm) is formed on at least the TFT forming region including the step 4 on one main surface of the insulating substrate 1. (~ 200 nm) 50 is formed. This crystalline sapphire film 50 has a high density plasma C
It is prepared by oxidizing trimethylaluminum gas or the like with an oxidizing gas (oxygen / moisture) and crystallizing it by a VD method, a catalytic CVD method (see JP-A-63-40314), or the like. As the insulating substrate 1, a high heat-resistant glass substrate (8 to 12)
Inch φ, 700-800 μm thick) can be used.

Then, as shown in FIG. 2 (6), a polycrystalline silicon film 5 is formed on the entire surface of the crystalline sapphire film 50 including the step 4 by a known catalytic CVD method, plasma CVD method, sputtering method or the like. The substrate is deposited to a thickness of several μm to 0.005 μm (for example, 0.1 μm) at a substrate temperature of about 100 to 400 ° C. Note that an amorphous silicon film may be formed in place of the polycrystalline silicon film 5, but a polycrystalline silicon film will be described below as a representative example.

Then, as shown in FIG. 2 (7), the indium film 6 is formed on the polycrystalline silicon film 5 by the MOCVD method, the sputtering method, or the vacuum evaporation method of trimethylindium, the number of the polycrystalline silicon film 5 It is formed to have a thickness several hundred times (for example, 10 to 15 μm).

Next, the substrate 1 is placed in a hydrogen atmosphere such as hydrogen or a nitrogen-hydrogen mixture or an argon-hydrogen mixture for 10 minutes.
It is kept at a temperature of not more than 00 ° C, especially 900 to 930 ° C for about 5 minutes. As a result, the polycrystalline silicon 5 is dissolved in the indium 6 melt. In this melt, silicon exhibits the property of precipitating at a much lower temperature than the original deposition temperature. The heating of the substrate 1 may be performed by a method of uniformly heating the entire substrate using an electric furnace or the like, or by using an optical laser, an electron beam, or the like.
A method of locally heating only a predetermined location, for example, only a TFT formation region, is also possible.

Then, by gradually cooling, the silicon dissolved in the indium becomes the seed (seed) using the crystalline sapphire film 50 (further, the bottom corner of the step 4) as shown in FIG. As shown, heteroepitaxial growth is performed, and a P-type single crystal silicon layer 7 having a thickness of, for example, about 0.1 μm is deposited.

In the single crystal silicon layer 7 deposited as described above, for example, the (100) plane is heteroepitaxially grown on the substrate in order for the crystalline sapphire film 50 to show good lattice matching with single crystal silicon. In this case, the step 4 also contributes to heteroepitaxial growth in consideration of a known phenomenon called graphoepitaxial growth, and a single crystal silicon layer 7 having higher crystallinity can be obtained. In this regard, as shown in FIG. 9, when a vertical wall such as the above-described step 4 is formed on an amorphous substrate (glass) 1 and an epitaxy layer is formed thereon, a random wall as shown in FIG. 9B, the (100) plane grows along the plane of the step 4 as shown in FIG. The size of the single crystal grain increases in proportion to the temperature and time. However, when the temperature and time are reduced or shortened, the interval between the steps must be shortened. Further, the shape of the step is shown in FIGS.
By changing variously as in (f), the crystal orientation of the growth layer can be controlled. When fabricating MOS transistors, the (100) plane is most often employed. In short, the cross-sectional shape of the step 4 may be such that the angle of the base corner (base angle) is a right angle, or may be inclined inward or outward from the upper end to the lower end. You only need to have it. Usually, the bottom angle of the step 4 is desirably a right angle or 90 ° or less, and the corner of the bottom surface preferably has a slight curvature.

After the single-crystal silicon layer 7 is deposited on the substrate 1 by heteroepitaxial growth, the indium film 6 deposited on the surface side as shown in FIG.
A is dissolved and removed with hydrochloric acid, sulfuric acid, or the like (in this case, post-processing is performed so as not to form a lower silicon oxide film), and a bottom gate type or top gate type MOS TFT using the single crystal silicon layer 7 as a channel region is manufactured. .

First, the single crystal silicon layer 7 formed by the heteroepitaxial growth described above contains P due to indium.
However, since the P-type impurity concentration varies, the p-channel MOSTFT portion is masked with a photoresist (not shown), and P-type impurity ions (for example, B
⁺ ) Is doped at 10 kV with a dose of 2.7 × 10 ¹¹ atoms / cm ² to adjust the specific resistance. Further, as shown in FIG. 3 (10), in order to control the impurity concentration in the pMOSTFT formation region, the nMOSTFT portion is masked with a photoresist 60 and N-type impurity ions (for example, P ⁺ ).
65 is doped at 10 kV at a dose of 1 × 10 ¹¹ atoms / cm ² to form an N-type well 7A.

Next, as shown in (11) of FIG. 4, SiO ₂ (about 200 μm) is formed on the entire surface of the single crystal silicon layer 7 by plasma CVD, high-density plasma CVD, catalytic CVD, or the like.
nm thick) and SiN (approximately 100 nm thick) in this order to form a gate insulating film 8, and further, a molybdenum-tantalum (Mo.Ta) alloy sputtered film 9 (500-6).
(Thickness: 00 nm).

Next, as shown in FIG. 4 (12), the TFT in the display area is formed by a general-purpose photolithography technique.
Photoresist pattern 10 in the step region (in the concave portion)
Is formed, and (Mo.Ta) is obtained by continuous etching.
Alloy gate electrode 11 and gate insulating film (SiN / SiO
₂ ) Step 12 is formed to expose the single crystal silicon layer 7. (Mo.Ta) alloy film 9 is made of an acid-based etching solution, Si
N is plasma-etched with CF ₄ gas, and SiO ₂ is processed with a hydrofluoric acid-based etchant.

Next, as shown in (13) of FIG. 4, all of the nMOS and pMOSTFTs in the peripheral driving region and the gate portion of the nMOSTFT in the display region are formed by a photoresist 13
And cover the exposed source / drain regions of the nMOS TFT with phosphorus ions 14 at 5 × 10 ¹³ at, for example, 20 kV.
By doping (ion implantation) at a dose of atoms / cm ^2, the LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned manner (self-aligned).

Next, as shown in (14) of FIG. 5, all of the pMOS TFTs in the peripheral drive region and n in the peripheral drive region
Gate portion of MOSTFT and nMOSTFT in display area
Is covered with a photoresist 16 and phosphorus or arsenic ions 17 are exposed to the
By doping (ion implantation) at 0 kV and a dose of 5 × 10 ¹⁵ atoms / cm ² , the source 18 and the drain 19 and the LDD 15 made of the N ⁺ type layer of the nMOS TFT are formed.

Next, as shown in FIG. 5 (15), the nMOSTFT in the peripheral driving region and the nMOST in the display region
The entire FT and the gate portion of the pMOSTFT are covered with a photoresist 20, and the exposed region is doped with boron ions 21 at, for example, 10 kV at a dose of 5 × 10 ¹⁵ atoms / cm ² , thereby ion-implanting the P ^{+ of the} pMOSTFT. The source part 22 and the drain part 23 of the layer are formed.
Note that this operation is performed in pM
This is unnecessary work because there is no OSTFT.

Next, as shown in FIG.
A photoresist 24 is provided to make an active element portion such as an FT or a diode or a passive element portion such as a resistor or an inductance into an island, and a single crystal other than the active element portion and the passive element portion in the peripheral driving region and the display region is provided. The silicon layer is removed by general-purpose photolithography and etching techniques. The etching solution is hydrofluoric acid.

Then, as shown in (17) of FIG. 6, an SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 300 nm thick) are formed by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. ) Are continuously formed on the entire surface in this order to form the protective film 25.

Then, in this state, the single crystal silicon layer is activated. In this activation, lamp annealing conditions such as halogen are about 1000 ° C. and about 10 seconds, and a gate electrode material that can withstand this is required.
-Ta alloy is suitable. This gate electrode material therefore
The wiring can be provided not only as a gate portion but also as a wiring over a wide range. Here, expensive excimer laser annealing is not used, but if it is used, the condition is that XeCl (308 nm wavelength) is used for the entire surface, or the selective overlap of 90% or more of only the active element portion and the passive element portion. Scanning is preferred.

Next, as shown in (18) of FIG. 6, contact windows for the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFTs are opened by general-purpose photolithography and etching techniques. .

Then, a sputtered film of aluminum or an aluminum alloy having a thickness of 500 to 600 nm, for example, aluminum containing 1% Si or aluminum or copper containing 1 to 2% copper is formed on the entire surface and is subjected to general-purpose photolithography and etching techniques to form a peripheral film. The data lines and the gate lines are formed simultaneously with the formation of the source electrodes 26 of all the TFTs in the driving circuit and the display section and the drain electrodes 27 of the peripheral driving circuit section. Then, forming gas (N ₂ +
Sinter treatment in H ₂ ) at about 400 ° C./1 h.

Next, as shown in (19) of FIG. 6, an insulating film 36 consisting of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) is formed by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. Is formed on the entire surface.
Next, a contact window is opened in the drain portion of the display TFT. Note that SiO ₂ , PSG and SiN in the pixel portion are used.
The film does not need to be removed.

As a basic requirement of the reflection type liquid crystal display device, the function of reflecting incident light and the function of scattering incident light must be provided inside the liquid crystal panel. This is because the direction of the observer with respect to the display is substantially determined, but the direction of the incident light cannot be uniquely determined.
For this reason, it is necessary to design a reflector assuming that a point light source exists in an arbitrary direction. Therefore, (2) in FIG.
0) As shown in FIG.
The photosensitive resin film 28 having a thickness of m is formed, and as shown in (21) of FIG. Is formed and reflowed to form a lower reflective surface made of the roughened uneven surface 28A.
At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, as shown in FIG. 7 (22), aluminum or 1% Si
An aluminum film or the like other than the pixel portion is removed by a general-purpose photolithography and etching technique to form a sputtered film made of aluminum or the like, and a reflective portion 29 made of uneven aluminum or the like connected to the drain portion 19 of the display TFT is formed.
To form This is used as a pixel electrode for display. Then, about 300 ° C / 1h in forming gas
Sintering to make the contacts sufficient. Note that silver or a silver alloy may be used instead of the aluminum-based material in order to increase the reflectance.

As described above, the single-crystal silicon layer 7 is formed using the crystalline sapphire film 50 including the step 4 as a seed for high-temperature heteroepitaxial growth, and the display section and the peripheral drive circuit section using the single-crystal silicon layer 7 are formed. In addition, a display-peripheral drive circuit unit-integrated active matrix substrate 30 incorporating a CMOS circuit including a top gate type nMOS LDD-TFT, a bottom gate type pMOSTFT, and an nMOSTFT can be manufactured.

Next, using this active matrix substrate (drive substrate) 30, a reflective liquid crystal display (LCD)
A method of manufacturing the semiconductor device will be described with reference to FIG. Hereinafter, this active matrix substrate is referred to as a TFT substrate.

When manufacturing the liquid crystal cell of this LCD by surface assembly (suitable for medium / large liquid crystal panels of 2 inch size or more), first, a TFT substrate 30 and a solid IT
A polyimide alignment film 3 is formed on an element forming surface of a counter substrate 32 provided with an O (Indium tin oxide) electrode 31.
3 and 34 are formed. This polyimide alignment film is formed to a thickness of 50 to 100 nm by roll coating, spin coating, or the like, and cured at 180 ° C. for 2 hours.

Next, rubbing or photo-alignment treatment is performed on the TFT substrate 30 and the counter substrate 32. Rubbing buff materials include cotton and rayon, but cotton is more stable in terms of buff residue (garbage) and retardation.
Photoalignment is a technique for aligning liquid crystal molecules by non-contact linearly polarized ultraviolet irradiation. In addition, the orientation other than rubbing,
A polymer alignment film can be formed by obliquely entering polarized light or non-polarized light (such a polymer compound includes, for example, a polymethyl methacrylate-based polymer having azobenzene).

Next, after cleaning, a common agent is applied to the TFT substrate 30 side, and a sealing agent is applied to the counter substrate 32 side.
Wash with water or IPA (isopropyl alcohol) to remove rubbing buff debris. Common agent is acrylic or epoxy acrylate containing conductive filler,
Alternatively, the sealant may be an acrylic adhesive, an epoxy acrylate, or an epoxy adhesive. Any of heat curing, ultraviolet irradiation curing, ultraviolet irradiation curing and heat curing can be used, but from the viewpoint of overlay accuracy and workability, the ultraviolet irradiation curing and heat curing type is preferable.

Next, a spacer for obtaining a predetermined gap is sprayed on the counter substrate 32 side, and is superposed on the TFT substrate 30 at a predetermined position. After the alignment marks on the counter substrate 32 and the alignment marks on the TFT substrate 30 are accurately aligned, the sealant is temporarily cured by irradiating with ultraviolet light, and then heat-cured collectively.

Next, a scribe break is performed to
A single liquid crystal panel in which the substrate 30 and the counter substrate 32 are overlapped is created.

Next, the liquid crystal 35 is injected into the gap between the two substrates 30-32, and the injection port is sealed with an ultraviolet adhesive, followed by IPA cleaning. Any type of liquid crystal may be used. For example, a high-speed TN (twisted nematic) mode using a nematic liquid crystal is generally used.

Next, the liquid crystal 35 is oriented by heating and quenching.

Next, a flexible wiring is connected to the panel electrode take-out portion of the TFT substrate 30 by thermocompression bonding of an anisotropic conductive film, and a polarizing plate is bonded to the counter substrate 32.

In the case of a single liquid crystal panel surface assembly (suitable for a small liquid crystal panel having a size of 2 inches or less), similarly to the above, the polyimide alignment 33, 34 are formed, and both substrates are subjected to rubbing or non-contact linear polarization ultraviolet light alignment treatment.

Next, the TFT substrate 30 and the opposing substrate 32 are divided into single pieces by dicing or scribe-break, and washed with water or IPA. A common agent is applied to the TFT substrate 30, a sealing agent containing a spacer is applied to the counter substrate 32,
Lay both substrates together. Subsequent processes follow the above.

In the above-mentioned reflection type LCD, the counter substrate 32 is a CF (color filter) substrate, and the color filter layer 46 is provided below the ITO electrode 31.
The incident light from the counter substrate 32 side is efficiently reflected by the reflection film 29 and emitted from the counter substrate 32 side.

On the other hand, as the TFT substrate 30, in addition to the above-described substrate structure as shown in FIG. 7, an on-chip color filter (OCCF) in which a color filter is provided on the TFT substrate 30 is used.
When a TFT substrate having a structure is used, the counter substrate 32 has I
Solid TO electrode (or ITO with black mask)
The electrodes are solid).

[0108] In the case of incorporating an auxiliary capacitance C _S shown in FIG. 12 in the pixel unit, by connecting the dielectric layer provided on the substrate 1 described above (not shown) and the drain region 19 of monocrystalline silicon Good.

As described above, according to the present embodiment, the following remarkable effects can be obtained.

(A) A crystalline sapphire film 50 is formed on a substrate 1 provided with a step 4 having a predetermined shape / dimension, and this is used as a seed to perform high-temperature heteroepitaxial growth (however, the heating temperature during growth is compared with 900 to 930 ° C.). (A low temperature), a single crystal silicon layer 7 having a high electron mobility of 540 cm ² / v · sec or more can be obtained, so that an LCD with a built-in high-performance driver can be manufactured. In this case, step 4
In order to promote this epitaxial growth, a single crystal silicon layer 7 having higher crystallinity can be obtained.

(B) Since the single crystal silicon layer exhibits high electron and hole mobilities comparable to those of a single crystal silicon substrate as compared with a conventional amorphous silicon layer or polycrystalline silicon layer, the single crystal silicon bottom Gate type MOST
FT is an LDD with high switching characteristics and low leakage current
NMOS or pMOS or cMOS TFT having structure
And a high drive capability cMOS, nMOS or pMOS
A configuration in which a MOST or a peripheral driving circuit portion composed of a mixture thereof is integrated becomes possible, and a display panel with high image quality, high definition, a narrow frame, a large screen, and high efficiency is realized. Since this single crystal silicon layer 7 shows a sufficiently high hole mobility,
A peripheral drive circuit for driving electrons and holes alone or in combination of both can be manufactured, and a panel in which this is integrated with an nMOS, pMOS or cMOS LDD display TFT can be realized. In the case of a small to medium-sized panel, there is a possibility that one of a pair of peripheral vertical drive circuits can be omitted.

(C) The polycrystalline silicon (or amorphous silicon) layer 5 is formed by plasma or low pressure CVD (chemical vapor deposition: substrate temperature of 100 to 400 ° C.).
The low melting point metal layer 6 can be formed by a method such as a vacuum evaporation method or a sputtering method.
Since a temperature of 30 ° C. or lower is possible, the single-crystal silicon layer 7 is formed on the insulating substrate at a relatively low temperature (for example, 900 to 930 ° C. or lower).
Can be formed uniformly. In addition, as a substrate,
Quartz glass, crystallized glass, a ceramic substrate, or the like can be used.

(D) Since long-time annealing at an intermediate temperature and excimer laser annealing as in the case of the solid phase growth method are not required, productivity is high, costly manufacturing equipment is not required, and cost can be reduced. .

(E) In this high-temperature heteroepitaxial growth, the crystallinity of the crystalline sapphire film and the like, the indium-silicon composition ratio, the shape of the step, the substrate heating temperature, the cooling rate,
By adjusting the N-type or P-type carrier impurity concentration to be added, a wide range of P-type impurity concentration and high mobility single crystal silicon layer can be easily obtained, so that Vth (threshold) adjustment is easy and low. High-speed operation by resistance is possible.

(F) If a color filter is formed on the display array unit, cost reduction can be realized by improving the aperture ratio and luminance of the display panel, omitting a color filter substrate, improving productivity, and the like.

(G) Since the above-mentioned material layer such as a crystalline sapphire film serves as a diffusion barrier for various atoms, diffusion of impurities from the glass substrate can be suppressed.

<Second Embodiment> FIG. 15 shows a second embodiment of the present invention.

The present embodiment relates to an active matrix reflective LCD similar to the above-described first embodiment, but is different from the first embodiment in FIG.
After the step (5), as shown in FIG. 15 (6), first, for example, an indium film 6 is formed on the entire surface of the crystalline sapphire film 50 including the step 4 by, for example, 10 to 20 μm by sputtering or vacuum evaporation. Formed to a thickness of

Next, as shown in FIG. 15 (7), an amorphous silicon film 5 is deposited on the indium film 6 to a thickness of several μm to 0.005 μm (for example, 0.1 μm) by a known plasma CVD method. .

In this case, the temperature at which the silicon film is formed should not significantly exceed the melting point of the low melting point metal 6 (indium: 156 ° C., gallium: 29.77 ° C.). Crystalline silicon film formation (600-65
0 ° C.) is difficult. Therefore, by plasma CVD,
An amorphous silicon film 5 is formed on the indium film 6.

Next, the substrate 1 was placed in a hydrogen-based atmosphere for 100 hours.
Hold at 0 ° C. or lower (particularly 900 to 930 ° C.) for about 5 minutes. Thereby, the amorphous silicon film 5 is dissolved in the indium melt.

Then, by gradually cooling, the silicon dissolved in the indium melt was used as the seed (seed) using the crystalline sapphire film 50 (and the step 4) as a seed.
As shown in (8), heteroepitaxial growth is performed, and a single-crystal silicon layer 7 having a thickness of, for example, about 0.1 μm is deposited.

In this case, the single crystal silicon layer 7 has the (100) plane epitaxially grown on the substrate in the same manner as described above, but the shape of the step is changed as shown in FIGS. 9 (a) to 9 (f).
The crystal orientation of the growth layer can be controlled by various changes as described above.

After the single-crystal silicon layer 7 is deposited on the substrate 1 by heteroepitaxial growth, indium on the surface side is dissolved and removed with hydrochloric acid or the like as in the first embodiment, and the single-crystal silicon layer is further removed. Through a step of performing a predetermined process on the silicon layer 7, each TFT of the display section and the peripheral drive circuit section is manufactured.

In the present embodiment, the low melting point metal layer 6 is formed on the step 4, the amorphous silicon layer 5 is formed thereon, and then heated and melted and cooled. The heteroepitaxial growth of single crystal silicon from silicon occurs in the same manner as in the above-described embodiment.

<Third Embodiment> FIG. 16 shows a third embodiment of the present invention.

The present embodiment relates to an active matrix reflective LCD similar to the above-described first embodiment, but is different from the above-described first embodiment in that FIG. After the step, as shown in FIG. 16 (6), for example, an indium film 6A containing a predetermined amount (for example, about 1% by weight) of silicon is sputtered on the entire surface of the crystalline sapphire film 50 including the step 4. For example, 10
It is formed to a thickness of ２０20 μm.

Next, the substrate 1 was placed in a hydrogen-based atmosphere for 100 hours.
Hold at 0 ° C. or lower (particularly 900 to 930 ° C.) for about 5 minutes. Thereby, the silicon is dissolved in the indium melt.

Next, by gradually cooling, the silicon dissolved in the indium melt is used as the seed (seed) using the crystalline sapphire film 50 (and the step 4) as a seed.
As shown in (7), heteroepitaxial growth is performed, and a single-crystal silicon layer 7 having a thickness of, for example, about 0.1 μm is deposited.

In this case, the (100) plane of the single-crystal silicon layer 7 is heteroepitaxially grown on the substrate in the same manner as described above.
By changing variously as in (f), the crystal orientation of the growth layer can be controlled.

After the single-crystal silicon layer 7 is deposited on the substrate 1 by heteroepitaxial growth, indium on the surface side is dissolved and removed with hydrochloric acid or the like as in the first embodiment, and the single-crystal silicon layer is further removed. Through a step of performing a predetermined process on the silicon layer 7, each TFT of the display section and the peripheral drive circuit section is manufactured.

In this embodiment, after the low-melting-point metal layer 6A containing silicon is formed on the step 4, heat melting and cooling are performed. Epitaxial growth occurs in the same manner as in the above-described embodiment.

<Fourth Embodiment> Referring to FIGS. 17 to 19, a fourth embodiment of the present invention will be described.

In this embodiment, as compared with the above-described first embodiment, a similar top gate type MOSTFT is provided in a display portion and a bottom gate type MOSTFT is provided in a peripheral drive circuit portion. Unlike the embodiment, the present invention relates to a transmission type LCD. That is, the steps from (1) in FIG. 1 to the step shown in (19) in FIG. 6 are the same, but after that step, as shown in (20) in FIG.
6 Open window for drain contact of display TFT 1
At the same time as Step 9, unnecessary portions of the SiO ₂ , PSG and SiN films in the pixel openings are removed to improve the transmittance.

Next, as shown in (21) of FIG.
A photosensitive acrylic transparent resin flattening film 28B having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like, and a window is opened in the transparent resin 28B on the drain side of the display TFT by general-purpose photolithography. Let it cure.

Next, as shown in FIG. 17 (22),
An ITO sputtered film having a thickness of 130 to 150 nm is formed on the entire surface, and is contacted with the drain portion 19 of the display TFT by general-purpose photolithography and etching technology.
The TO transparent electrode 41 is formed. Then, by heat treatment (200 to 250 ° C./1 h in a forming gas), the contact resistance between the drain of the display TFT and the ITO is reduced and the transparency of the ITO is improved.

Then, as shown in FIG.
2, and a transmissive LCD is assembled in the same manner as in the first embodiment. However, a polarizing plate is also attached to the TFT substrate side. In this transmissive LCD, transmitted light can be obtained as shown by the solid line, but the opposing substrate 3 can be obtained as shown by the dashed line.
It is also possible to obtain transmitted light from two sides.

In the case of this transmission type LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.

[0139] That is, steps up in FIG. 1 (1) of the to 6 (18) is carried out according to the above process, but then, as shown in (19) in FIG. 19, insulating the PSG / SiO ₂ Membrane 25
The drain portion is also opened as a window to form an aluminum buried layer 41A for a drain electrode, and then an insulating film 36 of SiN / PSG is formed.

Next, as shown in (20) of FIG.
After forming a photoresist 61 having a predetermined thickness (1 to 1.5 μm) in which each color of R, G, and B is dispersed in a pigment for each segment, as shown in (21) of FIG. Each of the color filter layers 61 (R), 61 (G), is patterned by leaving only predetermined positions (each pixel portion).
61 (B) is formed (on-chip color filter structure). At this time, the window of the drain part is also opened. In addition, an opaque ceramic substrate, glass with low transmittance, and a heat-resistant resin substrate cannot be used.

Next, as shown in (21) of FIG.
In a contact hole communicating with the drain of the display TFT, a light shielding layer 43 serving as a black mask layer is formed by metal patterning over the color filter layer. For example, molybdenum is sputtered by 200 to 250 n.
An m-thick film is formed and patterned into a predetermined shape that covers the display TFT and shields light (on-chip black structure).

Next, as shown in (22) of FIG.
A flattening film 28B made of a transparent resin is formed, and an ITO transparent electrode 41 is further formed in a through hole provided in the flattening film by a light shielding layer 4.
3 is formed.

As described above, by forming the color filter 61 and the black mask 43 on the display array section, the aperture ratio of the liquid crystal display panel can be improved, and the power consumption of the display module including the backlight can be reduced. Realize.

<Fifth Embodiment> A fifth embodiment of the present invention will be described.

In the present embodiment, the above-mentioned steps (concave portions) 4 and the crystalline sapphire film 50 are formed on a glass substrate having a low strain point, and these are used as seeds for indium / gallium / silicon or gallium / silicon melts. The present invention relates to an active matrix reflection type liquid crystal display (LCD) in which a crystalline silicon layer is heteroepitaxially grown at a low temperature and a bottom gate type MOSTFT is formed using the epitaxial layer.

That is, in the present embodiment, as compared with the above-described first embodiment, in the step shown in FIG.
For example, a glass substrate such as borosilicate glass or aluminosilicate glass having a strain point or a maximum use temperature as low as about 600 ° C. is used. This is inexpensive and easy to increase in size, and to increase the thickness of a thin plate (for example, 500 × 60).
If it is 0 × 0.1 to 1.1 mm thick), it can be rolled / lengthened. Of course, a quartz substrate or a crystallized glass substrate can also be employed.

After the step 4, the crystalline sapphire film 50, and the polycrystalline silicon layer 5 are formed in the same manner as described above, indium is formed on the polycrystalline silicon film 5 in the step shown in FIG.・ The gallium film (or gallium film) is made of MO of trimethylindium gallium or trimethylgallium.
The thickness (for example, 10 to 2 times) of the polycrystalline silicon film 5 by several tens to several hundreds times by the CVD method, the sputtering method, or the vacuum evaporation method.
0 μm).

Next, the substrate 1 was placed in a hydrogen-based atmosphere for 300 hours.
Hold at ~ 600C (or 420-600C) for about 5 minutes. As a result, the polycrystalline silicon 5 (or amorphous silicon) is dissolved in the melt of indium gallium or the melt of gallium. In this melt, silicon exhibits the property of precipitating at a much lower temperature than the original deposition temperature.

Then, by gradually cooling, the silicon dissolved in the indium gallium (or gallium) is used as a seed at the bottom corner of the step 4 as shown in FIG. Heteroepitaxial growth
It is deposited as a single-crystal silicon layer 7 having a thickness of, for example, about 0.1 μm.

In this case, the single crystal silicon layer 7 has the (100) plane epitaxially grown on the substrate in the same manner as described above.
By changing variously as in (f), the crystal orientation of the growth layer can be controlled.

After the single-crystal silicon layer 7 is deposited on the substrate 1 by low-temperature heteroepitaxial growth in this manner, the indium-gallium (or gallium) on the surface side is removed with hydrochloric acid, sulfuric acid or the like as shown in FIG. Dissolve and remove.

After that, using the single crystal silicon layer 7, the top gate type and bottom gate type MOSTs are formed in the display section and the peripheral drive circuit section in the same manner as in the first embodiment.
FT is manufactured. The structure shown in FIG. 8 may be similarly applied to the present embodiment.

According to the present embodiment, the following remarkable functions and effects can be obtained in addition to the functions and effects described in the first embodiment.

(A) On the glass substrate 1, about 300 to 60
The single crystal silicon layer 7 can be formed uniformly by heteroepitaxial growth at a lower temperature of 0 ° C. or 420 to 600 ° C.

(B) Therefore, since a single-crystal silicon layer can be formed not only on a glass substrate but also on an insulating substrate such as an organic substrate, a substrate material having a low strain point, low cost and good physical properties can be arbitrarily selected. In addition, the size of the substrate can be increased. Glass substrates and organic substrates can be manufactured at a lower cost than quartz substrates and ceramic substrates, and can be made thinner / longer / rolled. It is possible to manufacture a large-sized glass substrate or the like having a length / roll, with good productivity and at low cost. When a glass having a low glass strain point (or a maximum operating temperature) (for example, 500 ° C.) is used as the glass substrate, if the constituent elements diffuse from the inside of the glass to the upper layer and affect the transistor characteristics, this is used. For the purpose of suppressing, a barrier layer thin film (for example, silicon nitride: thickness 50 to 200)
nm). However, this can be omitted due to the diffusion preventing action of the sapphire film 50.

(C) In this low-temperature heteroepitaxial growth, a single-crystal silicon layer having a wide range of P-type impurity concentration and high mobility can be easily formed by adjusting the indium / gallium composition ratio of the indium / gallium film, the heating temperature, the cooling rate, and the like. Therefore, Vth adjustment is easy and high-speed operation can be performed by lowering the resistance.

<Sixth Embodiment> A sixth embodiment of the present invention will be described.

This embodiment relates to a transmissive LCD as compared with the above-described fifth embodiment, and its manufacturing process is similar to that of the above-described fourth embodiment, except that an indium gallium film is formed. A single crystal silicon layer can be formed by the used low-temperature heteroepitaxial growth.

Using this single crystal silicon layer, as described in the above-described fourth embodiment, FIGS.
The transmission type LCD can be manufactured by the process shown in FIG. However, an opaque ceramic substrate or an opaque or low transmittance organic substrate is not suitable.

Therefore, in the present embodiment, the fifth
It is possible to have both excellent functions and effects of the fourth embodiment and the fourth embodiment. That is, in addition to the functions and effects of the above-described first embodiment, it is possible to use a low-cost substrate 1 that can be made thin and long, such as an organic substrate such as borosilicate glass or heat-resistant polyimide. The composition ratio of gallium / gallium makes it easy to adjust the conductivity type and Vth of the single crystal silicon layer 7, and the color filter 42 and the black mask 43 are formed on the display array to improve the aperture ratio of the liquid crystal display panel. Another object is to realize low power consumption of a display module including a backlight.

<Seventh Embodiment> FIGS. 20 to 28 show
14 shows a seventh embodiment of the present invention.

In this embodiment, the peripheral drive circuit section has a bottom gate type pMO similar to that of the above-described first embodiment.
It is composed of a CMOS drive circuit composed of an STFT and an nMOSTFT. The display section is of a reflection type, but has various combinations of TFTs having various gate structures.

That is, FIG. 20A shows a top gate type nMOS LDD-T similar to that of the above-described first embodiment.
Although the FT is provided in the display portion, the display portion shown in FIG. 20B has a bottom-gate type nMOS LDD-TFT, and FIG.
The display part shown in FIG. 0 (C) has a dual gate type nMOS.
LDD-TFTs are provided. Both of these bottom gate type and dual gate type MOS TFTs
As will be described later, the bottom gate type MOS of the peripheral drive circuit section
Although it can be manufactured in the same process as the TFT, especially in the case of the dual gate type, the driving capability is improved by the upper and lower gate portions, suitable for high-speed switching, and by selectively using either the upper or lower gate portion. Depending on the case, it can be operated as a top gate type or a bottom gate type.

The bottom gate type MO shown in FIG.
In the STFT, reference numeral 71 in the drawing denotes a gate electrode of Mo / Ta, etc., reference numeral 72 denotes a SiN film, and reference numeral 73 denotes a SiO ₂ film, which forms a gate insulating film. A channel region using a single crystal silicon layer similar to that of the bottom gate type MOSTFT is formed. Also, the dual gate type MOST shown in FIG.
In the FT, the lower gate portion is a bottom gate type MOST
FT is the same as FT, but the upper gate is
2 is formed of a SiO ₂ film and a SiN film, on which an upper gate electrode 83 is provided. However, in each case, each gate portion is formed outside the step 4 which acts as a seed during heteroepitaxial growth and at the same time promotes the growth of the single crystal silicon layer and has the effect of increasing the crystallinity.

Next, the above bottom gate type MOSTFT
21 to 25, and a method of manufacturing the above-mentioned dual gate type MOSTFT will be described with reference to FIGS. 26 to 28, respectively. In addition, the bottom gate type MO of the peripheral drive circuit section
The method of manufacturing the STFT is the same as that described with reference to FIGS.

In the display section, a bottom gate type MOST
In order to manufacture the FT, first, as shown in FIG. 21A, a sputtered film 71 of a molybdenum / tantalum (Mo.Ta) alloy is formed on the substrate 1 in the same step as FIG.
(500-600 nm thick).

Then, as shown in FIG. 21 (2), in the same step as FIG. 1 (2), a photoresist 70 is formed in a predetermined pattern, and using this as a mask, Mo.Ta is used.
The film 9 is taper-etched so that the side end 71a has
A gate electrode 71 that is gently inclined at 0 to 45 degrees is formed.

Next, as shown in (3) of FIG. 21, in the same step as (3) of FIG. 1, after removing the photoresist 70, the substrate 1 including the molybdenum-tantalum alloy film 71 is formed on the substrate 1 by a plasma CVD method. The SiN film (about 10
A gate insulating film is formed by laminating a 0 nm thick film 72 and a SiO ₂ film (about 200 nm thick) 73 in this order.

Next, as shown in (4) of FIG. 21, in the same step as (4) of FIG. 2, a photoresist 2 is formed in a predetermined pattern at least in a TFT formation region, and this is used as a mask. Similarly, a plurality of steps 4 are formed in the gate insulating film on the substrate 1 (and also on the substrate 1) in appropriate shapes and dimensions. The step 4 serves as a seed in the later-described hetero-epitaxial growth of single crystal silicon together with the crystalline sapphire film, and has a depth d = 0.3.
０．４0.4 μm, width w = 2-3 μm, length (perpendicular to the paper surface) = 10-20 μm, and the angle between the base and the side (base angle) is a right angle.

Then, as shown in FIG. 21 (5), after removing the photoresist 2, in the same step as in FIG. 2 (5), a step 4 is formed on one main surface of the insulating substrate 1 as described above. A crystalline sapphire film (thickness: 20 to 200 nm) 50 is formed in at least the TFT formation region including

Then, as shown in FIG. 22 (6), a polycrystalline silicon film 5 is formed in the same step as in FIG. 2 (6).

Next, as shown in FIG. 22 (7), an indium (or indium-gallium or gallium) film 6 is deposited in the same step as in FIG. 2 (7).

Next, as shown in FIG. 22 (8), in the same step as FIG. 3 (8), single crystal silicon is heteroepitaxially grown to form a single crystal silicon layer 7 having a thickness of, for example, about 0.1 μm. Let it. At this time, the side end 71a of the underlying gate electrode 71 has a gentle slope, so that epitaxial growth due to the step 4 is not hindered and the single-crystal silicon layer 7
Will grow.

Next, as shown in FIG. 22 (9), the film 6A of indium or the like is removed, and further, as shown in FIG. 3 (10) to FIG.
After the step (12), as shown in (10) of FIG. 22, in the same step as (13) of FIG.
The gate portion of the MOSTFT is covered with a photoresist 13, and the exposed source / drain regions of the nMOSTFT are doped (ion-implanted) with phosphorus ions 14 to form N ^−.
An LDD portion 15 made of a mold layer is formed in a self-aligned manner. At this time, the surface height difference (or pattern) can be easily recognized by the presence of the bottom gate electrode 71, and the photoresist 13
(Mask alignment) is easy to perform, and alignment deviation hardly occurs.

Next, as shown in (11) of FIG.
In the same step as (14) in FIG. 5, the gate portion and the LDD portion of the nMOS TFT are covered with a photoresist 16 and the exposed region is doped (ion-implanted) with phosphorus or arsenic ion 17 to form an N ⁺ type layer of the nMOS TFT. The source part 18 and the drain part 19 are formed.

Next, as shown in (12) of FIG.
In the same step as (15) in FIG. 5, the entire nMOS TFT is covered with the photoresist 20 and the boron ions 2
Doping (ion implantation) into the peripheral drive circuit
A source portion and a drain portion of the P ⁺ layer of the MOSTFT are formed.

Next, as shown in (13) of FIG.
In the same step as (16) in FIG. 5, a photoresist 24 is provided to make the active element part and the passive element part islands, and the single crystal silicon layer is selectively removed by general-purpose photolithography and etching techniques.

Next, as shown in (14) of FIG.
In the same step as (17) in FIG.
SiO by high-density plasma CVD, catalytic CVD, etc.
_{A second} film 53 (about 300 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface in this order. The SiO ₂ film 53 and the PSG film 54 correspond to the above-described protective film 25. Then, in this state, the single crystal silicon layer is activated in the same manner as described above.

Next, as shown in FIG. 24 (15),
In the same step as (18) in FIG. 6, a contact window is opened in the source portion by general-purpose photolithography and etching technology. And 400 to 500 nm on the entire surface
A thick aluminum sputtered film is formed, and a data line and a gate line are formed simultaneously with the source electrode 26 of the TFT by general-purpose photolithography and etching techniques. Thereafter, sintering is performed in a forming gas at about 400 ° C. for 1 hour.

Next, as shown in (16) of FIG.
In the same step as (19) in FIG.
PSD film (about 300 nm) by VD, catalytic CVD, etc.
Thickness) and an insulating film 3 composed of a SiN film (about 300 nm thick)
6 is formed on the entire surface, and a contact window is opened in the drain of the display TFT.

Next, as shown in (17) of FIG.
In the same step as (20) in FIG. 7, a photosensitive resin film 28 having a thickness of 2 to 3 μm is formed by spin coating or the like, and as shown in (18) in FIG. A concave-convex pattern that obtains optimum reflection characteristics and viewing angle characteristics is formed in the portion, and reflow is performed to form a lower reflective surface including the concave-convex rough surface 28A. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, as shown in (18) of FIG.
In the same step as (21) in FIG.
A sputtered film made of aluminum or the like having a thickness of 00 nm is formed, and a reflective portion 29 made of aluminum or the like connected to the drain portion 19 of the display TFT is formed by general-purpose photolithography and etching technology.

As described above, the crystalline sapphire film 5
A bottom gate type nMOS LDD-TFT (a CMOS drive circuit including a bottom gate type pMOSTFT and an nMOSTFT in a peripheral portion) is formed on a display unit using the single crystal silicon layer 7 formed with the 0 and the step 4 as seeds for heteroepitaxial growth. The integrated active matrix substrate 30 of the display section and the peripheral drive circuit section can be manufactured.

FIG. 25 shows an example in which the gate insulating film of the above-mentioned bottom gate type MOSTFT provided in the display portion is formed by an anodic oxidation method of Mo · Ta.

That is, after the step (2) in FIG.
As shown in (3), the molybdenum-tantalum alloy film 71
Is subjected to a known anodic oxidation treatment so that T
a ₂ O ₅ gate insulating film 74 of 100 to 200 n
m thickness.

In the subsequent steps, as shown in FIG. 25 (4), steps 4 and further the crystalline sapphire film 50 are formed in the same manner as in the steps (4) to (9) of FIGS. Forming
After the single crystal silicon layer 7 is heteroepitaxially grown, an active matrix substrate 30 is manufactured as shown in FIG. 25 (5) in the same manner as in the steps (10) to (18) of FIG.

Next, in order to manufacture a dual gate type MOSTFT in the display section, first, FIG.
Steps up to (9) in FIG. 22 are performed in the same manner as described above.

That is, as shown in (10) of FIG. 26, a step 4 is formed on the insulating films 72 and 73 and the substrate 1, and a single-crystal silicon layer 7 is formed using the crystalline sapphire film 50 and the step 4 as seeds. Hetero-epitaxial growth. Next, in the same step as (11) in FIG. 4, an SiO ₂ film (about 200 nm thick) and a SiN film (about 100 nm thick) are formed on the entire surface of the single crystal silicon layer 7 by plasma CVD, catalytic CVD, or the like.
Insulating film 80 (this corresponds to the above-mentioned insulating film 8) is formed successively in this order to form a sputtered film 81 of Mo.Ta alloy (500-600 nm thick) (this is the above-mentioned sputtered film). (Corresponding to the film 9).

Next, as shown in FIG. 26 (11),
In the same step as (12) in FIG. 4, a photoresist pattern 10 is formed, and Mo.
A Ta alloy top gate electrode 82 (which corresponds to the above-described gate electrode 12) and a gate insulating film 83 (which corresponds to the above-described gate insulating film 11) are formed to expose the single crystal silicon layer 7.

Next, as shown in FIG. 26 (12),
In the same step as (13) in FIG. 4, the top gate portion of the nMOSTFT is covered with the photoresist 13, and the exposed source / drain regions of the display nMOSTFT are doped (ion-implanted) with phosphorus ions 14 to form N ^−.
The LDD part 15 of the mold layer is formed.

Next, as shown in FIG. 26 (13),
In the same step as (14) in FIG. 5, the gate portion and the LDD portion of the nMOS TFT are covered with a photoresist 16 and the exposed region is doped (ion-implanted) with phosphorus or arsenic ion 17 to form an N ⁺ type layer of the nMOS TFT. The source part 18 and the drain part 19 are formed.

Next, as shown in (14) of FIG.
In the same step as (15) in FIG. 5, the gate portion of the pMOSTFT is covered with a photoresist 20 and boron ions 21 are doped (ion-implanted) in the exposed region, and the source of the P ⁺ layer of the pMOSTFT in the peripheral drive circuit portion is formed. And a drain part are formed.

Next, as shown in FIG. 27 (15),
In the same step as (16) in FIG. 5, a photoresist 24 is provided in order to make the active element section and the passive element section into islands, and the single crystal silicon layer other than the active element section and the passive element section is subjected to general-purpose photolithography and etching techniques. To remove selectively.

Next, as shown in FIG. 27 (16),
In the same step as (17) in FIG.
SiO by high-density plasma CVD, catalytic CVD, etc.
_{A 2} film 53 (about 200 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface. These films 53 and 54 correspond to the protective film 25 described above. Then, the single crystal silicon layer 7 is activated.

Next, as shown in FIG. 27 (17),
In the same step as (18) in FIG. 6, a contact window is opened in the source section. And 400-500n on the whole surface
A m-thick aluminum sputtered film is formed, and the source electrode 2 is formed by general-purpose photolithography and etching techniques.
At the same time as forming 6, a data line and a gate line are formed.

Next, as shown in (18) of FIG.
In the same step as (19) in FIG.
Thickness) and an insulating film 3 composed of a SiN film (about 300 nm thick)
6 is formed on the entire surface, and a contact window is opened in the drain of the display TFT.

Next, as shown in FIG. 28 (19),
A photosensitive resin film 28 having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like, and as shown in FIG.
In the same manner as in the steps (21) and (22), the lower part of the reflection surface composed of the roughened surface 28A is formed at least in the pixel portion, and at the same time, a resin window for contact of the drain portion of the display TFT is opened. A reflection portion 29 made of aluminum or the like having an uneven shape for obtaining optimum reflection characteristics and viewing angle characteristics is connected to the drain portion 19 of the TFT for use.

As described above, the crystalline sapphire film 5
Using a single-crystal silicon layer 7 formed as a seed for heteroepitaxial growth with a 0 and a step 4, a dual gate type nMOSLDD TFT is used for the display unit, and a bottom gate type pMOSTFT and nMOSTF are used for the peripheral drive circuit unit.
A display-peripheral drive circuit unit integrated type active matrix substrate 30 incorporating a CMOS drive circuit made of T can be manufactured.

<Eighth Embodiment> FIGS. 29 to 34 show
14 shows an eighth embodiment of the present invention.

In the present embodiment, unlike the above-described embodiment, the gate electrode of the top gate portion is made of aluminum, an aluminum alloy such as aluminum containing 1% Si, aluminum containing 1 to 2% copper, copper or the like. It is made of a material with low heat resistance.

First, the top gate type MOSTF
In the case where a bottom gate type MOSTFT is provided in the peripheral drive circuit, T is the same as that in FIG.
Steps (1) to (10) in FIG. 3 are performed in the same manner.
As shown in (10) of FIG. 29, the pM
An N-type well 7A is formed in the OSTFT portion.

Next, as shown in FIG. 29 (11),
All of the nMOS and pMOSTFTs in the peripheral drive region and the gate portion of the nMOSTFT in the display region are photoresist 1
3 and cover the exposed source / drain regions of the nMOS TFT with phosphorus ions 14 at, for example, 20 kV and 5 × 10 5
^By doping (ion implantation) at a dose of ¹³ atoms / cm ² , an LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned manner.

Next, as shown in FIG. 30 (12),
All of the pMOSTFTs in the peripheral drive area, the gates of the nMOSTFTs in the peripheral drive area, and the nMOSTFs in the display area.
The gate of T and the LDD portion are covered with a photoresist 16, and the exposed region is doped (ion-implanted) with phosphorus or arsenic ion 17 at a dose of 5 × 10 ¹⁵ atoms / cm ² at, for example, 20 kV to form an nMOS TFT. N ⁺
LDD with Source 18 and Drain 19 Made of Mold Layer
The part 15 is formed. In this case, if the resist 13 is left like an imaginary line, and the resist 16 is provided so as to cover the resist 13, the mask 13 can be used as a guide for the mask alignment at the time of forming the resist 16, the mask alignment can be facilitated, and the misalignment can be achieved. Is also reduced.

Next, as shown in FIG. 30 (13),
NMOS TFT in peripheral drive area and nMOS in display area
The entirety of the TFT and the gate of the pMOSTFT are covered with a photoresist 20, and boron ions 21
(Ion implantation) at a dose of 5 × 10 ¹⁵ atoms / cm ^{2 at} 10 kV, for example,
The source part 22 and the drain part 23 of the P ⁺ layer are formed.

Next, after removing the resist 20, FIG.
As shown in (14), the single crystal silicon layers 7 and 7A are activated in the same manner as described above, and a gate insulating film 12 and a gate electrode material (aluminum or aluminum containing 1% Si or the like) 11 are further provided on the surface. Form. The gate electrode material layer 11 can be formed by a vacuum evaporation method or a sputtering method.

Next, in the same manner as described above, after patterning each gate section, the active element section and the passive element section are made into islands, and as shown in FIG.
₂ film (about 200 nm thick) and phosphorus silicate glass (P
An SG) film (about 300 nm thick) is continuously formed on the entire surface in this order to form the protective film 25.

Next, as shown in FIG. 31 (16),
By general-purpose photolithography and etching technology, contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFT.

Then, a sputtered film of 500-600 nm thick aluminum or aluminum containing 1% Si is formed on the entire surface, and the peripheral drive circuit and the source electrodes 26 of all TFTs in the display section are formed by general-purpose photolithography and etching techniques. A data line and a gate line are formed at the same time as the formation of the drain electrode 27 of the peripheral driving circuit. After that, forming gas (N ₂ + H ₂ )
Sintering is performed at about 400 ° C. for 1 hour.

Next, (19) in FIG. 6 to (22) in FIG.
A top gate type nMOS LDD-TFT and a bottom gate type pMOST having a gate electrode of aluminum or aluminum containing 1% Si, respectively, in the display section and the peripheral drive circuit section using the single crystal silicon layer 7 in the same manner as described above.
A display-peripheral drive circuit unit integrated type active matrix substrate 30 incorporating a CMOS drive circuit composed of FT and nMOSTFT can be manufactured.

In the present embodiment, the gate electrode 11 made of aluminum or aluminum containing 1% Si is formed after the activation treatment of the single crystal silicon layer 7, so that the influence of heat during the activation treatment is not affected by the gate electrode. Since it has no relation to the heat resistance of the material, the heat resistance of the top gate electrode material is relatively low, and even low-cost aluminum or aluminum containing 1% Si can be used. This is because the display unit has a bottom gate type MOSTF
The same applies to the case of T.

Next, a dual gate type MOST is provided in the display section.
In the case where the FT and the peripheral drive circuit are provided with a bottom gate type MOSTFT, FIG.
Steps (1) to (9) in FIG. 22 are performed in the same manner, and an N-type well 7A is formed in the pMOSTFT portion of the peripheral drive circuit as shown in (10) in FIG.

Next, as shown in FIG. 32 (11),
In the same manner as (11) of FIG. 29, the LDD part 15 is formed by doping the TFT part of the display part with phosphorus ions 14.

Next, as shown in FIG. 33 (12),
In the same manner as in (12) of FIG. 30, the nMOSTFT portion of the display portion and the peripheral drive circuit portion is doped with phosphorus ions 17 to form N
^{A +} type source region 18 and a drain region 19 are formed respectively.

Next, as shown in FIG. 33 (13),
The pMO of the peripheral drive circuit unit is similar to (13) of FIG.
The STFT portion is doped with boron ions 21 to form a P ⁺ type source region 22 and a drain region 23, respectively.

Next, after removing the resist 20, FIG.
As shown in (14) of FIG. 34, after patterning the single-crystal silicon layer 7 to make the active element portion and the passive element portion into islands, as shown in (15) of FIG. An activation process is performed in the same manner as described above, and a gate insulating film 80 is formed on the surface.

Next, as shown in FIG. 34 (16),
The upper gate electrode 83 of the display section is formed by patterning aluminum or the like formed over the entire surface by a sputtering method.

Next, as shown in FIG. 34 (17),
An SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 300 nm thick) are successively formed on the entire surface in this order to form a protective film 25.

Next, in the same manner as described above, the source electrodes 26 of all the TFTs in the peripheral drive circuit and the display section and the drain electrode 27 of the peripheral drive circuit section are formed, and the display section and the single crystal silicon layer 7 are used. A dual gate type nMOS LDD-TFT and a bottom gate type pMO using aluminum or the like as a gate electrode are respectively provided in the peripheral drive circuit section.
The display-peripheral drive circuit unit-integrated active matrix substrate 30 incorporating the CMOS drive circuit constituted by the STFT and the nMOSTFT can be manufactured.

Also in this embodiment, since the gate electrode 83 made of aluminum or the like is formed after the activation process of the single crystal silicon layer 7, the influence of heat during the activation process is different from the heat resistance of the gate electrode material. Since it is irrelevant, even a low-cost aluminum or the like can be used as the top gate electrode material with relatively low heat resistance, and the range of choice of the electrode material is widened. The source electrode 26 (and also the drain electrode) can be formed at the same time in the step (16) of FIG. 34, but in this case, there is an advantage in the manufacturing method.

In any of the above embodiments, for example, when fabricating a bottom gate type, a top gate type, or a dual gate type MOSTFT, FIG.
As schematically shown in FIG. 2A, when the step 4 is provided, the single crystal silicon film 7 grown thereon may be thin, resulting in step disconnection (poor connection) or thinning (increase in resistance). In order to surely connect to the source electrode 26 (or the drain electrode), it is desirable that the electrode be deposited on a region including the step 4, as shown in FIGS.

The process shown in FIG. 29 (11) or FIG.
In the step (11), after the formation of the top gate insulating film on the single crystal silicon layer 7, ion implantation and activation may be performed, and then the top gate electrode, the source, and the drain electrode may be simultaneously formed of aluminum.

Further, as shown in FIG. 36 (A), the above-described step 4 is formed on the substrate 1 (and further on the substrate
For example, as shown in FIG. 36B, a crystalline sapphire film 50 (which has a function of stopping diffusion of ions from the glass substrate 1) is formed on the substrate 1 as shown in FIG. You can also. The gate insulating films 72 and 73 described above may be provided instead of the crystalline sapphire film 50 or under the crystalline sapphire film, and the step 4 may be formed thereon. FIGS. 36 (C), (D), and (E) illustrate examples in which the steps 4 are provided in the crystalline sapphire film 50.

<Ninth Embodiment> FIGS. 37 to 39 show
It shows a ninth embodiment of the present invention.

In the present embodiment, various examples in which each TFT is formed outside the above-described step 4 (ie, on the substrate 1 other than the step) will be described. The single crystal silicon layer 7 and the gate /
The source / drain electrodes 26 and 27 are schematically illustrated.

First, FIG. 37 shows a top gate type TFT. FIG. 37 (a) shows that a recess 4 due to a step is formed on one side of the source side along the source region, and single crystal silicon is formed on the flat surface of the substrate other than the recess. A gate insulating film 12 and a gate electrode 11 are formed on the layer 7. Similarly, (b) shows an example in which the recess 4 due to the step is formed in an L-shaped pattern over two sides along the channel length direction up to the end of the drain region as well as the source region, and (c) shows the same recess 4 An example in which a rectangular shape is formed over four sides so as to surround a TFT active region is shown. (D) is an example in which the same concave portion 4 is formed over three sides, and (e) is an example in which the same concave portion 4 is formed in an L-shaped pattern over two sides. Recess 4-
It is not continuous between four.

As described above, since the recesses 4 of various patterns can be formed and the TFT is provided on the flat surface other than the recesses 4, the TFT can be easily manufactured.

FIG. 38 shows the case of a bottom gate type MOSTFT, but the steps (or recesses) 4 of various patterns shown in FIG. 37 can be formed in the same manner. That is, FIG.
FIG. 8A is an example corresponding to FIG. 37A, in which a bottom gate type MOSTFT is formed on a flat surface other than the recess 4 due to the step. Similarly, FIG. 38B shows FIG.
FIG. 7C shows an example corresponding to FIGS. 37C and 37D. FIG. 38D shows the crystalline sapphire film 5.
This is a case where a step 4 is provided at 0.

FIG. 39 shows a dual gate type MOSTFT.
In this case, the steps (or recesses) 4 of the various patterns shown in FIG. 37 can be formed in the same manner. For example, on the flat surface in the area inside the steps 4 shown in FIG. A dual-gate MOSTFT can be manufactured.

<Tenth Embodiment> FIGS. 40 to 42
Shows a tenth embodiment of the present invention.

FIG. 40 shows an example of a T-type LDD structure having a self-aligned structure.
The present invention relates to an FT, for example, a double gate type MOSTFT in which a plurality of top gate type LDD-TFTs are connected.

According to this, the gate electrode 11 is branched into two, one of which is used as the first gate and the first LDD-TF.
A second LDD-TF for T and the other as a second gate
Used for T (however, an N ⁺ -type region 100 is provided between gate electrodes at the center of the single crystal silicon layer to reduce resistance). In this case, a different voltage may be applied to each gate, and even if one gate becomes inoperable for some reason, carriers can be moved between the source and the drain by using the remaining gates. Thus, a highly reliable device can be provided. Further, since the first LDD-TFT and the second LDD-TFT are connected in series to form a thin film transistor for driving each pixel, the source of each thin film transistor is turned off when it is off. The voltage applied between the drains can be greatly reduced. Therefore, the leakage current flowing during the off state can be reduced, and the contrast and the image quality of the liquid crystal display can be improved satisfactorily. Further, since the two LDD transistors are connected using only the same semiconductor layer as the low-concentration drain region in the LDD transistor, the connection distance between the transistors can be shortened,
Even if two D transistors are connected, the required area can be prevented from increasing. In addition, the above-mentioned first and second
Can be completely separated from each other and operated independently.

FIG. 41 shows an example of a bottom gate type MOSTF.
T has a double-gate structure (A) and dual-gate MOSTFT has a double-gate structure (B).

These double-gate MOSTFTs also
It has the same advantages as the above-mentioned top gate type. Among them, the dual gate type has the further advantage that one of the upper and lower gate portions can be used even if one of the upper and lower gate portions becomes inoperable.

FIG. 42 shows each of the above-mentioned double gate type MOs.
FIG. 2 shows an equivalent circuit diagram of an STFT. In the above description, the gate is branched into two, but the gate may be branched or divided into three or more. In these double-gate or multi-gate structures, two
The gate electrode may have the above-mentioned branched gate electrode of the same potential, or may have a divided gate electrode of a different potential or the same potential.

<Eleventh Embodiment> FIG. 43 shows an eleventh embodiment of the present invention.
In the FT dual-gate type TFT, one of the upper and lower gates is operated as a transistor.
The other gate is operated as follows.

That is, FIG. 43A shows that in the nMOS TFT, an arbitrary negative voltage is always applied to the gate electrode on the top gate side to reduce the leakage current in the back channel. The case where the top gate electrode is opened is when the device is used as a bottom gate type. Also,
In FIG. 43B, an arbitrary negative voltage is always applied to the gate electrode on the bottom gate side to reduce the leakage current of the back channel. Also in this case, when the bottom gate electrode is opened, it can be used as a top gate type. In the case of a pMOSTFT, if an arbitrary positive voltage is always applied to the gate electrode, the leakage current of the back channel can be reduced.

In any case, the interface between the single crystal silicon layer 7 and the insulating film has poor crystallinity and a leak current easily flows, but the leak current can be cut off by applying a negative voltage to the electrode as described above. This is advantageous in combination with the effect of the LDD structure. In addition, a leak current may flow due to light incident from the glass substrate 1 side. However, since the light is blocked by the bottom gate electrode, the leak current can be reduced.

<Twelfth Embodiment> FIGS. 44 to 50
Shows a twelfth embodiment of the present invention.

In the present embodiment, the above-mentioned material layer (for example, a crystalline sapphire film) is formed on a flat surface of the substrate without providing the steps (recesses) as described above on the substrate, and this material layer is used as a seed. The present invention relates to an active matrix reflective liquid crystal display device (LCD) in which a single-crystal silicon layer is heteroepitaxially grown, and a top gate type MOSTFT is used as a display unit and a bottom gate type MOSTFT is used as a peripheral drive circuit unit.

The active matrix reflective LCD according to the present embodiment will be described with reference to FIGS. 44 to 49, the left side of each drawing shows the manufacturing process of the display unit, and the right side shows the manufacturing process of the peripheral drive circuit unit.

First, as shown in FIG. 44A, a sputtered film 71 (500) of a molybdenum / tantalum (Mo.Ta) alloy is formed on one main surface of an insulating substrate 1 such as quartz glass or transparent crystallized glass.厚 600 nm thick).

Next, as shown in (2) of FIG. 44, a photoresist 70 is formed in a predetermined pattern, and using this as a mask, the Mo / Ta film 71 is taper-etched so that the side end 71a has a trapezoidal shape. A gate electrode 71 that is gently inclined at an angle of about 45 degrees is formed.

Next, as shown in FIG. 44 (3), after removing the photoresist 70, an SiN film (about 100 nm thick) 72 is formed on the substrate 1 including the molybdenum-tantalum alloy film 71 by a plasma CVD method or the like. And a SiO ₂ film (about 200 nm thick) 73 are laminated in this order to form a gate insulating film.

Next, as shown in FIG. 45D, a crystalline sapphire film (thickness: 20 to 200 nm) 5 is formed on at least the TFT forming region on one main surface of the insulating substrate 1.
0 is formed. This crystalline sapphire film 50 is formed by a high-density plasma CVD method or a catalytic CVD method (Japanese Patent Laid-Open No. 63-40 / 1988).
314, etc.), and oxidize a trimethylaluminum gas or the like with an oxidizing gas (oxygen / moisture) and crystallize it. A high heat-resistant glass substrate (8 to 12 inches φ, 700 to 800 μm thick) can be used as the insulating substrate 1.

Next, as shown in (5) of FIG. 45, similarly to (6) of FIG.
A polycrystalline silicon film 5 is formed on the entire surface of the crystalline sapphire film 50 by a VD method, a sputtering method, or the like, at a substrate temperature of about 100.
Several μm to 0.005 μm (e.g., 0.1 μm
m).

Next, as shown in FIG. 45 (6), the indium film 6 is formed on the polycrystalline silicon film 5 by the MOCVD method, the sputtering method, or the vacuum deposition method of trimethylindium, the number of the polycrystalline silicon film 5 It is formed to have a thickness several hundred times (for example, 10 to 15 μm). Note that, instead of the indium film 6, an indium gallium or gallium film can be applied, but the indium film will be described below as a representative example.

Next, the substrate 1 is placed in a hydrogen atmosphere such as hydrogen or a nitrogen-hydrogen mixture or an argon-hydrogen mixture for 10 minutes.
It is kept at a temperature of not more than 00 ° C, especially 900 to 930 ° C for about 5 minutes. As a result, the polycrystalline silicon 5 is dissolved in the indium 6 melt. In this melt, silicon exhibits the property of precipitating at a much lower temperature than the original deposition temperature. The heating of the substrate 1 may be performed by a method of uniformly heating the entire substrate using an electric furnace or the like, or by using an optical laser, an electron beam, or the like.
A method of locally heating only a predetermined location, for example, only a TFT formation region, is also possible.

Then, by gradually cooling, the silicon dissolved in the indium is heteroepitaxially grown as shown in FIG. 45 (7) using the crystalline sapphire film 50 as a seed, and has a thickness of, for example, 0%. .1 μm
A P-type single crystal silicon layer 7 is deposited.

In the single-crystal silicon layer 7 deposited as described above, for example, the (100) plane is heteroepitaxially grown on the substrate in order for the crystalline sapphire film 50 to exhibit good lattice matching with single-crystal silicon.

After the single crystal silicon layer 7 is deposited on the substrate 1 by heteroepitaxial growth, the indium film 6A on the surface is dissolved and removed with hydrochloric acid, sulfuric acid or the like as shown in FIG. In the same manner as described above, a top-gate or bottom-gate MOSTFT using the single crystal silicon layer 7 as a channel region is manufactured.

First, a specific resistance is adjusted by doping a suitable amount of a P-type carrier impurity, for example, boron ion, over the entire surface of the single-crystal silicon layer 7 formed by the epitaxial growth.
Further, only the pMOSTFT formation region is selectively doped with an N-type carrier impurity to form an N-type well. For example, a p-channel TFT portion is masked with a photoresist (not shown), and P-type impurity ions (for example, B ⁺ ) are
Doping is performed at 0 kV at a dose of 2.7 × 10 ¹¹ atoms / cm ² to adjust the specific resistance. Also, (1) in FIG.
As described in (0), in order to control the impurity concentration in the pMOSTFT formation region, the nMOSTFT portion is masked with a photoresist 60 and N-type impurity ions (for example, P ⁺ ) 65 are formed.
At a dose of 1 × 10 ¹¹ atoms / cm ² at 10 kV to form an N-type well 7A.

Next, as shown in (9) of FIG. 46, SiO ₂ (about 200 μm) is formed on the entire surface of the single crystal silicon layer 7 by plasma CVD, high-density plasma CVD, catalytic CVD, or the like.
nm thick) and SiN (approximately 100 nm thick) in this order to form a gate insulating film 8, and further, a molybdenum-tantalum (Mo.Ta) alloy sputtered film 9 (500-6).
(Thickness: 00 nm).

Next, as shown in (10) of FIG.
The TF of the display area is obtained by using general-purpose photolithography technology.
A photoresist pattern 10 is formed in each step region (in the concave portion) between the T portion and the TFT portion in the peripheral drive region,
A gate electrode 11 of (Mo.Ta) alloy and a gate insulating film (SiN / SiO ₂ ) 12 are formed by continuous etching, and the single crystal silicon layer 7 is exposed. (Mo ・
The Ta) alloy film 9 is treated with an acid-based etching solution, SiN is treated with plasma etching of CF ₄ gas, and SiO ₂ is treated with a hydrofluoric acid-based etching solution.

Next, as shown in FIG. 46 (11),
All of the nMOS and pMOSTFTs in the peripheral drive region and the gate portion of the nMOSTFT in the display region are photoresist 1
3 and cover the exposed source / drain regions of the nMOS TFT with phosphorus ions 14 at, for example, 20 kV and 5 × 10 5
^By doping (ion implantation) at a dose of ¹³ atoms / cm ^2, the LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned manner (self-aligned).

Next, as shown in (12) of FIG.
All of the pMOSTFTs in the peripheral drive area, the gates of the nMOSTFTs in the peripheral drive area, and the nMOSTFs in the display area.
The gate of T and the LDD portion are covered with a photoresist 16, and the exposed region is doped (ion-implanted) with phosphorus or arsenic ion 17 at a dose of 5 × 10 ¹⁵ atoms / cm ² at, for example, 20 kV to form an nMOS TFT. N ⁺
LDD with Source 18 and Drain 19 Made of Mold Layer
The part 15 is formed.

Next, as shown in FIG. 47 (13),
NMOS TFT in peripheral drive area and nMOS in display area
The entirety of the TFT and the gate of the pMOSTFT are covered with a photoresist 20, and boron ions 21
(Ion implantation) at a dose of 5 × 10 ¹⁵ atoms / cm ^{2 at} 10 kV, for example,
The source part 22 and the drain part 23 of the P ⁺ layer are formed. This operation is unnecessary since the nMOS peripheral drive circuit does not have a pMOS TFT.

Next, as shown in (14) of FIG.
A photoresist 24 is provided to make an active element portion such as a TFT and a diode, and a passive element portion such as a resistor and an inductance into an island, and a single crystal other than the active element portion and the passive element portion in all of the peripheral driving region and the display region. The silicon layer is removed by general-purpose photolithography and etching techniques. The etching solution is hydrofluoric acid.

Next, as shown in (15) of FIG.
An SiO ₂ film (about 200 nm thick) and a phosphosilicate glass (PSG) film (about 300 nm thick) are successively formed on the entire surface in this order by plasma CVD, high-density plasma CVD, catalytic CVD, or the like to form a protective film 25. .

Then, in this state, the single crystal silicon layer is activated. In this activation, lamp annealing conditions such as halogen are about 1000 ° C. and about 10 seconds, and a gate electrode material that can withstand this is required.
-Ta alloy is suitable. This gate electrode material therefore
The wiring can be provided not only as a gate portion but also as a wiring over a wide range. Here, expensive excimer laser annealing is not used, but if it is used, the condition is that XeCl (308 nm wavelength) is used for the entire surface, or the selective overlap of 90% or more of only the active element portion and the passive element portion. Scanning is preferred.

Next, as shown in (16) of FIG.
By general-purpose photolithography and etching technology, contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFT.

Then, a sputtered film of aluminum or aluminum containing 1% Si having a thickness of 500 to 600 nm is formed on the entire surface, and the source electrodes 26 of all the TFTs in the peripheral drive circuit and the display section are formed by general-purpose photolithography and etching techniques. A data line and a gate line are formed at the same time as the formation of the drain electrode 27 of the peripheral driving circuit. After that, forming gas (N ₂ + H ₂ )
Sintering is performed at about 400 ° C. for 1 hour.

Next, as shown in (17) of FIG.
An insulating film 36 made of a PSG film (about 300 nm thick) and a SiN film (about 300 nm thick) is formed on the entire surface by plasma CVD, high-density plasma CVD, catalytic CVD, or the like. Next, a contact window is opened in the drain portion of the display TFT. It should be noted that SiO ₂ , PSG and S
It is not necessary to remove the iN film.

Next, for the same purpose as described in (20) of FIG. 7, as shown in (18) of FIG. 49, a photosensitive resin film 28 having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like. 48, as shown in FIG. 48 (19), by using general-purpose photolithography and etching techniques, a concavo-convex pattern is formed at least in the pixel portion to obtain optimal reflection characteristics and viewing angle characteristics, and is reflowed to form a concavo-convex rough surface 28A. The lower surface of the reflecting surface is formed. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, as shown in (20) of FIG.
400-500 nm thick aluminum or 1% S on the entire surface
An aluminum film or the like other than the pixel portion is removed by a general-purpose photolithography and etching technique to form a sputtered film made of i-containing aluminum or the like.
9 is formed. This is used as a pixel electrode for display. Then, about 300 ° C / 1h in forming gas
Sintering to make the contacts sufficient. Note that silver or a silver alloy may be used instead of the aluminum-based material in order to increase the reflectance.

As described above, the crystalline sapphire film 5
0 is used as a seed for high-temperature heteroepitaxial growth to form a single-crystal silicon layer 7, and a top gate type nMOS LDD-TFT and a bottom gate type pM are formed in a display portion and a peripheral drive circuit portion using the single crystal silicon layer 7, respectively.
The display-peripheral drive circuit unit-integrated active matrix substrate 30 in which a CMOS circuit composed of an OSTFT and an nMOSTFT is manufactured can be manufactured.

Using the active matrix substrate (drive substrate) 30 thus obtained, the reflection type liquid crystal display (LCD) shown in FIG. 50 is manufactured in the same manner as described with reference to FIG.

In this embodiment, it is clear that the excellent effects described in the first embodiment can be obtained. In addition, since the single-crystal silicon layer 7 is heteroepitaxially grown only by the crystalline sapphire film 50 without providing a step on the substrate 1, the step of forming the step can be omitted, and the manufacturing process can be further simplified and the growth can be simplified. Thus, problems such as disconnection of the single crystal silicon layer can be solved.

<Thirteenth Embodiment> FIG. 51 shows a thirteenth embodiment of the present invention.

This embodiment relates to an active matrix reflective LCD similar to the above-described twelfth embodiment, but is different from the above-described twelfth embodiment.
After the step (4) in FIG. 45, as shown in (5) in FIG. 51, first, for example, an indium film 6 is formed on the entire surface of the crystalline sapphire film 50 by sputtering or vacuum evaporation, for example, for 10 minutes.
It is formed to a thickness of ２０20 μm.

Next, as shown in FIG. 51 (6), an amorphous silicon film 5 is deposited on the indium film 6 to a thickness of several μm to 0.005 μm (for example, 0.1 μm) by a known plasma CVD method. .

In this case, the temperature for forming the silicon film should not greatly exceed the melting point of the low-melting metal 6 (indium: 156 ° C., gallium: 29.77 ° C.). Crystalline silicon film formation (600-65
0 ° C.) is difficult. Therefore, by plasma CVD,
An amorphous silicon film 5 is formed on the indium film 6.

Next, the substrate 1 was placed in a hydrogen-based atmosphere for 100 hours.
Hold at 0 ° C. or lower (particularly 900 to 930 ° C.) for about 5 minutes. Thereby, the amorphous silicon film 5 is dissolved in the indium melt.

Then, by gradually cooling, the silicon dissolved in the indium melt liquid is heteroepitaxially grown as shown in FIG. 51 (7) using the crystalline sapphire film 50 as a seed, and has a thickness of, for example, 0. .1μ
A single crystal silicon layer 7 having a thickness of about m is deposited.

In this case, the (100) plane of the single-crystal silicon layer 7 is epitaxially grown on the substrate in the same manner as described above.

After the single crystal silicon layer 7 is deposited on the substrate 1 by heteroepitaxial growth, indium on the surface side is dissolved and removed with hydrochloric acid or the like as in the twelfth embodiment. Through a step of performing a predetermined process on the silicon layer 7, each TFT of the display section and the peripheral drive circuit section is manufactured.

In this embodiment, the crystalline sapphire film 5
A low melting point metal layer 6 is formed on the substrate 0, an amorphous silicon layer 5 is formed thereon, and then heat melting and cooling are performed. However, heteroepitaxial growth of single crystal silicon from a low melting point metal melt is performed by: This occurs in the same manner as in the above-described embodiment.

<Fourteenth Embodiment> FIG. 52 shows a fourteenth embodiment of the present invention.

This embodiment relates to an active matrix reflective LCD similar to the twelfth embodiment described above, but differs from the first embodiment in FIG.
After the step (4) of FIG. 5, as shown in FIG. 52 (5),
On the entire surface of the crystalline sapphire film 50, for example, an indium film 6 containing a predetermined amount (for example, about 1% by weight) of silicon.
A is sputtered or vacuum deposited, for example, 10 to 20 μm
Formed to a thickness of

Next, the substrate 1 was placed in a hydrogen-based atmosphere for 100 hours.
Hold at 0 ° C. or lower (particularly 900 to 930 ° C.) for about 5 minutes. Thereby, the silicon is dissolved in the indium melt.

Then, by gradually cooling, the silicon dissolved in the indium melt is heteroepitaxially grown as shown in FIG. 52 (6) using the crystalline sapphire film 50 as a seed, and has a thickness of, for example, 0%. .1μ
A single crystal silicon layer 7 having a thickness of about m is deposited.

In this case, the (100) plane of the single crystal silicon layer 7 is heteroepitaxially grown on the substrate in the same manner as described above.

After depositing single-crystal silicon layer 7 on substrate 1 by heteroepitaxial growth, indium on the surface side is dissolved and removed with hydrochloric acid or the like as in the twelfth embodiment. Through a step of performing a predetermined process on the silicon layer 7, each TFT of the display section and the peripheral drive circuit section is manufactured.

In this embodiment, the crystalline sapphire film 5
After the formation of the low-melting metal layer 6A containing silicon on the substrate 0, heat melting and cooling are performed. However, the heteroepitaxial growth of single-crystal silicon from the melt of the low-melting metal is performed according to the above-described embodiment. The same occurs.

<Fifteenth Embodiment> A fifteenth embodiment of the present invention will be described with reference to FIGS.

In this embodiment, as compared with the twelfth embodiment, a similar top gate type MOSTFT is provided in a display portion and a bottom gate type MOSTFT is provided in a peripheral drive circuit portion. Unlike the embodiment, the present invention relates to a transmission type LCD. That is, (1) of FIG.
To the step shown in FIG. 48 (17) are the same,
After that step, as shown in FIG. 53 (18), a window 19 for contacting the drain portion of the display TFT is opened in the insulating films 25 and 36, and at the same time, unnecessary pixel openings are required to improve transmittance. The SiO ₂ , PSG and SiN films are removed.

Next, as shown in FIG. 53 (19),
A photosensitive acrylic transparent resin flattening film 28B having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like, and a window is opened in the transparent resin 28B on the drain side of the display TFT by general-purpose photolithography. Let it cure.

Next, as shown in (20) of FIG.
An ITO sputtered film having a thickness of 130 to 150 nm is formed on the entire surface, and is contacted with the drain portion 19 of the display TFT by general-purpose photolithography and etching technology.
The TO transparent electrode 41 is formed. Then, by heat treatment (200 to 250 ° C./1 h in a forming gas), the contact resistance between the drain of the display TFT and the ITO is reduced and the transparency of the ITO is improved.

Then, as shown in FIG.
2, and a transmission type LCD is assembled in the same manner as in the eighth embodiment. However, a polarizing plate is also attached to the TFT substrate side. In this transmissive LCD, transmitted light can be obtained as shown by the solid line, but the opposing substrate 3 can be obtained as shown by the dashed line.
It is also possible to obtain transmitted light from two sides.

In the case of this transmissive LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.

That is, (1) in FIG. 44 to (16) in FIG.
Are performed according to the above-described steps.
As shown in FIG. 5 (17), a drain portion of the PSG / SiO ₂ insulating film 25 is also opened to form an aluminum buried layer 41A for a drain electrode, and then a SiN / PSG insulating film 36 is formed.

Next, as shown in (18) of FIG.
After forming a photoresist 61 having a predetermined thickness (1 to 1.5 μm) in which each color of R, G, and B is dispersed in a pigment for each segment, as shown in (19) of FIG. Each of the color filter layers 61 (R), 61 (G), is patterned by leaving only predetermined positions (each pixel portion).
61 (B) is formed (on-chip color filter structure). At this time, the window of the drain part is also opened. An opaque ceramic substrate cannot be used.

Next, as shown in FIG. 55 (19),
In a contact hole communicating with the drain of the display TFT, a light shielding layer 43 serving as a black mask layer is formed by metal patterning over the color filter layer. For example, molybdenum is sputtered by 200 to 250 n.
An m-thick film is formed and patterned into a predetermined shape that covers the display TFT and shields light (on-chip black structure).

Next, as shown in FIG. 55 (20),
A flattening film 28B made of a transparent resin is formed, and an ITO transparent electrode 41 is further formed in a through hole provided in the flattening film by a light shielding layer 4.
3 is formed.

As described above, by forming the color filter 61 and the black mask 43 on the display array section, the aperture ratio of the liquid crystal display panel can be improved, and the power consumption of the display module including the backlight can be reduced. Realize.

<Sixteenth Embodiment> FIGS. 56 to 64
Shows a sixteenth embodiment of the present invention.

In this embodiment, the peripheral drive circuit section has a bottom gate pM similar to that of the twelfth embodiment.
It is composed of a CMOS drive circuit composed of an OSTFT and an nMOSTFT. The display section is of a reflection type, but has various combinations of TFTs having various gate structures.

That is, FIG. 56A shows a top gate type nMOS LDD-same as in the twelfth embodiment described above.
Although a TFT is provided in the display portion, a bottom gate type nMOS LDD-TFT is provided in the display portion shown in FIG. 56B, and a dual gate type nMO LD-TMO is provided in the display portion shown in FIG.
An SLDD-TFT is provided. As will be described later, the bottom gate type MFT of the peripheral drive circuit section is used for both of these bottom gate type and dual gate type MOS TFTs.
Although it can be manufactured in the same process as the OSTFT, especially in the case of the dual gate type, the driving capability is improved by the upper and lower gate portions, which is suitable for high-speed switching, and by selectively using one of the upper and lower gate portions. Depending on the case, it can be operated as a top gate type or a bottom gate type.

It should be noted that the bottom gate type MO shown in FIG.
In the STFT, reference numeral 71 in the figure denotes a gate electrode of Mo / Ta, etc., reference numeral 72 denotes a SiN film and reference numeral 73 denotes a SiO ₂ film, which forms a gate insulating film. On this gate insulating film, a top gate type MOS TFT is formed. A channel region and the like using a similar single crystal silicon layer are formed. FIG.
In the dual gate type MOSTFT of FIG. 6C, the lower gate portion is the same as the bottom gate type MOSTFT, but the upper gate portion has a gate insulating film 73 formed of a SiO ₂ film and a SiN film, and an upper gate portion formed thereon. An electrode 74 is provided.

Next, the above bottom gate type MOSTFT
57 to 61, and a method of manufacturing the above-described dual gate type MOSTFT will be described with reference to FIGS. 62 to 64, respectively. In addition, the bottom gate type MO of the peripheral drive circuit section
The method of manufacturing the STFT is the same as that described with reference to FIGS. 44 to 49, and is not illustrated here.

In the display section, a bottom gate type MOST
To manufacture the FT, first, as shown in FIG. 57A, a molybdenum / tantalum (Mo.Ta)
An alloy sputtered film 71 (500 to 600 nm thick) is formed.

Next, as shown in (2) of FIG. 57, a photoresist 70 is formed in a predetermined pattern, and the Mo.Ta film 71 is taper-etched using the photoresist as a mask, so that the side end 71a has a trapezoidal shape. A gate electrode 71 that is gently inclined at an angle of about 45 degrees is formed.

Next, as shown in FIG. 57C, after removing the photoresist 71, an SiN film (about 100 nm thick) 72 is formed on the substrate 1 including the molybdenum-tantalum alloy film 71 by a plasma CVD method or the like. And a SiO ₂ film (about 200 nm thick) 73 are laminated in this order to form a gate insulating film.

Next, as shown in (4) of FIG. 58, in the same step as (4) of FIG. 45, the crystalline sapphire is formed on at least the TFT formation region on one main surface of the insulating substrate 1 as described above. Film (thickness 20 to 200 nm) 50
To form

Next, as shown in (5) of FIG. 58, in the same step as (5) of FIG. 45 to (8) of FIG. It is deposited as a single crystal silicon layer 7 of about 0.1 μm. At this time, the side edge 71a of the underlying gate electrode 71 has a gentle slope, so that the single-crystal silicon layer 7 grows on this surface without interrupting the epitaxial growth due to the step 4. Will do.

Next, as shown in FIG. 58 (6), after going through the steps (9) to (10) in FIG. 46, (1) in FIG.
In the same step as 1), the gate portion of the nMOSTFT in the display section is covered with the photoresist 13 and the exposed nM
The source / drain region of the OSTFT is doped (ion-implanted) with phosphorus ions 14 to form an LD composed of an N ⁻ type layer.
The D portion 15 is formed in a self-aligned manner. At this time, the surface height difference (or pattern) can be easily recognized by the presence of the bottom gate electrode 71, the photoresist 13 can be easily positioned (mask-aligned), and alignment deviation hardly occurs.

Next, as shown in (7) of FIG. 59, in the same step as (12) of FIG. 47, the gate portion and the LDD portion of the nMOS TFT are covered with the photoresist 16 and the exposed region is doped with phosphorus or arsenic ion. 17 is doped (ion-implanted) to form a source portion 18 and a drain portion 19 made of an N ⁺ type layer of the nMOS TFT.

Next, as shown in (8) of FIG. 59, in the same step as (13) of FIG. 47, the entire nMOS TFT is covered with the photoresist 20 and boron ions 2
Doping (ion implantation) into the peripheral drive circuit
A source portion and a drain portion of the P ⁺ layer of the MOSTFT are formed.

Next, as shown in FIG. 59 (9), in the same step as FIG. 47 (14), a photoresist 24 is provided to make the active element section and the passive element section into islands, and a single crystal silicon layer is formed. Is selectively removed by general-purpose photolithography and etching techniques.

Next, as shown in FIG. 59 (10),
In the same step as (15) in FIG.
D, S by high density plasma CVD, catalytic CVD, etc.
An iO ₂ film 53 (about 300 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface in this order. The SiO ₂ film 53 and the PSG film 54 correspond to the above-described protective film 25. Then, in this state, the single crystal silicon layer is activated in the same manner as described above.

Next, as shown in (11) of FIG.
In the same step as (16) in FIG. 48, a contact window is opened in the source section by general-purpose photolithography and etching technology. And 400-500n on the whole surface
A m-thick sputtered film of aluminum or aluminum containing 1% Si is formed, and a data line and a gate line are formed simultaneously with the source electrode 26 of the TFT by general-purpose photolithography and etching techniques.
After that, at about 400 ° C / 1h in forming gas,
Sinter.

Next, as shown in FIG. 60 (12),
In the same step as (17) in FIG. 48, a PSG film (about 300 nm) is formed by high-density plasma CVD, catalytic CVD, or the like.
An insulating film 36 made of a m-thick film and a SiN film (about 300 nm-thick) is formed on the entire surface, and a contact window is opened in the drain of the display TFT.

Next, as shown in (13) of FIG.
In the same step as (18) in FIG. 49, a photosensitive resin film 28 having a thickness of 2 to 3 μm is formed by spin coating or the like.
As shown in (14), by using general-purpose photolithography and etching techniques, an uneven pattern is formed at least in the pixel portion so as to obtain optimal reflection characteristics and viewing angle characteristics, and is reflowed to form a reflection formed of the uneven surface 28A. Form the lower surface. At the same time, a resin window for contact of the drain portion of the display TFT is opened.

Next, as shown in (14) of FIG.
In the same step as (20) in FIG.
A sputtered film made of aluminum or aluminum containing 1% Si having a thickness of 500 nm is formed, and a reflection portion 29 made of a concavo-convex shape aluminum or the like connected to the drain portion 19 of the display TFT by general-purpose photolithography and etching technology.
To form

As described above, the crystalline sapphire film 5
0 is a bottom gate type nMOSLDD-TFT in the display unit using the single crystal silicon layer 7 formed as a seed for high-temperature heteroepitaxial growth (CM including bottom gate type pMOSTFT and nMOSTFT in the peripheral part).
An active matrix substrate 30 integrated with a display portion and a peripheral drive circuit portion incorporating an OS drive circuit) can be manufactured.

FIG. 61 shows an example in which the gate insulating film of the above-mentioned bottom gate type MOSTFT provided in the display portion is formed by the Mo.Ta anodic oxidation method.

That is, after the step (2) of FIG. 57, FIG.
As shown in (3), the molybdenum-tantalum alloy film 71
Is subjected to a known anodic oxidation treatment so that T
a ₂ O ₅ gate insulating film 74 of 100 to 200 n
m thickness.

In the subsequent steps, as shown in FIG. 61 (4), a crystalline sapphire film 50 is formed in the same manner as in the steps (4) to (5) of FIG. After heteroepitaxial growth, (6) to (6) of FIG.
The active matrix substrate 30 is manufactured as shown in FIG. 61 (5) in the same manner as in the step (14) of FIG.

Next, in order to manufacture a dual gate type MOSTFT in the display section, first, FIG.
The steps up to (5) in FIG. 58 are performed in the same manner as described above.

That is, as shown in FIG. 62- (6), a crystalline sapphire film 50 is formed on the insulating films 72 and 73, and the single-crystal silicon layer 7 is hetero-structured using the crystalline sapphire film 50 as a seed. Epitaxial growth is performed. Next, in the same step as (9) of FIG. 46, an SiO ₂ film (about 200 nm thick) and a SiN film (about 100 nm thick) are formed on the entire surface of the single crystal silicon layer 7 by plasma CVD, catalytic CVD, or the like.
Insulating film 80 (this corresponds to the above-mentioned insulating film 8) is formed successively in this order to form a sputtered film 81 of Mo.Ta alloy (500-600 nm thick) (this is the above-mentioned sputtered film). (Corresponding to the film 9).

Next, as shown in (7) of FIG. 62, in the same step as (10) of FIG. 46, a photoresist pattern 10 is formed, and Mo ·
A Ta alloy top gate electrode 82 (which corresponds to the above-described gate electrode 12) and a gate insulating film 83 (which corresponds to the above-described gate insulating film 11) are formed to expose the single crystal silicon layer 7.

Next, as shown in (8) of FIG. 62, in the same step as (11) of FIG. 46, the top gate portion of the nMOS TFT is covered with the photoresist 13 and the source / drain of the exposed nMOS TFT for display is exposed. The region is doped with phosphorus ions 14 (ion implantation) to form N ⁻
The LDD part 15 of the mold layer is formed.

Next, as shown in (9) of FIG. 62, in the same step as (12) of FIG. 47, the gate portion and the LDD portion of the nMOS TFT are covered with the photoresist 16, and the exposed region is doped with phosphorus or arsenic ion. 17 is doped (ion-implanted) to form a source portion 18 and a drain portion 19 made of an N ⁺ type layer of the nMOS TFT.

Next, as shown in (10) of FIG.
In the same step as (13) in FIG.
Is covered with a photoresist 20 and boron ions 21 are doped (ion-implanted) in the exposed regions to form the source and drain portions of the P ⁺ layer of the pMOSTFT of the peripheral drive circuit portion.

Next, as shown in FIG. 63 (11),
In the same step as (14) in FIG. 47, a photoresist 24 is formed to make the active element section and the passive element section into islands.
Is provided, and the single crystal silicon layer other than the active element portion and the passive element portion is selectively removed by general-purpose photolithography and etching techniques.

Next, as shown in FIG.
In the same step as (15) in FIG.
D, S by high density plasma CVD, catalytic CVD, etc.
An iO ₂ film 53 (about 200 nm thick) and a phosphosilicate glass (PSG) film 54 (about 300 nm thick) are formed on the entire surface. These films 53 and 54 correspond to the protective film 25 described above. Then, the single crystal silicon layer 7 is activated.

Next, as shown in (13) of FIG.
In the same step as (16) in FIG. 48, a contact window is opened in the source portion. And 400-500 on the whole surface
A data line and a gate line are formed at the same time as the source electrode 26 is formed by a general-purpose photolithography and etching technique by forming a sputtered film of aluminum or aluminum containing 1% Si with a thickness of nm.

Next, as shown in FIG. 64 (14),
In the same step as (17) in FIG. 48, the PSG film (about 300 nm
Thickness) and an insulating film 3 composed of a SiN film (about 300 nm thick)
6 is formed on the entire surface, and a contact window is opened in the drain of the display TFT.

Next, as shown in FIG. 64 (15),
A photosensitive resin film 28 having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like, and as shown in FIG.
In the same manner as in the steps (19) and (20) of No. 9, at least a lower portion of the reflection surface composed of the roughened surface 28A is formed in the pixel portion, and at the same time, a resin window for contact of the drain portion of the display TFT is opened. A reflection portion 29 of aluminum or the like having a concave and convex shape for obtaining optimum reflection characteristics and viewing angle characteristics is connected to the drain portion 19 of the display TFT.

As described above, the crystalline sapphire film 5
A display using a single-crystal silicon layer 7 formed with 0 as a seed for heteroepitaxial growth, a dual-gate nMOSLDDTFT in the display section, and a CMOS drive circuit composed of a bottom-gate pMOSTFT and nMOSTFT in the peripheral drive circuit section. The unit-peripheral drive circuit unit integrated type active matrix substrate 30 can be manufactured.

<Seventeenth Embodiment> FIGS. 65 to 67
Shows a seventeenth embodiment of the present invention.

In this embodiment, different from the above-described embodiment, the gate electrode of the top gate portion is formed of a material having relatively low heat resistance such as aluminum.

First, when the top gate type MOSTFT is provided in both the display section and the peripheral drive circuit section, the steps from (1) to (8) in FIGS. 44 to 46 in the twelfth embodiment are the same. Then, as shown in FIG. 65 (10), an N-type well 7A is formed in the pMOSTFT portion of the peripheral drive circuit portion.

Next, as shown in FIG. 65 (11),
All of the nMOS and pMOSTFTs in the peripheral drive region and the gate portion of the nMOSTFT in the display region are photoresist 1
3 and cover the exposed source / drain regions of the nMOS TFT with phosphorus ions 14 at, for example, 20 kV and 5 × 10 5
^By doping (ion implantation) at a dose of ¹³ atoms / cm ² , an LDD portion 15 made of an N ⁻ -type layer is formed in a self-aligned manner.

Next, as shown in (12) of FIG.
All of the pMOSTFTs in the peripheral drive area, the gates of the nMOSTFTs in the peripheral drive area, and the nMOSTFs in the display area.
The gate of T and the LDD portion are covered with a photoresist 16, and the exposed region is doped (ion-implanted) with phosphorus or arsenic ion 17 at a dose of 5 × 10 ¹⁵ atoms / cm ² at, for example, 20 kV to form an nMOS TFT. N ⁺
LDD with Source 18 and Drain 19 Made of Mold Layer
The part 15 is formed. In this case, if the resist 13 is left like an imaginary line, and the resist 16 is provided so as to cover the resist 13, the mask 13 can be used as a guide for the mask alignment at the time of forming the resist 16, the mask alignment can be facilitated, and the misalignment can be achieved. Is also reduced.

Next, as shown in (13) of FIG.
NMOS TFT in peripheral drive area and nMOS in display area
The entirety of the TFT and the gate of the pMOSTFT are covered with a photoresist 20, and boron ions 21
(Ion implantation) at a dose of 5 × 10 ¹⁵ atoms / cm ^{2 at} 10 kV, for example,
The source part 22 and the drain part 23 of the P ⁺ layer are formed.

Next, after removing the resist 20, FIG.
As shown in (14), the single crystal silicon layers 7 and 7A are activated in the same manner as described above, and a gate insulating film 12 and a gate electrode material (aluminum or aluminum containing 1% Si or the like) 11 are further provided on the surface. Form. The gate electrode material layer 11 can be formed by a vacuum evaporation method or a sputtering method.

Next, after patterning each gate portion in the same manner as described above, the active element portion and the passive element portion are made into islands, and as shown in FIG.
₂ film (about 200 nm thick) and phosphorus silicate glass (P
An SG) film (about 300 nm thick) is continuously formed on the entire surface in this order to form the protective film 25.

Next, as shown in FIG. 67 (16),
By general-purpose photolithography and etching technology, contact windows are opened in the source / drain portions of all the TFTs of the peripheral drive circuit and the source portions of the display TFT.

Then, a sputtering film of aluminum or the like having a thickness of 500 to 600 nm is formed on the entire surface, and the source electrodes 26 of all the TFTs in the peripheral driving circuit and the display section and the drains of the peripheral driving circuit section are formed by general-purpose photolithography and etching techniques. At the same time as the formation of the electrode 27, a data line and a gate line are formed. Thereafter, sintering is performed in a forming gas (N ₂ + H ₂ ) at about 400 ° C. for 1 hour.

Next, (17) in FIG. 48 to (2) in FIG.
In the same manner as in (0), the display section using the single crystal silicon layer 7 and the peripheral drive circuit section are made of aluminum or 1% S, respectively.
Top gate type nMOS LDD-TFT using i-containing aluminum or the like as a gate electrode, bottom gate type pMO
The display-peripheral drive circuit unit-integrated active matrix substrate 30 incorporating the CMOS drive circuit constituted by the STFT and the nMOSTFT can be manufactured.

In the present embodiment, the gate electrode 11 made of aluminum or aluminum containing 1% Si is formed after the activation process of the single crystal silicon layer 7, so that the influence of heat during the activation process is not affected by the gate electrode. Since it has no relation to the heat resistance of the material, the heat resistance is relatively low as the top gate electrode material, and low-cost aluminum or aluminum containing 1% Si or copper can be used. . This is because the display unit is a bottom gate type M
The same applies to the case of the OSTFT.

Next, a dual gate type MOST is provided in the display section.
In the case where a bottom gate type MOSTFT is provided in the FT and the peripheral drive circuit, the circuit shown in FIG.
2 (10) to (17) of FIG. 34, a dual-gate nMO using aluminum or the like as a gate electrode for each of the display unit and the peripheral drive circuit unit.
A display-peripheral drive circuit unit integrated active matrix substrate 30 incorporating a CMOS drive circuit composed of an SLDD-TFT, a bottom gate type pMOSTFT and an nMOSTFT can be manufactured.

<Eighteenth Embodiment> FIGS. 68 to 69
Shows an eighteenth embodiment of the present invention.

The example of FIG. 68 relates to a TFT having a self-aligned LDD structure, for example, a double-gate MOSTFT in which a plurality of top-gate LDD-TFTs are connected in the twelfth embodiment.

FIG. 69 shows an example of a bottom gate type MOSTF.
T has a double-gate structure (A) and dual-gate MOSTFT has a double-gate structure (B).

These double-gate MOSTFTs also
It has the same advantages as those described with reference to FIGS.

<Nineteenth Embodiment> FIGS. 70 to 78
Shows a nineteenth embodiment of the present invention.

As described above, the top gate type, bottom gate type, and dual gate type TFTs each have a difference in structure or function or a feature, so that these are employed in the display portion and the peripheral drive circuit portion. At this time, it may be advantageous to provide various combinations of TFTs between these units.

For example, as shown in FIG. 70, when any of a top gate type, a bottom gate type, and a dual gate type MOSTFT is adopted for the display portion, the top gate type MOSTFT and the bottom gate type MOSTFT are used for the peripheral driving circuit.
At least a bottom gate type of the TFT and the dual gate type MOSTFT may be adopted, or both may be mixed. There are 12 combinations (N
o.1 to No.12). Especially, MOS of peripheral drive circuit
When a dual gate structure is used for a TFT, such a dual gate structure can be easily changed to a top gate type or a bottom gate type by selecting upper and lower gate portions. When a TFT having a large driving capacity is required, a dual gate type may be required. For example, it is considered necessary when the present invention is applied to an organic EL or FED as an electro-optical device other than an LCD.

FIGS. 71 and 72 show the MOSTFT of the display section.
73 and FIG. 74 show the case where the MOSTFT of the display section has the LDD structure when FIG.
Reference numeral 6 denotes a TF having an LDD structure in which the MOSTFT of the peripheral drive circuit section
77 and FIG. 78, when both the peripheral drive circuit section and the display section include the MOSD having the LDD structure, the MOSTs of the peripheral drive circuit section and the display section are respectively shown.
Various examples (No. 1 to No. 216) showing combinations of FTs by channel conductivity type are shown.

As described above, the combination of each gate structure shown in FIG. 70 is specifically as shown in FIGS. 71 to 78. The same combination is possible even when the peripheral drive circuit section is composed of a mixed-type MOSTFT of a top gate type and another gate type. FIG. 70
The various combinations of the TFTs shown in FIGS. 78 to 78 are not limited to the case where the TFT channel region and the like are formed of single crystal silicon, but are similarly applied to the case where the TFTs are formed of polycrystalline silicon or amorphous silicon (only the display portion). It is possible.

<Twentieth Embodiment> FIGS. 79 to 80
Shows a twentieth embodiment of the present invention.

In the present embodiment, in the active matrix drive LCD, the peripheral drive circuit section is provided with the TFT using the above-described single crystal silicon layer based on the present invention in view of improvement of the drive capability. However, this is not limited to the bottom gate type, other gate types may be mixed, the channel conductivity type may be various, and a MOSTFT using a polycrystalline silicon layer other than a single crystal silicon layer is included. It may be. On the other hand, the MOSTFT of the display portion preferably uses a single-crystal silicon layer, but is not limited to this, and may use a polycrystalline silicon or amorphous silicon layer, or at least three types of silicon layers. A mixture of two types may be used. However, when the display section is formed of an nMOS TFT, a practical switching speed can be obtained by using an amorphous silicon layer.
The area can be reduced, and it is more advantageous than amorphous silicon in reducing pixel defects. In addition, not only single-crystal silicon but also polycrystalline silicon is generated at the same time as the above-mentioned grapho-epitaxial growth, so-called CGS (Continuo).
Us grain silicon) structures may also be included, but can also be used to form active and passive devices.

FIG. 79 shows examples (A), (B) and (C) of various combinations of MOSTFTs between the respective parts.
Shows a specific example. When single crystal silicon is used, the current driving capability is improved, so that the element can be made smaller.
The screen can be enlarged, and the aperture ratio in the display section is improved.

In the peripheral drive circuit section, the above MOS
Of course, not only the TFT but also an electronic circuit in which a diode, a capacitance, a resistance, a capacitance, an inductance and the like are integrated may be integrally formed on an insulating substrate (a glass substrate or the like).

<Twenty-first Embodiment> FIG. 81 shows a twenty-first embodiment of the present invention.

In the present embodiment, each of the above-described embodiments is directed to an example of active matrix driving, but the present invention is applied to passive matrix driving.

That is, the display section is provided with no switching element such as the MOSTFT described above, and the incident light or the reflected light of the display section is dimmed only by a potential difference caused by a voltage applied between a pair of electrodes formed on the opposing substrate. You. Such dimming devices include reflective and transmissive LCDs, organic or inorganic ELs (electroluminescent display devices), FEDs (field emission display devices), LEPDs (light emitting polymer display devices), LEDs (light emitting diodes). Display element).

<Twenty-second Embodiment> FIG. 82 shows a twenty-second embodiment of the present invention.

In the present embodiment, the present invention is applied to an electro-optical device other than an LCD, such as an organic or inorganic EL (electroluminescence) element, an FED (field emission display element), and an LEP.
It is applied to D (light emitting polymer display element), LED (light emitting diode display element) and the like.

That is, FIG. 82A shows an EL element driven by an active matrix. For example, an organic EL layer using an amorphous organic compound (or an inorganic EL layer using ZnS: Mn) 90 is formed on the substrate 1. The transparent electrode (ITO) 41 described above is formed at the lower part, and the cathode 91 is formed at the upper part. Light emission of a predetermined color can be obtained through the filter 61 by applying a voltage between these two electrodes.

At this time, in order to apply a data voltage to the transparent electrode 41 by active matrix driving, the present invention uses a single-crystal silicon layer heteroepitaxially grown using the crystalline sapphire film 50 and the step 4 on the substrate 1 as seeds. Single-crystal silicon MOSTFT (ie, n
MOSLDD-TFT) is formed on the substrate 1. A similar TFT is provided in a peripheral driving circuit. This EL element is a MOSLDD-type using a single crystal silicon layer.
Since it is driven by TFT, the switching speed is fast,
Also, the leakage current is small. The above filter 61
Can be omitted as long as the EL layer 90 emits a specific color.

In the case of the EL element, since the driving voltage is high, the peripheral driving circuit section includes, in addition to the above MOSTFT,
It is advantageous to provide a high breakdown voltage driver element (such as a high breakdown voltage cMOS TFT and a bipolar element).

FIG. 82B shows an FED driven by passive matrix. Electrons emitted from the cold cathode 94 by a voltage applied between the electrodes 92 and 93 in a vacuum section between the opposing glass substrates 1-32. Is incident on the opposing phosphor layer 96 by selecting the gate line 95, thereby obtaining light emission of a predetermined color.

Here, the emitter line 92 is guided to a peripheral driving circuit and driven by a data voltage. The peripheral driving circuit is provided with a MOSTFT using a single crystal silicon layer according to the present invention. This contributes to high-speed driving of the emitter line 92. The FED can be driven in an active matrix by connecting the above-mentioned MOSTFT to each pixel.

In the device shown in FIG. 82A, EL
If a known light emitting polymer is used instead of the layer 90, a passive matrix or active matrix driven light emitting polymer display device (LEPD) can be formed. In addition, a device similar to the FED using the diamond thin film on the cathode side in the element of FIG. 82B can also be configured. Further, in a light emitting diode, for example, a gallium-based (gallium.
It can drive a light-emitting portion made of a film of aluminum, arsenic, or the like.

The embodiments of the present invention described above can be variously modified based on the technical concept of the present invention.

For example, when the above-described polycrystalline silicon film 5 is formed, a Group 3 or Group 5 element having high solubility, for example, boron, phosphorus, antimony, arsenic, aluminum, gallium, indium, bismuth, etc. If the amorphous silicon film 5 is appropriately doped, the P-type or N-type channel conductivity type of the silicon epitaxial growth layer 7 to be grown and the carrier concentration thereof can be arbitrarily controlled.

The method of the second or third embodiment may be applied to the fifth embodiment (using indium gallium or metal gallium). Further, a SiN film (for example, 50 to 200 nm thick) and, if necessary, a SiO ₂ film (for example, 100 nm thick) may be provided on the substrate surface to prevent diffusion of ions from the glass substrate. The step 4 as described above may be formed. The above-described steps can be formed by ion milling or the like in addition to RIE. Further, as described above, it is a matter of course that the step 4 may be formed within the thickness of the crystalline sapphire film or the sapphire substrate itself other than forming the step 4 on the substrate 1.

The sapphire (Al ₂ O ₃ )
Instead, a spinel structure (eg, magnesia spinel) having good lattice matching with single crystal silicon (MgO.Al ₂
O ₃ ), CaF ₂ , SrF ₂ , BaF ₂ , BP, (Y
₂ O ₃ ) _m , (ZrO ₂ ) _{1-m and the} like can be used.

Although the present invention is suitable for a TFT of a peripheral driving circuit, the active region of an element such as a diode and the passive region such as a resistor, a capacitance, and an inductance can be formed by a single crystal silicon according to the present invention. It is also possible to form them in layers.

[0372]

According to the present invention, polycrystalline silicon, amorphous silicon, or a low-melting metal layer in which silicon is dissolved is used as a seed with a material layer such as a crystalline sapphire film having good lattice matching with single crystal silicon as a seed. Crystal silicon is heteroepitaxially grown, and the obtained single crystal silicon layer is used as a bottom gate type MOST for a peripheral drive circuit of an electro-optical device such as an LCD integrated with a display unit and a peripheral drive circuit.
Since it is used for FT and the like, the following remarkable functions and effects shown in (A) to (G) can be obtained.

(A) A material layer having good lattice matching with single crystal silicon (for example, a crystalline sapphire film) is formed on a substrate, and heteroepitaxial growth is performed using the material layer as a seed, whereby a high layer of 540 cm ² / v · sec or more is obtained. Since a single-crystal silicon layer having electron mobility can be obtained, it is possible to manufacture an electro-optical device such as a display thin-film semiconductor device with a built-in high-performance driver.

(B) In particular, the single-crystal silicon bottom gate type TFT using the single-crystal silicon layer has high switching characteristics, and has an nMOS or pMO having an LDD structure.
S or cMOSTFT display and high drive capability cM
A configuration in which an OS, an nMOS, a pMOSTFT, or a peripheral drive circuit composed of a mixture thereof is integrated becomes possible, and a high-quality, high-definition, narrow frame, high-efficiency, large-screen display panel is realized.

(C) The above-mentioned material layer is used as a seed for heteroepitaxial growth, and the above-mentioned polycrystalline or amorphous silicon layer or the like is formed on the material layer by plasma or low pressure CVD (chemical vapor deposition: substrate temperature of 100 to 100 ° C.).
400 ° C.) and the like, and the low melting point metal layer can be formed by a method such as a vacuum evaporation method or a sputtering method.
Furthermore, since the heat treatment temperature during the above-described silicon epitaxial growth can be 930 ° C. or lower, a single-crystal silicon layer can be uniformly formed at a relatively low temperature (eg, 400 to 450 ° C.) on an insulating substrate.

(D) Since long-time annealing at an intermediate temperature and excimer laser annealing as in the case of the solid phase growth method are not required, productivity is high, and expensive manufacturing equipment is not required and cost can be reduced. .

(E) In this heteroepitaxial growth, a wide range is adjusted by adjusting the crystallinity of a material layer such as a crystalline sapphire film, the composition ratio of polycrystalline or amorphous silicon to a low melting point metal, the heating temperature of the substrate, and the cooling rate. Since a single-crystal silicon layer having a P-type impurity concentration and high mobility can be easily obtained, Vth (threshold) can be easily adjusted, and high-speed operation can be performed by lowering the resistance.

(F) When forming a polycrystalline or amorphous silicon or silicon-containing low melting point metal layer, an appropriate amount of a Group III or Group V impurity element (boron, phosphorus, antimony, arsenic, bismuth, aluminum, etc.) is separately added. By doping, it is possible to arbitrarily control the impurity species and / or the concentration thereof, that is, the conductivity type such as P-type / N-type and / or the carrier concentration of the single crystal silicon layer formed by heteroepitaxial growth.

(G) The material layer such as a crystalline sapphire film serves as a diffusion barrier for various atoms, so that diffusion of impurities from the glass substrate can be suppressed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of an LCD (Liquid Crystal Display) according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 3 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 4 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 5 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 6 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 7 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 8 is a sectional view of a main part of the LCD.

FIG. 9 is a schematic perspective view for explaining the state of silicon crystal growth on an amorphous substrate.

FIG. 10 is a schematic cross-sectional view showing various step shapes and a silicon growth crystal orientation in the grapho-epitaxial growth technique.

11A and 11B are a Si-In phase diagram (A) and a Si-Ga phase diagram (B).

FIG. 12 is a perspective view showing an overall schematic layout of the LCD according to the first embodiment of the present invention.

FIG. 13 is an equivalent circuit diagram of the LCD.

FIG. 14 is a schematic configuration diagram of the same LCD.

FIG. 15 is a cross-sectional view showing a manufacturing process of the LCD according to the second embodiment of the present invention in the order of steps.

FIG. 16 is a cross-sectional view showing a process of manufacturing an LCD according to the third embodiment of the present invention in the order of steps.

FIG. 17 is a sectional view illustrating the manufacturing process of the LCD according to the fourth embodiment of the present invention in the order of steps.

FIG. 18 is a sectional view of a main part of the LCD.

FIG. 19 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 20 is a sectional view of a main part of an LCD according to a seventh embodiment of the present invention.

FIG. 21 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 22 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 23 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 24 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 25 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 26 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 27 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 28 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 29 is a cross-sectional view showing a manufacturing process of the LCD according to the eighth embodiment of the present invention in the order of steps.

FIG. 30 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 31 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 32 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 33 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 34 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps.

FIG. 35 is a fragmentary cross-sectional view of the same at the time of manufacturing the LCD;

FIG. 36 is a fragmentary cross-sectional view of the same at the time of manufacturing the LCD;

FIG. 37 is a plan view or a sectional view showing various TFTs of an LCD according to a ninth embodiment of the present invention.

FIG. 38 is a cross-sectional view showing various TFTs at the time of manufacturing the LCD.

FIG. 39 is a cross-sectional view of main parts of the LCD.

FIG. 40 is a sectional view or plan view of a main part of an LCD according to a tenth embodiment of the present invention.

FIG. 41 is a cross-sectional view of a principal part of various TFTs of the LCD.

FIG. 42 is an equivalent circuit diagram of a TFT of the LCD.

FIG. 43 is a sectional view showing a main part of a TFT of an LCD according to an eleventh embodiment of the present invention;

FIG. 44 is a cross-sectional view showing a manufacturing process of the LCD according to the twelfth embodiment of the present invention in the order of steps;

FIG. 45 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 46 is a cross-sectional view showing an LCD manufacturing process in the order of steps;

FIG. 47 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 48 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 49 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 50 is a cross-sectional view of main parts of the LCD.

FIG. 51 is a cross-sectional view showing a manufacturing process of the LCD according to the thirteenth embodiment of the present invention in the order of steps;

FIG. 52 is a cross sectional view showing the manufacturing process of the LCD according to the fourteenth embodiment of the present invention in the order of steps;

FIG. 53 is a cross sectional view showing the manufacturing process of the LCD according to the fifteenth embodiment of the present invention in the order of steps;

FIG. 54 is a cross-sectional view of a main part of the same LCD.

FIG. 55 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 56 is a cross-sectional view of a principal part of an LCD according to a sixteenth embodiment of the present invention.

FIG. 57 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 58 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 59 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 60 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 61 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 62 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 63 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 64 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 65 is a sectional view showing the manufacturing process of the LCD according to the seventeenth embodiment of the present invention in the order of steps;

FIG. 66 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 67 is a cross-sectional view showing a manufacturing process of the LCD in the order of steps;

FIG. 68 is a fragmentary cross-sectional view or plan view of an LCD according to an eighteenth embodiment of the present invention.

FIG. 69 is a cross-sectional view of a principal part of various TFTs of the LCD.

FIG. 70 is a view showing a combination of TFTs of each part of the LCD according to the nineteenth embodiment of the present invention.

FIG. 71 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 72 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 73 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 74 is a view showing a combination of TFTs in each part of the LCD.

FIG. 75 is a view showing a combination of TFTs of each part of the LCD.

FIG. 76 is a view showing a combination of TFTs of each part of the LCD.

FIG. 77 is a diagram showing a combination of TFTs of each part of the LCD.

FIG. 78 is a view showing a combination of TFTs of each part of the LCD.

FIG. 79 is a schematic layout diagram of an LCD according to a twentieth embodiment of the present invention;

FIG. 80 is a diagram showing a combination of TFTs in each part of the LCD.

FIG. 81 is a schematic layout diagram of a device according to a twenty-first embodiment of the present invention.

FIG. 82 is a cross-sectional view of a main part of an EL and FED according to a twenty-second embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Glass (or quartz) substrate, 4 ... Step, 7 ... Single crystal silicon layer, 9 ... Mo.Ta layer, 11, 71 ... Gate electrode, 12 ... Gate oxide film, 14, 17 ... N-type impurity ion, 15 ... LDD portions, 18, 19 ... N ⁺ type source or drain regions, 21 ... P type impurity ions, 22, 23 ... P
⁺ Type source or drain region, 25, 36 ... insulating film, 2
6, 27, 31, 41: electrode, 28: flattening film, 28A
... Rough surface (irregularity), 29 ... Reflective film (or electrode), 30 ... L
CD (TFT) substrate, 33, 34: alignment film, 35: liquid crystal, 37, 46: color filter layer, 43: black mask layer, 50: crystalline sapphire film, 72: SiN film,
73 ... SiO ₂ film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuichi Sato 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Hajime Yagi 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F term (reference) 2H092 JA02 JA24 JA25 JA26 JA27 JA34 JA37 JB52 JB69 KA03 KA04 KA05 MA04 MA05 MA06 MA07 MA13 MA17 MA22 MA29 MA30 NA05 NA19 NA27 NA29 PA01 PA08 QA07 QA08 QA10 QA11 QA13 A11A AA18 AA30 BB02 BB04 CC02 CC08 DD01 DD03 DD04 DD07 DD13 DD14 DD17 DD21 DD24 EE04 EE06 EE23 EE28 EE30 EE43 EE44 FF02 FF03 FF09 FF24 FF29 FF30 NN02NN12 NN NN73 PP23 PP24 PP31 PP34 QQ09 QQ11 QQ19

Claims (92)

[Claims] 1. A display device comprising: a display portion on which a pixel electrode is disposed; and a peripheral driver circuit portion disposed around the display portion on a first substrate. A method of manufacturing an electro-optical device having a predetermined optical material interposed therebetween, wherein a step of forming a gate portion comprising a gate electrode and a gate insulating film on one surface of the first substrate; Forming a material layer having good lattice matching with single crystal silicon on the one surface of one substrate; and forming a polycrystalline or amorphous silicon layer on the first substrate including the material layer and the gate portion. After forming to a predetermined thickness, a low melting point metal layer is formed on or below the polycrystalline or amorphous silicon layer on the first substrate, or on the first substrate including the material layer. Step of forming low melting point metal layer containing silicon Dissolving the polycrystalline or amorphous silicon layer or the silicon in the low-melting metal layer by a heat treatment; and then cooling the silicon (or silicon) of the polycrystalline or amorphous silicon layer by a cooling treatment (preferably a gradual cooling treatment). A step of heteroepitaxially growing silicon of the low melting point metal layer using the material layer as a seed to deposit a single crystal silicon layer; and performing predetermined processing on the single crystal silicon layer to form a channel region, a source region, and a drain region. And a step of forming a bottom-gate first thin film transistor having the gate portion below the channel region and forming at least a part of the peripheral driver circuit portion. A method for manufacturing an optical device. 2. The polycrystalline or amorphous silicon layer is formed by a low-temperature deposition technique, and the low-melting metal layer is deposited on or below the polycrystalline or amorphous silicon layer, or the silicon-containing low-melting metal layer is deposited, The method for manufacturing an electro-optical device according to claim 1, wherein the heating process and the cooling process (preferably, a slow cooling process) are performed. 3. A glass substrate or a heat-resistant organic substrate is used as the first substrate, and the material layer is made of sapphire, spinel structure, calcium fluoride, strontium fluoride, barium fluoride, boron phosphide, yttrium oxide. And the low melting point metal layer is formed of at least one selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony and aluminum. A method for manufacturing the electro-optical device according to claim 1. 4. When the low melting point metal layer is formed of indium, the heat treatment is performed in a hydrogen-based atmosphere at 850-1.
When the low melting point metal layer is formed of indium gallium or gallium, the heat treatment is performed at 300 to 1100 ° C. or 400 to 110 in a hydrogen atmosphere.
The method for manufacturing an electro-optical device according to claim 3, wherein the method is performed at 0 ° C. 5. The electric device according to claim 1, wherein a diffusion barrier layer is formed on the first substrate, and the polycrystalline or amorphous silicon layer or the low melting point metal layer containing silicon is formed thereon. A method for manufacturing an optical device. 6. The method according to claim 6, wherein said polycrystalline or amorphous silicon layer or said silicon-containing low melting point metal layer is formed at a time.
The method of manufacturing an electro-optical device according to claim 1, wherein an impurity element and / or concentration of the single crystal silicon layer is controlled by mixing an impurity element belonging to Group 5 or Group 5. 7. The method of manufacturing an electro-optical device according to claim 1, wherein said gate portion under said single-crystal silicon layer has a trapezoidal shape at a side end thereof. 8. The method according to claim 1, wherein the peripheral drive circuit section includes the first drive circuit.
Top gate type, bottom gate type or dual gate type thin film transistor having a polycrystalline or amorphous silicon layer as a channel region and a gate portion above and / or below the channel region, or the single crystal silicon The method for manufacturing an electro-optical device according to claim 1, wherein a diode, a resistor, a capacitance, an inductance element, or the like using a layer, a polycrystalline silicon layer, or an amorphous silicon layer is provided. 9. The method of manufacturing an electro-optical device according to claim 1, wherein a switching element for switching the pixel electrode in the display unit is provided on the first substrate. 10. The first thin film transistor is at least a bottom gate type selected from a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region, and
The method of manufacturing an electro-optical device according to claim 9, wherein the top gate type, the bottom gate type, or the dual gate type second thin film transistor is formed as the switching element. 11. The method for manufacturing an electro-optical device according to claim 10, wherein a gate electrode provided below the channel region is formed of a heat-resistant material. 12. When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. 11. The manufacturing of the electro-optical device according to claim 10, wherein after forming the lower gate portion, the second thin film transistor is formed through a process common to the first thin film transistor including a process of forming the material layer. Method. 13. After forming the single-crystal silicon layer on the lower gate portion, introducing a Group 3 or 5 group impurity element into the single-crystal silicon layer to form source and drain regions, and then activating the single-crystal silicon layer. The method for manufacturing an electro-optical device according to claim 12, wherein the processing is performed. 14. After the formation of the single crystal silicon layer, each source and drain region of the second thin film transistor is formed by ion implantation of the impurity element using a resist as a mask, and the activation process is performed after the ion implantation. 14. The method according to claim 13, wherein an upper gate electrode of the second thin film transistor is formed after the formation of the gate insulating film. 15. When the second thin film transistor is a top gate type, after forming the single crystal silicon layer, each source and drain region of the first and second thin film transistors is ion-implanted using a resist as a mask. 11. The method according to claim 10, wherein an activation process is performed after the ion implantation, and then a gate portion including a gate insulating film and a gate electrode of the second thin film transistor is formed.
2. The method for manufacturing an electro-optical device according to item 1. 16. When the second thin film transistor is of a top gate type, a gate portion is formed by forming a gate insulating film of the second thin film transistor and a gate electrode made of a heat resistant material after forming the single crystal silicon layer. 11. The method according to claim 10, wherein the source and drain regions of the first and second thin film transistors are formed by ion implantation of an impurity element using the gate portion and the resist as a mask, and an activation process is performed after the ion implantation. A method for manufacturing an electro-optical device. 17. The method of manufacturing an electro-optical device according to claim 10, wherein an n-channel, p-channel, or complementary insulated gate field effect transistor is configured as the thin film transistor of the peripheral driver circuit unit and the display unit. 18. The thin film transistor of the peripheral drive circuit section is formed by a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. The method for manufacturing an electro-optical device according to claim 17, wherein 19. At least a part of the thin film transistor of the peripheral driver circuit section and / or the display section is formed by an LDD (Li
(ghtly doped drain) structure, and the LDD structure is a single type having an LDD portion between a gate and a source or a drain, or a double type having an LDD portion between a gate and a source and a drain. 10. The method for manufacturing an electro-optical device according to item 10. 20. The electro-optic device according to claim 19, wherein a resist mask used for forming the LDD structure is left, and ion implantation for forming a source region and a drain region is performed using a resist mask covering the resist mask. Device manufacturing method. 21. A single crystal, polycrystalline, or amorphous silicon layer is formed on one surface of the first substrate, and the single crystal, polycrystalline, or amorphous silicon layer is used as a channel region, a source region, and a drain region. The method for manufacturing an electro-optical device according to claim 17, wherein the second thin film transistor having a gate portion at an upper portion and / or a lower portion thereof is formed. 22. When the thin film transistor of the peripheral driver circuit portion is the first thin film transistor of an n-channel type, a p-channel type or a complementary type, and the thin film transistor of the display portion is a single-crystal silicon layer in a channel region, n Channel type, p channel type or complementary type,
3. An n-channel type, a p-channel type or a complementary type when a polycrystalline silicon layer is used as a channel region, and an n-channel type, a p-channel type or a complementary type when an amorphous silicon layer is used as a channel region.
2. The method for manufacturing an electro-optical device according to item 1. 23. forming a step on the first substrate, forming the material layer on the first substrate including the step,
2. The method according to claim 1, wherein the single crystal silicon layer is formed on the material layer. 24. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in a cross section, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal silicon layer. The method for manufacturing an electro-optical device according to claim 23, wherein 25. The electro-optical device according to claim 23, wherein the first thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Production method. 26. The method according to claim 23, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the first thin film transistor. . 27. The method according to claim 1, wherein a step is formed in the material layer, and the single crystal silicon layer is formed on the material layer including the step. 28. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in a cross section, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal silicon layer. The method for manufacturing an electro-optical device according to claim 27, wherein 29. The electro-optical device according to claim 27, wherein the first thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the first substrate and / or a film thereon. Production method. 30. The method of manufacturing an electro-optical device according to claim 27, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the first thin film transistor. . 31. A step is formed on the one surface of the first substrate, and a single crystal, polycrystalline or amorphous silicon layer is formed on the first substrate including the step, and the single crystal, 22. The electro-optical device according to claim 21, wherein the second thin film transistor having a gate portion above and / or below the channel region is formed by using a polycrystalline or amorphous silicon layer as a channel region, a source region, and a drain region. Production method. 32. The step is formed as a recess whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and the step is used as a seed during epitaxial growth of the single crystal silicon layer. 31. The method for manufacturing an electro-optical device according to item 31. 33. The method according to claim 31, wherein a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step. 34. The method according to claim 31, wherein the second thin film transistor is provided in and / or outside a substrate recess formed by the step formed in the first substrate and / or a film thereon. A method for manufacturing an electro-optical device. 35. The method of manufacturing an electro-optical device according to claim 31, wherein an impurity species of Group 3 or Group 5 and / or a concentration thereof is controlled in the single crystal, polycrystal or amorphous silicon layer. 36. The electro-optical device according to claim 31, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Manufacturing method. 37. The method of manufacturing an electro-optical device according to claim 31, wherein the gate electrode under the single crystal, polycrystal or amorphous silicon layer has a trapezoidal shape at a side end thereof. 38. The method of manufacturing an electro-optical device according to claim 37, wherein a diffusion barrier layer is provided between the first substrate and the single crystal, polycrystalline or amorphous silicon layer. 39. The method according to claim 1, wherein the first substrate is a glass substrate or a heat-resistant organic substrate. 40. The method according to claim 1, wherein the substrate is optically opaque or transparent. 41. The method of manufacturing an electro-optical device according to claim 1, wherein the pixel electrode is provided for a reflective or transmissive display unit. 42. The method of manufacturing an electro-optical device according to claim 1, wherein a laminated structure of the pixel electrode and a color filter layer is provided in the display unit. 43. When the pixel electrode is a reflective electrode, unevenness is formed on a resin film, and a pixel electrode is provided thereon.
2. The method according to claim 1, wherein when the pixel electrode is a transparent electrode, the surface is flattened by a transparent flattening film, and the pixel electrode is provided on the flattened surface. 44. The method of manufacturing an electro-optical device according to claim 9, wherein the display section is configured to emit light or modulate light by being driven by the switching element. 45. The method of manufacturing an electro-optical device according to claim 9, wherein a plurality of the pixel electrodes are arranged in a matrix on the display unit, and the switching element is connected to each of the pixel electrodes. 46. The method of manufacturing an electro-optical device according to claim 1, comprising a liquid crystal display device, an electroluminescence display device, a field emission display device, a light emitting polymer display device, a light emitting diode display device, or the like. 47. A method of manufacturing a drive substrate for an electro-optical device, comprising: a display portion on which a pixel electrode is disposed; and a peripheral drive circuit portion disposed around the display portion on the substrate. Forming a gate portion including a gate electrode and a gate insulating film on one surface; forming a material layer having good lattice matching with single crystal silicon on the one surface of the substrate; After forming a polycrystalline or amorphous silicon layer to a predetermined thickness on the substrate including a layer and the gate portion, a low melting point metal layer is formed on the substrate and on or below the polycrystalline or amorphous silicon layer. Or a step of forming a low-melting metal layer containing silicon on the substrate including the material layer; and heating the polycrystalline or amorphous silicon layer or the silicon with the low melting point by heat treatment. A step of dissolving the polycrystalline or amorphous silicon or the silicon of the low melting point metal layer by heteroepitaxial growth using the material layer as a seed by a step of dissolving the single crystal silicon layer in a metal layer; Depositing; performing a predetermined process on the single-crystal silicon layer to form a channel region, a source region, and a drain region; and having the gate portion below the channel region; Forming a first bottom-gate thin film transistor that forms at least a part of the driving substrate for the electro-optical device. 48. The polycrystalline or amorphous silicon layer is formed by a low-temperature deposition technique, and the low-melting metal layer is deposited on or below the polycrystalline or amorphous silicon layer, or the silicon-containing low-melting metal layer is deposited. The method for manufacturing a driving substrate for an electro-optical device according to claim 47, wherein the heating process and the cooling process (preferably, a slow cooling process) are performed. 49. A glass substrate or a heat-resistant organic substrate is used as the substrate, and the material layer is sapphire, spinel structure, calcium fluoride, strontium fluoride, barium fluoride, boron phosphide, yttrium oxide, and zirconium oxide. Formed of a substance selected from the group consisting of
48. The low melting point metal layer is formed of at least one selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony and aluminum.
3. A method for manufacturing a drive substrate for an electro-optical device according to claim 1. 50. When the low melting point metal layer is formed of indium, the heat treatment is performed in a hydrogen-based atmosphere at 850 to 850.
When the low melting point metal layer is formed of indium gallium or gallium, the heat treatment is performed at 300 to 1100 ° C. or 400 to 11 in a hydrogen atmosphere.
50. The method of manufacturing a drive substrate for an electro-optical device according to claim 49, wherein the method is performed at 00C. 51. A diffusion barrier layer is formed on the substrate,
48. The method of manufacturing a drive substrate for an electro-optical device according to claim 47, wherein the polycrystalline or amorphous silicon layer or the low-melting-point metal layer containing silicon is formed thereon. 52. When forming the polycrystalline or amorphous silicon layer or the silicon-containing low melting point metal layer,
48. The method of manufacturing a driving substrate for an electro-optical device according to claim 47, wherein an impurity element and / or concentration of the single crystal silicon layer is controlled by mixing an impurity element belonging to Group V or Group V. 53. The method of manufacturing a driving substrate for an electro-optical device according to claim 47, wherein the gate portion below the single-crystal silicon layer has a trapezoidal shape at a side end thereof. 54. In the peripheral driver circuit section, in addition to the first thin film transistor, a polycrystalline or amorphous silicon layer is used as a channel region, and a top gate type and a bottom portion having a gate portion above and / or below the channel region. 48. An electro-optical device according to claim 47, wherein a gate type or dual gate type thin film transistor, or a diode, a resistor, a capacitance, an inductance element, or the like using the single crystal silicon layer, the polycrystal silicon layer, or the amorphous silicon layer is provided. Method for manufacturing a drive substrate. 55. The method for manufacturing a driving substrate for an electro-optical device according to claim 47, wherein a switching element for switching the pixel electrode in the display unit is provided on the substrate. 56. The first thin film transistor is at least a bottom gate type selected from a top gate type, a bottom gate type, or a dual gate type having a gate portion above and / or below a channel region; and
The method for manufacturing a driving substrate for an electro-optical device according to claim 55, wherein the top gate type, the bottom gate type, or the dual gate type second thin film transistor is formed as the switching element. 57. The method of manufacturing a driving substrate for an electro-optical device according to claim 56, wherein a gate electrode provided below the channel region is formed of a heat-resistant material. 58. When the second thin film transistor is a bottom gate type or a dual gate type, a lower gate electrode made of a heat-resistant material is provided below the channel region, and a gate insulating film is formed on the gate electrode. 57. The electro-optical device according to claim 56, wherein after forming the lower gate portion, the second thin film transistor is formed through a process common to the first thin film transistor including a process of forming the material layer. A method for manufacturing a drive substrate. 59. After forming the single-crystal silicon layer on the lower gate portion, introducing a Group 3 or Group 5 impurity element into the single-crystal silicon layer to form a source and drain region, The method for manufacturing a drive substrate for an electro-optical device according to claim 58, wherein the processing is performed. 60. After the single crystal silicon layer is formed, each source and drain region of the second thin film transistor is formed by ion implantation of the impurity element using a resist as a mask, and the activation process is performed after the ion implantation. 60. The method according to claim 59, wherein an upper gate electrode of the second thin film transistor is formed after forming the gate insulating film. 61. When the second thin film transistor is a top gate type, each source and drain region of the first and second thin film transistors is ion-implanted with an impurity element using a resist as a mask after the formation of the single crystal silicon layer. 57. An activation process is performed after the ion implantation, and then a gate portion including a gate insulating film and a gate electrode of the second thin film transistor is formed.
3. A method for manufacturing a drive substrate for an electro-optical device according to claim 1. 62. When the second thin film transistor is a top gate type, a gate portion is formed by forming a gate insulating film of the second thin film transistor and a gate electrode made of a heat-resistant material after forming the single crystal silicon layer. 57. The method according to claim 56, wherein the source and drain regions of the first and second thin film transistors are formed by ion implantation of an impurity element using the gate portion and the resist as a mask, and an activation process is performed after the ion implantation. A method for manufacturing a drive substrate for an electro-optical device. 63. The driving substrate for an electro-optical device according to claim 56, wherein an n-channel, p-channel or complementary insulated gate field-effect transistor is formed as the thin film transistor of the peripheral driving circuit section and the display section. Manufacturing method. 64. The thin film transistor of the peripheral drive circuit portion is formed by a set of a complementary type and an n-channel type, a set of a complementary type and a p-channel type, or a set of a complementary type, an n-channel type and a p-channel type. 64. The method of manufacturing a drive substrate for an electro-optical device according to claim 63. 65. At least a part of the thin film transistor of the peripheral drive circuit section and / or the display section is formed by an LDD (Li
(ghtly doped drain) structure, and the LDD structure is a single type having an LDD portion between a gate and a source or a drain, or a double type having an LDD portion between a gate and a source and a drain. 56. The method for manufacturing a drive substrate for an electro-optical device according to 56. 66. The electro-optical device according to claim 65, wherein a resist mask used for forming the LDD structure is left, and ion implantation for forming a source region and a drain region is performed using a resist mask covering the resist mask. A method for manufacturing a drive substrate for an apparatus. 67. A single crystal, polycrystalline or amorphous silicon layer is formed on one surface of the substrate, and the single crystal,
A polycrystalline or amorphous silicon layer in the channel region,
64. The method of manufacturing a driving substrate for an electro-optical device according to claim 63, wherein the second thin film transistor is formed as a source region and a drain region and has a gate portion above and / or below the second thin film transistor. 68. When the thin film transistor of the peripheral driver circuit portion is the n-channel, p-channel or complementary first thin film transistor, and the thin film transistor of the display portion is a single crystal silicon layer as a channel region, n Channel type, p channel type or complementary type,
7. An n-channel type, a p-channel type or a complementary type when a polycrystalline silicon layer is used as a channel region, and an n-channel type, a p-channel type or a complementary type when an amorphous silicon layer is used as a channel region.
8. The method for manufacturing a drive substrate for an electro-optical device according to item 7. 69. The electric device according to claim 47, wherein a step is formed on the substrate, the material layer is formed on the substrate including the step, and the single-crystal silicon layer is formed on the material layer. A method for manufacturing a drive substrate for an optical device. 70. The step is formed as a concave portion whose side surface is at right angles to the bottom surface or inclined toward the lower end in the cross section, and the step forms a seed together with the material layer during epitaxial growth of the single crystal silicon layer. 70. The method for manufacturing a drive substrate for an electro-optical device according to claim 69, wherein: 71. The driving device for an electro-optical device according to claim 69, wherein the first thin film transistor is provided inside and / or outside a substrate recess formed by the step formed on the substrate and / or a film thereon. Substrate manufacturing method. 72. The drive for an electro-optical device according to claim 69, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the first thin film transistor. Substrate manufacturing method. 73. The method of manufacturing a driving substrate for an electro-optical device according to claim 47, wherein a step is formed in the material layer, and the single crystal silicon layer is formed on the material layer including the step. 74. The step is formed as a concave portion whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and the step is formed together with the material layer as a seed during epitaxial growth of the single crystal silicon layer. 74. The method of manufacturing a drive substrate for an electro-optical device according to claim 73. 75. The electro-optical device according to claim 73, wherein the first thin film transistor is provided inside and / or outside the substrate recess due to the step formed on the first substrate and / or a film thereon. Method for manufacturing a drive substrate. 76. The driving device for an electro-optical device according to claim 73, wherein the step is formed along at least one side of an element region formed by a channel region, a source region, and a drain region of the first thin film transistor. Substrate manufacturing method. 77. A step is formed on the one surface of the substrate, and a single crystal, polycrystal or amorphous silicon layer is formed on the substrate including the step, and the single crystal, polycrystal or amorphous silicon layer is formed. 70. The method of manufacturing a driving substrate for an electro-optical device according to claim 67, wherein the second thin film transistor having a gate portion above and / or below the channel region is formed as a channel region, a source region, and a drain region. . 78. The step is formed as a concave part whose side surface is perpendicular to the bottom surface or inclined toward the lower end in the cross section, and the step is used as a seed during epitaxial growth of the single crystal silicon layer. 77. The method for manufacturing a drive substrate for an electro-optical device according to 77. 79. The method according to claim 77, wherein a source or drain electrode of the first and / or second thin film transistor is formed on a region including the step. 80. The method according to claim 77, wherein the second thin film transistor is provided inside and / or outside a concave portion of the substrate formed by the step formed on the first substrate and / or a film thereon. A method for manufacturing a drive substrate for an electro-optical device. 81. The method of manufacturing a driving substrate for an electro-optical device according to claim 77, wherein the impurity species of Group 3 or Group 5 and / or the concentration of the single crystal, polycrystalline or amorphous silicon layer is controlled. 82. The electro-optical device according to claim 77, wherein the step is formed along at least one side of an element region formed by the channel region, the source region, and the drain region of the second thin film transistor. Of manufacturing a driving substrate for a semiconductor device. 83. The method of manufacturing a driving substrate for an electro-optical device according to claim 77, wherein the gate electrode under the single-crystal, polycrystalline or amorphous silicon layer has a trapezoidal shape at a side end thereof. 84. providing a diffusion barrier layer between said substrate and said single crystal, polycrystalline or amorphous silicon layer;
A method for manufacturing a drive substrate for an electro-optical device according to claim 77. 85. The method of manufacturing a driving substrate for an electro-optical device according to claim 47, wherein the substrate is a glass substrate or a heat-resistant organic substrate. 86. The method according to claim 47, wherein the substrate is optically opaque or transparent. 87. The method according to claim 47, wherein the pixel electrode is provided for a reflective or transmissive display unit. 88. The method for manufacturing a driving substrate for an electro-optical device according to claim 47, wherein a laminated structure of the pixel electrode and a color filter layer is provided in the display unit. 89. When the pixel electrode is a reflective electrode, unevenness is formed on the resin film, and the pixel electrode is provided thereon.
48. The method according to claim 47, wherein when the pixel electrode is a transparent electrode, the surface is flattened by a transparent flattening film, and the pixel electrode is provided on the flattened surface. . 90. The method of manufacturing a driving substrate for an electro-optical device according to claim 55, wherein the display section is configured to emit light or adjust light by driving the switching element. 91. The manufacturing of the driving substrate for an electro-optical device according to claim 55, wherein a plurality of the pixel electrodes are arranged in a matrix on the display section, and the switching element is connected to each of the pixel electrodes. Method. 92. The driving substrate for an electro-optical device according to claim 47, which is configured for a liquid crystal display device, an electroluminescence display device, a field emission display device, a light emitting polymer display device, a light emitting diode display device, or the like. Production method.