JP6612520B2 - Dot matrix display device - Google Patents

Description

  The present invention relates to a dot matrix display device in which a large number of pixel electrode portions including thin film transistor (TFT) elements are formed on a substrate.

Conventionally, for example, a liquid crystal display (LCD) has a TFT array side substrate on which a large number of pixel electrode portions including TFT elements are formed and a color filter side substrate on which a color filter and a black matrix are formed. Then, the substrates are bonded together at a predetermined interval, and liquid crystal is filled and sealed between the substrates.

An example of a basic configuration of a conventional active matrix liquid crystal display device is shown in FIG. For example, the TFT array side substrate has a plurality of gate signal lines G1, G2, G3,... Gm formed in a first direction (row direction) thereon and a second crossing the first direction. A plurality of image signal lines S1, S2, S3,... Sn formed to intersect the gate signal line in the direction (column direction), and formed at the intersection of the gate signal line and the image signal line, TFT electrode 101, pixel electrode portions P11, P12, P13 including pixel electrodes (not shown)
... Pmn. Further, a common electrode (also referred to as a reference electrode; not shown) and a common voltage line 102 that supplies a common voltage (Vcom) to the common electrode generate a vertical electric field applied to the liquid crystal between the pixel electrode. In order to form, it is provided on the color filter side substrate. In FIG. 12, 103 is a gate signal driving circuit, 104 is an image signal (source signal) driving circuit, 110 is a display unit, and 111 is a liquid crystal display panel.

  The TFT element 101 includes a semiconductor film made of, for example, amorphous silicon (a-Si), and has a three-terminal portion including a gate electrode portion, a source electrode portion, and a drain electrode portion. Then, a switching element (gate transfer element) that causes a current to flow in the semiconductor film (channel) between the source electrode part and the drain electrode part by applying a voltage of a predetermined potential (for example, 3V, 6V) to the gate electrode part. Function as. The pixel electrode is generally composed of a transparent conductor layer made of indium tin oxide (ITO) or the like.

In addition, the color filter side substrate has a red (R), green (G), and blue (B) color filter corresponding to each pixel on the surface on which the common electrode and the common voltage line are formed or on the opposite surface. And a black matrix that prevents light passing through each pixel from interfering with each other is formed so as to surround the outer periphery of the color filter. Note that the color filter and the black matrix may be omitted if color display is not performed. In the case of a transmissive LCD, a backlight is provided, and in the case of a reflective LCD, there is no need for a backlight.

In such an LCD, in order to reduce power consumption of external circuits, signal line drive circuits, etc. when displaying still images, each pixel has a storage circuit such as a static random access memory (SRAM) and a D circuit. A configuration having a / A (Digital / Analog) conversion circuit has been proposed (see, for example, Patent Documents 1 and 2 below). In other words, an SRAM (inverted logic circuit) such as a CMOS (Complementary Metal Oxide Semiconductor) inverter connected in a loop and a digital signal of n bits (n is a natural number) can be displayed in grayscale. D / A converter circuit that converts the signal into a simple analog signal.During the still image display period, DAC (Digital
to Analog Converter) Drives only the controller, repeatedly reads the digital video signal stored in the memory circuit, performs D / A conversion to obtain the analog signal gradation signal, and uses the analog signal gradation signal to convert the still image Display. Then, the source signal line driver circuit and the gate signal line driver circuit are stopped when a still image is displayed. With this configuration, power consumption of an external circuit, a signal line driver circuit, and the like when displaying a still image can be reduced.

An SRAM as a storage circuit used in the conventional LCD or the like is configured by connecting two CMOS inverters each having a p-channel TFT element and an n-channel TFT element connected in common in a loop. Yes. FIG. 13 shows an example of a pixel electrode portion including an SRAM proposed by the inventor of the present application, which can select either still image driving or rewriting driving (Japanese Patent Application No. 2013-223838). FIG. 13A is a block circuit diagram of a pixel electrode unit including a drive selection circuit 164 having a holding circuit 162 and a pixel electrode control circuit 163, and FIG. 13B is a detailed view of TFT element groups constituting each block circuit. It is a circuit diagram. The drive selection circuit 164 is a circuit that selects either still image drive or rewrite drive, and includes a holding circuit 162 and a pixel electrode control circuit 163.

The input unit 161 in the previous stage of the drive selection circuit 164 has a first n-channel TFT element 161a and a second n-channel TFT 161a.
A transfer gate circuit formed by connecting channel TFT elements 161b in series is provided. In the first n-channel TFT element 161a on the image signal line DL137 side, a signal transmitted through the image signal line selection line SLn138 is controlled and input to the gate electrode portion. When the signal is H (6V), the first n-channel TFT element 161a is turned on, and when the signal is L (0V), the first n-channel TFT element 161a is turned off. In the second n-channel TFT element 161b on the gate signal line GLn side, a signal transmitted through the gate signal line GLn139 is controlled and input to the gate electrode portion. When the signal is H (6V), the second n-channel TFT element 161b is turned on, and when the signal is L (0V), the second n-channel TFT element 161b is turned off. Therefore, only when the signal transmitted through the gate signal line GLn139 is H and the signal transmitted through the image signal line selection line SLn138 is H, the transfer gate circuit is closed in an equivalent circuit (closed). Then, the signal transmitted through the image signal line DL137 is transmitted to the holding circuit 162.

The holding circuit 162 is an SRAM formed by connecting a first CMOS inverter 162a and a second CMOS inverter 162b in a loop. The holding circuit 162 connects the first CMOS inverter 162a and the second CMOS inverter 162b in series, and outputs the output from the common drain connection point of the second CMOS inverter 162b to the common gate of the first CMOS inverter 162a. Feedback input to the connection point. Thus, for example, when an H signal is input to the common gate connection point of the first CMOS inverter 162a, an L signal is then output from the common drain connection point of the first CMOS inverter 162a. Is input to the gate common connection point of the second CMOS inverter 162b, and then the H signal is output from the drain common connection point of the second CMOS inverter 162b, and then the H signal is the first CMOS inverter. The feedback is input to the common gate connection point of the inverter 162a. As a result, H (3 V), L (0 V), and H signals are always held on the loop transmission line. That is, the holding circuit 162 functions as a memory circuit. Of course, L, H, and L signals can be held on a loop-shaped transmission line.

The pixel electrode control circuit 163 shares the first CMOS inverter 162a of the holding circuit 162, and includes a first CMOS inverter 162a that outputs an inverted signal (iB) of the image signal data (B), a p-channel TFT element, and the like. It consists of an n-channel TFT element, and a common voltage Vcom (A) and image signal data (
B) and a first binary selection circuit 181 that outputs binary data by reference input of the output (iB) of the first CMOS inverter 162a, a p-channel TFT element, and an n-channel TFT element. The common voltage Vcom (A), the image signal data (B), and the output (iB) of the first CMOS inverter 162a are input by reference, and output binary data. The output line is the first binary selection circuit 181. And a second binary selection circuit 182 connected in parallel to the output line. The output of the first binary selection circuit 181 and the output of the second binary selection circuit 182 are the exclusive OR (EXOR) of the common voltage Vcom (A) and the image signal data (B). A logic gate circuit is configured.

Japanese Patent Laid-Open No. 2002-162947 JP 2002-196306 JP

However, the LCDs disclosed in Patent Documents 1 and 2 switch between a normal operation mode (analog operation mode) for displaying moving images and a digital display mode (memory operation mode) for displaying still images. Although the configuration is described, there is no disclosure regarding the point of performing display with a combination of still image display and moving image display with lower power consumption.

Further, the pixel electrode portion of FIG. 13 has the following problems. As shown in FIG. 13B, when the holding circuit 162 holds L, H, and L signals, a white still image display is held as long as it is normally white. When this is rewritten into black display, an H (6 V) signal is input from the image signal line selection line SLn138 to the gate electrode portion of the first n-channel TFT element 161a of the input portion 161, and the second n-channel TFT. By inputting a H (6 V) signal from the gate signal line GLn139 to the gate electrode portion of the element 161b, the first and second n-channel TFT elements 161a and 161b are turned on. Next, an H (3 V) signal from the image signal line DLn137 is input to the source electrode portion of the first n-channel TFT element 161a, output from the drain electrode portion of the second n-channel TFT element 161b, and the holding circuit 162. To perform rewrite driving. At this time, since the n-channel TFT element 162bn of the second CMOS inverter 162b of the holding circuit 162 is on, a current path 190 indicated by a broken line is generated.

Then, the H (3 V) signal input from the image signal line DLn137 to the input unit 161 is the first signal.
The n-channel TFT element 161a is divided by the on-resistance Ro1 of the second n-channel TFT element 161b, the on-resistance Ro2 of the second n-channel TFT element 161b, and the on-resistance Ro3 of the n-channel TFT element 162bn. The output voltage V161bo from the drain electrode portion is the first CMOS inverter 162a.
The threshold voltage (about 1.5V) of the n-channel TFT element 162an may be equal to or lower than that. In that case, it takes a long time to turn on the n-channel TFT element 162an or a situation in which it cannot be turned on easily occurs. As a result, there are problems that it takes time for the rewrite drive or the rewrite drive cannot be executed.

On the other hand, when the holding circuit 162 holds signals of H, L, and H, when normally white, a black still image display is held, and when rewrite driving is performed, the image signal line A signal of L (0 V) is input from the DLn 137 to the input unit 161, but in this case, the above-described problem hardly occurs. That is, the gate voltage (6V) applied to the gate electrode portion of the first n-channel TFT element 161a and the input voltage V161ai (
0V) is as large as 6V, the on-resistance of the first n-channel TFT element 161a is substantially reduced. Similarly, the on-resistance of the second n-channel TFT element 161b is substantially reduced. As a result, the rise of V161bo is suppressed and becomes a potential close to 0V, the p-channel TFT element 162ap of the first CMOS inverter 162a is easily switched on, and the rewrite drive is executed reliably.

  Accordingly, the present invention has been completed in view of the above-described conventional problems, and its purpose is to enable display with a combination of still image display and moving image display to be performed with extremely low power consumption. It is to be able to execute the rewriting drive reliably and quickly.

The dot matrix type display device of the present invention includes a plurality of gate signal lines formed in a predetermined direction on a substrate and a plurality of images formed by crossing the gate signal lines in a direction crossing the predetermined direction. A pixel electrode unit including a signal selection line and an image signal line selection line parallel to the signal line, and a drive selection circuit that is formed at an intersection of the gate signal line and the image signal line and selects either rewrite driving or still image driving A gate signal line driving circuit that arbitrarily selects and turns on one of the plurality of gate signal lines, and an image signal line driving circuit that arbitrarily turns on and turns on one of the plurality of image signal lines A dot matrix type display device comprising:
The pixel electrode unit includes a first n-channel thin film transistor element turned on by the image signal line selection line and a second n-channel thin film transistor element turned on by the gate signal line in series before the drive selection circuit. An image signal input unit connected to
The drive selection circuit includes: a pixel electrode control circuit that rewrites the selected pixel electrode portion at the intersection of the on-state gate signal line and the on-state image signal line selection line with the image signal; and the input A holding circuit that holds the image signal input from the unit and drives the non-selected pixel electrode unit as a still image, and
The holding circuit is a static memory in which a first CMOS inverter to which the image signal is input and a second CMOS inverter connected thereto are connected in a loop shape,
In the second CMOS inverter, the third on-resistance of the third n-channel thin film transistor element constituting the second CMOS inverter is the same as the first on-resistance of the first n-channel thin film transistor element and the second n-channel thin film transistor element. greater than the sum of the second on-resistance, Ri said first on-resistance and a second on-resistance equal der,
In the image signal line, a fourth n-channel thin film transistor element that is turned on by the image signal line selection line is connected in series to an input end of the image signal, and the third on-resistance is connected to the first signal line. The on-resistance, the second on-resistance, and the fourth on-resistance of the fourth n-channel thin film transistor element are larger than the sum .

  In the dot matrix display device of the present invention, preferably, the fourth on-resistance is the smallest among the first on-resistance, the second on-resistance, and the fourth on-resistance.

  In the dot matrix type display device of the present invention, preferably, a gate voltage transmitted through the image signal line selection line and inputted to a gate electrode portion of the first n-channel thin film transistor element, and a peak voltage of the image signal Is larger than the peak voltage of the image signal.

The dot matrix type display device of the present invention includes a plurality of gate signal lines formed in a predetermined direction on a substrate and a plurality of image signal lines formed so as to cross the gate signal lines in a direction crossing the predetermined direction. And a plurality of pixel electrode portions including a drive selection circuit for selecting either rewrite driving or still image driving, which is formed at the intersection of the gate signal line and the image signal line, and an image signal line selection line in parallel therewith. A dot matrix having a gate signal line driving circuit for arbitrarily selecting one of the gate signal lines to be turned on, and an image signal line driving circuit for arbitrarily selecting one of the plurality of image signal lines to be turned on Type display device,
The pixel electrode unit includes a first n that is turned on by the image signal line selection line before the drive selection circuit.
An image signal input unit formed by connecting a channel thin film transistor element and a second n-channel thin film transistor element turned on by a gate signal line in series;
The drive selection circuit includes a pixel electrode control circuit that rewrites a selected pixel electrode portion at an intersection of an on-state gate signal line and an on-state image signal line selection line with an image signal, and an image input from an input portion A holding circuit that holds a signal and drives a non-selected pixel electrode portion as a still image,
The holding circuit is a static memory in which a first CMOS inverter to which an image signal is input and a second CMOS inverter connected thereto are connected in a loop shape,
In the second CMOS inverter, the third on-resistance of the third n-channel thin film transistor element constituting the second CMOS inverter is equal to the first on-resistance of the first n-channel thin film transistor element and the second on-resistance of the second n-channel thin film transistor element. greater than the sum of the oN resistance, the first on-resistance and a second on-resistance Ri equal der,
In the image signal line, a fourth n-channel thin film transistor element that is turned on by the image signal line selection line is connected in series to the input end of the image signal, and the third on-resistance is the first on-resistance and the second on-resistance. And the fourth on-resistance of the fourth n-channel thin film transistor element . With this configuration, the gate signal line and the image signal line are turned off in the pixel electrode portion that is driven for still image, and the gate signal line and the image signal line are selectively turned on only in the pixel electrode portion that is driven for rewriting. Power consumption can be kept extremely low. In addition, since the third on-resistance is larger than the sum of the first on-resistance and the second on-resistance, the pixel electrode portion held in the low (L) state is displayed by the high (H) image signal. When rewriting, the output voltage of the drain electrode portion of the second n-channel thin film transistor element increases, and as a result, the rewriting drive can be executed reliably and quickly. In addition, the image signal line has a fourth n-channel thin film transistor element that is turned on by the image signal line selection line connected in series to the input end of the image signal, and the third on-resistance is the first on-resistance. Since it is larger than the sum of the second on-resistance and the fourth on-resistance of the fourth n-channel thin film transistor element, the pixel electrode portion held in the low (L) state is caused by the high (H) image signal. When rewriting, the output voltage of the drain electrode portion of the second n-channel thin film transistor element becomes high, and as a result, the rewriting drive can be executed more reliably and quickly.

  In the dot matrix display device of the present invention, when the fourth on-resistance is the lowest among the first on-resistance, the second on-resistance, and the fourth on-resistance, the potential of the high (H) image signal is reduced. It is advantageous to suppress the decrease. Further, since the first n-channel thin film transistor element and the second n-channel thin film transistor element are in a limited space in the pixel electrode portion, the fourth n-channel thin film transistor element is less flexible in design. Since the degree of freedom in design is high, the fourth on-resistance control is most easily performed. This makes it easy to increase the output voltage of the drain electrode portion of the second n-channel thin film transistor element when the pixel electrode portion held in the low (L) state is rewritten with a high (H) image signal. It will be something that can be done.

  In the dot matrix type display device of the present invention, the voltage difference between the gate voltage transmitted through the image signal line selection line and inputted to the gate electrode portion of the first n-channel thin film transistor element and the peak voltage of the image signal is When the voltage is higher than the peak voltage of the signal, the on-resistance of the first n-channel thin film transistor element becomes smaller. As a result, when the pixel electrode portion held in the low (L) state is rewritten with the high (H) image signal, the output voltage of the drain electrode portion of the second n-channel thin film transistor element becomes high, and as a result Rewriting drive can be executed more reliably and more quickly.

FIG. 1 is a diagram showing an example of an embodiment of a dot matrix type display device of the present invention, and is a block circuit diagram of a basic configuration of the dot matrix type display device. FIGS. 2A and 2B are diagrams showing an example of an embodiment of the dot matrix display device of the present invention. FIG. 2A includes a drive selection circuit having a holding circuit and a pixel electrode control circuit. A block circuit diagram of the pixel electrode portion, (b) is a detailed circuit diagram taking into account the connection relationship of the TFT element group constituting each block circuit of (a). FIG. 3 is a circuit diagram showing a detailed configuration of the gate signal line driving circuit in the dot matrix type display device of the present invention. FIG. 4 is a circuit diagram showing a detailed configuration of the image signal line driving circuit in the dot matrix type display device of the present invention. 5A is a block circuit diagram of a drive circuit unit for turning on and off one gate signal line in the gate signal line drive circuit in the dot matrix display device of the present invention, and FIG. 5B is a detail of FIG. FIG. 6A is a block circuit diagram of a drive circuit unit for turning on and off one image signal line in the image signal line drive circuit in the dot matrix display device of the present invention, and FIG. 6B is a detail of FIG. FIG. FIG. 7 is a block circuit diagram showing one embodiment of a pixel electrode portion including a drive selection circuit having a holding circuit and a pixel electrode control circuit in the dot matrix display device of the present invention. FIG. 8 is a detailed circuit diagram taking into account the connection relation of the TFT element groups constituting each block circuit of FIG. FIG. 9 is a detailed circuit diagram depicting the connection relationship of the TFT element groups constituting the pixel electrode control circuit in the dot matrix display device of the present invention. FIG. 10 shows an output of an exclusive OR logic gate circuit that uses a common voltage Vcom (A) and an image signal data (B) as binary inputs for the pixel electrode control circuit in the dot matrix type display device of the present invention. It is a truth table describing Y). FIG. 11 is a plan view of a display panel of a digital display wristwatch to which the dot matrix display device of the present invention is applied. FIG. 12 is a block circuit diagram showing a basic configuration of a conventional dot matrix display device. FIGS. 13A and 13B are diagrams showing an example of a dot matrix display device related to the present invention. FIG. 13A is a pixel electrode including a drive selection circuit having a holding circuit and a pixel electrode control circuit. FIG. 5B is a detailed circuit diagram in which the connection relationship of the TFT element groups constituting each block circuit of FIG.

  Hereinafter, embodiments of a dot matrix display device of the present invention will be described with reference to the drawings. However, the drawings referred to below show the main members necessary for explaining the configuration of the present invention among the components of the dot matrix display device of the present invention. Therefore, the dot matrix display device according to the present invention may include well-known components such as wiring conductors, circuit boards, control ICs, and control LSIs that are not shown in the drawings.

An embodiment of a dot matrix type display device of the present invention will be described with reference to FIGS. The dot matrix display device of the present invention includes a plurality of gate signal lines GL1 to GL128 formed in a predetermined direction (for example, row direction) on a substrate such as a glass substrate, and a direction (for example, a column) intersecting the predetermined direction. Direction) and a plurality of image signal lines DL1 to DL128 formed to intersect with the gate signal lines GL1 to GL128, the image signal line selection lines SL1 to SL128 parallel thereto, the gate signal lines GL1 to GL128, and the image signal lines DL1. Pixel electrodes P11 to Pmn that include a drive selection circuit that selects either rewrite drive or still image drive, and one of the multiple gate signal lines GL1 to GL128, formed at the intersection of DL128 Gate signal line driving circuit 3 to be selectively turned on and a plurality of image signal lines DL1
Image signal line driving circuit 4 that arbitrarily selects one of DL128 and turns it on, and a pixel electrode unit has an image signal line selection line in front of the drive selection circuit 64
It has an image signal input section 61 formed by connecting in series a first n-channel TFT element 61a turned on by SL1 to SL128 and a second n-channel TFT element 61b turned on by gate signal lines GL1 to GL128. The drive selection circuit 64 rewrites the selected pixel electrode portion at the intersection of the on-state gate signal line GLn (on) and the on-state image signal line selection lines SL1 to SL128 (on) with the image signal. A pixel electrode control circuit 63; and a holding circuit 62 that holds an image signal input from the input unit 61 and drives a non-selected pixel electrode unit as a still image. This is a static memory formed by connecting a first CMOS inverter 62a inputted thereto and a second CMOS inverter 62b connected thereto in a loop, and the second CMOS inverter 62b is a third memory constituting the third CMOS inverter 62b. N-channel TFT element 62bn third on Anti is larger configuration than the sum of the second on-resistance of the first on-resistance and the second n-channel TFT element 61b of the first n-channel TFT element 61a. With this configuration, the gate signal line and the image signal line are turned off in the pixel electrode portion that is driven for still image, and the gate signal line GLn and the image signal line DLn are selectively turned on only in the pixel electrode portion that is driven for rewriting. Therefore, power consumption can be kept extremely low. In addition, since the third on-resistance is larger than the sum of the first on-resistance and the second on-resistance, the pixel electrode portion held in the low (L) state is displayed by the high (H) image signal. When rewriting, the output voltage of the drain electrode portion of the second n-channel TFT element becomes high, and as a result, the rewriting drive can be executed reliably and quickly. Note that the holding circuit 62 is a static memory configured by connecting two CMOS inverters that are inversion logic circuits in which an n-channel TFT element and a p-channel TFT element are connected in common to each other and connecting them in series and in a loop. (SRAM).

2A and 2B are diagrams showing an example of an embodiment of the dot matrix display device of the present invention. FIG. 2A is a drive selection circuit having a holding circuit 62 and a pixel electrode control circuit 63. FIG. The block circuit diagram of the pixel electrode part including 64, (b) is a detailed circuit diagram taking into account the connection relationship of the TFT element group constituting each block circuit of (a). The drive selection circuit 64 is a circuit that selects either still image drive or rewrite drive, and includes a holding circuit 62 and a pixel electrode control circuit 63.

A transfer gate circuit formed by connecting a first n-channel TFT element 61a and a second n-channel TFT element 61b in series is provided in the input section 61 in the previous stage of the drive selection circuit 64. In the first n-channel TFT element 61a on the image signal line DLn37 side, the signal transmitted through the image signal line selection line SLn38 is controlled and input to the gate electrode portion. When the signal is H (6V), the first n-channel TFT element 61a is turned on. When the signal is L (0V), the first n-channel TFT 61a is turned on.
The element 61a is turned off. In the second n-channel TFT element 61b on the gate signal line GLn39 side, a signal transmitted through the gate signal line GLn39 is controlled and input to the gate electrode portion. The signal is H
In the case of (6V), the second n-channel TFT element 61b is turned on, and in the case of L (0V), the second n-channel TFT element 61b is turned off. Therefore, only when the signal transmitted through the gate signal line GLn39 is H and the signal transmitted through the image signal line selection line SLn38 is H, the transfer gate circuit is closed in an equivalent circuit (closed). The image signal line DLn37
Is transmitted to the holding circuit 62.

The holding circuit 62 is an SRAM formed by connecting a first CMOS inverter 62a and a second CMOS inverter 62b in a loop. The holding circuit 62 connects the first CMOS inverter 62a and the second CMOS inverter 62b in series, and outputs the output from the common drain connection point of the second CMOS inverter 62b to the common gate of the first CMOS inverter 62a. Feedback input to the connection point. Thus, for example, when an H signal is input to the gate common connection point of the first CMOS inverter 62a, an L signal is then output from the drain common connection point of the first CMOS inverter 62a. Is input to the gate common connection point of the second CMOS inverter 62b, and then the H signal is output from the drain common connection point of the second CMOS inverter 62b, and then the H signal is the first CMOS inverter.
The feedback is input to the common gate connection point of the inverter 62a. As a result, always H (3V), L (
0V), H signals are held on the loop transmission line. That is, the holding circuit 62 functions as a memory circuit. Of course, L, H, and L signals can be held on a loop-shaped transmission line.

The pixel electrode control circuit 63 shares the first CMOS inverter 62a of the holding circuit 62, and includes a first CMOS inverter 62a that outputs an inverted signal (iB) of the image signal data (B), a p-channel TFT element, and the like. It consists of an n-channel TFT element, and a common voltage Vcom (A) and an image signal data (B
) And the output (iB) of the first CMOS inverter 62a are referred to and input, a first binary selection circuit 81 that outputs binary data, a p-channel TFT element and an n-channel TFT element, The binary data is output by the reference input of the voltage Vcom (A), the image signal data (B), and the output (iB) of the first CMOS inverter 62a. The output line of the first binary selection circuit 81 And a second binary selection circuit 82 connected in parallel to the output line. The output of the first binary selection circuit 81 and the output of the second binary selection circuit 82 are the exclusive OR (EXOR) of the common voltage Vcom (A) and the image signal data (B). A logic gate circuit is configured.

As shown in FIG. 2B, when the holding circuit 62 holds L, H, and L signals, a white still image display is held as long as it is normally white. When this is rewritten into black display, an H (6 V) signal is input from the image signal line selection line SLn38 to the gate electrode portion of the first n-channel TFT element 61a of the input portion 61, and the second n-channel TFT. By inputting a H (6 V) signal from the gate signal line GLn39 to the gate electrode portion of the element 61b, the first and second n-channel TFT elements 61a and 61b are turned on. Next, the image signal lines DLn37 to H
A signal of (3V) is input to the source electrode portion of the first n-channel TFT element 61a, is output from the drain electrode portion of the second n-channel TFT element 61b, is input to the holding circuit 62, and rewrite driving is performed. . At this time, since the n-channel TFT element 62bn of the second CMOS inverter 62b of the holding circuit 62 is in the ON state, a current path 90 indicated by a broken line is generated.

Then, the H (3 V) signal input from the image signal line DLn37 to the input unit 61 is the first on-resistance Ro1 of the first n-channel TFT element 61a and the second of the second n-channel TFT element 61b.
Is divided by the third on-resistance Ro2 of the third n-channel TFT element 62bn. In the dot matrix display device of the present invention, the third on-resistance Ro3 is larger than the sum of the first on-resistance Ro1 and the second on-resistance Ro2. As a result, the output voltage V161bo from the drain electrode portion of the second n-channel TFT element 61b becomes larger than the threshold voltage (about 1.5 V) of the n-channel TFT element 62an of the first CMOS inverter 62a. Driving can be performed reliably and quickly.

On the other hand, when the holding circuit 62 holds signals of H, L, and H, when normally white, a black still image display is held, and when rewrite driving is performed, an image signal line is used. An L (0 V) signal is input from the DLn 37 to the input unit 61. In this case, the potential difference between the gate voltage (6V) applied to the gate electrode portion of the first n-channel TFT element 61a and the input voltage V161ai (0V) of the source electrode portion of the first n-channel TFT element 61a is 6V. Therefore, the on-resistance of the first n-channel TFT element 61a is substantially reduced. That is, the first n-channel TFT
This is because the rise in the gate voltage-drain current (Vgs-Ids) characteristic curve of the element 61a becomes steeper, which means that the on-resistance becomes smaller. Similarly, the on-resistance of the second n-channel TFT element 61b is substantially reduced. As a result, the rise of V61bo is suppressed,
The potential is close to 0 V, and the p-channel TFT element 62ap of the first CMOS inverter 62a is easily switched on, so that the rewriting drive is reliably performed.

In the present invention, Ro3> Ro1 + Ro2, but (Ro1 + Ro2) / Ro3 is preferably 0.1 to 0.9. If it is less than 0.1, the width (W) of the channel of the first n-channel TFT element 61a and the second n-channel TFT element 61b is increased or the length (L) is shortened in order to reduce Ro1 and Ro2. However, it tends to be difficult due to space limitations of the pixel electrode portion. Above 0.9,
There exists a tendency for the effect of the said invention to become difficult to express. More preferably, it is 0.1 to 0.5.

  Ro1 and Ro2 are the same. Thereby, the channel width (W) and length (L) of the first n-channel TFT element 61a and the second n-channel TFT element 61b can be made the same, and the element design becomes easy.

  Note that Ro1, Ro2, and Ro3 are adjusted by adjusting the width (W) and length of the first n-channel TFT element 61a, the second n-channel TFT element 61b, and the third n-channel TFT element 62bn. This can be done by adjusting (L) and adjusting the magnitude of the gate voltage applied to these gate electrode portions.

In the dot matrix type display device of the present invention, the image signal line DLn37 has a fourth n-channel TFT element (indicated by reference numeral 35 in FIG. 4) which is turned on by the image signal line selection line SLn38 at the input end of the image signal. are connected in series, the third on-resistance Ro3 is greater than the sum of the fourth on-resistance Ro4 the first oN resistance Ro2 and a second on-resistance R02 fourth n-channel TFT element 35. This Reniyo
Ri, when rewriting the image signal of a low (L) state high pixel electrode portion held in the (H), the output voltage V61bo the drain electrode of the second n-channel TFT element 61b is increased, the The result rewriting drive can be executed more reliably and more quickly.

In this case, Ro3> Ro1 + Ro2 + Ro4, but (Ro1 + Ro2 + Ro4) / Ro3 is preferably 0.1 to 0.9. If less than 0.1, the channel width (W) of the first n-channel TFT element 61a, the second n-channel TFT element 61b, and the fourth n-channel TFT element 35 is increased in order to reduce Ro1, Ro2, and Ro4. In other words, the adjustment to shorten the length (L) tends to be difficult due to the space limitation of the pixel electrode portion and the space around the display portion 10. If it exceeds 0.9, the effect of the present invention tends to be hardly exhibited. More preferably, it is 0.1 to 0.5.

In the dot matrix type display device of the present invention, it is preferable that the fourth on-resistance Ro4 is the smallest among the first on-resistance Ro1, the second on-resistance Ro2, and the fourth on-resistance Ro4. In this case, a decrease in the potential of the high (H) image signal can be suppressed at the input end of the image signal line DLn37, which is advantageous in suppressing a decrease in the potential of the high (H) image signal. Further, since the first n-channel TFT element 61a and the second n-channel TFT element 61b are in a limited space in the pixel electrode portion, the fourth n-channel TFT has a small degree of design freedom. Since the TFT element 35 has a high degree of design freedom, the control of the fourth on-resistance Ro4 is most easily performed. Thus, when the pixel electrode portion held in the low (L) state is rewritten with the high (H) image signal, the output voltage V61bo of the drain electrode portion of the second n-channel TFT element 61b is increased. Can be easily performed.

In addition, the dot matrix type display device of the present invention transmits the image signal line selection line SLn38 and the gate voltage (for example, more than 6V) input to the gate electrode portion of the first n-channel TFT element 61a and the peak voltage of the image signal. It is preferable that the voltage difference (for example, more than 3V) with (for example, more than 3V) is larger than the peak voltage of the image signal (for example, more than 3V). In this case, the on-resistance Ro1 of the first n-channel TFT element 61a becomes smaller. As a result, when the pixel electrode portion held in the low (L) state is rewritten with a high (H) image signal, the output voltage V61bo of the drain electrode portion of the second n-channel TFT element 61b becomes high, As a result, the rewriting drive can be executed more reliably and more quickly. In this case, the gate voltage can be, for example, more than 6V and about 7V or less.

Furthermore, the voltage difference (for example, more than 3V) between the gate voltage (for example, more than 6V) input to the gate electrode portion of the second n-channel TFT element 61b and the peak voltage (for example, 3V) of the image signal is the peak of the image signal. It is preferably larger than the voltage (for example, more than 3V). In this case, the on-resistance Ro2 of the second n-channel TFT element 61b becomes smaller. As a result, when the pixel electrode portion held in the low (L) state is rewritten with a high (H) image signal, the output voltage V61bo of the drain electrode portion of the second n-channel TFT element 61b becomes high, As a result, the rewriting drive can be executed more reliably and more quickly. In this case, the gate voltage can be, for example, more than 6V and about 7V or less.

  The dot matrix display device of the present invention can provide a plurality of display areas each having an optimum rewrite cycle in one display panel. In this case, the power consumption can be controlled by setting a very long period between rewriting in one display area and setting a short period between rewriting in the other display area. Can be performed with high accuracy. As a result, power consumption can be further reduced.

The overall configuration of the dot matrix display device of the present invention will be described below. FIG. 1 is a block circuit diagram of a basic configuration of a dot matrix type display device, and a display panel is a monochrome display LCD having a number of pixels of 16384 dots (vertical 128 dots × horizontal 128 dots). In FIG. 1, a gate signal line drive circuit 3 is provided on one side of the LCD panel, and an image signal (source signal) line drive circuit 4 is provided on the lower side of the LCD panel. In FIG. 1, 1 is a TFT element, 2
Denotes a common voltage line for supplying the common voltage Vcom to the common electrode of the pixel electrode portion, 10 denotes a display portion, and 11 denotes an LCD panel.

FIG. 3 is a circuit diagram showing a detailed configuration of the gate signal line driving circuit 3. The gate signal line driving circuit 3 is an inverted gate selection signal line for transmitting an inverted output from an inverter 21 composed of a CMOS inverter or the like for generating inverted signals of the gate selection signal lines GS1 to GS7 and the gate selection signal lines GS1 to GS7. 7 signals out of 14 signals consisting of iGS1 to iGS7 (in FIG. 3, the inverted symbol of the superscript bar is attached), gate selection signal lines GS1 to GS7 and inverted gate selection signal lines iGS1 to iGS7 Is increased, and the voltage amplitude of the output of the logic gate circuit 22 is boosted to operate the first n-channel TFT element 61a on the gate signal line GLn39 side of the pixel electrode section. A booster circuit (level shifter (Level / Shifter: L / S)) 23, and an inverter 24 composed of a CMOS inverter or the like for inverting the output of the booster circuit 23. In FIG. 2, reference numeral 10 denotes a display unit.

In this gate signal line driving circuit 3, the logic gate circuit 22 is high (“H”) when all of the seven signals input thereto are low (represented by “L”, for example, a signal of 0V). For example, 3V signal). There are 2 ⁷ = 128 combinations of wirings of the gate selection signal lines GS1 to GS7 and the inverted gate selection signal lines iGS1 to iGS7, which are input to the logic gate circuit 22, and are input to the gate selection signal lines GS1 to GS7 7 One logic gate circuit 22 can be selected by one set of signals. Thereby, one of the gate signal lines GL1 to GL128 can be arbitrarily selected and turned on. Note that control of a set of seven signals input to the gate selection signal lines GS1 to GS7 can be performed by a control LSI (Large Scale Integrated Circuit) provided on the LCD panel 11 or externally.

FIG. 4 is a circuit diagram showing a detailed configuration of the image signal line driving circuit 4. The image signal line driving circuit 4 includes an image selection signal line SS1 to SS7, an inverter 31 including a CMOS inverter that generates an inverted signal of each of the image selection signal lines SS1 to SS7, and an inverted image that transmits an inverted output from the inverter 31. A logic gate circuit 32 of a logical sum negation (NOR) to which seven signals out of 14 signals composed of the selection signal lines iSS1 to iSS7, the image selection signal lines SS1 to SS7, and the inverted image selection signal lines iSS1 to iSS7 are input.
The booster circuit (L / S) 33 for boosting the voltage amplitude of the output of the logic gate circuit 32 and operating the second n-channel TFT element 61b on the image signal line DLn37 side of the pixel electrode portion, And an inverter 34 composed of a CMOS inverter or the like for inverting the output. Further, a fourth n-channel which is a transfer gate element that is turned on by the output from the image signal line 36 for transmitting the image signal (Data) and the inverter 34 and outputs the image signal Data from the image signal line 36 to the pixel electrode portion. TFT element 35 is provided.

In the image signal line driving circuit 4, the logic gate circuit 32 outputs H (for example, a 3V signal) when all of the seven signals input thereto are L (for example, a 0V signal). Then, there are 2 ⁷ = 128 combinations of wirings of the image selection signal lines SS1 to SS7 and the inverted image selection signal lines iSS1 to iSS7, which are input to the logic gate circuit 32, and are input to the image selection signal lines SS1 to SS7 7 One logic gate circuit 32 can be selected by one set of signals. Thereby, one of the image signal line selection lines SL1 to SL128 can be arbitrarily selected and turned on. The control of a set of seven signals input to the image selection signal lines SS1 to SS7 can be performed by a control LSI or the like provided on the LCD panel 11 or outside.

  Further, one arbitrarily selected image signal line selection line SLn turns on one fourth n-channel TFT element 35, and the fourth n-channel TFT element 35 receives one image signal Data as an image signal. The signal is transmitted on the line DLn37 and transmitted to the pixel electrode unit. Such input control of the image signal Data can be controlled by the control LSI or the like.

FIGS. 5A and 5B are circuit diagrams showing an embodiment of a drive circuit unit for turning on and off one gate signal line GL128 in the gate signal line drive circuit 3. FIG. Each of the inverted gate selection signal lines iGS1 to iGS6 (in FIG. 5A and FIG. 5B, the symbol is indicated by the inverted symbol of the superscript bar) and the gate selection signal line GS7 are respectively connected to the p-channel TFT element 41 and n. An inverter composed of a channel TFT element 42 is connected.

Each of these seven inverters has a common gate connection point connected to one of the inverted gate selection signal lines iGS1 to iGS6 and the gate selection signal line GS7, and the seven common drain connection points are connected in common. Yes. Accordingly, only when the L signal is input to all of the inverted gate selection signal lines iGS1 to iGS6 and the gate selection signal line GS7, the H signal is output from the seven commonly connected drain connection points. In other words, it functions as a logical gate circuit 22 for logical sum negation (NOR).

The output (H signal) of the NOR logic gate circuit 22 includes an inverter 43, a transfer gate circuit 44 in which a p-channel TFT element and an n-channel TFT element are connected in series with a common drain electrode, and a p-channel circuit. The voltage is input to a booster circuit (L / S) 23 comprising a transfer gate circuit 45 in which a TFT element and an n-channel TFT element are connected in series with a common drain electrode. The common drain connection point of one transfer gate circuit 44 is connected to the gate electrode portion of the p-channel TFT element of the other transfer gate circuit 45. The common drain connection point of the other transfer gate circuit 45 is connected to the gate electrode portion of the p-channel TFT element of the one transfer gate circuit 44.

The gate electrode part of the n-channel TFT element of one transfer gate circuit 44 is H
Is input, a current flows through the n-channel TFT element, and the common drain connection point of one transfer gate circuit 44 becomes a potential (L) of 0V. This potential of 0V is input to the gate common connection point of the inverter 24. As a result, an H signal (6 V) is input from the drain common connection point of the inverter 24 to the gate signal line GL128. At this time, a potential (L) of 0V is applied to the gate electrode portion of the p-channel TFT element of the other transfer gate circuit 45, the p-channel TFT element is turned on, and the drain electrode portion of the p-channel TFT element is set to a potential of 6V. However, this potential is not transmitted to the inverter 24. Further, since the L signal is input to the gate electrode portion of the n-channel TFT element of the other transfer gate circuit 45 from the drain common connection point of the inverter 43, the n-channel TFT element is turned off.

6A and 6B show one image signal line selection line SL128 in the image signal line drive circuit 4. FIG.
FIG. 2 is a circuit diagram showing an embodiment of a drive circuit unit for turning on / off. An inverter composed of a p-channel TFT element 51 and an n-channel TFT element 52 is connected to each of the inverted image selection signal lines iSS1 to iSS6 and the image selection signal line SS7.

Each of these seven inverters has a common gate connection point connected to each of the inverted image selection signal lines iSS1 to iSS6 and the image selection signal line SS7, and the seven drain common connection points are commonly connected. Yes. Thus, the inverted image selection signal lines iSS1 to iSS6 and the image selection signal line SS7
Only when the L signal is input to all of the two, the H signal is output from the seven commonly connected drain connection points. In other words, it functions as a logical gate circuit 32 of a logical sum negation (NOR).

The output (H signal) of the NOR logic gate circuit 32 includes an inverter 53, a transfer gate circuit 54 in which a p-channel TFT element and an n-channel TFT element are connected in series with a common drain electrode, and a p-channel. The voltage is input to a booster circuit (L / S) 33 including a transfer gate circuit 55 in which a TFT element and an n-channel TFT element are connected in series with a common drain electrode portion. The common drain connection point of one transfer gate circuit 54 is connected to the gate electrode portion of the p-channel TFT element of the other transfer gate circuit 55. The common drain connection point of the other transfer gate circuit 55 is connected to the gate electrode portion of the p-channel TFT element of the one transfer gate circuit 54.

The gate electrode part of the n-channel TFT element of one transfer gate circuit 54 is H
When the above signal is input, a current flows through the n-channel TFT element, and the common drain connection point of one transfer gate circuit 54 becomes a potential (L) of 0V. This 0 V potential is input to the common gate connection point of the inverter 34. As a result, the H signal (6 V) is input from the common drain connection point of the inverter 34 to the image signal line selection line SL128. At this time, a potential (L) of 0 V is applied to the gate electrode portion of the p-channel TFT element of the other transfer gate circuit 55,
The p-channel TFT element is turned on and the drain electrode portion of the p-channel TFT element has a potential of 6V, but this potential is not transmitted to the inverter 34. Further, since the L signal is input to the gate electrode portion of the n-channel TFT element of the other transfer gate circuit 55 from the common drain connection point of the inverter 53, the n-channel TFT element is turned off.

Further, a fourth n-channel TFT element 35 is connected to the image signal line selection line SL128. The fourth n-channel TFT element 35 receives a signal transmitted through the image signal line selection line SL128 as a control input to the gate electrode portion. An image signal line 36 is connected to the source electrode portion of the TFT element 35. Thus, when the signal transmitted through the image signal line selection line SL128 is H, the fourth n-channel TFT element 35 is turned on, and the image signal Data is transmitted to the pixel electrode portion through the image signal line DL128.

7 and 8 are circuit diagrams showing an embodiment of a pixel electrode unit including a drive selection circuit 64 having a holding circuit 62 and a pixel electrode control circuit 63. FIG. FIG. 7 is a block circuit diagram, and FIG. 8 is a detailed circuit diagram in which TFT element groups constituting each block circuit are taken. The drive selection circuit 64 is a circuit that selects either still image drive or rewrite drive, and includes a holding circuit 62 and a pixel electrode control circuit 63.

As shown in FIGS. 7 and 8, a transfer gate circuit formed by connecting first and second n-channel TFT elements 61a and 61b in series is provided in the input section 61 in the previous stage of the drive selection circuit 64. ing. In the first n-channel TFT element 61a on the image signal line DLn37 side, the signal transmitted through the image signal line selection line SLn38 is controlled and input to the gate electrode portion. First when the signal is H
The n-channel TFT element 61a is turned on, and in the case of L, the first n-channel TFT element 61a is turned off. In the second n-channel TFT element 61b on the gate signal GLn39 side, a signal transmitted through the gate signal line GLn39 is controlled and input to the gate electrode portion. Second if the signal is H
The n-channel TFT element 61b is turned on, and in the case of L, the second n-channel TFT element 61b is turned off. Therefore, only when the signal transmitted through the gate signal line GLn39 is H and the signal transmitted through the image signal line selection line SLn38 is H, the transfer gate circuit is closed in an equivalent circuit (closed). Then, the signal transmitted through the image signal line DLn37 is transmitted to the holding circuit 62.

FIG. 8 shows a configuration of a static memory as the holding circuit 62. The holding circuit 62 connects the first and second CMOS inverters 62a and 62b in series, and outputs the output from the common drain connection point of the second (rear stage) CMOS inverter 62b to the first (previous stage) CMOS. A feedback input is made to the common gate connection point of the inverter 62a. As a result, when an H signal is input to the gate common connection point of the first CMOS inverter 62a, an L signal is then output from the drain common connection point of the first CMOS inverter 62a. The signal is input to the gate common connection point of the second CMOS inverter 62b, and then the H signal is output from the drain common connection point of the second CMOS inverter 62b, and then the H signal is the first CMOS inverter. It is fed back to the gate common connection point of 62a. As a result, for example, H, L, and H signals are always held on the loop transmission line.

FIG. 9 is a circuit diagram depicting the connection relationship of the TFT element groups constituting the pixel electrode control circuit 63. As shown in FIG.
The pixel electrode control circuit 63 shares the first CMOS inverter 62a of the holding circuit 62, and outputs the inverted signal iB of the image signal B (in the figure, the symbol is attached with the inverted symbol of the superscript bar). A first CMOS inverter 62a, a p-channel TFT element 81a and an n-channel TFT element 81b,
A first binary selection circuit 81 that outputs binary data by reference input of the common voltage Vcom (A), the image signal data (B), and the output (iB) of the first CMOS inverter 62a, and p channel It consists of a TFT element 82a and an n-channel TFT element 82b, and a common voltage Vcom (A) and image signal data.
(B) and the output (iB) of the first CMOS inverter 62a are referenced and input to output binary data. The output line is connected in parallel to the output line of the first binary selection circuit 81. And a second binary selection circuit 82. The output of the first binary selection circuit 81 and the output of the second binary selection circuit 82 are the exclusive OR (EXOR) of the common voltage Vcom (A) and the image signal data (B). Configures the logic gate output.

  The first binary selection circuit 81 is a CMOS inverter in which a p-channel TFT element 81a and an n-channel TFT element 81b are connected in common to the gate electrode portion and the drain electrode portion, and the image signal data (B) is Only when the signal is H (1), binary data (Y) is output. On the other hand, when the image signal data (B) is a signal of L (0), the first binary selection circuit 81 does not function as an inverter and is in a high impedance state, that is, in an open state in terms of an equivalent circuit. Therefore, binary data (Y) is not output.

The second binary selection circuit 82 is a four-terminal transfer gate circuit in which a p-channel TFT element 82a and an n-channel TFT element 82b are connected to each other between source electrode portions and drain electrode portions, and an n-channel TFT element 82b. Output of the first inverter 62a input to the gate electrode portion (
iB) is used as a control input. Only when the output (iB) of the first inverter 62a is the H signal (1), that is, when the image signal data (B) is the L signal (0), the binary data (Y) is obtained. Output. On the other hand, when the output (iB) of the first inverter 62a is the L signal (0), the second binary selection circuit 82 does not function as a transfer gate circuit and is in a high impedance state, that is, equivalent circuit-like. Open (open) state, and binary data (Y) is not output.

Since the output line of the second binary selection circuit 82 is connected in parallel to the output line of the first binary selection circuit 81 in this way, the output of the first binary selection circuit 81 and the second The output of the binary selection circuit 82 constitutes an exclusive OR logic gate output for the common voltage Vcom (A) and the image signal data (B). That is, the pixel electrode control circuit 63 is a logic gate circuit that performs an exclusive OR operation on the common voltage Vcom (A) and the image signal data (B).

FIG. 10 is a truth table describing the output (Y) of an exclusive-OR logic gate circuit in which the common voltage Vcom (A) and the image signal data (B) are binary input. When the image signal data (B) is input to the pixel electrode portion, that is, when the image signal data (B) is a signal of H (3V: “1”), the pixel voltage Pixel and the common voltage Vcom (A) In the normally white mode, black is displayed, and in the normally black mode, white is displayed. Thus, even if the common voltage Vcom (A) is driven to be inverted, the potential difference between the pixel voltage Pixel and the common voltage Vcom (A) is maintained. AC drive for liquid crystal to prevent deterioration is realized. On the other hand, when the image signal data (B) is not input to the pixel electrode portion, that is, when the image signal data (B) is a signal of L (0 V: “0”), the pixel voltage Pixel and the common voltage Vcom (A). There is no potential difference between the two and the white display in the normally white mode, and the black display in the normally black mode. Thus, the common voltage Vcom (A
) Is inverted, the state in which there is no potential difference between the pixel voltage Pixel and the common voltage Vcom (A) is maintained. Therefore, in order to prevent the liquid crystal from being deteriorated while maintaining the display in the pixel electrode portion. AC drive for liquid crystal is realized.

Further, when rewriting the display in the pixel electrode section, a transfer gate formed by connecting first and second n-channel TFT elements 61a and 61b in series in the input section 61 in the previous stage of the drive selection circuit 64 shown in FIG. Turn on the circuit. That is, the signal transmitted through the gate signal line GLn39 is H, and the signal transmitted through the image signal line selection line SLn38 is H. In this state, the signal (data) transmitted through the image signal line DLn37 is transmitted to the holding circuit 62. For example, when the signal (data) is H, the holding circuit 62 holds the H signal (data). Then, a display corresponding to the case where data (B) in FIG. That is, the display of the pixel electrode portion is black in the normally white mode and white in the normally black mode. On the other hand, when the signal (data) is L, the holding circuit 62 holds the L signal (data). Then, a display corresponding to the case where data (B) in FIG. 10 is L is executed on the pixel electrode portion. That is, the display of the pixel electrode portion is rewritten so that white display is performed in the normally white mode and black display is performed in the normally black mode.

With the above-described configuration, the dot matrix display device of the present invention can perform rewrite driving in the display area for each pixel (dot), and can drive all other pixels as still images. The power can be very low. For example, in a conventional black and white display LCD for a wristwatch, the power consumption of about 100 μW when performing still image driving and rewriting driving by full screen scanning is 10 μW in the dot matrix type display device of the present invention. It can be suppressed to about less than or equal to about 3 μW. As a result, even with an LCD having a complicated display configuration, for example, it is possible to extend the drivable period by 10 times or more by replacing the battery once.

  Furthermore, the dot matrix type display device of the present invention is preferably provided with a plurality of display regions to which the rewrite drive is applied with different rewrite cycles, and the ratio of the different rewrite cycles is 10 times or more. With this configuration, the power consumption can be reduced by setting a very long period between rewriting and the next rewriting in a certain display area, and shortening a period between rewriting and the next rewriting in other display areas. The control can be performed with fine and high accuracy. As a result, power consumption can be further reduced. Furthermore, the effect of further reducing power consumption is enhanced by setting the ratio of different rewrite cycles to 10 times or more.

FIG. 11 shows a display panel of a digital display wristwatch to which the dot matrix type display device of the present invention is applied.As shown in FIG. 11, for example, in the display panel, a display area 91 for displaying time, The rewrite cycle can be greatly different between the display area 92 for displaying the minute and the display area 93 for displaying the second. In the display area 93 for displaying seconds, rewriting is driven every second, whereas in the display area 92 for displaying minutes, rewriting is driven every minute and in the display area 91 for displaying time, every hour. The rewriting drive may be performed. Accordingly, the display area other than the display areas 91 to 93 is a still image display area 94. As a preferred embodiment, the ratio of the rewrite drive cycle of the display area 92 for displaying minutes and the display area 93 for displaying seconds is 60 times. In other words, it can be said to be 1/60. Further, in the display area 91 for displaying the time, the rewriting drive may be performed every hour, so the ratio of the rewriting driving cycle of the display area 93 for displaying the second and the display area 91 for displaying the time is 3600 times. . In other words, it can be said to be 1/3600. In the display areas 91 to 93, the rewrite drive can be performed for each pixel (dot), but the rewrite drive may be performed for each of a plurality of pixels. In the display areas 91 to 93, all the pixels may be rewritten, or only the pixels necessary for rewriting may be rewritten. For example, in the case where the display of “5” is rewritten to “6” in one display region, it is possible to distinguish between pixels that do not need to be rewritten and pixels that need to be rewritten, so that only the pixels that need to be rewritten can be rewritten.

In addition, when a wristwatch receives a radio signal for incoming mail from a mobile phone, smartphone, tablet terminal, personal computer, etc., the pixel selection drive system described above displays the mail reception on the display panel consisting of the wristwatch's LCD, etc. This can be done by rewriting driving. Such a complicated display function can be performed with extremely low power consumption. For example, temperature, humidity, altitude, direction, illuminance, barometric pressure, water depth, water pressure, weather forecast, time difference with foreign countries, pedometer, tide time, sunrise / sunset time, blood pressure, pulse, email content, breaking news, Notifications such as earthquake early warnings can be displayed at their optimum rewriting cycle or at an arbitrary timing. In addition, the rewrite cycle or display timing can be controlled by an external input or change by a person. Control LSI provided around the dot matrix display device for changing the rewrite cycle, controlling the display or controlling the display timing
Etc.

  In the dot matrix type display device of the present invention, the rewriting period corresponding to the rewriting cycle of the display area includes an operation period in which rewriting is performed and other rewriting suspension periods, and the rewriting suspension period is longer than the operation period. Is preferred. With this configuration, the display switching operation by rewriting becomes quick and the display switching process is not visually recognized, so that the display switching is easy to see. For example, when rewriting the second display of the clock, the rewriting period is 1 second, the operation period for executing rewriting is about 0.1 to 0.3 seconds (10% to 30%), and the other period is about 0.7 to 0.9 seconds. A rewriting suspension period may be used.

  In addition, the number of pixels in a display area with a short rewrite cycle, such as a display area that displays seconds of a clock, is made smaller than the number of pixels in a display area with a long rewrite cycle, such as a display area that displays time by the time of the clock. It is preferable. Thereby, power consumption can be further reduced. For example, the number of pixels in the display region with a short rewrite cycle is preferably 30% or less, more preferably 10% or less, of the number of pixels in the display region with a long rewrite cycle.

  As described above, as a preferred embodiment, since the pixel electrode control circuit 63 shares the first CMOS inverter 62a of the holding circuit 62, the number of TFT elements is reduced. The reduction effect increases and the aperture ratio of the pixel electrode portion increases.

Further, the dot matrix type display device of the present invention is preferably a reflection type LCD having a pixel electrode as a reflection type electrode. In this case, the holding circuit 62 and the like can be disposed below the pixel electrode, and a decrease in light reflectance due to the holding circuit 62 and the like can be eliminated. On the other hand, in a transmissive LCD, if the transparent pixel electrode and the holding circuit 62 are arranged so as to overlap with each other, the TFT elements constituting the holding circuit 62 and the like may malfunction due to the transmitted light. For this reason, it is necessary to cover the gate electrode portion of the TFT element with a light-shielding film, and the aperture ratio tends to decrease. In addition, since the reflective LCD does not require a backlight, it is effective in reducing power consumption. Further, the dot matrix type display device of the present invention may be a transflective liquid crystal display device provided with a reflective region having the reflective electrode and a transmissive region having a transmissive electrode in the region of the pixel electrode.

  In addition, the number of bits held by the holding circuit 62 is preferably 1 or more. When the number of bits is increased to a plurality of bits, gradation display can be performed during still image display. Further, if the holding circuit 62 for storing an analog signal is used, full-color display can be performed.

In addition, the pixel electrode control circuit 63 generates the H / L of the common voltage Vcom as shown in the truth table of FIG.
For any of these signals, still image driving and rewriting driving are performed. That is, when the common voltage Vcom (A) is H (3 V) and the image signal data (B) is H (3 V), there is a potential difference between the common voltage Vcom (A) and the pixel voltage Pixel (L: 0 V). Formed, common voltage Vcom
Similarly, when (A) is L (0 V) and the image signal data (B) is H (3 V), a potential difference is formed between the common voltage Vcom (A) and the pixel voltage Pixel (H: 3 V). The liquid crystal is AC driven. Thereby, for example, the H / L of the common voltage Vcom (A) can be inverted every second in accordance with the rewriting cycle of the second display, and deterioration of the liquid crystal molecules can be suppressed. That is, when a DC voltage component is applied to the liquid crystal molecules for a long time, it is possible to prevent the liquid crystal molecules from causing a bias of positive and negative charges (fixation of a small amount of impurities) on the pixel electrode surface and shortening the lifetime.

As described above, it is preferable to periodically invert the H / L inversion of the common voltage Vcom in conjunction with the rewrite cycle. In this case, compared with the case where the H / L inversion of the common voltage Vcom is not linked to the rewrite cycle, it is not necessary to add a control circuit or the like for individually controlling the common voltage Vcom, and the power consumption is further reduced. It is effective for. In addition, H / L of common voltage Vcom
The inversion drive has two roles of inversion drive for suppressing deterioration of liquid crystal molecules and a pixel voltage control signal as a control input of the pixel electrode control circuit 63 constituting the logic gate circuit of EXOR. This also contributes to further reduction in power consumption.

  In the dot matrix display device of the present invention, it is preferable to periodically invert the high / low of the common voltage supplied to each pixel electrode portion in a display region to which still image driving is applied. Thereby, the deterioration of the liquid crystal molecules is suppressed not only in the display area to which the rewrite drive is applied but also in the area to which the still image drive is applied.

Further, the periodic period of inversion of the common voltage Vcom can be appropriately set by the control LSI or the like every second, every several tens of seconds, minutes, or hours. Further, the inversion cycle of the common voltage Vcom may be set every n seconds (n is a natural number). In this case, the rewrite cycle of the second display can be used as a base for controlling the inversion of the common voltage Vcom. It becomes easy to control the inversion.

  In the dot matrix display device of the present invention, an auxiliary capacitor of about 1 to 3 pF may be connected in parallel between the pixel electrode control circuit 63 and the pixel electrode. As a result, when rewriting driving is performed, it is possible to suppress the pixel voltage from gradually decreasing and becoming difficult to hold for one field period, and to hold the pixel voltage for one field period.

Further, the n-channel TFT element and the p-channel TFT element may be formed using low-temperature polycrystalline silicon (LTPS). In this case, a driving circuit based on a CMOS circuit, an SRAM circuit, a D / A converter, an image display unit, and the like can be integrated on a glass substrate. Therefore, an LCD equipped with an audio processing circuit and a microprocessor can also be manufactured using LTPS. Since the liquid crystal display panel and its peripheral drive circuit can be integrally formed on the glass substrate, the electrical reliability is improved. In other words, the number of electrical connections between the liquid crystal display panel and the driving circuit can be greatly reduced, and it is resistant to vibrations and light in weight, which is suitable for a portable information terminal. In addition, since the current driving capability is high, an LCD having high-definition pixels and pixels with a high aperture ratio can be manufactured.

The manufacturing method of LTPS is shown below. First, an amorphous silicon film is formed on a glass substrate by a plasma CVD (Chemical Vapor Deposition) method. Next, in order to polycrystallize the amorphous silicon film, the amorphous silicon film is irradiated with excimer laser light at a temperature of a glass substrate of 450 ° C. or lower. As the excimer laser device, for example, a gas laser light source that uses ArF (wavelength 193 nm), KrF (wavelength 248 nm), or the like, which oscillates ultraviolet light having a large absorption of the amorphous silicon film can be used. Amorphous silicon film is irradiated with pulsed laser light with a laser oscillation frequency of about 300 Hz, laser light energy of about 300 W, pulse width of about 20 ns to about 60 ns, and irradiation energy density of about 500 mJ / cm ^{2 to 1} J / cm ^2. It is solidified after being melted and supercooled. As a result, the film changes to a polycrystalline silicon film having an average grain size of about 0.3 μm.

In addition, when the pixel electrode has translucency, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), zinc oxide (ZnO), phosphorus or boron It can be formed using a light-transmitting conductive material such as silicon (Si).

Display elements placed in the pixel electrode section include LCD elements, organic EL (Electro Luminescence) elements, inorganic EL elements, FED (Field Emitting Display) elements, SED (Surface-conduction Electron-emitter Display) elements, and GLV (Grating Light). Display elements such as a Valve element, a PDP (Plasma Display) element, an electronic paper display element, a DMD (Digital micro Mirror Device) element, and a piezoelectric ceramic display element can be used. The dot matrix type display device of the present invention is preferably of an in-plane switching (IPS) system or a fringe field switching (FFS) system. In this case, the common voltage is controlled for each pixel electrode part by forming the common electrode for each pixel electrode part on the main surface of the array side substrate on which the pixel electrode is formed (the substrate on which the TFT element is formed). It can be done independently.

Further, the dot matrix display device of the present invention can be applied to various electronic devices. The electronic devices include smart watches and other digital display watches, car route guidance systems (car navigation systems), ship route guidance systems, aircraft route guidance systems, smartphone terminals, mobile phones, tablet terminals, personal digital assistants (PDAs).
Video cameras, digital still cameras, electronic notebooks, electronic books, electronic dictionaries, personal computers, copying machines, terminal devices for game machines, televisions, product display tags, price display tags, industrial programmable display devices, car audio, There are a head-up display, a digital audio player, a facsimile, a printer, a copier, an automated teller machine (ATM), a vending machine, a head mounted display device (HMD), and the like.

1 TFT element 2 Common voltage line 3 Gate signal line drive circuit 4 Image signal line drive circuit
10 Display section
11 LCD panel
21,31 inverter
22,32 NOR logic gate circuit
23,33 Booster circuit (level shifter)
24,34 inverter
35 Fourth n-channel TFT device
36,37 Image signal line
38 Image signal line selection line
39 Gate signal line
41,51 p-channel TFT device
42,52 n-channel TFT device
43,53 inverter
44,54 One transfer gate circuit
45,55 Transfer gate circuit on the other side
61 Input section
61a First n-channel TFT element on the image signal line side
61b Second n-channel TFT element on the gate signal line side
62 Holding circuit
62a First inverter
62b Second inverter
63 Pixel electrode control circuit
64 Drive selection circuit
81 First binary selection circuit
81a p-channel TFT device
81b n-channel TFT device
82 Second binary selection circuit
82a p-channel TFT device
82b n-channel TFT device
91 Display area for displaying time
Display area displaying 92 minutes
Display area displaying 93 seconds
94 Display area for displaying still images

Claims (3)

A plurality of gate signal lines formed in a predetermined direction on the substrate, a plurality of image signal lines formed so as to cross the gate signal lines in a direction crossing the predetermined direction, and an image signal line selection in parallel therewith A pixel electrode unit including a drive selection circuit for selecting either rewrite driving or still image driving, formed at an intersection of the gate signal line and the image signal line, and a plurality of the gate signal lines A dot matrix type display device comprising: a gate signal line driving circuit that arbitrarily selects one to turn on; and an image signal line driving circuit that arbitrarily selects and turns on one of the plurality of image signal lines. There,
The pixel electrode unit includes a first n-channel thin film transistor element turned on by the image signal line selection line and a second n-channel thin film transistor element turned on by the gate signal line in series before the drive selection circuit. An image signal input unit connected to
The drive selection circuit includes: a pixel electrode control circuit that rewrites the selected pixel electrode portion at the intersection of the on-state gate signal line and the on-state image signal line selection line with the image signal; and the input A holding circuit that holds the image signal input from the unit and drives the non-selected pixel electrode unit as a still image, and
The holding circuit is a static memory in which a first CMOS inverter to which the image signal is input and a second CMOS inverter connected thereto are connected in a loop shape,
In the second CMOS inverter, the third on-resistance of the third n-channel thin film transistor element constituting the second CMOS inverter is the same as the first on-resistance of the first n-channel thin film transistor element and the second n-channel thin film transistor element. greater than the sum of the second on-resistance, Ri said first on-resistance and a second on-resistance equal der,
In the image signal line, a fourth n-channel thin film transistor element that is turned on by the image signal line selection line is connected in series to an input end of the image signal, and the third on-resistance is connected to the first signal line. A dot matrix display device having a larger ON resistance, a second ON resistance, and a fourth ON resistance of the fourth n-channel thin film transistor element . 2. The dot matrix display device according to claim 1 , wherein the fourth on-resistance is the smallest among the first on-resistance, the second on-resistance, and the fourth on-resistance. The voltage difference between the gate voltage transmitted through the image signal line selection line and inputted to the gate electrode portion of the first n-channel thin film transistor element and the peak voltage of the image signal is larger than the peak voltage of the image signal. The dot matrix type display device according to claim 1 or 2 .