JP2002289518A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of sufficiently decreasing a catalyst element of a crystalline silicon film, and raising performance and reliability of the semiconductor device. SOLUTION: A crystallization of a first amorphous silicon film 103 on a glass substrate 101 is promoted with nickel 104, to obtain a crystalline silicon film 103a. On a crystalline silicon film 103b obtained by enhancing crystallization of the crystalline silicon film 103a, a second amorphous silicon film composed of amorphous silicon films 107, 108 is provided. A high-speed thermal annealing process is carried out, so that the nickel 104 in the crystalline silicon film 103 is moved toward the second amorphous silicon film. The second amorphous silicon film is eliminated and a crystalline silicon film 103c is patterned to form a semiconductor element forming region 110.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a method of manufacturing a semiconductor device. More specifically, the present invention relates to a method for manufacturing a semiconductor device in which a semiconductor element formation region is formed using a crystalline silicon film obtained by crystallizing an amorphous silicon film. In particular, the present invention is effective for a semiconductor device using a thin film transistor (hereinafter, referred to as a TFT) provided on a substrate having an insulating surface. It can be used for ICs.

[0002]

2. Description of the Related Art In recent years, large and high resolution liquid crystal display devices have been developed.
High-speed, high-resolution contact image sensor, 3D IC
In order to realize the above, attempts have been made to form a high-performance semiconductor element on an insulating substrate such as glass or on an insulating film. In general, a thin film silicon semiconductor is used for a semiconductor element used in such an apparatus. As the thin film silicon semiconductor, an amorphous silicon semiconductor (a-S
i) and those composed of a crystalline silicon semiconductor.

[0003] Amorphous silicon semiconductors are low fabrication temperature, since the rich possible mass production can be produced relatively easily by a gas phase method, but the most commonly used, the physical properties such as conductivity Since it is inferior to a crystalline silicon semiconductor, in order to obtain higher speed characteristics in the future, it is strongly required to establish a method of manufacturing a semiconductor device in which a semiconductor element formation region is formed using a crystalline silicon semiconductor. Was.

The following methods (1) and (2) are known as methods for obtaining a crystalline silicon semiconductor in the form of a thin film.

[0005] (1) After forming an amorphous silicon semiconductor film, it causes the crystal growth by irradiating an energy beam such as a laser beam.

(2) After forming an amorphous silicon semiconductor film, crystal growth is performed in a solid state by a heat treatment.

Generally, the method (1) is often used. In this method, since the crystallization phenomenon in the melt-solidification process is used, a relatively high-quality crystalline silicon film having a small grain size but few crystal defects is obtained. However, the crystalline silicon film has a high defect density at the grain boundary, and the grain boundary acts as a large trap for carriers. Therefore, it cannot be said that the crystalline silicon film is sufficient in terms of the performance of the semiconductor device. In addition, as an example of a light source, an excimer laser which is most commonly used at present has not yet obtained a light source having sufficient stability, and has a drawback of characteristic variations between semiconductor elements.

The heat treatment of the method (2) is advantageous in terms of uniformity and stability as compared with the method (1), but requires a heat treatment at 600 ° C. for a long time of about 30 hours. Therefore, a long processing time, there is a problem that throughput is low. Further, in the method (2), since the structure of the obtained crystal grains has a twin structure, one crystal grain is relatively large as several μm, but contains a large number of twin defects in the crystal grain and (1) crystallinity compared with the method of) it is inferior.

However, recently, these (1),
As improvements in the method (2), by using a catalytic element which promotes crystallization of the amorphous silicon film, a method to achieve a low temperature of the heating temperature, shortening of the crystallization process time and the improvement of crystallinity There has been attracting attention. Specifically, a metal element such as nickel (Ni) on the surface of the amorphous silicon film is introduced a small amount, in which heat treatment is performed thereafter. In this way, the crystal nucleation of the metal element as nuclei occurs early, then the metal element to promote crystal growth becomes a catalyst, crystallization proceeds rapidly. Further crystalline silicon film crystal-grown in this way, unlike the conventional solid phase growth method (the above (method 2)), rather than a large twin structure within a grain crystal defects, How many The interior of each columnar crystal is almost in a single crystal state although it is small.

In Japanese Patent Application Laid-Open Nos. 10-223534 and 10-229048, after a Group V element such as phosphorus is selectively introduced into a part of a silicon film crystallized by a catalytic element, By performing heat treatment on the silicon film, the catalyst element is to be moved (gettered) to the region where the group V element is introduced. further,
In these publications is performed step, i.e. by strong light irradiation heat treatment gettering step of moving the catalyst element. Then, in order to increase the heating efficiency of the light during the strong light irradiation, a film having a high absorption efficiency for the strong light to be used is laminated on the silicon film. In Japanese Patent Application Laid-Open No. 10-223534, a film having a high absorption efficiency for strong light is selectively used as an introduction mask when introducing a Group V element, and also disclosed in Japanese Patent Application Laid-Open No. 10-229048. According to the gazette, after introducing the element of group V B, the whole surface of the substrate is newly added.
Each is provided.

In Japanese Patent Application Laid-Open No. 11-31660,
A thermal oxide film is formed on the surface of the silicon film crystallized by a catalyst element, the phosphorus on the thermal oxide film in a state in which a silicon film containing a high concentration, by performing the heat treatment, the upper layer of silicon The catalyst element is transferred to the film to reduce the concentration of the catalyst element in the underlying crystalline silicon film. Then, the upper silicon film containing phosphorus is removed, and the lower crystalline silicon film is used as a semiconductor element formation region.

[0012]

The method of crystallizing an amorphous silicon film into which a catalytic element has been introduced by heat treatment can lower the heating temperature and shorten the heating time, and can be obtained after crystallization. crystalline silicon film is better apparent than other crystallization methods. However, the presence of a large amount of a catalytic element mainly composed of these metals in a silicon film impairs the reliability and electrical stability of a semiconductor device using the silicon film. Not good. In other words, a catalyst element that promotes crystallization, such as nickel, is necessary when crystallizing an amorphous silicon film, but it is desirable that the catalyst element be minimized in the crystallized silicon film.

As a first method for achieving such an object, a method of minimizing the amount of a catalyst element necessary for crystallization and performing crystallization with a minimum amount is considered. However, as the introduction amount of the catalyst element is reduced, the growth state becomes very unstable. A crystalline silicon film formed in such a state has a very large variation in crystallinity in the film, and cannot be used as a film constituting a semiconductor element formation region. Therefore, Japanese Patent Application Laid-Open No. 10-22353
No. 4, JP-A-10-229048 and JP-A-11-31660, after crystal growth using a catalyst element, the catalyst element is moved (gettered) to form a semiconductor element formation region. such a way as to eliminate or reduce the catalytic element in the region should be is considered as a second method.

[0014] However, the present inventors have actually disclosed in
An experiment was conducted using a method as described in Japanese Patent Application Laid-Open No. 223534 and Japanese Patent Application Laid-Open No. 10-229048, and trial production of a TFT revealed that sufficient effects were not obtained. Specifically, even after the gettering process referred, it is still a large amount of the catalyst element, is present in the region to be the semiconductor device formation regions had had a clear negative effect on the TFT element. In particular, after the gettering step, the catalytic element introduction region is removed to form a semiconductor element formation region, and when this semiconductor element formation region is further subjected to a high-temperature heat treatment, the semiconductor element formation region remains in the semiconductor element formation region. The catalytic element re-aggregates and appears in a silicide state. This is disclosed in JP-A-10-223534 and JP-A-10-22.
The method of JP 9048 proves that gettering is still insufficient. And, the catalyst element is TF
If it exists at the junction of T, it becomes a leak source, and the leak current at the time of the off operation greatly increases. When a TFT is actually manufactured as a prototype, Japanese Patent Application Laid-Open Nos. 10-223534 and
In the method disclosed in Japanese Patent Application No. 0-229048, a defective TFT having an extremely large off-state leak current appears with a probability of about 3%. When the cause of the defective TFT was analyzed, it was confirmed that silicide due to the catalytic element was present at the junction between the channel and the drain.

JP-A-11-31660 discloses that a crystalline silicon film for forming a semiconductor element forming region is
After providing a silicon film containing high concentration of phosphorus over the entire surface,
By performing the heat treatment, a unique way of moving the catalyst element from the underlying crystalline silicon film with an upper layer of the silicon film in the vertical direction (thickness direction). Therefore, the gettering distance of the catalyst (the distance to which the catalyst element must move) is only about the thickness of the crystalline silicon film.
Compared with the method disclosed in Japanese Patent Application Laid-Open No. 3534 and Japanese Patent Application Laid-Open No. 10-229048, that is, as compared with lateral gettering, a shorter distance is required, and a high gettering effect can be expected. However, as a result of a prototype TFT experimenting with this method, rather than never gettering capability was high, as it does not say exactly enough also for the reduction of the catalyst element concentration. This result is shown in JP-A-10-22353.
As compared with JP-A-10-229048 and JP-A-10-229048, the results were the same or rather inferior.

[0016] As described above, JP-A-10-2235
No. 34, Japanese Patent Application Laid-Open No. 10-229048 and Japanese Patent Application Laid-Open No. 11-31660 cannot sufficiently reduce the amount of a catalytic element in an element region formed using a crystalline silicon film. As a result, even if a high-performance semiconductor device can be partially produced stochastically, the defect rate is high, the reliability is very poor, and it is not a technology that can be mass-produced.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of sufficiently reducing the number of catalytic elements in a crystalline silicon film and improving the performance and reliability of the semiconductor device.

[0018]

Means for Solving the Problems In order to solve the above-mentioned problems, the present inventors have paid attention to a high-quality crystalline silicon film crystallized using a catalytic element, and have managed to reduce this from the current laboratory level. We continued our research day and night, thinking that we could evolve it into a process that could withstand mass production. And, finally we found a way to solve the above problems.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention comprises forming a first amorphous silicon film on a substrate having an insulating surface, and forming the first amorphous silicon film on the first amorphous silicon film.
A step of introducing a catalytic element for accelerating crystallization of silicon, and a step of subjecting the first amorphous silicon film to a heat treatment to crystallize the first amorphous silicon film, Forming a film, providing a second amorphous silicon film on the crystalline silicon film, and subjecting the crystalline silicon film and the second amorphous silicon film to rapid thermal annealing Accordingly, a step of moving the catalytic element of the crystalline silicon film to the second amorphous silicon film, and removing the second amorphous silicon film, a semiconductor device of the above crystalline silicon film Forming a formation region.

According to the method of manufacturing a semiconductor device having the above structure, a catalytic element for promoting crystallization is introduced into the first amorphous silicon film formed on the substrate having an insulating surface, and the first amorphous silicon film is subjected to heat treatment. Crystal growth of one amorphous silicon film.
Then, a catalytic element in the crystalline silicon film is moved to the second amorphous silicon film by providing a second amorphous silicon film on the crystalline silicon film and performing a rapid thermal annealing treatment. make. Then, by removing the second amorphous silicon film, which mean that the crystalline silicon film and the semiconductor element forming region. As described above, the catalyst element in the crystalline silicon film is moved to the second amorphous silicon film by performing the above-described rapid thermal annealing treatment, and the method is disclosed in JP-A-10-223534.
JP-A-10-229048 and JP-A-11-3
Compared with the method disclosed in Japanese Patent No. 1660, the amount of the residual catalyst element in the semiconductor element formation region can be significantly reduced.

Further, because they greatly reduce the residual catalytic element amount in the semiconductor device forming region, not seen abnormalities of the leakage current in the OFF operation in the semiconductor element manufactured using the semiconductor device forming region. Therefore, the performance and reliability of the semiconductor device can be improved. That is,
JP-10-223534, JP-A No. 10-229
It is possible to obtain a high-performance semiconductor device having a higher current driving capability than the methods disclosed in Japanese Patent Application Laid-Open No. 048 and Japanese Patent Application Laid-Open No. 11-31660.

[0022] Hereinafter, will be described in more detail the mechanism of the gettering using the rapid thermal annealing process.

One of the mechanisms for moving the catalyst element in the crystalline silicon film to a certain region, that is, for gettering, is to increase the solid solubility of the catalyst element in the certain region from that in the other region. , there is a method of moving the catalyst element to it. As another method, there is a method of forming a defect or a segregation site for trapping a catalytic element, and moving the catalytic element there to trap. In the present invention, the advantage of the latter method can be maximized by performing the rapid thermal annealing. That is, the defects of the second amorphous silicon film serve as segregation sites for the catalyst element, and the catalyst element is moved from the crystalline silicon film and trapped by the second amorphous silicon film. As a result, the concentration of the catalytic element in the crystalline silicon film as a semiconductor element forming region is greatly reduced, there is no abnormality in the leak current in the off operation of the semiconductor device manufactured using the semiconductor device formation regions, highly reliable Can be obtained.

The manufacturing method of a semiconductor device of one embodiment, in the rapid thermal annealing treatment, heated from the preheating temperature to at least a portion of said second amorphous silicon film can be maintained in the state of amorphous First, the temperature is increased at a rate that can maintain at least a part of the second amorphous silicon film in an amorphous state.

According to the manufacturing method of the semiconductor device of this embodiment, a big point of the present invention, a state of the second amorphous silicon film serving as a gettering sink, to the heating rate in the rapid thermal annealing is there. More specifically, it is important that the silicon film provided on the crystalline silicon film is amorphous, and further, at least one of the silicon films serving as gettering sinks in the subsequent rapid thermal annealing treatment. The temperature is increased from a preheating temperature at which the portion can be maintained in an amorphous state, and the temperature is increased at a temperature rising rate capable of maintaining at least a part of the silicon film serving as a gettering sink in an amorphous state. This is very important. By doing so, the catalytic element in the crystalline silicon film moves to the second amorphous silicon film by using a large number of crystal defects existing in the second crystalline silicon film as segregation sites. And the second amorphous silicon film is trapped by the second amorphous silicon film, so that the so-called defect-induced gettering action can be maximized.

The effect of transferring (gettering) the catalytic element in the crystalline silicon film to the second amorphous silicon film as a gettering sink is caused by the rate of temperature increase in the rapid thermal annealing process. to differ greatly. Increasing the temperature of the heat treatment at this time generally improves the gettering effect. This is because the diffusion rate of the catalyst element in the crystalline silicon film is improved, and the solid solubility limit is increased.
However, the gettering effect of this time, as shown by × in FIG. 6, when gradually increasing the processing temperature of the annealing treatment,
The processing temperature becomes plateau at about 600 ° C., no effect can be obtained even by raising the higher temperature. Even if a non-doped amorphous silicon film is used as a gettering sink, a gettering effect can be obtained, but the result indicated by x in FIG.
This is a result when an amorphous silicon film containing phosphorus of Group B element is used as a gettering sink. In FIG. 6, the vertical axis shows the residual ratio of the catalytic element in the crystalline silicon film before and after the annealing, and the horizontal axis shows the processing temperature in the annealing. Then, a data dotted line made in a conventional manner in Fig. As described above, the effect of reducing the catalytic element treatment temperature at about 600 ° C. has been peaked, the residual ratio of the catalyst element at this time is about 0.
2, i.e. about 20% of the catalytic element present in the crystalline silicon film are still remains, and not be removed even by raising the further temperature.

When the present inventors examined the reason in detail, it was determined whether or not the amorphous silicon film serving as a gettering sink was crystallized in this heat treatment in terms of the gettering efficiency. It turned out to be. Then, while maintaining the amorphous state of the second amorphous silicon film, when heated by elevating the temperature of the second amorphous silicon film to a higher temperature, limit temperature 600 ° C. in the conventional method
As described above, it was found that a higher gettering effect, which had not been seen until now, can be obtained. The data at the time of using the present invention in this case is shown by the solid line in FIG. In particular, at a temperature of 600 ° C. or higher, a clear difference from the conventional method is observed, and the residual ratio of the catalytic element is greatly reduced. Therefore, the reason for restricting the conventional gettering effect is as follows.
It is considered that the amorphous silicon film containing Group B element is recrystallized during the heat treatment for gettering. However, since the gettering effect cannot be obtained unless the second amorphous silicon film serving as the gettering sink is also kept at a uniform high temperature, crystal growth will inevitably occur during the temperature rise process. That is, in the conventional method, the gettering effect is reduced at the point where the second amorphous silicon film serving as the gettering sink has been crystallized in the temperature increasing process, and the temperature at that stage is reduced. It is considered that there is a limit to the effect on the processing temperature. The gettering effect that is reduced at this time is a defect-induced gettering effect in which defects in the amorphous state are trapped mainly. The gettering effect cannot be obtained at all at the stage of crystallization. In the experiment results shown in FIG. 6, but using the amorphous silicon film obtained by introducing a phosphorus by using rapid thermal annealing as in the present invention, to elicit a gettering effect of defect-induced at a high temperature You will be able to, can act as a gettering sink in the amorphous silicon film of non-doped.

Further, the mechanism of the rapid thermal anneal moves the catalytic element in the lateral direction of the conventional method (parallel to the substrate surface) (gettered) can also be applied in the case. However, in the method of the present invention in which gettering is performed in the film thickness direction, the gettering distance is as short as the film thickness, so that gettering can be completed by a short annealing process. That is, the second amorphous silicon film, which is a gettering sink is also possible to end the gettering process prior to crystallization, if such, be drawn a large gettering effect over the entire annealing process it can. This is because the defect-induced gettering effect is lost at the stage when the second amorphous silicon film is completely crystallized.

As described above, high-speed thermal annealing is used as the heat treatment for gettering, and in the high-speed thermal annealing, preheating capable of maintaining at least a part of the second amorphous silicon film in an amorphous state is performed. with start heating from the temperature, at least part of the second amorphous silicon film be heated at a Atsushi Nobori rate capable of maintaining the state of the amorphous takes place, a very important point. In this way, for the first time, in the intended annealing temperature, it can be annealed to the second amorphous silicon film, which is a gettering sink as an amorphous state, the original temperature of the heat treatment at this time High gettering effect can be obtained.

The crystalline silicon film thus obtained was subjected to a light etching treatment using a hydrofluoric acid-based etchant, which was used as a method for simply confirming the residual catalytic element. As a result, in the evaluation for revealing the remaining catalyst element, no etch pit conventionally observed was observed.

Further, as a more severe evaluation, heat treatment at a higher temperature was performed. If the catalytic element in the semiconductor element formation region has not been significantly reduced, the catalytic element re-aggregates due to the heat treatment and appears in a silicide state. 3
No re-aggregation of the catalytic element was observed at all as seen in the techniques of JP 1660, JP-A-10-223534 and JP-A-10-229048. And
When a TFT was actually produced using the above-mentioned semiconductor element formation region, a TF was similarly obtained in the above three publications and the prior art.
TFT seen in more than 3% of the probability when you created the T
The abnormal increase phenomenon of the leak current at the time of off was not observed at all in the method of the present invention, and was exactly 0%. Further, in the liquid crystal display device manufactured using the TFT thus obtained, the linear display unevenness (caused by the sampling TFT in the driver portion) and the pixel defect due to the leak current at the time of off, which frequently occur in the conventional method, are also reduced. There was nothing at all, and the display quality could be greatly improved, and the non-defective rate could be dramatically increased.

In one embodiment of the present invention, in the method of manufacturing a semiconductor device, the preheating temperature is 550 ° C. or less, and the heating rate is 30.
℃ / greater than the minute.

According to the method of manufacturing a semiconductor device of the above embodiment, the high-speed thermal annealing process starts with a preheating temperature of 550 ° C. or less, and the rate of temperature rise is at least 30 ° C.
It is desirable that the temperature be raised at a rate of temperature increase exceeding / minute. More preferably, the heating rate is more desirable that greater than 100 ° C. / min.

If the preheating temperature is 550 ° C. or lower, the gettering effect can be increased without any crystal growth in the second amorphous silicon film.
On the other hand, if the preheating temperature exceeds 550 ° C., and got crystal growth occurs in the second amorphous silicon film, the gettering effect is reduced.

[0035] Then, if the heating rate is 30 ° C. / min or more, in the Atsushi Nobori process, the crystallization of the second amorphous silicon film is not terminated completely, leaving the amorphous component in the state, it can enter the catalytic element of the crystalline silicon film on the main heat treatment for gettering. In addition, when the temperature increase rate is 100 ° C./min or more, crystallization hardly occurs in the second amorphous silicon film during the temperature increase process,
The main heat treatment can be started while almost all of the second amorphous silicon film remains in the amorphous state.

FIGS. 5 (a) and 5 (b) show experimental data conducted by the present inventors regarding the heating rate at this time. Figure 5 (a), (b) shows the experimental results was performed with 675 ° C. rapid thermal annealing temperature. FIG. 5A shows the residual ratio of the catalytic element in the silicon film before and after the rapid thermal annealing. The measurement of the residual ratio of the catalyst element is performed by micro area SIMS.

As can be seen from FIG. 5 (a), the residual rate of the catalytic element greatly changes at about 30 ° C./min of the rate of temperature rise in the high-speed thermal annealing treatment.
° C. / min becomes more than a further decrease in the residual ratio of the catalyst element starts to occur. Meanwhile, in the above heating rate is less than 30 ° C. / min, even at elevated temperatures of the rapid thermal annealing, the effect of the catalytic element is reduced not observed, the Atsushi Nobori rate of 30 ° C. / min, the effect of the present invention It can be seen that the rate of temperature rise is the minimum necessary for obtaining the temperature. The residual ratio of the catalyst element,
According 30 ° C. / min heating rate increases further decreased, the saturation at about 100 ° C. / min or more. Accordingly, by the heating rate and 100 ° C. / min or more,
The gettering effect of a catalyst element may be maximized at a temperature of rapid thermal annealing.

Further, in FIG. 5 (b), shows the results of experiments conducted to elucidate the mechanism to maximize the gettering effect. Specifically, FIG.
Is a graph of examining the proportion of amorphous regions in the second amorphous silicon film, the relationship between the heating rate in the rapid thermal annealing process. In the above experiment, using a quartz substrate,
Quenched at a point where the annealing temperature reaches 675 ° C., 1 [mu] m
The measurement was performed by examining the Raman peak ratio between crystalline silicon and amorphous silicon by Raman spectroscopy of the spot of φ. As can be seen from FIG. 5 (b), a similar result was obtained with respect to the reduction rate of the catalytic element, and an amorphous peak began to appear at a heating rate of 30 ° C./min. peak ratio increases, and has a saturated at about 100 ° C. / min. Therefore, it can be clearly understood that the cause is the crystal state of the second amorphous silicon film serving as a gettering sink.

In one embodiment, in the method of manufacturing a semiconductor device, in the rapid thermal annealing treatment, the main heating for moving the catalyst element in the crystalline silicon film to the second amorphous silicon film is performed by the main heating. The main heating is performed after the temperature is raised, and the main heating is performed at an average temperature of 600 ° C. to 750 ° C. for 1 second to
Performed for 15 minutes.

According to the manufacturing method of the semiconductor device of this embodiment, in the rapid thermal annealing process conducted after the Atsushi Nobori, for moving the catalytic element of the crystalline silicon film to the second amorphous silicon film of the main heating, 600 ℃ ~7
It is preferably performed 1 second to 15 minutes at an average temperature in the range of 50 ° C.. This is because, as can be seen from the graph of FIG. 6, the effect of greatly reducing the catalyst element concentration according to the present invention appears only when the processing temperature corresponding to the main heating temperature is 600 ° C. or higher. Note that the data in FIG. 5 was obtained by setting the heating rate to 120 ° C./min. In the conventional method shown by the dotted line in FIG. 5, as as previously described, the effect of reducing the catalytic element has plateaued at about 600 ° C., in the present invention is shown by the solid line in FIG. 5, this 600
℃ or more, was not seen until now, higher gettering effect can be obtained. However, the higher the processing temperature is, the better it is not, and there is an upper limit. The reason will be described below.

When the treatment temperature is higher, random diffusion of the catalytic element occurs, and the catalytic element moves from the second amorphous silicon film to the outside. As a result, the concentration of the catalytic element in the crystalline silicon film starts to increase. In particular, when the treatment temperature is 750 ° C. or higher, the residual ratio of the catalytic element sharply increases. At this time, if any oxygen is present, the silicide of the catalytic element is selectively oxidized to form a hole in the silicon film. Become. Therefore, the upper limit of the processing temperature is restricted by these two points, and is 750 ° C. The annealing time (time during which the main heating is performed) ranges from 1 second to 15 minutes.
A sufficient effect can be seen. Therefore, the main heating for transferring the catalyst element in the crystalline silicon film to the second amorphous silicon film may be performed at an average temperature in the range of 600 ° C. to 750 ° C. for 1 second to 15 minutes. desirable.

In one embodiment of the present invention, the main heating is performed at an average temperature in the range of 650 ° C. to 700 ° C. for 1 minute to 10 minutes.

[0043] According to the manufacturing method of the semiconductor device of this embodiment, more preferably, the main heating, 650 ° C. ~
More preferably, it is performed at an average temperature in the range of 700 ° C. for 1 minute to 10 minutes. As can be seen from FIG. 5, when the processing temperature corresponding to the temperature of the main heating is about 650 ° C., the effect of reducing the catalytic element becomes almost saturated state, then about 700
° C. Furthermore gradually drops toward, but the residual ratio of the catalyst element at 700 ° C. becomes an extreme value, at 700 ° C. or higher out up conversely residual ratio of the catalyst element. This is for the reasons described above. Thus, the average temperature in the range of 650 ° C. to 700 ° C. is an optimum temperature range in the main heating. Also,
If the time for the main heating is within the range of 1 minute to 10 minutes, the effect of reducing the catalytic element can be sufficiently obtained. Also, the main heating time is 1 minute to 10 minutes.
Within the range of minutes, thermal damage (warpage or shrinkage) when, for example, glass is used as the substrate can be minimized.

In one embodiment of the present invention, the high-speed thermal annealing is performed using a tungsten-halogen lamp, a xenon arc lamp, a resistive heating furnace, and high-temperature gas heating.

According to the method of manufacturing a semiconductor device of the above embodiment, as the specific method of the high-speed thermal annealing, a tungsten-halogen lamp, a xenon arc lamp, a resistive heating furnace, and high-temperature gas heating are used. desirable. The above-described tungsten-halogen lamp or xenon arc lamp can heat not only the Si layer but also the entire substrate instantaneously, and is suitable for the present invention. In the case of using the above-described resistance heating furnace, the resistive heating furnace is inserted into the furnace one by one in order to provide a temperature gradient in the furnace and reduce the heat capacity of the substrate. The heating rate may be controlled by controlling the insertion speed at that time. Further, at this time, when a high-temperature gas heating such as blowing an inert gas such as nitrogen heated to a high temperature onto the substrate is also used, the temperature of the substrate can be increased at a faster rate. In this case, it is possible to heat the entire substrate more uniformly instantaneously, since the heating rate and cooling rate is accurately controllable, as compared to the above-described lamp heating method, and more invention Are suitable.

In one embodiment of the method of manufacturing a semiconductor device, the catalyst element is Ni (nickel), Co (cobalt),
Fe (iron), Pd (palladium), Pt (platinum), Cu
Is one or more kinds of elements selected from among the (copper) and Au (gold).

According to the method of manufacturing a semiconductor device of the above embodiment, Ni, Co, Fe, Pd,
One or more elements selected from Pt, Cu and Au can be used. Ni, Co,
Fe, Pd, Pt, if one or more kinds of elements selected from among Cu, and Au, the effect for accelerating crystallization of even trace amounts of amorphous silicon film. Among them, it is possible to obtain particularly most remarkable effect in the case of using Ni as a catalyst element. For this reason,
Models such as the following can be considered. The catalytic element alone does not act combines with Si acting on crystal growth by silicidation. This is a model in which the crystal structure at that time acts like a kind of template when the amorphous silicon film is crystallized, and promotes the crystallization of the amorphous silicon film. Specifically, Ni forms NiSi ₂ silicide with _two Sis. The NiSi ₂ shows the crystal structure of the fluorite type, the crystal structure was very similar to the diamond structure of single crystal silicon. In addition, NiSi ₂ has a lattice constant of 5.406 °, which is very close to the lattice constant of 5.430 ° in the diamond structure of crystalline silicon. Therefore, NiSi ₂ is the best as a template for crystallizing an amorphous silicon film, and it is most preferable to use Ni as a catalyst element.

In one embodiment of the present invention, the second amorphous silicon film contains an element selected from Group V B.

[0049] According to the manufacturing method of the semiconductor device of this embodiment, since including a second amorphous silicon film is selected from Group 5 B element, the catalyst element of the crystalline silicon film and the second non moving efficiently well into amorphous silicon film, it is possible to improve the gettering effect. In other words, in order to increase the gettering effect of the catalyst element, it is necessary to add 5
It is very effective to contain an element selected from group B. This is because when the second amorphous silicon film contains an element selected from Group V B, the solid solubility of the catalyst element in the second amorphous silicon film is dramatically increased, This is because the movement of the catalyst element is performed at the same time due to the difference in the degree. That is, the two mechanisms and effects of gettering of the catalyst element can be simultaneously obtained,
In the crystalline silicon film to be the semiconductor element formation region, the concentration of the catalyst element in the film can be greatly reduced.

Further, the present invention relates to a method disclosed in Japanese Patent Application Laid-Open No. H11-31660.
As described in Japanese Patent Application Laid-Open Publication No. H10-207, a catalyst element is moved and gettered in a vertical direction (thickness direction) to a second amorphous silicon film formed on a crystalline silicon film to be a semiconductor element formation region. But the points are completely different. In the present invention, by using the rapid thermal annealing, the second gettering sink is used.
Gettering is possible even if the amorphous silicon film does not contain a Group V element such as phosphorus. This is because it has a defect-induced segregation gettering effect as described above. Also, in such gettering in the film thickness direction, the gettering distance (the distance to move the catalyst element) is only for the film thickness.
The distance is shorter than that in general gettering in a horizontal direction (a direction parallel to the surface of the substrate) as disclosed in Japanese Patent Application Laid-Open No. 34-294 and Japanese Patent Application Laid-Open No. 10-229048. As a result, gettering can be performed in a short time, and the matching with the rapid thermal annealing is very good. In a long-time annealing process, warpage or bending occurs when an inexpensive glass substrate is used.

Further, the present invention relates to the above-mentioned JP-A-10-2235.
No. 34 and JP-A-10-229048 are different from those of JP-A-10-229048 in that a mask for absorbing heat is used for heat treatment for irradiating strong light to selectively heat a silicon film. In contrast to using a film, the present invention uniformly anneals the entire substrate by rapid thermal annealing. Therefore, the present invention does not require an extra mask film as described in the above publication. It is important to uniformly heat-treat the entire substrate. For example, in Japanese Patent Application Laid-Open No. Hei 10-223534, a region covered with a strong light absorption mask is annealed intensively. Tribe B
The temperature in the region where the element is introduced does not rise sufficiently. In this case, it has been found that no sufficient gettering is obtained. For this reason, the inventors of Japanese Patent Application Laid-Open No. 10-223534 have continued the following Japanese Patent Application Laid-Open No. 10-2290.
No. 48 discloses the invention. JP-A-10-2290
In JP-A-48-48, a film for thermally absorbing strong light is formed on the entire surface, and the entire substrate, including the region into which Group V element B has been introduced, is to be uniformly annealed. Although this method has a higher gettering effect, formation of a mask film for heat absorption of strong light is an extra step. Also, the gettering effect is not yet sufficient with this method alone, and a plus α is required.

In one embodiment of the method of manufacturing a semiconductor device, the element selected from Group V B is one or more elements selected from P (phosphorus), As (arsenic) and Sb (antimony). it is.

[0053] According to the manufacturing method of the semiconductor device of this embodiment, as an element selected from the Group V B, it may be at least one element selected from among P, As and Sb. If at least one element selected from P, As, and Sb, the catalyst element in the crystalline silicon film can be efficiently moved, and a sufficient gettering effect can be obtained. Although no detailed knowledge has been obtained on the mechanism of this gettering,
It has been found that among the elements P, As and Sb, P has the highest effect.

In one embodiment of the present invention, the second amorphous silicon film contains two elements, P and B (boron).

[0055] According to the manufacturing method of the semiconductor device of this embodiment, on the second amorphous silicon film, in addition to P as the element selected from Group 5 B, when the further B also be included, larger gettering effect can be obtained. The second amorphous silicon film serving as a gettering sink, when also doped B not only P, it has been found that the mechanism of the gettering changes. That is, when the second amorphous silicon film contains only P, the diffusion transfer type gettering utilizing the difference in the solid solubility of the catalyst element with the non-doped non-gettering region is used. In addition, the inclusion of B makes it easier for the catalyst element to be precipitated at the gettering sink, and the defect or segregation-induced gettering action becomes dominant. This defect or segregation-inducing type gettering has higher gettering ability, but is more severe with respect to the annealing temperature because of the defect or segregation-inducing type. Since the high-speed thermal annealing is performed at a high temperature while leaving gettering sites such as defects, it is very effective against the defect / segregation-induced gettering action as described above. Therefore, the second
Amorphous silicon film by the inclusion P, and B, more can be obtained a gettering effect of a large catalytic element, it can be reduced in concentration of the catalytic element in the crystalline silicon film to be the semiconductor device forming region.

In one embodiment of the present invention, in the method of manufacturing a semiconductor device, the second amorphous silicon film is formed by using at least a SiH ₄ (silane) gas and a PH ₃ (phosphine) gas as material gases at a film forming temperature. formed by a plasma CVD method at 400 ° C. or less.

According to the method of manufacturing a semiconductor device of the above embodiment, the step of forming the second amorphous silicon film includes forming at least a SiH ₄ gas and a PH ₃ gas as material gases at a film forming temperature of 400 ° C. It is desirable to form it by a plasma CVD method at a temperature of not more than ℃. When phosphorus is contained in the second amorphous silicon film, an ion doping method is usually used. However, the temperature of the substrate becomes high at the time of ion doping, and the second amorphous silicon film may become microcrystalline. Many. When such microcrystallization is performed, the effect of the present invention is reduced. In addition, a plasma CVD method using a SiH ₄ gas and a PH ₃ gas as material gases at a deposition temperature of 400 ° C. or lower can obtain an amorphous silicon film in an almost complete amorphous state. The concentration can also be very high. Moreover, the plasma CV at a film forming temperature of 400 ° C. or less using SiH ₄ gas and PH ₃ gas as material gases.
Method D has a high processing capability and is suitable for mass production.

[0058] The method of manufacturing a semiconductor device of one embodiment, the second amorphous silicon film, using at least a SiH ₄ gas and PH ₃ gas and _B 2 _{H 6} (diborane) material gas and a gas, The film is formed by a plasma CVD method at a film formation temperature of 400 ° C. or lower.

According to the method of manufacturing a semiconductor device of the above embodiment, at least the SiH ₄ gas, the PH ₃ gas, and the B ₂ H ₆ gas are used as a material gas for forming the second amorphous silicon film. It is desirable to form by a plasma CVD method at a film formation temperature of 400 ° C. or lower. By doing so, a silicon film in an almost perfect amorphous state can be obtained, and the concentration of phosphorus and boron in the film can be made very high. Moreover, a film forming temperature of 400 ° C. using the above SiH ₄ gas, PH ₃ gas and B ₂ H ₆ gas as material gases.
The plasma CVD method described below has a high processing capability and is suitable for mass production.

In one embodiment of the method of manufacturing a semiconductor device, the second amorphous silicon film is formed of Ar (argon), Kr
(Krypton) and one or more rare gas elements selected from Xe (xenon).

According to the method of manufacturing a semiconductor device of the above embodiment, one of the methods for improving the gettering effect using the second amorphous silicon film is selected from Ar, Kr, and Xe. It is also very effective to include one or more kinds of rare gas elements in the second amorphous silicon film serving as a gettering sink. If one or more rare gas elements selected from Ar, Kr, and Xe are present in the second amorphous silicon film serving as the gettering sink, a large interstitial distortion occurs at the location where the rare gas elements are present. Defects caused by rapid thermal annealing, which is a feature of the invention,
The segregation-inducing type gettering works extremely strongly. This is a well-known technique in the field of ICs using Si wafers. By the presence of the rare gas element in the second amorphous silicon film, the crystal growth of the second amorphous silicon film is inhibited, and the incubation period until crystal growth (generation of crystal nuclei) becomes longer, This has the effect of slowing down the crystal growth rate of the second amorphous silicon film. This allows
At the time of the rapid thermal annealing treatment, the second amorphous silicon film serving as a gettering sink can be kept in an amorphous state for a longer time, and a larger defect-induced gettering action can be obtained. it can. Therefore, Ar, Kr,
The inclusion of one or more rare gas elements selected from Xe in the second amorphous silicon film is a very effective means that is consistent with the concept and purpose of the present invention.
Among the rare gas elements, the most effective is Ar gas.
, And the when using Ar, can be obtained the greatest effect. That is, it is possible to increase significantly the gettering effect by the second amorphous silicon film.

As a method of forming the second amorphous silicon film containing the rare gas element, an amorphous silicon film formed by a plasma CVD method may be formed by adding one kind selected from Ar, Kr and Xe. Alternatively, a method of forming a second amorphous silicon film by doping a plurality of types of rare gas elements by an ion doping method is preferable. In the second amorphous silicon film obtained by doping and introducing a rare gas element after the amorphous silicon film is formed first, interstitial distortion is further increased. Thus, a higher gettering effect can be obtained by using the second amorphous silicon film. The material gas for doping at this time is a rare gas and has a purity of 1%.
Since it is 00%, the processing capability (throughput) of doping is also very high.

[0063] The method of manufacturing a semiconductor device of an embodiment, between the crystalline silicon film and the second amorphous silicon film, an etching stopper when removing the second amorphous silicon film a barrier film comprising a.

According to the method of manufacturing a semiconductor device of the above embodiment, a second amorphous silicon film is provided on the crystalline silicon film, and the catalyst element is moved to the second amorphous silicon film. However, after the gettering of the catalytic element, the second amorphous silicon film serving as the gettering sink is unnecessary for the semiconductor device. Therefore, it is necessary to remove the second amorphous silicon film. At this time, the second amorphous silicon film is removed so as to leave a lower crystalline silicon film with respect to the second amorphous silicon film. it is necessary to remove the only quality silicon film. For this purpose, the crystalline silicon film and the second
It is desired to perform an etching process having an etching selectivity close to 100% with the amorphous silicon film. However, since the same silicon film-based material is used, the selective etching is impossible. Therefore, it is effective to provide a barrier thin film serving as an etching stopper when removing the second amorphous silicon film between the crystalline silicon film and the second amorphous silicon film. The barrier film of this time, as an etching stopper when removing the second amorphous silicon film, but it is of course need to have a sufficient etching selection ratio, a crystalline silicon film move through the barrier film into the second amorphous silicon film of the catalytic element needs to be performed. If the barrier thin film hinders the movement at this time, sufficient movement of the catalyst element to the second amorphous silicon film serving as a gettering sink is not performed.
A sufficient gettering effect cannot be obtained. Therefore, as the barrier film provided between the crystalline silicon film and the second amorphous silicon film, it is desirable to use the following silicon oxide film thickness 50 Å. With such a barrier thin film, the barrier thin film enables selective etching and does not hinder the movement of the catalytic element. Further, if the thickness of the barrier thin film is more than 50 °, sufficient movement of the catalytic element between the crystalline silicon film and the second amorphous silicon film is not performed,
A high gettering effect cannot be obtained.

In one embodiment of the present invention, in the method of manufacturing a semiconductor device, the second amorphous silicon film is provided on the crystalline silicon film whose crystallinity has been improved by laser light irradiation.

According to the method of manufacturing a semiconductor device of the above embodiment, a method of further improving the crystallinity of a crystalline silicon film crystallized by the above catalyst element and further improving the performance of the semiconductor device, particularly the current driving capability. the further or subjected to heat treatment at a high temperature in an oxidizing atmosphere with respect to the crystallized crystalline silicon film by the catalytic element, or it is effective to irradiate a laser beam to the crystalline silicon film . In the former method of further improving the crystallinity of the crystalline silicon film by performing the heat treatment in an oxidizing atmosphere at a high temperature, the crystalline silicon film crystallized by the catalyst element is heated at a higher temperature (800 ° C. When the oxidation treatment is performed at 1100 ° C.), supersaturated Si atoms generated by the oxidation are supplied into the crystalline silicon film and enter crystal defects (particularly dangling bonds) in the crystalline silicon film. Thereby, the crystal defect can be eliminated. However, in such a method, an inexpensive glass substrate cannot be used as a substrate. From that viewpoint, the latter method of irradiating laser light is more effective.

When the crystalline silicon film crystallized by the above-mentioned catalyst element is irradiated with laser light, a difference in melting point between the crystalline silicon film and the amorphous silicon film causes a grain boundary portion or minute residual non-uniformity. The crystalline region (uncrystallized region) is intensively treated. However, in a crystalline silicon film formed by a normal solid-phase growth method, the crystalline structure is in a twinned state, and thus after irradiation with strong light. Also remains as twin defects inside the crystal grains. In contrast, the crystalline silicon film crystallized by the catalytic element is formed by columnar crystals, the inside thereof because of the single-crystal state, if the crystal grain boundary portion by the irradiation of strong light is processed entire substrate Thus, a high-quality crystalline silicon film close to a single crystal state can be obtained, and its effectiveness is extremely high from the viewpoint of crystallinity.
Further, since it is performed with a laser irradiation with respect to the crystal silicon film originally having a crystallinity, by laser irradiation directly to the amorphous silicon film, unlike the method of crystallizing the amorphous silicon film, laser variation of irradiation is significantly alleviated, not caused problems on uniformity. However, the step of performing such a laser beam irradiation treatment is performed before the step of providing the second amorphous silicon film on the crystalline silicon film to be a semiconductor element formation region.
That is, before gettering a catalytic element into the second amorphous silicon film, it is desirable to perform. This is because, when irradiated with a laser beam to the crystalline silicon film obtained in the solid-phase crystallization by the catalyst element, a change in the existing form of the catalyst element occurs. To be specific, it mean that aggregation and reaggregation as a silicide occurs. It is desirable that the gettering step of removing the catalytic element from the crystalline silicon film be performed after the crystalline state of the crystalline silicon film is completely solidified, so that ideal gettering can be performed. Conversely, when performing the process that promotes crystallinity of the crystalline silicon film after gettering, the catalytic element which remains dissolved after gettering will silicided by re-agglomeration. When a semiconductor element is formed using the semiconductor element formation region containing the silicidized catalyst element, there is a possibility that the semiconductor element is adversely affected.

[0068] The method of manufacturing a semiconductor device of one embodiment, the concentration of the catalytic element in the semiconductor device forming region,
1 × 10 ¹⁶ atoms / cm ³ to 2 × 10 ¹⁷ atoms
ms / cm ³ .

[0069] According to the manufacturing method of the semiconductor device of this embodiment, to reduce as much as possible the catalytic element amount remaining in the semiconductor device forming region, high reliability performance, to realize a semiconductor device with high stability It is intended to be. For this purpose, the concentration of the catalyst element in the semiconductor device formation regions of the finally obtained semiconductor device, 1 × 10 16 ^atoms /
It may be in the range of cm ^{3 to} 2 × 10 ¹⁷ atoms / cm ³ . By setting the concentration of the catalyst element in the semiconductor element formation region to 2 × 10 ¹⁷ atoms / cm ³ or less, there is no electrical adverse effect of the catalyst element on the characteristics of the semiconductor element. As a result of using the method for manufacturing the semiconductor device of the present invention, it is possible to realize such a low concentration. In addition, as long as crystallization is performed using the above catalyst element,
Catalytic element concentration of least 1 × 10 16 ^atoms / cm ³ remains in the semiconductor device forming region, be reduced to less is not possible even with any method conceivable situation. Therefore, as a result of crystallization using the above catalyst element, at least 1 × 10 ¹⁶ atoms
/ Cm ³ or more concentrations of the catalyst element remains in the semiconductor device forming region.

[0070]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIGS.
FIG. 2G is a process sectional view illustrating the method for manufacturing the semiconductor device of the first embodiment of the present invention. In the first embodiment, the present embodiment relates to a process for manufacturing an N-type TFT on a glass substrate. a description will be given with respect to the case of utilizing the invention. The above N-type TF
T can be used not only as a driver circuit and a pixel portion of an active matrix type liquid crystal display device but also as an element constituting a thin film integrated circuit. Incidentally, according to the manufacturing method of the semiconductor device, FIG. 1 (a), (b), ...,
The steps sequentially proceed in the order of (g).

Hereinafter, a method for manufacturing the semiconductor device will be described.

First, as shown in FIG. 1A, a base film 102 made of silicon oxide having a thickness of about 300 to 500 nm is formed on a glass substrate 101 as a substrate having an insulating surface by, for example, a plasma CVD method. The base film 102, the impurity of the glass substrate 101 to the layer stacked on the glass substrate 101 is provided to prevent the diffusion.

Subsequently, by the plasma CVD method,
Intrinsic (I-type) first amorphous silicon film (a-Si film) 103 having a thickness of 20 nm to 80 nm, for example, 40 nm
Is formed on the base film 102. In the first embodiment, a parallel plate type plasma CVD apparatus is used, and the heating temperature is set to 30.
At 0 ° C., silane (SiH ₄ ) gas and hydrogen (H ₂ ) gas are used as material gases. Then, the power density of the RF power ^{10mW / cm 2 ~200mW / cm 2} , for example, in the 80 mW / cm ^2, the first amorphous silicon film 103
The formation of.

Then, the first amorphous silicon film 103
On the surface of, performing slight amount of nickel 104 as a catalyst element. This small amount of nickel 104 is added by holding a solution in which nickel is dissolved on the first amorphous silicon film 103, and using the solution to spin the first amorphous silicon film 1 by a spinner.
03 and uniformly dried. In the first embodiment, nickel acetate is used as a solute of the solution, and water is used as a solvent of the solution.
Nickel concentration in the solution is adjusted to be 10 ppm. Further, the first amorphous silicon film 103
Total reflection X-ray fluorescence analysis (TRX)
As measured by RF) method, the nickel concentration is 7 × 1
0 was ¹² atoms / cm ² about.

Next, under an inert atmosphere, a heat treatment at e.g. nitrogen performed. In this heat treatment, first, a hydrogen desorption treatment in the first amorphous silicon film 103 is performed during the temperature rise, and then the first amorphous silicon film 103 is heated at a higher temperature.
Is being crystallized. Specifically, an annealing treatment is performed at 450 ° C. to 520 ° C. for 1 hour to 2 hours as a first step heat treatment, and a 5 hour heat treatment is performed as a second step heat treatment.
For 2 to 8 hours annealing at 20 ° C. to 570 ° C.. In the first embodiment, for example, at 500 ° C., 1
After performing the heat treatment for 4 hours, heat treatment is performed at 550 ° C. for 4 hours. Thus, the first amorphous silicon film 1
03 is diffused into the first amorphous silicon film 103 and the amorphous silicon film 1
The silicide is generated in the silicon oxide film 03, and crystallization of the first amorphous silicon film 103 proceeds with the silicide as a nucleus. Then, as shown in FIG. 1B, the amorphous silicon film 103 is crystallized to become a crystalline silicon film 103a.

Next, the crystalline silicon film 103a is irradiated with a laser beam 105 to thereby form the crystalline silicon film 103a.
3a is recrystallized to improve the crystallinity of the crystalline silicon film 103a. The laser beam 105 has a wavelength of 308 n
m, XeCl of pulse width 40nsec (xenon chlorine)
Irradiation is performed using an excimer laser device. The irradiation conditions of the laser beam 105 are as follows:
Is heated to 200 ° C. to 450 ° C., for example, 400 ° C., and the energy density is 250 mJ / cm ^{2 to} 450 mJ / cm ² ,
For example, irradiation is performed at 350 mJ / cm ² . The beam size of the laser light 105 is set to be 150 mm × 1 mm long on the surface of the glass substrate 101, and 0.05 mm in a direction perpendicular to the long direction.
Were sequentially scanned at a step width of That is, laser irradiation is performed a total of 20 times at any one point of the crystalline silicon film 103a. In this manner, the crystalline silicon film 103a obtained by the solid-phase crystallization, crystal defects are reduced by melt solidification process of laser irradiation, a higher quality crystalline silicon film 103b.

Next, the surface layer of the crystalline silicon film 103b is thinly oxidized to form a silicon oxide film 106 as a barrier thin film serving as an etching stopper, as shown in FIG. 1C. The formation of the silicon oxide film 106 is performed by holding ozone water on the surface of the crystalline silicon film 103b. At this time, the ozone concentration in the ozone water is desirably 5 mg / l or more. In the first embodiment, the ozone concentration in the ozone water is, for example, 8 m / l.
g / l. Further, the crystalline silicon film 103b
The holding time of the ozone water on the surface of is, for example, 1 minute. To form a more dense silicon oxide film 106,
Before the ozone water treatment, it is desirable to keep a natural oxide film on the surface of the crystalline silicon film 103b, performing hydrofluoric acid cleaning before the ozone water treatment, even the first embodiment, the active silicon film surface Is exposed, and then treatment with ozone water is performed. Silicon oxide film 1 thus formed
06 of the film thickness was measured by spectroscopic ellipsometry, the film thickness was about 30Å.

Next, a second amorphous silicon film is formed on the silicon oxide film 106 by plasma CVD at a film formation temperature of 400 ° C. or less. This second amorphous silicon film is
Non-doped (intrinsic) amorphous silicon film 1
07 and an amorphous silicon film 108 formed on the amorphous silicon film 107 and containing phosphorus (P). The non-doped amorphous silicon film 107 is formed by a plasma CVD method so as to cover the silicon oxide film 106. Then, an amorphous silicon film 108 containing phosphorus is laminated on the amorphous silicon film 107 by using a plasma CVD method. In the first embodiment, the amorphous silicon film 107 and the amorphous silicon film 108 are not exposed to the air using a multi-chamber plasma CVD apparatus.
Are formed continuously. The amorphous silicon film 107 is a gettering sink for nickel, and diffuses phosphorus from the amorphous silicon film 108 to the crystalline silicon film 103b.
It also plays the role of a buffer layer to prevent contamination.
For the formation of the amorphous silicon film 107 at this time, the substrate heating temperature was set to 350 ° C., and silane gas and hydrogen gas were used as material gases. In forming the amorphous silicon film 108, a silane gas and a phosphine (PH ₃ ) gas are used as material gases. At this time, the concentration of phosphorus in the amorphous silicon film 108 can be arbitrarily changed by the flow rate ratio of the phosphine gas. In the first embodiment,
The PH ₃ / SiH ₄ flow ratio is set to 3/100. At this time, the phosphorus concentration in the amorphous silicon film 108 is about 1%.

Next, high-speed thermal annealing is performed in an inert atmosphere, for example, in a nitrogen atmosphere. In the high-speed thermal annealing treatment at this time, the temperature rise starts from a preheating temperature of 550 ° C. or less, and at least 30 ° C./min or more, preferably 10 ° C. or more.
It is desirable that the temperature is raised at a rate of 0 ° C./min or more. The main heating to be performed after the temperature rise in the high-speed thermal annealing treatment is performed at a temperature of 600 ° C. to 750 ° C.
It is preferably carried out in seconds to 15 minutes, 650 ° C. to 700
More preferably, the temperature is 1 minute to 10 minutes at a temperature of ° C. Further, in the first embodiment, since the glass substrate 101 is used, the temperature is reduced from the temperature of the main heating to at least 550 ° C. in order to prevent the glass substrate 101 from warping and shrinkage (thermal shrinkage or thermal expansion). The speed is 100 ° C /
It is desirable that it be less than minutes. By doing this,
The warpage of the glass substrate 101 does not occur, and the shrinkage value can be suppressed to 25 ppm or less within a practical range.
Indeed in the first embodiment, as shown in FIG. 7 (a),
The glass substrate 101 from preheat state to 400 ° C., rising rate of 138 ° C. / min temperature, by performing the heating for approximately 2 minutes,
Increase the temperature of the main heating to 675 ° C. And that 6
After the main heating of 75 ° C. 3 min, cooling rate 69 ° C.
The temperature is lowered to 400 ° C. by lowering the temperature for about 4 minutes per minute, and further lowered to 200 ° C. from 400 ° C. by lowering the temperature to 200 ° C. for 1 minute. In the first embodiment, although not shown, a resistive heating furnace is used. A temperature gradient is created in this resistance heating furnace, and the glass substrate 10
By controlling the speed at which the sample No. 1 was inserted into the resistance heating furnace, a high-speed thermal annealing process having a temperature profile shown in FIG. 7A was realized. At this time, the glass substrate 10
The point 1 is to process one sheet at a time and to minimize the heat capacity when inserting the resistive superheater into the furnace. The high-speed thermal annealing is performed by uniformly spraying a high-temperature heated N ₂ gas on the surface of the glass substrate 101, and a high-temperature heating rate that cannot be obtained only by heat radiation. 101, and soaking properties within the surface. As an advantage of using a single-wafer type resistive heating furnace combined with such high-temperature gas heating, the temperature of each part of the glass substrate 101 can be increased and decreased while the temperature of each part is kept uniform. It is unlikely to occur. In addition, it is possible to control the temperature rising / falling rate with very high control, and it is more suitable for use of the glass substrate 101 than other lamp irradiation methods.

The amorphous silicon film 107 and the phosphorus-containing amorphous silicon film 108 are not completely crystallized by the above-mentioned rapid thermal annealing, and the amorphous silicon films 107 and 108 are not crystallized.
Defects serve as segregation traps for nickel, and nickel 104 in the crystalline silicon film 103b is removed as shown in FIG.
In the direction indicated by arrow 109. At this time, in the phosphorus-containing amorphous silicon film 108, a gettering effect of nickel by phosphorus is added, and the amorphous silicon film 108 acts as a more intense gettering sink. In this case nickel moves through the silicon oxide film 106 of the thin film, but a silicon oxide film 106 having a film thickness of about 30Å is not an obstacle to its movement. Thereby, most of the nickel in the crystalline silicon film 103b moves to the amorphous silicon film 107 and the amorphous silicon film 108 containing phosphorus, and the nickel concentration of the amorphous silicon films 107 and 108 is increased. Will be higher. Conversely, the nickel concentration in the crystalline silicon film 103b is much lower, low nickel concentrations high quality crystalline silicon film 10
3c is obtained. At this time, the actual crystalline silicon film 10
The nickel concentration in 3c was determined by secondary ion mass spectrometry (SI
MS) and 5 × 10 ¹⁶ atoms /
cm ³ . By the way, in the case of the conventional method which does not use the rapid thermal annealing as in the present invention, it is about 2 × 10 ¹⁷ atoms / cm ³ . Nickel concentration in the film of the crystalline silicon film 103b is 1 × 1
0 ¹⁸ atoms / cm ³ , and the high-speed thermal annealing reduced the residual nickel concentration to about 1/20. At this stage, the nickel remaining in the crystalline silicon film 103c is not in a silicide state but in a solid solution state, so that there is no problem in electrical characteristics of the TFT.

Next, the above-mentioned nickel is gettered to form amorphous silicon films 107 and 108 having a high nickel concentration.
Is entirely removed by etching. In the etching at this time, an etchant having a sufficient etching selectivity with the silicon oxide film 106 is required so that the silicon oxide film 106 sufficiently functions as an etching stopper. In the first embodiment, a strong alkaline solution such as a developer is used. After removal of the amorphous silicon film 107 and 108,
The silicon oxide film 106 is removed by etching. At this time,
Wet etching is performed using a 1: 100 buffered hydrofluoric acid (BHF), which has a sufficiently lower crystalline silicon film 103c and selectivity, as an etchant.

Thereafter, unnecessary portions of the crystalline silicon film 103c are removed to perform element isolation, and as shown in FIG. 1E, an island-shaped semiconductor element forming region (for forming a TFT) is formed. a source region, drain region, channel region) 1
10 are formed.

Next, as shown in FIG. 1F, a gate insulating film 111 made of silicon oxide and having a thickness of 20 nm to 150 nm, for example, 100 nm is formed to cover the semiconductor element formation region 110. The gate insulating film 111
After forming the gate insulating film 111 itself bulk properties,
And the semiconductor element forming region 110 and the gate insulating film 11
Annealing was performed at 500 ° C. to 600 ° C. for 1 hour to 4 hours in an inert gas atmosphere in order to improve the interfacial properties with respect to 1. In the formation of the gate insulating film 111 according to the first embodiment, TEOS (Tetra Ethoxy Ortho Silicate) is used as a raw material, and is used together with oxygen at a substrate temperature of 150 ° C. to 600 ° C.
RF plasma CVD preferably at 300 ° C. to 450 ° C.
It is decomposed and deposited by law. The gate insulating film 11
1 is formed by using TEOS as a raw material and using it as an ozone gas at a substrate temperature of 350 ° C. to 600 ° C., preferably 400 ° C.
C. to 550.degree. C. may be formed by a low pressure CVD method or a normal pressure CVD method.

[0084] Then, by a sputtering method,
An aluminum film having a thickness of 400 nm to 800 nm, for example, 600 nm is formed over the gate insulating film 111. Then, the gate electrode 112 is formed by patterning the aluminum film into a desired shape. Further, the surface layer of the gate electrode 112 is anodized to form an oxide layer 113. When the gate electrode 112 is used as, for example, a gate electrode of a pixel TFT on an active matrix substrate, the gate electrode 112 also constitutes a gate bus line in plan view. The anodic oxidation is performed in an ethylene glycol solution containing tartaric acid at 1% to 5%. The voltage is first increased to 220 V at a constant current, and the state is maintained for 1 hour to end the process. The thickness of the oxide layer 113 thus obtained is 200 nm. Note that since the oxide layer 113 has a thickness for forming an offset gate region in a later ion doping step,
The length of the offset gate region may be determined in the above anodization step.

Next, phosphorus as an impurity is implanted by ion doping using the gate electrode 112 and the oxide layer 113 around the gate electrode 112 as a mask. Thus, impurity diffusion regions of the N type which the phosphorus is implanted 115
Are regions to be used as a source region and a drain region of the TFT, and include a gate electrode 112 and an oxide layer 113 around the gate electrode 112.
Region 114, which is masked by
This is a region to be a T channel region. Embodiment 1
In using a phosphine as a doping gas, the acceleration voltage 60KV～90kV, for example 80 kV, and the dose amount ^{1 × 10 15 cm-2~8 ×} 10 15 cm -2, for example, 2 × ¹⁰ 15 ^{cm -2.}

Thereafter, an annealing process is performed by irradiation with the laser beam 120 to activate the ion-implanted impurity phosphorus, and at the same time, to improve the crystallinity of the portion where the crystallinity has deteriorated in the impurity introducing step. The laser device used at this time is an X-ray having a wavelength of 308 nm and a pulse width of 40 nsec.
It is an eCl excimer laser device, and the energy density of the laser beam 120 is 150 mJ / cm ^{2 to} 400 mJ / c.
m ^2, preferably 200mJ ^/ cm 2 ~250mJ ^/ c
a m ^2. The sheet resistance of the N-type impurity diffusion regions 115 and 116 thus formed is 200Ω / □ to 500Ω.
Ω / □.

Subsequently, in order to form the interlayer insulating film 121 shown in FIG. 1G, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is laminated. In the case of laminating the silicon oxide film, TEOS is used as a raw material, and a plasma CVD method using the raw material and oxygen or a reduced pressure C using ozone is used.
When formed by the VD method or the normal pressure CVD method, a good interlayer insulating film 121 having excellent step coverage can be obtained. When a silicon nitride film formed by a plasma CVD method using silane gas and ammonia (NH ₃ ) gas as a source gas is used, the semiconductor element formation region 110 and the gate insulating film 11 are formed.
1 interface hydrogen atoms is supplied to the, the effect of reducing the dangling bonds that degrade the TFT characteristic.

Next, a contact hole is formed in the silicon oxide film or silicon nitride film to obtain an interlayer insulating film 121. And so as to fill the contact hole,
By stacking a metal material, for example, a titanium nitride film and an aluminum film, the electrodes and wirings 122 of the TFT 123 are formed. The titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. When the above-mentioned TFT 123 is used as a pixel TFT, the TFT 123 is an element for switching a pixel electrode.
2, a pixel electrode made of a transparent conductive film such as ITO is provided. In this case, the other electrode / wiring 122 constitutes a source bus line, a video signal is supplied via the source bus line, and a video signal is supplied to the pixel electrode based on a gate signal of the gate electrode 112 also serving as a gate bus line. The required charge is written.

Finally, at 350 ° C. in a hydrogen atmosphere of 1 atm.
Annealing is performed for one hour, to complete the TFT123. If necessary, a protective film made of a silicon nitride film or the like may be provided on the TFT 123 for the purpose of protecting the TFT 123.

The TFT 123 thus manufactured has a field effect mobility of about 250 cm ² / Vs and a threshold voltage of 1.
Despite the very high as about 5V, conventional abnormal increase without any frequently seen TFT off operation when the leakage current in the fabricated TFT by a method, the following 1pA per unit W Very low values were shown stably. This value is not much different from that of a conventional TFT formed without using a catalytic element, and the production yield was greatly improved. Further, even when the durability test is performed by repeated measurement or bias or temperature stress, almost no characteristic deterioration is observed, and the reliability is much higher than the conventional one.

Then, when the active matrix substrate for a liquid crystal display manufactured according to the first embodiment was actually evaluated for lighting, the display unevenness was clearly smaller than that of the active matrix substrate manufactured by the conventional method, and TFT leakage was caused. A pixel defect was extremely small, and a high display quality liquid crystal panel having a high contrast ratio was obtained.

The TFT 123 can be easily applied to a thin film integrated circuit or the like.
A contact hole may be formed thereover and a necessary wiring may be provided.

(Embodiment 2) FIGS. 2A to 2D and 3E to 3G are cross-sectional views showing steps of a method for manufacturing a semiconductor device according to Embodiment 2 of the present invention. In the second embodiment, an N-type TF which forms a peripheral driving circuit of an active matrix type liquid crystal display device and a general thin film integrated circuit is used.
A circuit having a CMOS structure in which a T-type TFT and a P-type TFT are configured to be complementary is manufactured on a glass substrate. The method of manufacturing the semiconductor device is described in FIGS. 2 (a),.
The steps sequentially proceed in the order of (g).

First, as shown in FIG. 2A, a base film 202 made of silicon oxide having a thickness of about 300 to 500 nm is formed on a glass substrate 201 as a substrate having an insulating surface by, for example, a sputtering method. The base film 202 is provided to prevent impurities of the glass substrate 201 from diffusing into a layer stacked on the glass substrate 201.

Next, the thickness 2 is formed by the plasma CVD method.
0Nm～80nm, forming a first amorphous silicon film 203 of for example 40nm intrinsic (I type). Embodiment 2
Here, a parallel plate type plasma CVD apparatus is used, the heating temperature is set to 300 ° C., and silane gas and hydrogen gas are used as material gases. And the power density of the RF power is 10 m
W / cm ^{2 to} 200 mW / cm ² , for example, 80 mW / c
It is carried out with the m ^2.

Next, on the surface of the first amorphous silicon film 203, a trace amount of nickel 204 as a catalyst element is added. This addition of a small amount of nickel 204 is performed by holding a solution in which nickel is dissolved on the first amorphous silicon film 203, and using the spinner to deposit the solution.
03 and uniformly dried. In the second embodiment, nickel acetate is used as a solute of the solution, and ethanol is used as a solvent of the solution. The nickel concentration in the solution is adjusted to be 1 ppm. The nickel concentration on the surface of the first amorphous silicon film 203 measured by total reflection X-ray fluorescence analysis was about 5 × 10 ¹² atoms / cm ² .

Then, heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere. As this heat treatment, 520
It is desirable to perform annealing at 2 to 8 hours at a temperature of 5 to 570 ° C. In the second embodiment, for example, 55
Heat treatment is performed at 0 ° C. for 4 hours. Thus, occur silicidation of the first amorphous silicon nickel 204 is added on the surface of the film 203, a silicide nickel crystallization of the first amorphous silicon film 203 progresses as nuclei As shown in FIG. 2B, a crystalline silicon film 203a is formed. However, the amount of the nickel 204 added is such that the amount of the catalytic element is insufficient to crystallize the entire amorphous silicon film 203 and the crystalline silicon film 20
A minute (about several μm) amorphous region remains in a part of 3a, and crystal growth is stopped. At a temperature of 570 ° C. or lower, the crystal growth of the silicon film itself does not occur, so that an uncrystallized region that does not reach the crystal growth remains as it is. In short, the crystalline silicon film 203a obtained after the heat treatment at 550 ° C. for 4 hours in Embodiment Mode 2 has a state in which minute amorphous regions are mixed in the crystallized regions.

Next, laser is applied to the crystalline silicon film 203a.
By irradiating the light 205, the crystalline silicon film 20
3a is further crystallized to obtain a crystalline silicon film 203b.
You. The laser light 205 has a wavelength of 308 nm and a pulse width of 308 nm.
Using a 40 nsec XeCl excimer laser device
Fired. The irradiation conditions of the laser light 205 are as follows.
When the glass substrate 201 is irradiated at 200 ° C. to 450 ° C., for example,
Heat to 400 ° C, energy density 200mJ / cm²~
450mJ / cm², For example, 350 mJ / cm ²Do
That is. The beam size of the laser beam 205 is
Long shape of 150 mm x 1 mm on the surface of the lath substrate 201
Is set so that it is perpendicular to the long direction.
Scanning was sequentially performed in the direction with a step width of 0.05 mm. You
That is, at any one point of the crystalline silicon film 203a,
Thus, a total of 20 laser irradiations are performed. This
Remains in the crystalline silicon film 203a by the laser irradiation of
The amorphous region that has been melted preferentially
The entire film is crystallized by reflecting only favorable crystal components.

[0099] Next, the surface layer of the crystalline silicon film 203b by thin oxidized to form a silicon oxide film 206 as a barrier thin film as an etching stopper. The formation of the silicon oxide film 206, the crystalline silicon film 203
This is performed by irradiating the surface of b with excimer UV (ultraviolet) light. The irradiation time of the excimer UV light was 1 minute, and the film thickness of the silicon oxide film 206 was measured by spectroscopic ellipsometry.

Next, as shown in FIG. 2C, a second film containing phosphorus and boron (B) is formed so as to cover the silicon oxide film 206 by a plasma CVD method at a film forming temperature of 400 ° C. or lower. An amorphous silicon film 208 is formed. In the second embodiment, a parallel plate type plasma CVD apparatus is used, the substrate heating temperature is set to 350 ° C., and silane gas, phosphine gas, and diborane (B ₂ H ₆ ) gas are used as material gases.
Of the amorphous silicon film 208 is formed. On this occasion,
The concentration of phosphorus and boron in the second amorphous silicon film 208 can be arbitrarily changed by the flow ratio of these three gases. In the second embodiment, PH ₃ / B
_The flow rate ratio of ₂ H ₆ / SiH ₄ was set to 3/1/100. At this time, the phosphorus concentration in the second amorphous silicon film 208 was about 1.0%, and the boron concentration was about 0.5%.

Next, high-speed thermal annealing is performed in an inert atmosphere, for example, in a nitrogen atmosphere. In the high-speed thermal annealing treatment at this time, the temperature rise starts from a preheating temperature of 550 ° C. or less, and at least 30 ° C./min or more, preferably 10 ° C. or more.
It is desirable that the temperature be raised at a rate of 0 ° C./min or more. The main heating to be performed after the temperature rise in the high-speed thermal annealing treatment is performed at a temperature of 600 ° C. to 750 ° C.
It is preferably carried out in seconds to 15 minutes, 650 ° C. to 700
More preferably, it is carried out at a temperature of 1C for 1 minute to 10 minutes. In the second embodiment, since the glass substrate 201 is used, the rate of temperature decrease from the temperature of the main heating to at least 550 ° C. is taken in consideration of the warpage of the glass substrate 201 and measures against shrinkage (thermal shrinkage or thermal expansion). 100 ℃ /
It is desirable that it be less than minutes. By doing this,
The warpage of the glass substrate 201 does not occur, and the shrinkage value can be suppressed to 25 ppm or less in a practical range. Actually, in the second embodiment, as shown in FIG.
By raising the temperature at a rate of 200 ° C./min for 1 minute, the temperature of the main heating is increased to 700 ° C. And 7
After the main heating of 00 ° C for 1 minute, the temperature decreasing rate is 50 ° C
The temperature is lowered to 500 ° C. for 4 minutes per minute. Further, the temperature is lowered at 200 ° C./min for 1 minute to lower the temperature from 500 ° C. to the substrate taking-out temperature of 300 ° C. In Embodiment 2, a temperature gradient is formed in the resistance heating furnace using a resistance heating furnace, and the speed at which the glass substrate 201 is inserted into the resistance heating furnace is controlled. High-speed thermal annealing with the temperature profile shown is realized. At this time, the point is that the glass substrates 201 are processed one by one, and the heat capacity when the glass substrates 201 are inserted into the resistance heating furnace is made as small as possible. In the high-speed thermal annealing treatment, a nitrogen (N ₂ ) gas heated at a high temperature is uniformly sprayed on the surface of the glass substrate 201, so that a high-speed heating rate that cannot be obtained only by thermal radiation and a high-speed heating The temperature uniformity within the surface of the glass substrate 201 is obtained. An advantage of using a single-wafer type resistive heating furnace that uses such high-temperature gas heating is that the temperature of each part of the glass substrate 21 can be raised and lowered while the temperature of each part is kept uniform.
Is hardly distorted. Further, it is possible to control the temperature rising / falling rate with very high control, and it is more suitable for use of the glass substrate 201 than other lamp irradiation methods.

By the above-described rapid thermal annealing, the second amorphous silicon film 208 is not completely crystallized, and its defects serve as segregation traps for nickel, and the nickel 204 in the lower crystalline silicon film 203b is removed. 2C is pulled out in a direction indicated by an arrow 209 in FIG. At this time, this gettering effect is greatly enhanced by the action of phosphorus and boron, and acts as a more intense gettering sink. At this time, nickel moves through the thin silicon oxide film 206, but the silicon oxide film 206 having a thickness of about 30 ° does not hinder the movement. As a result, most of the nickel in the crystalline silicon film 203b moves to the second amorphous silicon film 208, and the nickel concentration in the second amorphous silicon film 208 increases. Conversely, the nickel concentration of the crystalline silicon film 203b is significantly reduced, and a high-quality crystalline silicon film 203c having a low nickel concentration is obtained. At this time, the actual nickel concentration in the crystalline silicon film 203c was 4 × 10 ¹⁶ atoms / cm ^{3 as} measured by secondary ion mass spectrometry.
To a degree. Incidentally, in the case of the conventional method not using the rapid thermal annealing treatment as in the present invention, 2 ×
It is about 10 ¹⁷ atoms / cm ³ . The nickel concentration in the crystalline silicon film 203b is 1 × 10
¹⁸ atoms / cm ³ and about 1 atom / cm ^{3 according} to the present invention.
The residual nickel concentration could be reduced to / 20.
At this stage, the nickel remaining in the crystalline silicon film 203c is not in a silicide state but in a solid solution state, so that there is no problem in electrical characteristics of the TFT.

Next, the nickel is gettered, and the entire surface of the second amorphous silicon film 208 having a high nickel concentration is removed by etching. Etching at this time requires an etchant having a sufficient etching selectivity with the silicon oxide film 206 so that the silicon oxide film 206 sufficiently functions as an etching stopper. In the second embodiment, a strong alkaline solution such as a developer is used. After removing the second amorphous silicon film 208,
The silicon oxide film 206 is removed by etching. At this time,
The etching is performed by wet etching using a 1: 100 buffered hydrofluoric acid, which is sufficiently selective with the lower crystalline silicon film 203c, as an etchant.

Thereafter, the crystalline silicon film 203c is patterned into a desired shape to leave semiconductor element forming regions 210n and 210p for forming a TFT as shown in FIG. The region is removed by etching to separate elements.

Next, the semiconductor element formation region 210n,
To cover 210p, as shown in FIG. 3E, it is made of silicon oxide and has a thickness of 20 nm to 150 nm, for example, 1 nm.
The gate insulating film 211 is formed to have a thickness of 00 nm. The gate insulating film 211 of the second embodiment is formed by using TEOS as a raw material and using it as a substrate at a substrate temperature of 150 ° C. to 600 ° C. together with oxygen.
C, preferably 300-450 C, RF plasma C
Decomposed and deposited by VD method.

Subsequently, a high-melting point metal is deposited on the gate insulating film 211 by a sputtering method, and this is patterned and formed into a desired shape.
2n, 212p. At this time, the high melting point metal is preferably tantalum (Ta) or tungsten (W). In the second embodiment, the gate electrodes 212n and 212p each having a thickness of 300 nm to 600 nm, for example, 450 nm are formed using Ta to which a slight amount of nitrogen is added.

Next, the gate is formed by ion doping.
Using the electrodes 212n and 212p as masks,
Is injected. Doping at this time is
So-called through doping over the gate insulating film 211
Applied. Phosphine is used as a doping gas.
The doping conditions used are an acceleration voltage of 60 kV-
90 kV, for example, 80 kV, and the dose amount is 2 × 10
^Fifteencm^-2~ 8 × 10 ^Fifteencm^-2, For example, 5 × 10
^Fifteencm^-2And By the injection of phosphorus 217,
Is masked by the gate electrodes 212n and 212p,
The regions 214n and 215p into which is not implanted are TFT chips.
This is the area that should be the channel area. Also phosphorus is injected
N-type impurity diffusion regions 215n, 216n, 215n
, 216n 'of the impurity diffusion regions 215n, 216
Is the region to be the source and drain regions of the N-type TFT
It is. Further, the impurity diffusion regions 215n ', 216
n ′ is all in the source region and the drain region of the P-type TFT.
Area due to phosphorus ion implantation.
N type. Therefore, the impurity diffusion region 2
15n 'and 216n' must be P-type in the later process
Must be.

Next, a photolithography step is performed.
As shown in FIG. 3F, the region 214n and the impurity
In the photoresist above the diffusion regions 215n and 216n
To form a mask 219 for selective doping.
You. After that, the mask 219 and the gate electrode 212p are removed.
Ion implantation of boron 218 using as a mask
And an impurity diffusion region 215 into which boron 218 has been implanted.
p, 216p are obtained. At this time, doping gas and
And diborane (B₂H₆), And 40 kV to 80 k
V, for example, at an accelerating voltage of 65 kV, 1 × 10¹⁶cm
^-2~ 5 × 10¹⁶cm ^-2, For example, 2 × 10¹⁶cm
^-2Doping at a high dose. This
And the previously doped N-type impurity phosphorus
And is inverted by excess boron to form P-type impurities.
Diffusion regions 215p and 216p are formed. So-called mosquito
Unter doping was performed. Like this
In the step of ion-implanting the element 218, the gate electrode 212
The region 214n contains boron because it is masked with p.
Not injected.

After removing the mask 219 for selective doping, heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere. In the second embodiment, the treatment was performed at 600 ° C. for 4 hours in a nitrogen atmosphere. This heat treatment activates the N-type impurity diffusion regions 215n and 216n and the P-type impurity diffusion regions 215p and 215p. When the sheet resistance is measured after the activation, the N-type impurity diffusion regions 215n and 216n
kΩ / □ to 0.8 kΩ / □, and P-type impurity diffusion regions 215 p and 216 p are 1.0 kΩ / □ to 2.0 kΩ / □.
It was □. In addition, the baking process of the gate insulating film 211 is performed at the same time, so that the bulk characteristics of the gate insulating film 211 itself and the interface characteristics between the semiconductor element formation regions 210n and 210p and the gate insulating film 211 can be improved. Further, by performing the heat treatment, the phosphorus doped in the impurity diffusion regions 215n, 216n, 215p, and 216p is converted into a region 214 to be a channel region.
The nickel remaining in n, 214p is moved to impurity diffusion regions 215n, 216n, 215p, 216p. That is, the region 21 to be the channel region again
It is possible to add gettering limited to 4n and 214p, and two-stage complete gettering can be performed together with the gettering described above. In addition, the heat treatment process can be performed by a high-speed thermal annealing process. In this case, the impurity diffusion regions 215n, 216n, 215p, and 2
Activation of 16p and region 2 to be channel region
More excellent results are obtained in the gettering effect of 14n and 214p.

Subsequently, in order to form an interlayer insulating film 221 as shown in FIG. 3G, a silicon oxide film having a thickness of, for example, 900 nm is laminated by a plasma CVD method.

Then, a contact hole is formed in the silicon oxide film, and the contact hole is filled.
By stacking a metal material, for example, a titanium nitride film and an aluminum film, electrodes / wirings 222 of the N-type TFT 223 and the P-type TFT 224 are formed. Finally, an annealing process is performed at 350 ° C. for 1 hour in a hydrogen atmosphere at 1 atm to form an N-type TFT 2.
23 and the P-type TFT 224 are completed. If necessary, contact holes may be provided on the gate electrodes 212n and 212p to connect the gate electrodes 212n and 212p to wiring. Further, the N-type TFT 223,
In order to protect the P-type TFT 224, the N-type TFT 22
3. A protective film made of a silicon nitride film or the like may be provided on the P-type TFT 224.

The CMO manufactured according to the above embodiment
In the S structure circuit, the field effect mobility is N-type TFT 22
3 in ^{200cm 2 / Vs~250cm 2 / Vs,} P -type T
FT224 in 100cm ² / Vs~130cm ² / Vs
The threshold voltage is about 1.5 V for the N-type TFT 223,
The P-type TFT 224 shows very good characteristics of about -2V. In addition, there was no abnormal increase in the leakage current during the TFT off operation, which was frequently seen in the conventional example, and the leakage current itself was stably shown as a very low value of 1 pA or less per unit W. This value is not much different from that of a conventional TFT formed without using a catalytic element, and the production yield was greatly improved. Further, even if the durability test by repeating the measurement and the bias or temperature stress, little characteristic degradation is not observed, very reliable as compared with the conventional, showed stable circuit characteristics.

(Embodiment 3) FIGS. 4 (a) to 4 (g)
FIG. 14 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention. The case where the present invention is used will be described.
The N-type TFT can be used not only as a driver circuit and a pixel portion of an active matrix type liquid crystal display device but also as an element constituting a thin film integrated circuit. In addition,
According to the method of manufacturing a semiconductor device, FIG.
The steps proceed sequentially in the order of (b),..., (G).

Hereinafter, a method of manufacturing the semiconductor device will be described.

First, as shown in FIG. 4A, a base film 302 made of silicon oxide having a thickness of about 300 nm to 500 nm is formed on a glass substrate 301 as a substrate having an insulating surface by, for example, a plasma CVD method.

Next, the thickness 2 is formed by the plasma CVD method.
An intrinsic (I-type) first amorphous silicon film 303 having a thickness of 0 nm to 80 nm, for example, 40 nm is formed.

Next, a slight amount of nickel 304 as a catalyst element is added to the surface of the first amorphous silicon film 303. This addition of a small amount of nickel 304 is performed by holding a solution in which nickel is dissolved on the first amorphous silicon film 303, and using the spinner to spin the solution.
03 and uniformly dried. In the third embodiment, nickel acetate is used as the solute of the solution, water is used as the solvent of the solution, and the nickel concentration in the solution is adjusted to 10 ppm. When the nickel concentration on the surface of the first amorphous silicon film 303 is measured by total reflection X-ray fluorescence spectroscopy, the nickel concentration is 7 × 10 ¹² atoms / cm.
It was about ² .

Subsequently, heat treatment is performed in an inert atmosphere, for example, in a nitrogen atmosphere. In this heat treatment, 520
Annealing is performed at a temperature of 550 ° C. to 570 ° C. for 2 hours to 8 hours, for example, 4 hours. As a result, the amorphous silicon film 303 is crystallized with the nickel 304 added to the surface of the amorphous silicon film 303, and FIG.
The crystalline silicon film 303a shown in FIG.

Further, by irradiating the crystalline silicon film 303a with a laser beam 305, the crystalline silicon film 303a is recrystallized to improve its crystallinity. The laser light 305 has a wavelength of 308 nm and a pulse width of 40 n.
Irradiation is performed using a XeCl excimer laser device for sec. The irradiation conditions of the laser light 305 are as follows.
And heated to an energy density of 250 mJ / cm ^{2 to} 450
mJ / cm ^2, it is to irradiate, for example, 350 mJ / cm ^2. In this manner, the crystalline silicon film 303a obtained by the solid-phase crystallization has a crystal defect reduced by a melting and solidifying process by laser irradiation, and becomes a higher quality crystalline silicon film 303b.

Next, as shown in FIG. 4C, the surface layer of the crystalline silicon film 303b is thinly oxidized to form a silicon oxide film 306 as a barrier thin film serving as an etching stopper. The formation of the silicon oxide film 306 is performed by holding ozone water on the surface of the crystalline silicon film 303b. When the thickness of the silicon oxide film 306 thus obtained was measured by spectroscopic ellipsometry, the thickness was about 30 °.

Then, so as to cover the oxide film 306,
A non-doped second amorphous silicon film 307 is formed by plasma CVD (an intrinsic second amorphous silicon film 307 is formed). Further, an argon (Ar) 30 is formed on the second amorphous silicon film 307.
8 is introduced by an ion doping method. At this time,
As the doping gas, 100% argon gas is used, the acceleration voltage is set to, for example, 30 kV, and the dose is 1 × 1.
0 ¹⁵ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² , for example, 3 × 1
0 ¹⁵ cm ^-2 .

Then, high-speed thermal annealing is performed in an inert atmosphere, for example, in a nitrogen atmosphere. In this high-speed thermal annealing treatment, the temperature is raised from a preheating temperature of 550 ° C. or less, and at least 30 ° C./min or more, preferably 1 ° C. or more.
It is desirable that the temperature be raised at a rate of at least 00 ° C./min. The main heating to be performed after the temperature rise in the high-speed thermal annealing treatment is desirably performed at a temperature of 600 ° C. to 750 ° C. for 1 second to 15 minutes.
More preferably, it is performed at a temperature of 0 ° C. for 1 minute to 10 minutes. In the third embodiment, high-speed thermal annealing is performed with the same temperature profile as in the first embodiment. That is, as shown in FIG.
From the state of being preheated to 00 ° C., the temperature is raised at a rate of 138 ° C./min.
Raise the temperature to 5 ° C. Then, after the main heating at 675 ° C. is performed for 3 minutes, the temperature is reduced to 400 ° C. by lowering the temperature at a rate of 69 ° C./min for 4 minutes, and further reduced to 200 ° C./min.
The temperature is taken out from 400 ° C. for 2 minutes,
Lower to 00 ° C. Although not shown, an apparatus similar to that of the first embodiment is used as an apparatus for performing the high-speed thermal annealing.

By the above-mentioned rapid thermal annealing, the second amorphous silicon film 307 is not completely crystallized, and the defects of the second amorphous silicon film 307 serve as segregation traps for nickel to form crystalline silicon. Nickel 3 in film 303b
04 is pulled out upward as indicated by an arrow 309 in FIG. At this time, in the second amorphous silicon film 307, the doped argon 308 causes a larger interstitial distortion, so that the second amorphous silicon film 307 functions as a stronger gettering sink. . At this time, the nickel moves through the thin silicon oxide film 306, but the silicon oxide film 306
Has a thickness of about 30 °, so that it does not hinder its movement. Thus, most of the nickel in the crystalline silicon film 303b moves to the second amorphous silicon film 307, and the nickel concentration in the second amorphous silicon film 307 increases. Conversely, the nickel concentration of the crystalline silicon film 303b is significantly reduced, and a high-quality crystalline silicon film 303c having a low nickel concentration is obtained. The actual nickel concentration in the crystalline silicon film 303c at this time was measured by secondary ion mass spectrometry to be 5 × 10 ¹⁶ a
It was reduced to about toms / cm ³ .

Next, the nickel is gettered, and the entire surface of the second amorphous silicon film 307 having a high nickel concentration is removed by etching. Etching at this time requires an etchant having a sufficient etching selectivity with the silicon oxide film so that the silicon oxide film 306 sufficiently functions as an etching stopper. In the third embodiment, a strong alkaline solution such as a developer is used. After removing the second amorphous silicon film, the silicon oxide film 3
06 is removed by etching. As an etchant at this time, wet etching is performed using a sufficiently lower crystalline silicon film 303c and 1: 100 buffered hydrofluoric acid having selectivity.

After that, unnecessary portions of the crystalline silicon film 303c are removed to perform element isolation, and as shown in FIG. 4E, a semiconductor element forming region (source region, (Drain region, channel region) 310
To form

Next, as shown in FIG. 4F, a gate insulating film 311 made of silicon oxide and having a thickness of 20 nm to 150 nm, for example, 100 nm is formed to cover the semiconductor element formation region 310. Then, after the gate insulating film 311 is formed, in order to improve the bulk characteristics of the gate insulating film 111 itself and the interface characteristics between the semiconductor element formation region 310 and the gate insulating film 111, the gate insulating film 311 is formed under an inert gas atmosphere. Annealing was performed at 500 ° C. to 600 ° C. for 1 hour to 4 hours.

Subsequently, by the sputtering method,
An aluminum film with a thickness of 400 nm to 800 nm, for example, 600 nm is formed over the gate insulating film 311. Then, by patterning the aluminum film,
A gate electrode 312 is formed. Further, an oxide layer 313 is formed by anodizing the surface layer of the gate electrode 312.

Next, phosphorus, which is an impurity, is implanted by ion doping using the gate electrode 312 and the oxide layer 313 around the gate electrode 312 as a mask. As a result, the N-type impurity diffusion regions 315 and 316 into which phosphorus has been implanted are formed.
Is a region to be used as a source region and a drain region of the TFT. The gate electrode 312 and the oxide layer 313 around the gate electrode 312
The region 314 where the impurity is not implanted is masked by TF
This is a region to be a T channel region.

Thereafter, an annealing process is performed by irradiation with the laser beam 320 to activate the ion-implanted impurity phosphorus, and at the same time, to improve the crystallinity of the portion where the crystallinity is deteriorated in the impurity introducing step. The laser device used at this time is an X-ray having a wavelength of 308 nm and a pulse width of 40 nsec.
This is an eCl excimer laser device, and the energy density of the laser beam 320 is 150 mJ / cm ^{2 to} 400 mJ / c.
m ^2, preferably 200mJ ^/ cm 2 ~250mJ ^/ c
a m ^2.

Subsequently, in order to form an interlayer insulating film 321 as shown in FIG. 4G, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is laminated. When laminating the silicon oxide film, TEOS is used as a raw material,
If this is formed by a plasma CVD method with oxygen, a reduced pressure CVD method with ozone, or a normal pressure CVD method, a good interlayer insulating film 121 having excellent step coverage can be obtained. If a silicon nitride film formed by a plasma CVD method using silane gas and ammonia gas as a source gas is used, hydrogen atoms are supplied to an interface between the element formation amount region 310 and the gate insulating film 311 to degrade TFT characteristics. This has the effect of reducing the number of dangling bonds to be caused.

Next, a contact hole is formed in the silicon oxide film or the silicon nitride film to obtain an interlayer insulating film 321. And so as to fill the contact hole,
By stacking a metal material, for example, a titanium nitride film and an aluminum film, electrodes / wirings 322 and 322 of the TFT 323 are formed.

Finally, at 350 ° C. in a hydrogen atmosphere of 1 atm.
The TFT 123 is completed by performing an annealing process for one hour. If necessary, a protective film made of a silicon nitride film or the like may be provided on the TFT 123 for the purpose of protecting the TFT 123.

As described above, the catalyst element in the crystalline silicon film 303b is moved to the second amorphous silicon film 307 by performing the above-described rapid thermal annealing treatment.
As compared with the methods described in JP-A-223534, JP-A-10-229048 and JP-A-11-31660, the amount of the residual catalyst element in the semiconductor element formation region 310 can be greatly reduced.

Further, since the amount of the residual catalytic element in the semiconductor element formation region 310 is greatly reduced, no abnormality in the leakage current during the OFF operation is observed in the TFT 123 manufactured using the semiconductor element formation region 310. Therefore, the performance and reliability of the semiconductor device can be improved. That is, JP-A-10-223534, JP-A-10-229048 and JP-A-11-316
A high-performance semiconductor device having a higher current driving capability can be obtained as compared with the method disclosed in Japanese Patent Application Laid-Open No. 60-260.

While the first, second, and third embodiments of the present invention have been specifically described, the present invention is not limited to the first, second, and third embodiments.
The present invention is not limited to the above examples, and various modifications based on the technical idea of the present invention are possible.

For example, in the third embodiment, as a high-speed thermal annealing process for moving nickel to the second amorphous silicon film of the gettering sink, a method using a resistive heating furnace by blowing high-temperature gas is used. Was shown,
The same treatment can be performed by a lamp annealing method using a tungsten-halogen lamp or a xenon arc lamp.

In the first, second and third embodiments, as a method for introducing nickel as the catalyst element, a method in which a solution in which a nickel salt is dissolved is applied to the surface of the first amorphous silicon film is used. A method was adopted in which nickel was introduced into the surface of the base film before the formation of the first amorphous silicon film, and nickel was diffused from the base film into the first amorphous silicon film to cause crystal growth. May be adopted. That is, crystal growth may be performed from the upper surface side (the side opposite to the glass substrate) of the amorphous silicon film, or may be performed from the lower surface side (the glass substrate side). In addition, as the method for introducing the above nickel,
Various approaches can be used. For example, there is a method in which an SOG (spin-on-glass) material is used as a solvent for dissolving a nickel salt and is diffused from a silicon oxide film. Further, for example, a method of forming a thin film by a sputtering method, an evaporation method, a plating method, or the like, a method of directly introducing a thin film by an ion doping method, and the like can be used. Further, the same effect can be obtained by using cobalt, iron, palladium, platinum, copper, or gold in addition to nickel as a catalyst element for promoting crystallization of silicon. Accordingly, the catalyst element may be one or more elements selected from nickel, cobalt, iron, palladium, platinum, copper and gold.

In the first and second embodiments, in order to enhance the effect of gettering nickel in the crystalline silicon film, the second amorphous silicon film contains phosphorus of Group V element B. But the second amorphous silicon film has
Elements may be included. For example, one or more elements selected from nitrogen, arsenic, antimony, and bismuth may be included in the second amorphous silicon film. In short, one or more elements selected from nitrogen, phosphorus, arsenic, antimony, and bismuth may be included in the second amorphous silicon film. Of course, although it is a feature of the present invention, a non-doped second amorphous silicon film may be used, and even if the second amorphous silicon film is non-doped, a gettering effect can be obtained.

In the third embodiment, the second amorphous silicon film serving as the gettering sink is doped with argon. However, krypton or xenon may be doped. In short, the second amorphous silicon film is made of one selected from the group consisting of argon, krypton, and xenon.
It may contain one or more rare gas elements. Also in this case, the catalyst element of the crystalline silicon film can be gettered to the second amorphous silicon film. Argon was introduced into the second amorphous silicon film by an ion doping method. A second amorphous silicon film containing argon was formed by sputtering using a silicon target and using argon as a sputtering gas. You may. Also in this method, a large amount of argon can be included in the second amorphous silicon film. In addition, even when the CVD method is used, a second amorphous silicon film containing argon can be formed by adding Ar as a material gas and performing the treatment.

The barrier thin film serving as an etching stopper when removing the second amorphous silicon film serving as a gettering sink is not limited to the silicon oxide film described in the first, second, and third embodiments. Various other films, such as films, can be used. Also, as for the method of forming the silicon oxide film, a method other than the thin film oxidation method such as the ozone water treatment or the excimer UV treatment as described in the first, second, and third embodiments, for example, the thin film formation by CVD, There is no problem even if plasma treatment, thermal oxidation, sulfuric acid oxidation, or the like is used.

In the first and second embodiments, as a means for further promoting the crystallinity of the crystalline silicon film crystallized with nickel, a heating method using excimer laser irradiation as a pulse laser is used. , A heating method using a continuous wave Ar laser or the like may be used.
Also in this case, the same processing as the excimer laser irradiation can be performed.

The concentration of the catalyst element in the semiconductor element formation region is 1 × 10 ¹⁶ atoms / cm ³ to 2 × 10 ¹⁶ atoms / cm ^3.
It may be within the range of × 10 ¹⁷ atoms / cm ³ .

Further, as an application of the method of manufacturing a semiconductor device of the present invention, in addition to an active matrix type substrate for liquid crystal display, for example, a contact type image sensor, a thermal head with a built-in driver, an organic EL, etc. An optical writing element or display element with a built-in driver, a three-dimensional IC, or the like can be considered. By using the present invention, high performance such as high speed and high resolution of these elements is realized. Further, the present invention is not limited to the MOS type transistors described in the above embodiments, but can be widely applied to all semiconductor processes including bipolar transistors and electrostatic induction transistors using a crystalline semiconductor as an element material.

In the first, second, and third embodiments, a part of the crystalline silicon film is used as the half-element forming region.
The entire crystalline silicon film may be used as a semiconductor element formation region.

[0145]

As is clear from the above, in the method of manufacturing a semiconductor device according to the present invention, the catalytic element in the crystalline silicon film is moved to the second amorphous silicon film by performing a rapid thermal annealing treatment. Therefore, the amount of residual catalyst elements in the semiconductor element formation region made of the crystalline silicon film can be extremely reduced.

Further, since the amount of the residual catalyst element in the semiconductor element formation region is extremely small, it is possible to prevent the generation of a leak current at the time of off operation in the semiconductor element manufactured using the semiconductor element formation region. Performance and reliability can be improved.

That is, it is possible to manufacture a high-performance semiconductor element having stable characteristics with little characteristic variation such as an abnormal increase in leakage current. Further, a high-performance semiconductor device with a high degree of integration can be manufactured by a simple manufacturing process. can get. Also,
In the manufacturing process, the non-defective product rate can be greatly improved,
Product cost can be reduced. In particular, in a liquid crystal display device, the switching characteristics of the pixel switching TFT required for the active matrix substrate are improved, and the high performance and high integration required for the TFTs constituting the peripheral drive circuit are simultaneously satisfied. In addition, a driver monolithic active matrix substrate constituting an active matrix section and a peripheral drive circuit section can be realized, and the module can be made compact, high-performance, and low in cost.

[Brief description of the drawings]

FIGS. 1A to 1G are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2D are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

3 (e) to 3 (g) are process cross-sectional views illustrating a method for manufacturing the semiconductor device of the second embodiment.

FIGS. 4A to 4G are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 5 (a) is a graph showing the residual ratio of the catalytic element in the silicon film before and after the rapid thermal annealing treatment, and FIG. 4 is a graph showing a relationship between a ratio of a crystalline region and a heating rate in a rapid thermal annealing process.

FIG. 6 is a graph showing a relationship between a residual ratio of a catalytic element in a crystalline silicon film before and after performing an annealing process and a processing temperature in the annealing process.

FIG. 7A is a graph showing a temperature profile in the high-speed thermal annealing in the first and third embodiments, and FIG. 7B is a graph showing a temperature profile in the high-speed thermal annealing in the second embodiment. It is a graph.

[Explanation of symbols]

 101, 201, 301 Glass substrate 103, 203, 303 First amorphous silicon film 104, 204, 304 Nickel 103a, 103b, 103c Crystalline silicon film 203a, 203b, 203c Crystalline silicon film 303a, 303b, 303c Crystal Silicon film 107,108 Amorphous silicon film 208,307 Second amorphous silicon film

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) HJ23 HL01 HL03 HL07 HL11 HM14 NN03 NN04 NN23 NN24 NN35 NN72 PP03 PP10 PP29 PP34 PP35 PP38 QQ11 QQ23 QQ28

Claims (19)

[Claims] A step of forming a first amorphous silicon film on a substrate having an insulating surface, and introducing a catalytic element for promoting crystallization of silicon into the first amorphous silicon film; Performing a heat treatment on the first amorphous silicon film to crystallize the first amorphous silicon film to form a crystalline silicon film; Providing a second amorphous silicon film, and subjecting the crystalline silicon film and the second amorphous silicon film to a high-speed thermal annealing treatment so that the catalytic element in the crystalline silicon film 2. A semiconductor device, comprising: a step of moving the crystalline silicon film to an amorphous silicon film; and a step of removing the second amorphous silicon film to make the crystalline silicon film a semiconductor element formation region. Manufacturing method. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in said rapid thermal annealing, a preheating temperature capable of maintaining at least a part of said second amorphous silicon film in an amorphous state. A method of manufacturing a semiconductor device, characterized in that the temperature rise starts at a temperature rising rate at which at least a part of the second amorphous silicon film can be maintained in an amorphous state. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the preheating temperature is 550 ° C. or less, and the heating rate is 3
A method for manufacturing a semiconductor device, wherein the temperature is higher than 0 ° C./min. 4. The method of manufacturing a semiconductor device according to claim 3, wherein said temperature increasing rate is higher than 100 ° C./min. 5. The method for manufacturing a semiconductor device according to claim 2, wherein in the rapid thermal annealing, the catalyst element in the crystalline silicon film is replaced with the second amorphous material. Manufacturing the semiconductor device, wherein the main heating for transferring to the silicon film is performed after the temperature increase, and the main heating is performed at an average temperature in a range of 600 ° C. to 750 ° C. for 1 second to 15 minutes. Method. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the main heating is performed at an average temperature in a range of 650 ° C. to 700 ° C. for 1 minute to 10 minutes. Method. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the high-speed thermal annealing includes a tungsten-halogen lamp, a xenon arc lamp, a resistive heating furnace, and high-temperature gas heating. A method for manufacturing a semiconductor device, wherein the method is performed by using the method. 8. The method of manufacturing a semiconductor device according to claim 1, wherein the catalyst element is Ni, Co, Fe, Pd, Pt, Cu.
And one or more elements selected from Au and Au. 9. The method for manufacturing a semiconductor device according to claim 1, wherein the second amorphous silicon film contains an element selected from Group V B. A method for manufacturing a semiconductor device. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the element selected from Group V B is one or more elements selected from P, As, and Sb. Manufacturing method of a semiconductor device. 11. The method for manufacturing a semiconductor device according to claim 1, wherein the second amorphous silicon film contains two kinds of elements, P and B. Manufacturing method of a semiconductor device. 12. The method of manufacturing a semiconductor device according to claim 1, wherein the second amorphous silicon film uses at least a SiH ₄ gas and a PH ₃ gas as a material gas. And a film forming temperature of 400 ° C.
A method for manufacturing a semiconductor device, characterized by being formed by a plasma CVD method described below. 13. Manufacturing of the semiconductor device according to claim 11.
In the method, the second amorphous silicon film comprises at least SiH₄gas
And PH₃Gas and B₂H ₆Using gas as the source gas,
Formed by a plasma CVD method at a film temperature of 400 ° C. or less.
A method of manufacturing a semiconductor device. 14. The method for manufacturing a semiconductor device according to claim 1, wherein the second amorphous silicon film is one or more selected from Ar, Kr, and Xe. A method for manufacturing a semiconductor device, comprising a plurality of types of rare gas elements. 15. The method for manufacturing a semiconductor device according to claim 14, wherein the second amorphous silicon film is formed by ion doping the amorphous silicon film formed by a plasma CVD method with the rare gas element. A method for manufacturing a semiconductor device, wherein the semiconductor device is formed by doping with a semiconductor. 16. The method of manufacturing a semiconductor device according to claim 1, wherein the second non-crystalline silicon film is provided between the crystalline silicon film and the second amorphous silicon film. A method for manufacturing a semiconductor device, comprising: providing a barrier thin film serving as an etching stopper when removing a crystalline silicon film. 17. The method according to claim 16, wherein the barrier thin film is a silicon oxide film having a thickness of 50 ° or less. 18. The method for manufacturing a semiconductor device according to claim 1, wherein the second amorphous layer is formed on the crystalline silicon film whose crystallinity has been increased by laser light irradiation. A method for manufacturing a semiconductor device, comprising providing a porous silicon film. 19. The method of manufacturing a semiconductor device according to any one of claims 1 to 18, the concentration of the catalytic element in the semiconductor device forming ^{region, 1 × 10 16 atoms / cm} 3 ~2 × 10 ¹⁷ a
A method for manufacturing a semiconductor device, wherein the thickness is in the range of toms / cm ³ .