JP3454467B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device formed on a semiconductor substrate such as single crystal silicon or an insulating substrate such as glass and a method for manufacturing the same, and particularly to an electrode or wiring material thereof. The present invention relates to a polycrystalline silicon film used.

[0002]

2. Description of the Related Art In recent years, large-sized, high-resolution liquid crystal display devices, monolithic liquid-crystal display devices in which driver circuits are formed on the same substrate for cost reduction, high-speed, high-resolution contact image sensors, three-dimensional Attempts have been made to form a high-performance semiconductor element on an insulating substrate such as glass or an insulating film for the purpose of realizing it as an IC or the like. Generally, a thin film silicon semiconductor is generally used for the semiconductor element used in the above-mentioned device. Then, such a thin film silicon semiconductor is roughly classified into two, that is, an amorphous silicon semiconductor and a crystalline silicon film.

Since this amorphous silicon semiconductor has a low production temperature, it can be produced relatively easily by a vapor phase method, and it is most commonly used because it has high mass productivity. However, the amorphous semiconductor has a problem that the physical properties such as conductivity are inferior to those of a crystalline silicon semiconductor. Therefore, in the future, there has been a strong demand for establishment of a method of manufacturing a thin film semiconductor device made of the above-described crystalline silicon semiconductor in order to realize higher speed characteristics of the above device. Note that polycrystalline silicon, microcrystalline silicon, and the like are known as silicon semiconductors having crystallinity.

The polycrystalline silicon thin film plays an important role as a material for forming a semiconductor device as various electrodes, wiring materials or low resistance materials. For example, a capacitor electrode, a gate electrode in a memory device,
Alternatively, it has been put into practical use in recent years by being applied to a material for embedding a device active layer and a wiring layer and used as an active layer of a liquid crystal driving element of a liquid crystal display device.

As a method of obtaining this polycrystalline silicon thin film, (1) a film having crystallinity is directly formed at the time of film formation. (2) The amorphous semiconductor film is made to have crystallinity by irradiating the amorphous semiconductor film previously formed on the substrate with strong light energy. (3) An amorphous semiconductor film is formed on a substrate in advance, and the amorphous semiconductor is made crystalline by heating it and applying heat energy. There are mainly three known methods.

However, in the above method (1), crystallization progresses at the same time as the film forming step. Therefore, in order to obtain crystalline silicon having a large grain size, it is indispensable to increase the film thickness, and it has good semiconductor physical properties. It is technically difficult to form a film on the entire surface of a substrate. Moreover, it is difficult to reduce the resistance because the average crystal grain size is small, and the film forming temperature is 600 ° C.
Since the cost is high as described above, there is a cost problem that an inexpensive glass substrate cannot be used and a more expensive substrate must be used.

On the other hand, in the above method (2), since the crystallization phenomenon in the melting and solidification process is utilized, the obtained crystal grain size is small, but the crystal grain boundaries are well treated, High quality crystalline silicon can be obtained. However, in such a method, taking the case of using the most commonly used excimer laser as an example, the stability of the laser beam is not sufficient, so that the entire surface of a large area substrate is uniformly processed. In this case, it is difficult to obtain a silicon film having uniform crystallinity, and thus it is difficult to obtain a plurality of semiconductor elements having uniform characteristics on the same substrate. Further, in this case, there is a problem that throughput is low because the irradiation area of the laser beam is small.

The method of (3) above is based on (1),
Compared with the method (2), there is an advantage that it can handle a large area, and examples of using a polycrystalline silicon film formed by this method as an electrode material are disclosed in JP-A-6-314661 and JP-A-6-97194. It is proposed in the official gazette.
However, according to this method, in order to crystallize amorphous silicon, heat treatment at a high temperature of 600 ° C. or higher for several tens of hours is required, and thus an inexpensive glass substrate is used to reduce manufacturing cost, In addition, in order to improve the throughput, it is necessary to simultaneously solve the contradictory problems of lowering the treatment temperature and shortening the treatment time in the heat crystallization treatment. Further, in the method (3), since the solid phase crystallization phenomenon is utilized, the crystal grains spread in parallel to the substrate surface, and the obtained crystal grain size has a relatively large grain size of several μm. Even things appear. However, since the grown grain diameters collide with each other to form grain boundaries, the grain boundaries act as a trap level for carriers and reduce the mobility of the TFT, and impurities such as phosphorus and boron are also present. There is a problem that segregation at the grain boundaries hinders resistance reduction.

By applying the above method (3),
A method for forming a silicon film having high quality and uniform crystallinity by heat treatment at a lower temperature for a shorter time is disclosed in Japanese Patent Laid-Open No. 6-3.
It is proposed in JP-A-33824, JP-A-6-333825 and JP-A-8-330602. According to these publications, a trace amount of a metal element such as nickel is introduced onto the surface of the amorphous silicon film, and then heat treatment is performed, so that a low treatment temperature of 600 ° C. or lower and a short treatment time of about several hours. Amorphous silicon is crystallized in.

The crystallization mechanism in the above-mentioned method is as follows. First, the generation of crystal nuclei centering on a metal element occurs at an early stage, and thereafter, the metal element serves as a catalyst to promote the crystal growth, and the crystallization is rapid. Understood to progress to. In that sense, a metal element having such a function is hereinafter referred to as a catalyst element. The crystalline silicon film crystallized by using these catalytic elements is composed of many columnar crystals, whereas the silicon film crystallized by the usual solid phase growth method has a twin structure. There is. further,
The inside of each columnar crystal is in a state close to a single crystal and has good crystallinity.

[0011]

As described above, Japanese Patent Laid-Open Nos. 3-314661 and 6-97194.
As described in the publication, when an amorphous silicon film is crystallized by applying heat energy without a catalytic element, a high temperature of 600 ° C. or higher is required. In this case, the higher the temperature, the faster the crystallization, but the higher the nucleus generation density, the smaller the crystal grain size. Therefore, in order to increase the crystal grain size and reduce the resistance, crystallization occurs. It is necessary to crystallize at the lowest temperature for a long time.

[0012] Further, in Japanese Patent Application Laid-Open No. 6-97194, heat treatment is performed at 600 ° C for 30 hours, and the treatment time is extremely long. Further, since grown crystal grains collide with each other to form a grain boundary, the grain boundary acts as a trap level for carriers, and segregation of impurities lowers the amount of impurities that can be activated, resulting in a low level. It has a drawback that it hinders resistance.
When forming a semiconductor device on glass, 6
Since high temperature annealing above 00 ° C cannot be performed, 100
It is impossible to improve the crystallinity by high temperature annealing at about 0 ° C.

Further, as described in JP-A-3-314661, the thickness of the polycrystalline silicon film is 1
The resistivity tends to increase as the thickness becomes thinner than 00 nm. In particular, when the film thickness is 50 nm or less, the resistivity rapidly increases, which is a major obstacle when applied to various electrode materials for highly integrated semiconductor devices. The reason for this is that the crystal grain size of the polycrystalline silicon becomes smaller as the film thickness becomes thinner, the crystallinity decreases and the amount of impurities segregated at the grain boundaries increases, and the number of activatable impurity atoms becomes insufficient. Conceivable.

The present invention has been made in view of the above problems, and an object thereof is to provide a polycrystalline silicon thin film having a low resistance and a thin film thickness at a low temperature and a short processing time. is there.

[0015]

The semiconductor device of the present invention comprises:
A first polycrystalline silicon film formed in an island shape on the substrate,
A gate formed to cover the first polycrystalline silicon film.
In the first insulating film and the first polycrystalline silicon film.
Regions other than the regions functioning as the source and drain of T
25 nm or more on the gate insulating film corresponding to the region, 80
Amorphous, formed with a thickness of nm or less
The result is obtained by adding a catalytic element to the silicon film and heating it.
The crystallized second polycrystalline silicon film and the second polycrystalline silicon film.
A gate electrode formed on the recon film,
The polycrystalline silicon film of No. 1 has a TFT source and a drain.
In contact with the region that functions as an impurity,
The LDD regions each having a low concentration are provided, and
Is the gate electrode part removed corresponding to each LDD region?
It is characterized in that it is in a closed state, whereby the above object is achieved.

The concentration of the catalytic element in the second polycrystalline silicon film is 1 × 10 ¹⁶ atoms / cm ^-3.
As described above, it is preferably 1 × 10 ¹⁹ atoms / cm ⁻³ or less.

Further, the present invention is the method for manufacturing a semiconductor device, wherein a step of forming a first polycrystalline silicon film in an island shape on a substrate and a step of covering the first polycrystalline silicon film. A step of forming a gate insulating film, a step of adding a catalytic element to the amorphous silicon film and crystallizing the amorphous silicon film by heating to form a second polycrystalline silicon film on the gate insulating film; A step of forming an aluminum film on the polycrystalline silicon film, the aluminum film and the second
Patterning step of forming the polycrystalline silicon film of the first polycrystalline silicon film corresponding to the regions other than the regions functioning as the source and drain of the TFT in the first polycrystalline silicon film,
Implanting impurities into the first polycrystalline silicon film using the patterned aluminum film as a mask;
A step of removing the aluminum film portion corresponding to a region functioning as an LDD of the TFT in the first polycrystalline silicon film, a step of implanting impurities into the first polycrystalline silicon film using the aluminum film as a mask, Removing the aluminum film and activating the implanted impurities, and then forming a gate electrode on the second polycrystalline silicon film.
Thereby, the above object is achieved.

Process for forming the second polycrystalline silicon film
In the above step, the catalytic element is formed by the spin coating method.
It is preferably added on the rufus silicon film .

The catalyst element added on the amorphous silicon film is preferably Ni or a plurality of elements containing Ni.

[0020]

The amorpha containing the catalytic element
The process of heating the silicon film is performed at a temperature of 500 ° C.
It is desirable to be performed within a temperature range of ℃ or less.

The amorphous silicon film has a thickness of 2
It is desirable to have a thickness of 5 nm or more and 80 nm or less.

[0023]

In the patterning process, BCl ₃ and HC are used.
It is desirable to carry out by a reactive ion etching method using a chlorine-based gas containing 1 g.

The operation of the present invention will be described below.

The present invention uses polycrystalline silicon obtained by crystallizing an amorphous silicon film with a catalytic element as an electrode material of a semiconductor device, particularly as a gate electrode. The mechanism of crystallization with this catalytic element will be described below.

First, the silicide of the catalytic element is formed by the reaction between the catalytic element and amorphous silicon.
The silicide of the catalytic element functions as a crystal nucleus in the initial stage of crystallization. It is considered that the catalytic element does not act as a catalyst for crystallization of amorphous silicon in its single state, but becomes catalytic by binding to silicon to form a silicide. The reason for this is that the crystal structure of the catalyst element silicide is considered to act as a kind of template for crystallizing amorphous silicon to promote crystallization.

The catalyst element forming the crystal nucleus (catalyst element silicide) exists at the boundary between the amorphous silicon and the crystallized region. This is because, in terms of the difference in chemical potential, the most energy-stable state can be obtained by being present at the boundary between the amorphous silicon and the crystallized region.

As the crystallization of amorphous silicon progresses, the boundary between the amorphous silicon and the crystallized region moves, and at the same time, the catalytic element that constitutes the crystal nucleus also moves to the amorphous region around the crystal nucleus with crystallization.
As a result, further crystallization of the amorphous silicon is promoted, the entire surface of the silicon film is crystallized, and the crystallization ends when the amorphous / crystallized region boundary portion disappears.

In the crystalline silicon film which is crystallized by promoting crystallization by these catalytic elements, the silicon film crystallized by the usual solid phase growth method has a twin structure.
It is composed of many columnar crystals, and the inside of each columnar crystal is in a state close to a single crystal.

On the other hand, in the case of crystallization by the usual solid phase growth method, the grown crystal grains collide with each other to form a grain boundary, so that the grain boundary functions as a trap level for carriers and phosphorus. Since impurities such as boron are also segregated at the grain boundaries, there is a drawback in that resistance reduction is hindered. Therefore, as shown in FIG.
When a catalytic element is used, the crystallinity is higher than that of a polycrystalline silicon film crystallized by a normal solid phase growth method, and a polycrystalline silicon film having a lower resistance can be obtained.

When the concentration of the catalytic element is low, the entire surface of the silicon film cannot be crystallized, and when the concentration of the catalytic element is high, the nucleation density becomes high and the crystal grain size becomes small. . Therefore, as the concentration of the catalytic element,
1 × 10 ¹⁶ atoms / cm ⁻³ to 1 × 10 ¹⁹ atoms
It is desirable to keep it within the range of / cm ^-3 .

The catalyst element is added by the spin coating method, so that the concentration can be controlled easily and easily. At this time, by using ethanol as a solution for dissolving the catalytic element, it becomes possible to add it evenly even for a large substrate.

Further, as the catalytic element of the present invention, Ni,
Co, Pd, Pt, Cu, Ag, Au, In, Sn, A
It is possible to use 1, Is, Sn, Al, and Sd, and by using one or more elements selected from these, it is possible to obtain a crystallization promoting effect in a small amount. Furthermore, among these elements, a remarkable effect can be obtained by using the Ni element. The following model can be considered as the reason for this. The catalytic element does not act alone, but promotes crystal growth by combining with silicon to form a silicide. This is a model in which the crystal structure at that time acts like a kind of template during crystallization of the amorphous silicon film to promote crystallization. Ni is two Si
To form a silicide represented by NiSi ₂ . NiSi ₂ has a fluorite crystal structure, which is very similar to the diamond structure of single crystal silicon. Moreover, the lattice constant of NiSi ₂ is 5.406A, which is very close to the lattice constant of crystalline silicon (5.430A).
Therefore, NiSi ₂ serves as an optimum template for crystallizing the amorphous silicon film, and it is most desirable to use Ni as a catalyst element also in the present invention.

Here, when the amorphous silicon film to which the catalytic element is added is crystallized by the heat treatment, if natural nucleation occurs in the amorphous silicon film, the crystal grown by the catalytic element is generated by natural nucleation. The grown crystal bends and branches to collide with the generated nuclei to deteriorate the crystallinity, and the catalytic element is trapped at the collision position. Therefore, it is desirable to perform the heat treatment at a temperature at which the catalytic element diffuses inside the silicon film, but the spontaneous nucleation does not occur in the silicon film. Specifically, 50
The temperature is preferably 0 to 620 ° C., and therefore, it can be applied to a material such as a glass substrate that requires a process at 600 ° C. or lower.

The amorphous silicon film in the present invention preferably has a film thickness of 25 to 80 nm.
This is because when the film thickness of the amorphous silicon film is less than 25 nm, sufficient crystals cannot be obtained from the amorphous silicon, and when the film thickness is more than 80 nm, the columnar crystal structure in silicon is obtained. Is a two-layer structure, which causes a problem that crystallinity deteriorates.

Further, since many catalytic elements exist in silicon as a silicide compound, it is desirable that the silicon film, the catalytic element and the silicide compound of the catalytic element are simultaneously removed. As this method, there is a wet etching removal method using a mixed solution of hydrofluoric acid and nitric acid, but since it is unsuitable for fine processing, removal by dry etching suitable for fine processing is desirable. This is because by using a reactive ion etching (RIE) method using a chlorine-based gas containing chlorine gas, BCl ₃ , or HCl, the catalyst element and the silicide compound of the catalyst element are simultaneously etched together with the silicon film, A clean etching region free of residues in the removal region is obtained.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.

(Embodiment 1) Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a process of forming a gate electrode on a substrate,
The steps sequentially proceed in the order of (A) to (E).

First, as shown in FIG. 1A, the Si substrate 101 is thermally oxidized to form a gate oxide film 102 having a film thickness of 100 nm on the Si substrate.

Next, as shown in FIG. 1B, a low pressure CVD apparatus is used to deposit 25 to 80 n on the gate oxide film 102.
m amorphous silicon film 103a is formed. In the first embodiment, as film forming conditions at this time,
The substrate temperature was 470 ° C., the pressure was 0.15 Torr, and Si ₂ H ₆ was used as the reaction gas.

Then, this amorphous silicon film 10
Nickel 104 was added to the upper surface of 3a by a spin coating method at a surface concentration of about 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² , and in the first embodiment, 3 × 10 ¹² atoms / cm ² . By adding nickel 104 at such a surface concentration, the concentration of the catalytic element in the final polycrystalline silicon film is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ atoms / c.
It becomes m ^-3 .

Thereafter, as shown in FIG. 1C, this substrate is heat-treated at a temperature of about 500 to 620 ° C. for several hours in an inert atmosphere to obtain a polycrystalline silicon film 103b. In the first embodiment, the heat treatment is performed in a nitrogen atmosphere at a temperature of about 540 ° C. for about 2 hours. It should be noted that, under this nitrogen atmosphere, at a temperature of about 540 ° C.,
In the heat treatment for a long time, crystal nucleation does not occur without the catalytic element, and crystallization occurs due to the entire catalytic element.

Next, as shown in FIG. 1 (D), impurities (phosphorus) 10 are formed toward the substrate by ion doping.
5 was doped. In this step, phosphine (PH ₃ ) is used as a doping gas, the acceleration voltage is about 60 to 90 kV, and the dose amount is 8 × 10 ^{15 to} 3 × 10 ¹⁶ c.
m done as ^-2, but in the first embodiment, about 80kV accelerating voltage was performed the dosage of 2 × 10 ¹⁶ cm ^-2.

Then, as shown in FIG. 1E, heat treatment at 900 ° C. for about 1 hour is performed to reduce the damage to the silicon film due to activation of the implanted phosphorus and recovery of the ion doping. A resistive polycrystalline silicon thin film 103c is obtained.

According to the method as described above, the crystallization time can be shortened from several tens of hours to about 2 hours.
Moreover, since the crystallinity is most preferably 25 to 80 nm, 1
Even a thin film having a thickness of 00 nm or less has few impurities segregated at the crystal grain boundaries and is a low resistance polycrystalline silicon film.

The polycrystalline silicon film obtained according to the first embodiment can be used as a gate electrode material or a contact burying material between a device active layer and a wiring layer.

Although only the phosphorus (P) doped film has been described in the first embodiment, the dopant impurity may be arsenic (As) or boron (B).

(Second Embodiment) A second embodiment of the present invention will be described with reference to the drawings. In this embodiment, a semiconductor device including an N-channel TFT and a manufacturing method thereof, more specifically, a manufacturing method of an active matrix substrate for a liquid crystal display device including a pixel TFT, refer to FIGS. 2 and 3. While explaining. Among semiconductor devices including N-channel TFTs, particularly for active matrix substrates for liquid crystal display, it is necessary to uniformly prepare hundreds of thousands to millions of N-channel TFTs on the substrate. The TFT described in the second embodiment
Can also be used for other active matrix type driver circuits, pixel portions, elements constituting thin film integrated circuits, and the like.

FIGS. 2A to 2C are schematic partial plan views for explaining the manufacturing process of the active matrix substrate for liquid crystal display including the pixel TFT according to the second embodiment, and FIGS. (F) is an N-channel TF on the substrate
It is a schematic partial cross section which showed the process at the time of producing T.
Actually, hundreds of thousands or more of TFTs are formed on the liquid crystal display active matrix substrate.
In (A) to (C), a total of 12 TFTs in 3 rows × 4 columns will be described.

First, as shown in FIG. 3A, an intrinsic (I) film having a thickness of about 25 to 80 nm, or about 30 nm in the second embodiment, is formed on the entire upper surface of the glass substrate (Corning 1737) 201 by the plasma CVD method. Type amorphous silicon film (a-Si film) 202a was formed.

Next, as shown in FIG. 3B, a polycrystalline silicon film 202b was obtained by irradiating the glass substrate 201 with laser light 203. At this time, XeCl excimer laser (wavelength 308 nm, pulse width 40 nm) is used as the laser light 203, and the irradiation condition of the laser light 203 is the glass substrate 2 at the time of irradiation.
01 is about 200 to 450 ° C., 400 in the second embodiment.
Energy density of about 250-450mJ /
cm ² , and in the second embodiment, irradiation was performed at 360 mJ / cm ² . The beam size of the laser light 203 is shaped to be a long shape of 150 mm × 1 mm on the glass substrate 201, and is sequentially scanned in a step width of 0.1 mm in the direction perpendicular to the long direction. I went.

Next, as shown in FIGS. 3 (C) and 2 (A), unnecessary portions of the polycrystalline silicon film 202b on the glass substrate 201 are removed to separate the elements from each other, and the polycrystalline silicon film is separated. The film 202b was formed in an island shape. After that, a thickness of 20 to 150 nm is formed as a gate insulating film so as to cover the island-shaped polycrystalline silicon 202b.
A 00 nm silicon oxide film 204 was formed by a plasma CVD method.

Then, on the silicon oxide film 204, a phosphorus-doped amorphous silicon film (a-Si) 205a having a thickness of 25 to 80 nm, which is about 60 nm in the second embodiment, is formed by the plasma CVD method. As the reaction gas at this time, a mixed gas of PH ₃ and SiH ₄ with a mixing ratio of 1:20 and H ₂ were used. Nickel 206 is formed on the phosphorus-doped amorphous silicon film 205a.
The surface concentration is about 1 × 10 ¹² to 1 × 10 ¹⁴ by spin coating.
atoms / cm ² , 5 × 10 ¹² a in the second embodiment
Added at toms / cm ² . By adding nickel 206 at such a surface concentration, the concentration of the catalytic element in the final polycrystalline silicon film is 1 × 10 ¹⁶ to 1 ×.
It becomes 10 ¹⁹ atoms / cm ^-3 .

Then, as shown in FIGS. 3D and 2B, the substrate is placed under an inert atmosphere at about 500-62.
By performing heat treatment at a temperature of 0 ° C. for several hours, a polycrystalline silicon film 205b is obtained. In the second embodiment, the heat treatment is performed in a nitrogen atmosphere at a temperature of about 550 ° C. for about 3 hours. Also, under this nitrogen atmosphere,
In the heat treatment at a temperature of 0 ° C. for about 3 hours, crystal nucleation does not occur without the catalytic element, but crystallization occurs due to the catalytic element on the entire surface. Furthermore, the thickness is about 4 by the sputtering method.
By patterning the aluminum film 207 having a thickness of 00 to 800 nm, and 600 nm in the second embodiment, the aluminum electrode as the gate electrode and the gate bus line are integrally formed at the same time.

Here, dry etching was performed with a chlorine-based gas so that the aluminum electrode, the polycrystalline silicon film, the catalytic element, and the silicide compound were etched. Here, the etching is performed only with BCl ₃ at 20 mTorr, and then with BCl ₃ and Cl at 8 mTorr.
Etching at ₂ (mixing ratio 1: 4) and finally 90mT
Etching was performed at orr with CF ₄ and O ₂ (mixing ratio 1:10).

In this state, an impurity (phosphorus) 208 was implanted from the upper surface of the substrate using the aluminum film 207 as a mask by the ion doping method. As a result, FIG.
As shown in FIG.
And a region where impurities are not implanted are formed, and the regions 209 and 210 where the impurities are implanted are formed in the TFT.
Function as source / drain regions of the. In this doping process, phosphine (PH ₃ ) is used as a doping gas, the acceleration voltage is about 5 to 20 kV, the second embodiment is 10 kV, and the dose amount is about 1 × 10 ¹⁵ to.
8 × 10 ¹⁵ cm ^-2 , which is about 2 × 10 ¹⁵ c in the second embodiment.
It went as m ^-2 . Further, although not shown, this aluminum film 207 was anodized to form an oxide layer on the surface. This anodic oxidation is performed in an ethylene glycol solution containing tartaric acid in an amount of 1 to 5% at a constant current of about 220
The voltage was raised to V and the state was maintained for about 1 hour. The oxide layer thus obtained has a thickness of about 200 nm.
Had a thickness of. Then, the part of the anodic oxide film of the aluminum film 207 was removed.

Next, as shown in FIG. 3E, an impurity (phosphorus) 212 was implanted from the upper surface of the substrate by ion doping using the aluminum film 207 as a mask. As a result, as shown in FIG. 3E, the LD having a lower impurity concentration than the regions 209 and 210 into which the impurities are implanted.
D regions 213 and 214 are formed. Note that the above-described anodic oxide film thickness of the aluminum film 207 has the LDD region 21.
Since the lengths are 3 and 214, the lengths of the LDD regions 213 and 214 can be controlled by the above-described anodizing process. In this doping process, phosphine (PH ₃ ) is used as a doping gas, the acceleration voltage is about 60 to 100 kV, the second embodiment is 90 kV, and the dose amount is about 5 × 10 ¹² to.
1 × 10 ¹⁴ cm ⁻² , which is about 1 × 10 ¹³ c in the second embodiment.
It went as m ^-2 .

Subsequently, the aluminum film 207 was removed, and the substrate was heat-treated at 600 ° C. for about 8 hours to activate the impurities (phosphorus). Then, the aluminum film 207 was formed again as a gate electrode on the polycrystalline silicon film 205b.

Next, as shown in FIG. 3F, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm was formed on the upper surface of the substrate by a plasma CVD method to form an interlayer insulating film 215. Then, a contact hole was formed in the interlayer insulating film 215, and a source electrode wiring 216 of a TFT made of a two-layer film of a metal material, for example, titanium nitride and aluminum was formed on the interlayer insulating film 215 including the contact hole. Further, since this TFT is an element for switching the pixel electrode, the pixel electrode 217 is formed on one drain electrode wiring 216 of the TFT by ITO or the like which is a transparent electrode.

Finally, at a temperature of about 4 in a hydrogen atmosphere of 1 atm.
Annealing was performed at 10 ° C. for about 60 minutes to fabricate a TFT substrate as shown in FIGS. 2 (C) and 3 (F). In order to protect the TFT, a protective film made of silicon nitride or the like may be formed on the TFT as needed.

As described above, in the second embodiment, the example of manufacturing the element for switching the pixel electrode on the substrate has been described. However, the present invention is not limited to the above-mentioned embodiments, and the technical scope of the present invention is not limited to this. Various modifications based on the idea are possible, for example, an N-type TFT and a P-type TFT forming an active matrix type liquid crystal peripheral circuit or a general thin film integrated circuit.
It can also be applied to a case where a circuit having a CMOS structure in which and are complementary is formed on a substrate.

In the second embodiment, the amorphous silicon film for the gate electrode is doped as a mixed gas of impurities (phosphorus) when it is deposited, but as described in the first embodiment, for example, as described in the first embodiment, It is also possible to dope the impurities by a doping method. In that case, the impurity can be doped without increasing the number of steps by also performing the impurity doping step for forming the source / drain regions. On the contrary, when the amorphous silicon for electrodes in the first embodiment is deposited, it can be doped as a mixed gas of impurities (phosphorus).

[0064]

According to the present invention, a semiconductor device using a polycrystalline silicon film, which has good crystallinity and is less likely to segregate impurities at crystal grain boundaries as an electrode material, can be manufactured by a simple manufacturing process,
It can be realized at low cost.

[Brief description of drawings]

1A to 1E are cross-sectional views showing a process of forming a gate electrode on a substrate according to the first embodiment.

2A to 2C are schematic partial plan views illustrating a manufacturing process of an active matrix substrate for liquid crystal display including a pixel TFT according to the second embodiment.

3 (A) to 3 (F) are schematic partial cross-sectional views showing a process of forming an N-channel TFT on a substrate.

FIG. 4 is a drawing showing a relationship between an impurity concentration and a resistivity in a polycrystalline silicon film according to the present invention.

[Explanation of symbols]

101 Silicon substrate 102 thermal oxide film 103a amorphous silicon film 103b Polycrystalline silicon film 103c gate electrode 104 catalytic element (nickel) 105 Impurity (phosphorus) 201 glass substrate 202a amorphous silicon film 202b Polycrystalline silicon film 203 laser light 204 Silicon oxide film 205a Phosphorus-doped amorphous silicon film 205b Phosphorus-doped polycrystalline silicon film 206 catalytic element (nickel) 207 Aluminum film 208 Impurity (phosphorus) 209 Source area 210 drain region 212 Impurity (phosphorus) 213 LDD area 214 LDD region 215 Interlayer insulation film 216 Source electrode wiring 217 pixel electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 616A (56) References JP-A-10-303129 (JP, A) JP-A-3-248434 (JP, A) JP-A-10-326898 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21/28 H01L 29/40

Claims (8)

(57) [Claims] 1. A first polycrystalline silicon film formed in an island shape on a substrate, a gate insulating film formed so as to cover the first polycrystalline silicon film, and the first polycrystalline silicon. The film is formed on the gate insulating film to have a thickness of 25 nm or more and 80 nm or less corresponding to regions other than the regions functioning as the source and drain of the TFT, and a catalytic element is added to the amorphous silicon film. Second crystallized by heating by heating
And a gate electrode formed on the second polycrystalline silicon film, the first polycrystalline silicon film being in contact with a region functioning as a source and a drain of a TFT. LDD regions each having an impurity concentration lower than that of the regions are provided, and the gate electrode is in a state in which a portion corresponding to each LDD region is removed. 2. The concentration of the catalyst element in the second polycrystalline silicon film is 1 × 10 ¹⁶ atoms / cm 2.
^-3, the semiconductor device according to claim 1, characterized in that 1 × ¹⁰ 19 atoms / ^{cm -3} or less. 3. The method of manufacturing a semiconductor device according to claim 1, wherein a step of forming a first polycrystalline silicon film in an island shape on a substrate, and covering the first polycrystalline silicon film. Forming a gate insulating film, forming a second polycrystalline silicon film on the gate insulating film by adding a catalytic element to an amorphous silicon film and crystallizing by heating the amorphous silicon film; And a step of forming an aluminum film on the second polycrystalline silicon film, the aluminum film and the second polycrystalline silicon film being a region other than a region functioning as a source and a drain of a TFT in the first polycrystalline silicon film. A patterning step of forming the first polycrystalline silicon film using the patterned aluminum film as a mask, and a step of implanting impurities in the first polycrystalline silicon film. Removing a step of removing said aluminum film portion corresponding to the region serving as the LDD TFT in crystal silicon film, a step of implanting impurities into the first polycrystalline silicon film the aluminum film as a mask, the aluminum layer And activating the implanted impurities, and then forming a gate electrode on the second polycrystalline silicon film, the method for manufacturing a semiconductor device. 4. The semiconductor device according to claim 3, wherein in the step of forming the second polycrystalline silicon film, the catalytic element is added on the amorphous silicon film by a spin coating method. Production method. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the catalytic element added on the amorphous silicon film is Ni or a plurality of elements containing Ni. 6. The step of heating the amorphous silicon film to which the catalytic element has been added is 500 ° C. or higher, 62
The method for manufacturing a semiconductor device according to claim 5, wherein the method is performed within a temperature range of 0 ° C. or lower. 7. The amorphous silicon film is 25 n
7. The method for manufacturing a semiconductor device according to claim 3, wherein the semiconductor device has a thickness of not less than m and not more than 80 nm. 8. The patterning process comprises using BCl ₃ and H.
The reactive ion etching method using a chlorine-based gas containing Cl is performed by a reactive ion etching method.
A method for manufacturing a semiconductor device according to any one of 1.