JP2003007716A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

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Publication number
JP2003007716A
JP2003007716A JP2001182890A JP2001182890A JP2003007716A JP 2003007716 A JP2003007716 A JP 2003007716A JP 2001182890 A JP2001182890 A JP 2001182890A JP 2001182890 A JP2001182890 A JP 2001182890A JP 2003007716 A JP2003007716 A JP 2003007716A
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Japan
Prior art keywords
silicon film
film
insulating film
heat treatment
semiconductor device
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Pending
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JP2001182890A
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Japanese (ja)
Inventor
Takeshi Nakanishi
健 中西
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Sharp Corp
シャープ株式会社
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Application filed by Sharp Corp, シャープ株式会社 filed Critical Sharp Corp
Priority to JP2001182890A priority Critical patent/JP2003007716A/en
Publication of JP2003007716A publication Critical patent/JP2003007716A/en
Application status is Pending legal-status Critical

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Abstract

(57) [Summary] [PROBLEMS] Since a long-time heat treatment is required at a high temperature and a long time is required for raising and lowering the temperature of a furnace, productivity is lowered and manufacturing cost is increased. In addition, since the activation and hydrogenation processes are performed separately, there is a problem that productivity is deteriorated. SOLUTION: A catalytic element for promoting crystallization is introduced into an amorphous silicon film 103 formed on a glass substrate 101, a crystalline silicon film 103C is formed, and a gate insulating film 104, a gate electrode 105, a crystalline silicon film 103C are formed. After an impurity is introduced into the film 103C and the interlayer insulating film 110 is formed using silicon nitride, high-pressure heat treatment is performed in a nitrogen gas atmosphere of 1 atm or more at 600 ° C. or less for 20 hours or less. By this high-pressure heat treatment, gettering of the catalytic element, activation of the silicon film, and hydrogenation can be simultaneously performed. As a result, the hydrogen concentration in the channel region
07 and the hydrogen concentration of the drain region 109,
A highly reliable TFT can be obtained.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor device having a crystalline silicon film obtained by crystallizing an amorphous silicon film as an active region, and a method of manufacturing the same. In particular, the present invention is effective for a semiconductor device using a thin film transistor (TFT) provided on a base having an insulating surface, and includes an active matrix liquid crystal display device, a contact image sensor, and a three-dimensional IC (integrated circuit). Etc. can be used. 2. Description of the Related Art In recent years, large-scale, high-resolution liquid crystal display devices, high-speed, high-resolution contact-type image sensors, and three-dimensional ICs have been developed to achieve high performance on insulating substrates such as glass. It has been attempted to form a simple semiconductor device. Normal,
In general, a thin film silicon semiconductor is used as a semiconductor element used in the above-described apparatus. Note that the thin-film silicon semiconductor is roughly classified into an amorphous silicon film (a-Si) and a crystalline silicon film. The above-mentioned amorphous silicon film can be relatively easily produced by a vapor phase method because of its low production temperature, and is most commonly used because of its high productivity. However, physical properties such as conductivity are inferior to those of a crystalline silicon film. Therefore, in order to realize higher-speed characteristics in the above-described liquid crystal display device and the like,
There is a strong demand for a method for manufacturing a thin film semiconductor device made of a silicon film having the above crystallinity. Note that as a silicon film having crystallinity, a polycrystalline silicon film, a microcrystalline silicon film, and the like are known. The following method is known as a method for obtaining the above-mentioned crystalline silicon thin film semiconductor. (1) A film having crystallinity is directly formed at the time of film formation. (2) An amorphous silicon film is formed and irradiated with intense light to make the film crystalline by its energy. (3) An amorphous silicon film is formed and crystallinity is imparted by applying thermal energy. However, in the above method (1), crystallization proceeds simultaneously with the film-forming step, so that a thick silicon film is indispensable to obtain a crystalline silicon film having a large grain size. It is technically difficult to form a film having the above all over the substrate. When the film formation temperature is 60
There is a cost problem that the temperature is as high as 0 ° C. or higher and an inexpensive glass substrate cannot be used. In the above method (2), a grain boundary is favorably treated with a small grain size in order to utilize a crystallization phenomenon in a melting and solidification process, and a high-quality crystalline silicon film is obtained. However, taking the case of using an excimer laser, which is currently most commonly used, as an example, the stability of the laser beam is not sufficient, so that the entire surface of a large-area substrate is uniformly processed to have uniform crystallinity. There is a problem that it is difficult to obtain a silicon film and it is difficult to obtain a plurality of semiconductor elements having uniform characteristics on the same base. Further, there is a problem that the irradiation area of the laser beam is small and the throughput is low. Although the method (3) has an advantage that it can cover a large area as compared with the methods (1) and (2), the crystallization requires several tens of degrees at a high temperature of 600 ° C. or more. Time-consuming heat treatment is required. That is, in order to use an inexpensive glass substrate and improve the throughput, it is necessary to simultaneously solve the conflicting problems of lowering the heating temperature and causing crystallization in a short time. Further, in the method (3), in order to utilize the solid-phase crystallization phenomenon, crystal grains spread parallel to the substrate surface and even appear with a grain size of several μm. However, since the grown crystal grains collide with each other to form a grain boundary, the grain boundary acts as a trap level for carriers, which causes a reduction in TFT mobility. A method for producing a high quality silicon film having uniform crystallinity by lower temperature and shorter time heat treatment by applying the above method (3) is disclosed in Japanese Patent Application Laid-Open No. Hei 6-333.
824, JP-A-6-333825 and JP-A-8-330602. In these publications, a metal element such as nickel is introduced into the surface of an amorphous silicon film in a characteristic amount, and then a heat treatment is performed to crystallize the film at a low temperature of 600 ° C. or less and a processing time of several hours. Are doing. The mechanism of the above-mentioned crystallization is understood from the fact that crystal nucleus generation with a metal element as a nucleus occurs at an early stage, and then the metal element acts as a catalyst to promote crystal growth, whereby crystallization proceeds rapidly. Is done. In that sense, these metal elements will be referred to as catalyst elements in the future. Crystallization is promoted by these catalytic elements, and the crystalline silicon film grown by crystal growth has a twin structure, whereas the silicon film crystallized by the ordinary solid phase growth method has many columnar crystals. The inside of each columnar crystal is close to a single crystal. [0010] If the catalyst element promoting the crystallization remains in the silicon film, normal TFT characteristics cannot be obtained. Therefore, Japanese Patent Application Laid-Open Nos. Hei 6-333824 and Hei 8-
As disclosed in JP-A-236471, gettering using P ions or the like is performed. A method in which a PSG (phosphorus silicide glass) film is provided on the surface of a silicon film containing a catalyst element and the catalyst element is gettered by phosphorus contained in the film, and phosphorus ions are implanted into the silicon film containing the catalyst element by an ion doping method. A method of doing so has been proposed. However, all of the above methods require high-temperature heat treatment for a long time, and also require a long time for raising and lowering the temperature of the furnace, resulting in low productivity.
Manufacturing costs increase. Conventionally, the heat activation process and the hydrogenation process are performed separately. However, since the heat treatment process is performed twice, there is a problem that productivity is deteriorated. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device capable of simultaneously performing gettering of a catalytic element, activation of a silicon film into which impurities are implanted, and hydrogenation. It is intended to provide a manufacturing method. It is another object of the present invention to obtain a highly reliable semiconductor device which can reduce the off-state current of a TFT, has less variation in characteristics, and has high reliability. A semiconductor device according to the present invention comprises:
A semiconductor device including a channel region, a source region, a drain region, a gate insulating film, a gate electrode, and an interlayer insulating film over a substrate having an insulating surface, wherein the hydrogen concentration of the channel region is the source region or the hydrogen concentration. It is characterized by being equal to the hydrogen concentration of the drain region. Preferably, the interlayer insulating film is made of silicon nitride. The channel region contains a catalyst element for promoting crystallization of silicon, and the concentration of the catalyst element is preferably 1 × 10 16 atoms / cm 3 or less. It is preferable that the catalyst element contains nickel. According to the method of manufacturing a semiconductor device of the present invention, there are provided a step of forming an amorphous silicon film on a substrate having an insulating surface, and a step of introducing a catalytic element for promoting crystallization of silicon into the amorphous silicon film. A first crystallization step of forming a crystalline silicon film by heating the amorphous silicon film into which the catalytic element has been introduced, and a second crystallization step of crystallizing the crystalline silicon film by laser annealing. Forming a gate insulating film covering the crystalline silicon film; forming a gate electrode on the gate insulating film; introducing an impurity into the crystalline silicon film; Forming an interlayer insulating film and performing a high-pressure heat treatment at 600 ° C. or less for 20 hours or less in an inert gas atmosphere of 1 atm or more. Characterized in that it. The inert gas atmosphere is preferably performed in at least one kind of gas atmosphere selected from nitrogen, argon and helium. Preferably, the interlayer insulating film is formed of silicon nitride. Further, it is preferable that the heat treatment in the first crystallization step is performed within a temperature range of 540 ° C. to 600 ° C. It is preferable to use nickel as the catalyst element. The method of manufacturing a semiconductor device according to the present invention can be applied to, for example, manufacturing an N-type TFT on a glass substrate. Such a TFT can be used as a constituent element of a thin film integrated circuit as well as an active matrix driver circuit and a pixel portion. In the present embodiment, a method for manufacturing hundreds of thousands to millions of N-type TFTs, which are TFTs for pixels, on an active matrix substrate for a liquid crystal display device will be described. Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A to 1D show the steps of manufacturing an N-type TFT according to the present invention in the order of steps. Although an active matrix substrate for a liquid crystal display device is provided with hundreds of thousands or more TFTs, one TFT will be described to facilitate understanding of the present invention. First, as shown in FIG. 1A, a base film 102 made of silicon oxide is formed to a thickness of 200 nm on a glass substrate 101 as an insulating substrate by a plasma CVD method. Next, an intrinsic amorphous (amorphous) silicon film 103 having a thickness of 25 to 80 nm is formed by a plasma CVD method. Amorphous silicon film 103
If the thickness of is less than 25 nm, sufficient crystal growth cannot be obtained by the subsequent introduction of the catalytic element, and if it exceeds 80 nm, the columnar crystal obtained by the subsequent introduction of the catalytic element has a two-layer structure. Crystallinity may deteriorate, and
The catalyst element may remain. Therefore, the thickness of the amorphous silicon film 103 is preferably 25 to 80 nm.
In this embodiment, the intrinsic amorphous silicon film 103
Was formed to a thickness of 40 nm. After that, unnecessary portions of the amorphous silicon film 103 are removed to perform element isolation. The amorphous silicon film 103 will be an element forming region which will be a source, drain and channel region of the TFT in a later step, and will form a number of island regions. In order to apply the present invention to an active matrix substrate for a liquid crystal display device, the amorphous silicon films 103 are arranged in a matrix. Next, Ni as a catalyst element is added to the amorphous silicon film 103 by a sputtering method. The surface concentration of Ni is 1 × 10 13 to 1 × 10 15 at.
oms / cm 2 . In the present embodiment, Ni is added so that the surface concentration of Ni becomes 7 × 10 13 atoms / cm 2 . However, the method of adding Ni is not limited to the sputtering method.
A method of forming a coating film may be used. The catalyst element to be added is Ni
In addition, one of cobalt, palladium, platinum, copper, silver, gold, indium, tin, aluminum, antimony and the like, or a plurality of types of metal elements can be used. The crystallization of the amorphous silicon film can be promoted. However, silicidation of the catalyst element promotes crystal growth of the amorphous silicon film. Among the silicide compounds of various catalytic elements, the crystal structure of NiSi 2 , which is a silicide compound of nickel as a catalytic element, is the most similar to that of single-crystal silicon. Very close. Therefore, NiSi 2 becomes the best mold for crystallization of the amorphous silicon film,
Ni is suitable as a catalyst element because crystallization of the amorphous silicon film is greatly promoted. Thereafter, as a first crystallization step, heat treatment is performed at 540 ° C. to 600 ° C. for several hours in an inert atmosphere. In the present embodiment, 580 in a nitrogen atmosphere
A heat treatment is performed at 4 ° C. for 4 hours to crystallize the amorphous silicon film 103 to form a crystalline silicon film 103C. Thus, the crystallization with the catalyst metal as a nucleus is 5 times.
By performing the heat treatment at 40 ° C. to 600 ° C. for several hours, spontaneous generation of crystal nuclei independent of the catalyst metal in the amorphous silicon film 103 can be prevented. Next, a second crystallization step for further promoting crystallization of the crystalline silicon film 103C by laser irradiation is performed. As the laser light, a KrF excimer laser having a wavelength of 248 nm and a pulse width of 20 nsec is used, but other lasers may be used. By this laser irradiation, crystallization can be further promoted and transistor characteristics can be improved. The condition of laser irradiation is that the energy density is 2
00 to 400 mJ / cm 2 , for example, 250 mJ / cm 2, and 2 to 10 shots, for example, 2 shots per one place. If the glass substrate 101 is heated to about 200 ° C. to 450 ° C. in conjunction with the laser irradiation, the crystallization of the crystalline silicon film 103C is further promoted. Next, as shown in FIG. 1B, a plasma CVD method is performed on the crystalline silicon film 103C.
A gate insulating film 104 made of a silicon oxide film having a thickness of 50 nm to 250 nm is formed. In this embodiment, the gate insulating film 104 has a thickness of 150 nm. Next, as shown in FIG. 1C, a gate insulating film 104 having a thickness of 4
A film of aluminum having a thickness of 00 nm to 800 nm is formed. In this embodiment, the thickness of the aluminum film is 600 nm. Then, the aluminum film is patterned to form the gate electrode 1.
05 is formed. Further, the surface of the gate electrode 105 is anodized to form an anodized layer 106 on the surface.
This anodization is performed in an ethylene glycol solution containing tartaric acid at 1 to 5%. The thickness of the obtained anodized layer 106 is 200 nm. The anodic oxide layer 106
Becomes the thickness for forming the offset gate region in the subsequent ion doping process, so that the length of the offset gate region can be determined in the anodic oxidation process. Next, impurities such as phosphorus or boron are implanted into the crystalline silicon film 103C by using the gate electrode 105 and the anodic oxide layer 106 around the gate electrode 105 as a mask by an ion doping method. Phosphine (PH 3 ) was used as a doping gas, and the accelerating voltage was 60 to 90 kV.
The dose is 1 × 10 15 to 8 × 10 15 cm −2 . In this embodiment, the acceleration voltage is 80 kV and the dose is 2 × 10
15 cm -2 . In this step, the region into which the impurities are implanted becomes the source region 107 and the drain region 109 of the TFT later, and is masked by the gate electrode 105 and the anodic oxide layer 106 around the gate electrode 105. The region into which the impurity is not implanted becomes the channel region of the TFT later. 108. At this time, N
In the case of fabricating a circuit in which a type TFT and a P-type TFT are formed in a complementary type, each element is selectively doped by covering a region where impurity doping is required with a photoresist, so that an N-type impurity is doped. A region and a P-type impurity region are separately formed. Next, as shown in FIG.
An interlayer insulating film 110 made of a 0-nm silicon nitride film,
It is formed by a plasma CVD method. Interlayer insulating film 110
Is a silicon nitride film, so that activation and hydrogenation can be performed simultaneously in a high-pressure heat treatment performed later. Next, in this embodiment, the heat treatment is performed for one hour in a nitrogen atmosphere at 400 ° C. and 20 atm to activate the source region 107 and the drain region 109.
Gettering, in which nickel as a catalyst element in the channel region 108 moves to the source region 107 and the drain region 109, and hydrogenation of the crystalline silicon film 103C can be performed at the same time, so that production efficiency can be improved. Source region 107 and drain region 109
Then, after phosphorus is doped, high-pressure heat treatment is performed, so that the source region 107 and the drain region 109 are activated. At the same time, Ni in the channel region 108 is changed to N by the phosphorus in the source region 107 and the drain region 109.
i is gettered, and Ni in the channel region 108 is reduced. At the same time, after the formation of the interlayer insulating film 110 made of the silicon nitride film, the silicon nitride film is heated by performing a high-pressure heat treatment. Since this silicon nitride film contains a large amount of hydrogen, the hydrogen diffuses into the crystalline silicon film 103C by heating, and
Hydrogen bonds with the dangling bonds of silicon in 3C, and hydrogenation is performed. By this high-pressure heat treatment, the source region 107
-The hydrogen concentrations in the drain region 109 and the channel region 108 become equal. A conventional TFT which does not perform high-pressure heat treatment;
For comparison with the TFT of the present embodiment, the source region 10
7. The distribution of the hydrogen concentration in the drain region 109 and the channel region 108 is shown in Table 1 and FIG. [Table 1] From Table 1 and FIG. 2, the present embodiment is more suitable for the source region 107 / drain region 109 and the channel region 10.
It can be seen that the hydrogen concentrations in 8 are equivalent. On the other hand, in the conventional case, the hydrogen concentration in the source region 107 / drain region 109 and the hydrogen concentration in the channel region 108 are not equal. Conventionally, the hydrogenation of the channel region 108 immediately below the gate electrode 105 is insufficient due to the presence of the gate electrode 105, and the hydrogen concentration is reduced by about one digit. In the high-pressure heat treatment, hydrogen is also pushed right below the gate electrode 105, so that the channel region 108 and the source region 10
7. The same is applied to the drain region 109, and hydrogenation is sufficiently performed. Source region 107 and drain region 109
This indicates that the higher the hydrogen concentration in the channel region 108, the better the dangling bonds of silicon and hydrogen. The fact that the hydrogen concentrations are the same means that the source region 107 / drain region 109 and the channel region 108 have the same film quality. Therefore, when the hydrogen concentration is high and the hydrogen concentration is equal between the source region 107 / drain region 109 and the channel region 108, the off-state current of the TFT can be reduced, the variation in characteristics is small, and the reliability is high. A TFT can be obtained. This high-pressure heat treatment is performed at a temperature of 50 ° C. or more and 600 ° C.
In the following, the conditions may be 1 minute to 20 hours in an inert gas atmosphere of 1 to 50 atmospheres. The inert gas atmosphere may be selected from one or more of nitrogen, argon, and helium. Further, since the treatment is carried out at a high pressure, the time for raising and lowering the temperature thermodynamically is reduced. That is, the process time can be reduced, and the productivity can be improved. After the gettering of the catalytic element, the concentration of the catalytic element remaining in the channel region 108 is 1 × 10 16
If the value is not more than atoms / cm 3 , a TFT free from an increase in leakage current and deterioration in characteristics can be obtained. Next, as shown in FIG. 1D, a contact hole is formed in the interlayer insulating film 110 and the gate insulating film 104. Thereafter, the source region 107 and the drain region 109 of the TFT are filled with a metal material, for example, a multilayer film of titanium nitride and aluminum in the formed contact hole.
The source electrode 111 and the drain electrode 1 conducting to the
12 is formed. When this TFT is used as a pixel switching element of a liquid crystal display device or the like, a pixel electrode made of ITO or the like is formed instead of the source electrode 111 and the drain electrode 112 made of a metal material, and the TFT is formed. Complete. According to the production method of the present invention, at least one
By performing the heat treatment under a high pressure condition higher than the atmospheric pressure, gettering of the catalytic element, activation of the crystalline silicon film, and hydrogenation can be performed at the same time, and the production efficiency can be improved. Further, since the treatment is performed at a high pressure, the time required for raising and lowering the temperature thermodynamically is reduced. That is, the process time can be reduced, and the productivity can be improved. By this high-pressure heat treatment, the channel region,
The hydrogen concentration in the source region and the drain region becomes equal and high, and the off-state current of the TFT can be reduced, so that a highly reliable TFT with less variation in characteristics can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a process sectional view showing an example of a manufacturing process of a TFT according to an embodiment of the present invention. FIG. 2 is a diagram showing a comparison between the present invention and a conventional example with respect to hydrogen concentrations in a source region 107, a drain region 109, and a channel region 108. DESCRIPTION OF SYMBOLS 101 Glass substrate 102 Base film 103 Amorphous silicon film 103C Crystalline silicon film 104 Gate insulating film 105 Gate electrode 106 Anodized layer 107 Source region 108 Channel region 109 Drain region 110 Interlayer insulating film 111 Source electrode 112 Drain electrode

Continued on the front page (51) Int.Cl. 7 Identification code FI Theme coat II (Reference) H01L 29/786 H01L 29/78 616L 627G F-term (Reference) 2H092 JA24 JA28 JB56 KA05 KB25 MA27 MA29 MA30 NA11 NA24 5C094 AA43 AA44 BA03 BA43 CA19 DA15 EA04 EA07 FB14 JA01 5F052 AA02 AA11 AA17 BB07 CA04 DA02 DB03 FA06 FA19 HA01 JA01 5F110 AA06 AA14 AA16 BB02 BB04 BB10 BB11 CC02 DD02 DD13 EE03 EE34 EE44 FF02 GG30 H01 GG30 GG02GG HM14 NN04 NN24 NN35 PP01 PP03 PP04 PP05 PP10 PP13 PP29 PP34 QQ08 QQ23 QQ28 QQ30

Claims (1)

  1. Claims 1. A semiconductor device including a channel region, a source region, a drain region, a gate insulating film, a gate electrode, and an interlayer insulating film over a substrate having an insulating surface, The semiconductor device according to claim 1, wherein a hydrogen concentration in the region is equal to a hydrogen concentration in the source region or the drain region. 2. The semiconductor device according to claim 1, wherein said interlayer insulating film is made of silicon nitride. 3. The channel region contains a catalytic element that promotes crystallization of silicon.
    2. The semiconductor device according to claim 1, wherein the density is not more than × 10 16 atoms / cm 3 . 4. The semiconductor device according to claim 3, wherein said catalyst element contains nickel. 5. A step of forming an amorphous silicon film on a substrate having an insulating surface; a step of introducing a catalytic element for promoting crystallization of silicon into the amorphous silicon film; A first crystallization step of forming a crystalline silicon film by heat treatment of the silicon film; a second crystallization step of crystallizing the crystalline silicon film by laser annealing; and covering the crystalline silicon film. Forming a gate insulating film; forming a gate electrode on the gate insulating film; introducing an impurity into the crystalline silicon film; forming an interlayer insulating film on the gate electrode Process, in an inert gas atmosphere of 1 atm or more, 600 ° C. or less, 2
    Performing a high-pressure heat treatment for 0 hour or less. 6. The method according to claim 5, wherein the inert gas atmosphere is performed in at least one kind of gas atmosphere selected from nitrogen, argon, and helium. 7. The method according to claim 5, wherein the interlayer insulating film is formed of silicon nitride. 8. The heat treatment in the first crystallization step may include:
    The method according to claim 5, wherein the method is performed within a temperature range of 40 ° C. to 600 ° C. 7. 9. The method according to claim 5, wherein nickel is used as the catalyst element.
JP2001182890A 2001-06-18 2001-06-18 Semiconductor device and its manufacturing method Pending JP2003007716A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100685395B1 (en) * 2004-06-30 2007-02-22 삼성에스디아이 주식회사 Fabrication method of display device
KR100731745B1 (en) 2005-06-22 2007-06-22 삼성에스디아이 주식회사 OLED and method of fabricating the same
US7791074B2 (en) 2005-09-06 2010-09-07 Canon Kabushiki Kaisha Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous oxide film
CN103715094A (en) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 Thin film thyristor and manufacturing method thereof, array substrate and manufacturing method thereof and display device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100685395B1 (en) * 2004-06-30 2007-02-22 삼성에스디아이 주식회사 Fabrication method of display device
KR100731745B1 (en) 2005-06-22 2007-06-22 삼성에스디아이 주식회사 OLED and method of fabricating the same
US8044576B2 (en) 2005-06-22 2011-10-25 Samsung Mobile Display Co., Ltd. Organic light emitting display and method of fabricating the same
US7791074B2 (en) 2005-09-06 2010-09-07 Canon Kabushiki Kaisha Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous oxide film
US7935582B2 (en) 2005-09-06 2011-05-03 Canon Kabushiki Kaisha Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous oxide film
US7956361B2 (en) 2005-09-06 2011-06-07 Canon Kabushiki Kaisha Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous oxide film
US8154024B2 (en) 2005-09-06 2012-04-10 Canon Kabushiki Kaisha Field effect transistor using amorphous oxide film as channel layer, manufacturing method of field effect transistor using amorphous oxide film as channel layer, and manufacturing method of amorphous oxide film
CN103715094A (en) * 2013-12-27 2014-04-09 京东方科技集团股份有限公司 Thin film thyristor and manufacturing method thereof, array substrate and manufacturing method thereof and display device
US9806108B2 (en) 2013-12-27 2017-10-31 Boe Technology Group Co., Ltd. Manufacturing method of thin film transistor, manufacturing method of array substrate and array substrate

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