JP2000216089A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent catalystic elements from segregating so as to lessen a leakage current in a thin film transistor, by a method wherein an amorphous silicon film that contains catalystic and gettering elements is heated, and gettering of catalystic elements and crystallization in a prescribed region are carried out in a single heating process. SOLUTION: An intrinsic amorphous silicon film α-Si 2 is formed on all the top surface of a glass board 1. A photoresist film formed on the film 2 is patterned into an island-like mask 3. Phosphorus is not injected into the regions 2b of the silicon film 2 covered with the mask 3 but selectively injected into only the regions 2a of the film 2. After the mask 3 is separated off, nickel is added to the top surface of the film 2 to form a discontinuous film 5. Thereafter, the substrate 1 is thermally treated in an atmosphere of inert nitrogen and then cooled down to a room temperature. In this thermal process, the film 2 is crystallized, and nickel contained in the nickel-containing film 5 is turned to nickel silicide reacting on silicon contained in the film 2 located under the film 5. Nickel is trapped and gettered by phosphorus contained in the regions 4a or regions 2a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device having a crystalline silicon film obtained by crystallizing an amorphous silicon film as an active region. The present invention is particularly directed to a thin film transistor (TFT) provided on a substrate having an insulating surface.
, For example, an active matrix type liquid crystal display device, a contact type image sensor, and a three-dimensional IC.

[0002]

2. Description of the Related Art In recent years, high-performance semiconductor devices have been mounted on insulating substrates such as glass for realizing high-resolution large-sized liquid crystal display devices, high-speed and high-resolution contact-type image sensors, and three-dimensional ICs. Attempted to form. In general, a thin-film silicon semiconductor is used for a semiconductor element used in these devices. As a thin film silicon semiconductor, an amorphous silicon semiconductor (a-Si)
And a silicon film having crystallinity.

[0003] Amorphous silicon semiconductors are most commonly used because they have a low manufacturing temperature, can be manufactured relatively easily by a gas phase method, and have high mass productivity. However, amorphous semiconductors have a problem that physical properties such as conductivity are inferior to crystalline silicon semiconductors. Therefore, in order to obtain higher-speed characteristics in the future, there is a strong demand for establishing a method of manufacturing a semiconductor device made of a crystalline silicon semiconductor. Note that polycrystalline silicon, microcrystalline silicon, and the like are known as silicon semiconductors having crystallinity.

[0004] The following three methods are known as methods for obtaining a thin film silicon semiconductor having such crystallinity. (1) A film having crystallinity is formed directly on a substrate during film formation. (2) The amorphous semiconductor is crystallized by applying strong light energy to the amorphous semiconductor film previously formed on the substrate. (3) An amorphous semiconductor film is formed on a substrate in advance, and the amorphous semiconductor is crystallized by heating and applying thermal energy.

However, in the method (1), the crystallization proceeds simultaneously with the film forming step, so that a thick film is indispensable to obtain crystalline silicon having a large grain size, and a film having good semiconductor properties is required. It is technically difficult to form a film over the entire surface of the substrate. In addition, since the film formation temperature is as high as 600 ° C. or more and an inexpensive glass substrate cannot be used, a more expensive substrate has to be used, and there is a problem that the cost increases.

On the other hand, in the method (2), since the crystallization phenomenon in the melting and solidification process is used, the obtained crystal grain size is small, but the crystal grain boundaries are well treated and high quality is obtained. Crystalline silicon can be obtained. In such methods, excimer lasers are currently most commonly used. In this case, since the stability of the laser is not sufficient, it is difficult to obtain a silicon film having uniform crystallinity when uniformly processing the entire surface of a large-area substrate, and therefore, it is difficult to obtain a silicon film having uniform characteristics on the same substrate. There is a problem that it is difficult to obtain a plurality of semiconductor elements. Further, in this case, since the irradiation area of the laser beam is small, there is a problem that the throughput is low.

In contrast to the methods (1) and (2), the method (3) has an advantage that it can be applied to a large-area substrate. However, the method (3) requires a heat treatment for several tens of hours at a high temperature of 600 ° C. or higher for crystallization of amorphous silicon. In other words, in order to reduce the manufacturing cost using an inexpensive glass substrate and to improve the throughput, in the heat crystallization process, there is a conflicting problem that the processing temperature is reduced and the processing time is shortened. Must be resolved at the same time. In addition, in the method (3), since the solid phase crystallization phenomenon is used, the crystal grains spread in parallel to the substrate surface, and the obtained crystal grain size is relatively large (up to several μm). ) Has a problem that the crystal grain boundaries are not well treated. More specifically, the crystal grains grown according to the method (3) collide with each other to form a grain boundary, and the grain boundary acts as a trap level for carriers, which causes a problem of lowering carrier mobility. is there.

Japanese Patent Application Laid-Open No. 6-333824 discloses a method of applying the above method (3) to produce a high-quality silicon film having uniform crystallinity by lower-temperature and shorter-time heat treatment.
And Japanese Patent Application Laid-Open Nos. Hei 6-333825 and Hei 8-330602. According to these publications, a small amount of a metal element such as nickel is introduced into the surface of an amorphous silicon film, and then a heat treatment is performed. Crystallization of amorphous silicon is performed in a short time.

[0009] The crystallization mechanism in the above-mentioned method is that crystal nuclei having a metal element as a nucleus are generated at an early stage, and then the metal element serves as a catalyst to promote crystal growth, whereby crystallization proceeds rapidly. It is understood by doing. Throughout this specification, a metal element having such a function is referred to as a catalyst element. A crystalline silicon film crystallized using these catalytic elements is composed of many columnar crystals, whereas a silicon film crystallized by a normal solid-phase growth method has a twin structure. I have. Furthermore, the inside of each columnar crystal is in a state close to a single crystal, and has good crystallinity.

[0010]

The above-described method of crystallizing a silicon film using a catalytic element is very effective in that it is performed in a low-temperature and short-time process. However, a transistor using crystalline silicon manufactured according to such a method has a problem in stability and reliability of transistor characteristics. This is caused by impurities in the crystalline silicon film.

[0011] Examples of the impurity include a catalyst element itself. The catalyst element as described above promotes the crystallization of the amorphous silicon film in the heating crystallization step, and is thereafter trapped at the crystal grain boundaries and remains in the crystalline silicon film in a state unevenly distributed near the grain boundaries. . The presence of a large amount of these catalytic elements in the crystalline silicon film that forms the active region (element region) of a semiconductor device such as a transistor reduces the reliability and / or electrical stability of the semiconductor device. Inhibits and is not preferred.

In particular, elements such as nickel, cobalt, and platinum, which have a high ability to promote crystallization of an amorphous silicon film, form impurity levels near the center of the band gap in the silicon film, and adversely affect TFT characteristics. give. In particular, when a TFT is made of a silicon film crystallized using such a catalyst element, phenomena such as an increase in leak current and a decrease in reliability mainly at the time of TFT off operation are mainly caused by the influence of a residual catalyst element. Appears. The catalytic element is T
Since the crystallinity of the channel region of the FT element is improved, the current driving capability such as the field effect mobility and the on-current rise coefficient (S coefficient) is improved.
It causes deterioration of off-characteristics, reliability, stability, and the like.

As a method for solving the problem of the catalytic element impurities as described above, the above three publications disclose a method of removing a catalytic element by using a phosphorus atom having an effect of collecting the catalytic element (a gettering effect). are doing. This method is based on the idea that the catalyst element used for crystallization of amorphous silicon is removed from the silicon film when the crystallization is completed and the catalyst element becomes unnecessary. However, in practice, it is very difficult to completely remove a large amount of catalytic elements by gettering. Specifically, JP-A-6-333824 and JP-A-6-3
No. 33825 describes a method in which phosphorus for gettering a catalytic element is used in the form of a PSG (phospho-silicate glass) film. Here, if the PSG film and the silicon film are in direct contact with each other, phosphorus in the PSG film is diffused and introduced into the silicon film. Therefore, the silicon film and the PSG film are provided with a silicon oxide film interposed therebetween. Have been. However, Japanese Patent Application Laid-Open Nos.
The method of gettering a catalytic element through a silicon oxide film as described in 33825 has almost no effect in practice. The reason is that the diffusion rate of the catalytic element in the silicon oxide film is much lower than the diffusion rate in the silicon film. In the case of nickel, which is a typical catalyst element, the diffusion rate in a silicon oxide film is lower than the diffusion rate in a silicon film by five digits or more.

On the other hand, in Japanese Patent Application Laid-Open No. 8-330602, T is used as phosphorus for gettering a catalytic element.
A method using doped phosphorus in the source / drain regions of the FT active region is described. According to this method, since the silicon film is doped with phosphorus,
A certain gettering effect can be obtained without lowering the diffusion rate of the catalytic element. However, in this method, since the phosphorus is doped into the source / drain region of the TFT active region, the catalytic element is gettered inside the element region. As a result, a region in which the catalytic elements are collected remains in the element region, so that sufficient reliability of the TFT cannot be obtained. Furthermore, according to this method, the catalyst element at the junction between the drain region and the channel region is not doped with phosphorus, so that the catalyst element remains as it is. Therefore, this method cannot solve the problem of increase in TFT leak current.

Further, in the above three publications, after a heat treatment step for crystallization using a catalytic element, a heat treatment for gettering the catalytic element is further performed using an element having a gettering effect. Requires processing steps.
Therefore, in the conventional technique, since two heat treatment steps are required, the throughput is very slow. According to these methods, the substrate is cooled to room temperature after the heat treatment step for crystallization. The catalytic element is dissolved in the silicon during the heat treatment. However, as the substrate (including silicon) is cooled, the solid solubility limit of the catalytic element in silicon is lowered, so that the catalytic element segregates. There is a problem that the segregation of the catalytic element lowers the gettering efficiency in the subsequent heating step for gettering. Furthermore, the region where this catalytic element has segregated
When it is present in the channel region of the element and in the junction between the channel region and the drain region, it is a major cause for increasing the leak current of the TFT.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to perform crystallization of amorphous silicon by a catalytic element and gettering of a catalytic element by an element having a gettering effect. A method of manufacturing a semiconductor device, wherein segregation of a catalyst element is prevented,
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a leakage current of a TFT is reduced and throughput is improved.
It is a further object of the present invention to provide a method of manufacturing the above semiconductor device, which manufactures a semiconductor device having very high performance and high reliability on a substrate having an insulating surface at a higher yield. It is in.

Note that throughout this specification, the term "gettering element" refers to an element having an effect of collecting (gettering) a catalytic element. Also, the term "silicon" is intended to include both amorphous silicon and crystalline silicon.

[0018]

A method of manufacturing a semiconductor device according to the present invention comprises a step of crystallizing an amorphous silicon film using a catalytic element to form a crystalline silicon film. Forming an amorphous silicon film on a substrate having an insulating surface;
A step of introducing a gettering element into a predetermined region of the amorphous silicon film, a step of introducing a catalytic element into the amorphous silicon film, and heating and crystallizing the amorphous silicon film into which the catalytic element has been introduced. A crystallization step of forming a crystalline silicon film by heating the amorphous silicon film containing the catalyst element and the gettering element to collect the catalyst element in the predetermined region of the amorphous silicon film. A crystallization step and the gettering step are performed in a single heating step, thereby solving the above-mentioned problem.

The step of introducing the catalyst element includes forming a catalyst element-containing film on the amorphous silicon film, and heating the catalyst element-containing film and the amorphous silicon film to form the catalyst element-containing film. A crystal nucleus forming step of forming a crystal nucleus by thermally introducing a catalyst element from the film to the amorphous silicon film, and introducing the gettering element, wherein a mask film is formed on the catalyst element-containing film. Forming, patterning the mask film, removing the mask film formed on the predetermined region of the amorphous silicon film, and using the patterned mask film to form the gettering element. Introducing the crystal silicon into the predetermined region of the amorphous silicon film, wherein the heating step includes the crystal nucleus forming step, and The method is performed in a state where the catalyst element-containing film and the patterned mask film are provided, and a gettering element is introduced into the predetermined region of the amorphous silicon film. After the step, the method may further include a step of removing the patterned mask film from the crystalline silicon film and a step of removing at least the predetermined region of the crystalline silicon film.

In the step of introducing the gettering element,
Forming a mask film on the amorphous silicon film, patterning the mask film, and removing a mask film formed on the predetermined region of the amorphous silicon film; A step of introducing the gettering element into the predetermined region of the amorphous silicon film using a mask film, and a step of removing the patterned mask film from the amorphous silicon film. The step of introducing includes forming a catalyst element-containing film on the amorphous silicon film into which the gettering element is introduced, and heating the catalyst element-containing film and the amorphous silicon film to form the catalyst element. A crystal nucleus forming step of forming a crystal nucleus by heat-introducing a catalyst element from the containing film into the amorphous silicon film. Extent encompasses the crystal nucleation step,
The catalyst element-containing film is disposed on the amorphous silicon film, the mask film is not disposed, and the operation is performed in a state where the gettering element is introduced into the predetermined region of the amorphous silicon. The method may further include a step of removing at least the predetermined region of the crystalline silicon film after the heating step.

The gettering element is preferably phosphorus.

The step of removing at least the predetermined region may include a step of patterning the crystalline silicon film to form an active region of a semiconductor device.

In the step of removing at least a predetermined region, the crystalline silicon film is etched to include the crystalline silicon film including at least the predetermined region, the catalyst element, and a silicide compound of the catalyst element. May be included.

The step of removing at least the predetermined region may be performed by a reactive ion etching method using a chlorine gas or a chlorine-based gas containing BCl ₃ and HCl.

In the heating step, the catalyst element is diffused inside the amorphous silicon film and / or the crystalline silicon film, the gettering element is not diffused, and natural nucleation is not generated. It is preferably performed within a temperature and time range.

The heating step is performed at a temperature of 520 ° C. or more and 620 ° C.
It is preferable to perform the reaction in the following temperature range.

The amorphous silicon film has a thickness of 25 nm.
As described above, it is preferable to have a thickness of 80 nm or less.

The concentration of the catalytic element contained in the active region is preferably 1 × 10 ¹⁶ atoms / cm ³ or less.

The above-mentioned catalyst elements are Ni, Co, Pd, P
t, Cu, Ag, Au, In, Sn, Al, and Sb
It is preferably at least one element selected from the group consisting of

It is preferable that the catalyst element contains at least Ni.

Hereinafter, the operation of the present invention will be described.

According to the method of the present invention, in the same heating step, the amorphous silicon film is crystallized by the catalytic element, whereby the crystalline silicon film is formed, and the predetermined silicon containing the gettering element is introduced. The catalytic element is collected in the region. The crystallization and gettering mechanism in this heating step will be described as follows.

First, a silicide of a catalytic element is formed by a reaction between the catalytic element and amorphous silicon.
The silicide of this catalytic element, in the early stage of crystallization,
Functions as a crystal nucleus. It is considered that the catalyst element does not act as a catalyst for crystallization of amorphous silicon in its own state, but has a catalytic action by forming silicide by bonding with silicon.
The reason for this is that the crystal structure of the catalyst element silicide is considered to act like a kind of template when crystallizing amorphous silicon and promote crystallization.

The catalyst element constituting the crystal nucleus (silicide of the catalyst element) exists at the interface between amorphous silicon and crystalline silicon. This is because, due to the difference in chemical potential, by being present at the interface between amorphous silicon and crystalline silicon, the most stable state in terms of energy can be obtained.

As the crystallization of amorphous silicon progresses, the interface between amorphous silicon and crystalline silicon moves, and at the same time, the catalyst element constituting the crystal nucleus also moves. This promotes further crystallization of amorphous silicon. When the entire silicon film is crystallized and the amorphous silicon / crystalline silicon interface disappears, the catalyst element is gettered by the gettering element and collected in a predetermined region. In this heating step, the solid solubility of the catalytic element in silicon is sufficiently high, so that the catalytic element does not segregate.

Therefore, according to the present invention, the step of crystallizing the amorphous silicon using the catalytic element and the step of gettering the catalytic element with the gettering element include:
It can be performed simultaneously by one heating step. This makes it possible to reduce the number of heating steps that were conventionally required twice to one, and to improve the throughput. In the conventional method, there is a cooling step of cooling to around room temperature between the crystallization step and the catalyst element gettering step. During the cooling step, the solid solubility of the catalyst element in silicon is reduced, and there is a problem that segregation of the catalyst element may occur. In contrast, according to the present invention, the crystallization step and the catalyst element gettering step are performed in the same heating step, and the catalyst element is gettered inside a predetermined region during the heating step. I have. Therefore, even after the cooling step, the segregation of the catalytic element never occurs outside the predetermined region. Therefore, according to the present invention, a trap level due to segregation of the catalytic element is not formed, so that a leak current of the TFT can be reduced.

In one embodiment of the present invention, as described later in Embodiment 2, the heating step comprises disposing a catalyst element-containing film and a patterned mask film on an amorphous silicon film, In addition, the process is performed in a state where a gettering element is introduced into a predetermined region of the amorphous silicon film. Thus, since the heat treatment can be performed in a state where the mask film is provided on the amorphous silicon film, contamination of the amorphous silicon film (that is, the obtained crystalline silicon film) from the heating device can be prevented. Can be. As this mask film, a silicon oxide film or the like can be used. Further, in this embodiment,
At least a predetermined region of the crystalline silicon film into which the gettering element is introduced, that is, a region where the catalyst element is gettered by the above-described heating step is removed.
This makes it possible to obtain a semiconductor device free of a catalyst element and a gettering element. Therefore, a high-performance semiconductor device having stable characteristics with little leakage current can be realized.

In one embodiment of the present invention, as described later in Embodiment 1, a catalyst element-containing film is provided on an amorphous silicon film, a mask film is not provided, and amorphous silicon This is performed in a state where a gettering element is introduced into a predetermined region. In this method, the mask film is made of a photoresist or the like, and the heat treatment cannot be performed with the mask film provided.
It is suitably used when it is necessary to peel off the mask film before the heating step. In the case where the catalyst element-containing film is provided between the mask film and the amorphous silicon film as in the above-described embodiment, the catalyst element-containing film is also separated at the same time as the mask film is separated. Even if heat crystallization is performed later, an effective catalytic action cannot be obtained. On the other hand, according to the present embodiment, the catalyst element-containing film is provided on the amorphous silicon film, the mask film is not provided, and the gettering is performed inside the predetermined region of the amorphous silicon. Heating can be performed with the element introduced. In particular, when a photoresist is used as the mask film, a film formation step or the like is not required, and the number of steps can be further reduced. Furthermore, during the heating step, nothing is disposed on the amorphous (or crystalline) silicon film and the silicon film is exposed, so that the silicon film is stress-free, and the crystal growth and the catalyst by the stable catalytic element are performed. Gettering of elements becomes possible. Further, also in this embodiment, at least a predetermined region of the crystalline silicon film into which the gettering element is introduced, that is, a region where the catalyst element is gettered by the above-described heating step. This makes it possible to obtain a semiconductor device free of a catalyst element and a gettering element. Therefore, a high-performance semiconductor device having stable characteristics with little leakage current can be realized.

In the present invention, the same effect can be obtained by using phosphorus, sulfur, arsenic, selenium, or the like as the gettering element. Among these elements,
It is particularly preferred to use phosphorus which has the greatest catalytic element gettering effect.

In one embodiment of the present invention, the step of removing at least a predetermined region includes the step of patterning the crystalline silicon film to form an active region of a semiconductor device. More preferably, the step of forming the active region is performed simultaneously. This not only reduces the number of steps, but also
All unnecessary regions can be removed, and contamination of the element region with the catalytic element can be further reduced. In this removing step, even if the silicon film is removed, if the catalytic element remains without being removed, the active region may be contaminated by the diffusion of the catalytic element. It is important to consider the etching selectivity with the catalytic element.

Since most of the catalytic element is present in silicon as a silicide compound, it is preferable that the silicon film, the catalytic element and the silicide compound of the catalytic element be removed at the same time. As this method, there is a wet etching method using a mixed solution of hydrofluoric acid and nitric acid,
Not suitable for microfabrication. On the other hand, the dry etching method is preferable because it is suitable for fine processing. In particular, reactive ion etching (RI) using a chlorine gas or a chlorine-based gas containing BCl ₃ and HCl.
By using the method E), the catalyst element and the silicide compound of the catalyst element are simultaneously etched together with the silicon film, so that a clean etching region having no etching residue can be obtained.

In one embodiment of the present invention, the heating step is such that the catalyst element diffuses inside the amorphous silicon film and / or the crystalline silicon film, the gettering element does not diffuse, and the natural nucleation occurs. Is carried out within a temperature and time range such that no occurrence occurs. Preferably, about 56
0 to about 20 hours at 0 ° C, 0 to about 14 hours at about 580 ° C,
0-about 5 hours at about 600 ° C. Within such a temperature and time range, the absence of spontaneous nucleation can be observed with an optical microscope. In order to getter the catalytic element in a predetermined region, the higher the processing temperature, the higher the thermal diffusion coefficient of the catalytic element. Therefore, a higher gettering effect can be obtained by treating at a higher temperature. However, if the processing temperature is too high, the gettering element introduced into the predetermined region may also be thermally diffused, and the gettering element may diffuse from the predetermined region to reach the channel region. According to this embodiment, the catalyst element diffuses inside the amorphous silicon film and / or the crystalline silicon film,
Since the gettering element is performed in a temperature range that does not diffuse, the gettering element can be kept in a predetermined region, and the catalyst element can be gettered inside the predetermined region. Further, when natural nucleation occurs in the amorphous silicon film, the crystal grown by the catalytic element collides with the nucleus generated by the natural nucleation, and the grown crystal bends and / or branches. This allows
As the crystallinity of the obtained crystalline silicon deteriorates,
The catalytic element is trapped at the collision position, and the gettering efficiency of the catalytic element may decrease. Specifically, this heating step is preferably performed within a temperature range of 520 to 620 ° C.

In the present invention, the amorphous silicon film preferably has a thickness of 25 to 80 nm. If the film thickness is less than 25 nm, crystal growth of crystalline silicon obtained from amorphous silicon cannot be sufficiently obtained. On the other hand, when the film thickness is larger than 80 nm, the columnar crystal structure in the obtained crystalline silicon has a two-layer structure, which causes problems such as deterioration of crystallinity and / or residual catalytic elements. An object of the present invention is to significantly reduce the concentration of a catalytic element in an active region of a semiconductor device. For that purpose, the concentration of the catalytic element contained in the finally obtained active region is 1 × 10 ¹⁶ atoms /
cm ³ or less. According to the conventional method, the concentration of the catalytic element contained in the active region is 1 × 10 ¹⁷ to 1
About 10 ¹⁸ atoms / cm ³ ,
There has been an increase in leak current and / or deterioration of characteristics in the TFT element. To eliminate this effect, the concentration of the catalyst element contained in the active region should be 1 × 10 ^{16 at.}
The concentration needs to be not more than ms / cm ³ . As in the present invention, the thickness of the amorphous silicon is 25 to 80 nm.
By doing so, these problems can be avoided.

Further, in the present invention, the catalytic elements include Ni, Co, Pd, Pt, Cu, Ag, Au, and I.
A similar effect can be obtained by using one or more elements selected from the group consisting of n, Sn, Al, and Sb. These elements have a sufficient effect of promoting crystallization even in a trace amount. Among these elements, it is particularly preferable to use Ni. Ni combines with _two Sis to form a silicide represented by NiSi2. NiSi ₂ has a fluorite-type crystal structure and is very similar to the diamond structure of single crystal silicon. In addition, the lattice constant of NiSi ₂ is 5.406 A,
Very close to the lattice constant of crystalline silicon (5.430 A). That is, NiSi ₂ is an optimal template when crystallizing an amorphous silicon film. For this reason, the use of Ni is particularly preferred.

[0045]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention are shown in FIGS.
This will be described below with reference to FIG.

(Embodiment 1) In this embodiment, N
FIG. 1 shows a method of manufacturing a semiconductor device having a channel type TFT, and more specifically, a method of manufacturing an active matrix substrate for a liquid crystal display device having a pixel TFT.
This will be described with reference to FIG. N-channel type TF
Among semiconductor devices provided with T, in particular, an active matrix substrate for liquid crystal display requires that hundreds of thousands to millions of N-channel TFTs be uniformly formed on the substrate. Note that the TFT described in this embodiment can also be used for other active matrix driver circuits, pixel portions, elements included in a thin film integrated circuit, and the like.

FIGS. 1A to 1D are schematic partial plan views illustrating a method for manufacturing a liquid crystal display active matrix substrate 100 having a pixel TFT according to the present embodiment. Actually, hundreds of thousands or more TFTs are formed on an active matrix substrate for liquid crystal display.
In (d), a total of 12 TFTs of 3 rows × 4 columns will be described. FIG. 2 is a manufacturing process diagram in a TFT cross section along the line AA ′ in FIG. FIG.
2 and FIG. 2, the manufacturing process proceeds in the order of FIGS. 1 (a) to (d) and FIGS. 2 (a) to (f).

First, as shown in FIG. 2A, the entire surface of the glass substrate (Corning 1737) 1
An intrinsic (I-type) amorphous silicon film (a-Si film) 2 having a thickness of about 25 to about 80 nm, in this embodiment, about 30 nm, was formed by the VD method.

Next, as shown in FIGS. 1A and 2B, a mask film 3 was formed in an island shape on the a-Si film 2 by patterning a photoresist. This allows
A region 2a where the a-Si film 2 is exposed in a mesh shape through the through holes of the mask film 3, and an a-Si film 2 covered with the mask film 3
The unexposed region 2b of the Si film 2 was formed.

Next, referring to FIG. 2B, phosphorus was doped toward the glass substrate 1 from above the mask film 3 (indicated by an arrow in the figure). Here, phosphorus was not implanted into the region 2b covered with the mask film 3, but was selectively implanted only into the region 2a. In this step, phosphine (PH ₃ ) is used as a doping gas, the acceleration voltage is set to about 5 to about 20 kV, for example, about 10 kV, and the dose is about 5 × 10 ¹⁵ to about 1 × 10 ¹⁷ cm ⁻² , for example, about 5 × 10 ¹⁶
cm ^-2 . In the present embodiment, this phosphorus is a gettering element.

After the mask film 3 is peeled off, as shown in FIG. 2C, nickel is coated on the upper surface of the a-Si film 2 by a spin coating method at a surface concentration of about 1 × 10 ¹² to about 1 × 10 ¹⁴ atoms.
s / cm ² , 3 × 10 ¹² atoms / c in the present embodiment
m ² to form a nickel-containing film 5. In the present embodiment, this nickel is a catalyst element. Here, the nickel-containing film 5 is a discontinuous film existing in an island shape.

Thereafter, the substrate is placed in an inert atmosphere for about 5 minutes.
The heat treatment was performed at a temperature of 20 to about 620 ° C for several hours. In the present embodiment, after heat-treating at a temperature of about 580 ° C. for about 1 hour in a nitrogen atmosphere, the temperature is raised to about 60 ° C.
The heat treatment was performed at 0 ° C. for about 5 hours. Thereafter, the substrate was cooled to room temperature.

In this heating step, the a-Si film 2 is crystallized to become a crystalline silicon film 4. The crystallization mechanism will be described below. First, nickel of the nickel-containing film 5 is silicided with silicon of the underlying a-Si film 2. With the nickel silicide (not shown) serving as a nucleus, crystallization of the amorphous silicon in the a-Si film 2 proceeds. The crystallization of the amorphous silicon proceeds from the nucleus to the peripheral region, and finally the a-Si film 2 becomes
The whole crystallizes to form a crystalline silicon film 4. Since this crystallization is performed under the temperature and time conditions under which no spontaneous nucleation occurs, crystallization is caused by nickel which is a catalytic element. In FIG. 2C, the crystalline silicon film 4 is composed of regions 4a and 4b, which correspond to the regions 2a and 2b, respectively.

In this heating step, the nickel silicide, which is the nucleus, gathers in the phosphorus-doped region 4a (or region 2a) as shown in FIG. 2 (c). The reason for this is that phosphorus attracts nickel and then a compound of phosphorus and nickel is formed, ie, phosphorus has the effect of trapping nickel. The nickel silicide moves by thermal diffusion and is trapped by phosphorus in region 4a (or region 2a) and collected (ie, gettered) in this region. In this heating step, the solid solubility of nickel in crystalline silicon is sufficiently large at high temperatures, so that nickel segregation hardly occurs. In the subsequent cooling step, the solid solubility of nickel in crystalline silicon decreases depending on the decrease in the substrate temperature, so that nickel segregation may occur. However, since nickel has already been collected in the region 4a due to the phosphorus gettering effect during the heating process, even if nickel segregation occurs during the cooling process, nickel segregation occurs only inside the region 4a. Occur.

After the cooling step, FIG. 1 (b) and FIG.
As shown in (d), the crystalline silicon film 4 is patterned into an island shape to form a region 4c to be an active region of the TFT, whereby the nickel-containing film 5, nickel silicide (not shown), Unnecessary portions of the crystalline silicon film were removed, and isolation between elements was formed. Here, the unnecessary portion of the crystalline silicon film includes the region 4a containing nickel gettered by phosphorus, and is preferably
This is a portion including a part of the region 4b located around the region 4a. This removal step was performed by dry etching (reactive ion etching). Specifically, RF
Power: about 1500W, pressure: about 20mTorr, BC
l ₃ flow rate: etched at about 140 sccm, further subsequently, RF power: about 400W, pressure: about 95mT
Etching was performed at orr, CF ₄ / O ₂ flow rate: about 100/300 sccm.

At this stage, when the nickel concentration in the region 4c was measured by secondary ion mass spectrometry (SIMS), it showed a value of 5 × 10 ¹⁵ atoms / cm ³ or less, which is the lower limit of measurement. Therefore, the region 4 which becomes the active region of the TFT
c did not contain nickel, and nickel (and phosphorus) was completely removed from the substrate. By removing nickel from the substrate, it is possible to completely prevent the TFT active region from being contaminated by nickel in a later step.

Next, referring to FIG. 2D, a laser beam (indicated by an arrow in the drawing) was irradiated to promote the crystallinity of the region 4c to be the TFT active region. As described above, since nickel has been removed from the substrate, no precipitation, rediffusion, or autodoping of nickel occurs during this step. Here, the laser light is XeC
1 An excimer laser (wavelength: about 308 nm, pulse width: about 40 nm) was used. The irradiation conditions of the laser beam are as follows: the irradiation temperature is about 200 to about 450 ° C .;
0 ° C. and the energy density of the laser beam is 250-4
50 mJ / cm ^2, in this embodiment about 360 mJ / cm ²
And The size and shape of the laser beam were approximately elliptical on the substrate, about 150 mm × about 1 mm. The substrate was irradiated with laser light by scanning the substrate with laser light in a direction perpendicular to the major axis direction at a step width of about 0.1 mm. That is, a total of 10 irradiations were performed at an arbitrary point in the region 4c.

Next, referring to FIG.
The silicon oxide film 6 is used as a gate insulating film by the VD method.
To a thickness of about 20 so as to cover the crystalline silicon region 4c.
The thickness is about 150 nm, in this embodiment, about 100 nm. Thereafter, in order to improve the characteristics of the gate insulating film 6 itself and the characteristics of the interface between the gate insulating film 6 and the crystalline silicon region 4c, the temperature is about 40 ° C. in an inert gas atmosphere.
The substrate was annealed at 0 to about 600 ° C. for about 30 to about 120 minutes. In this embodiment, the temperature is set to about 450 ° C. for 60 minutes in an N ₂ atmosphere.

Then, as shown in FIG. 1C, an aluminum film having a thickness of about 400 to about 800 nm, in this embodiment about 600 nm in this embodiment, is patterned by sputtering to form an aluminum electrode 7 serving as a gate electrode. And the gate bus line were integrally formed. Thereafter, as shown in FIG. 2 (e), the gate electrode (aluminum electrode) 7 and the gate bus line formed integrally therewith were anodized to form an oxide layer 8 on the exposed surface. This anodizing step involves removing tartaric acid from about 1 to 5
% Of ethylene glycol solution, the voltage was first raised to about 220 V under a constant current, and the state was maintained for about 1 hour. The oxide layer 8 thus obtained had a thickness of about 200 nm. Oxide layer 8
Is equal to the thickness for forming the offset gate region in the ion doping process described later, so that the desired length of the offset region can be obtained by appropriately setting the conditions of the anodic oxidation process. When the thickness of the offset region is controlled by the photolithography technique, it is usually impossible to control the offset region thickness with an accuracy of 1 μm or less due to the limit of the alignment accuracy. On the other hand, according to the above-described method, it is possible to easily perform control in a self-aligned manner.

Next, impurities (phosphorus) were implanted from the upper surface of the substrate by ion doping using the gate electrode 7 and the oxide layer 8 surrounding the gate electrode 7 as a mask. As a result, as shown in FIG. 2E, regions 10 and 11 into which the impurities were implanted and regions 9 into which the impurities were not implanted were formed. Regions 10 and 11 function as source / drain regions of the TFT, and region 9 functions as a channel region of the TFT. In this ion doping step, phosphine (PH ₃ ) is used as a doping gas.
Was used. Here, the acceleration voltage is about 60 to about 90 kV, about 80 kV in the present embodiment, the dose is about 1 × 10 ¹⁵ to about 8 × 10 ¹⁵ cm ⁻² , and about 2 × 10 ¹⁵ cm ^{−2 in the} present embodiment.
And

Thereafter, the substrate is annealed by laser light irradiation to activate the impurities introduced into the regions 10 and 11 by ion implantation, and at the same time, to improve the crystallinity of the regions 10 and 11 whose crystallinity has been degraded by the impurity introduction. did. Here, using a XeCl excimer laser (wavelength: about 308 nm, pulse width: about 40 nsec) as a laser, the energy density is about 150 to 400 mJ / cm ² ,
In this embodiment, the irradiation is performed at about 250 mJ / cm ² . At this time, the measured values of the sheet resistance of the regions 10 and 11 into which the N-type impurity (phosphorus) is introduced are about 200 to about 800 Ω /
cm ² .

Next, referring to FIG. 2F, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm was formed on the upper surface of the substrate by a plasma CVD method to form an interlayer insulating film 12. Source electrode / wiring 13 was formed on interlayer insulating film 12 so as to be electrically connected to source region 10 through a contact hole passing through interlayer insulating film 12 and gate insulating film 6. The source electrode / wiring 13 is made of a metal material, for example, a two-layer film of titanium nitride and aluminum. On the other hand, a pixel electrode 14 such as a transparent electrode made of ITO is provided on the interlayer insulating film 12 so as to be electrically connected to the drain region 11 through a contact hole passing through the interlayer insulating film 12 and the gate insulating film 6. .

Finally, under a hydrogen atmosphere of 1 atm.
Annealing was performed at 50 ° C. for about 30 minutes to produce an active matrix substrate for liquid crystal display 100 shown in FIGS. 1D and 2F. In the present embodiment, the active matrix substrate 100 for liquid crystal display includes a plurality of pixel TFTs.
(N-channel TFTs) are formed in a matrix, and each of the pixel TFTs has a gate electrode 7, a channel region 9, a source region 10, and a drain region. TF
In order to protect T, a protective film made of a silicon nitride film or the like may be formed on the TFT as needed.

(Embodiment 2) In this embodiment, N
A method for manufacturing a semiconductor device including a circuit having a CMOS structure in which a channel TFT and a P-channel TFT are configured complementarily will be described with reference to FIGS. Such a CMOS circuit forms an active matrix type liquid crystal peripheral circuit and a general thin film integrated circuit.

FIG. 3 shows the semiconductor device 20 according to the present embodiment.
0 is a schematic plan view for explaining a manufacturing method of No. 0. FIG. 4A and 4B are manufacturing process diagrams of the semiconductor device 200 in a cross section taken along AA ′ of FIG.
The process proceeds in the order of (a) to (i).

First, as shown in FIG. 4A, an intrinsic (I-type) film having a thickness of about 25 to about 80 nm, about 30 nm in the present embodiment, is formed on the entire upper surface of a glass substrate (Corning 1737) 21 by a plasma CVD method. ) An amorphous silicon film (a-Si film) 22 was formed.

Next, as shown in FIG.
Nickel is added to the upper surface of the i film 22 by spin coating at a surface concentration of about 1 × 10 ¹² to about 1 × 10 ¹⁴ atoms / cm ² , in this embodiment, 3 × 10 ¹² atoms / cm ^2. The film 25 was formed. In the present embodiment, this nickel is a catalyst element.

Next, a silicon oxide film having a thickness of about 80 to about 1 is formed on the nickel-containing film 25 by a plasma CVD method.
The film was formed to have a thickness of 50 nm, in this embodiment, about 100 nm. Thereafter, as shown in FIG. 4A (c), the silicon oxide film is patterned with a photoresist to form a mask film 23.
Was formed in an island shape. FIG. 4A (c) shows the state of an arbitrary TFT, and a-Si is formed through a through hole of the mask film 23.
A region 22a where the film 22 is exposed in a mesh pattern;
3 uncovered area 2 of a-Si film 22
2b are formed.

Next, referring to FIG. 4C, phosphorus was doped toward the glass substrate 21 from above the mask film 23 (indicated by an arrow in the figure). Here, phosphorus was not implanted into the region 22b covered with the mask film 23, but was selectively implanted only into the region 22a. In this step, phosphine (PH ₃ ) is used as a doping gas, and the accelerating voltage is about 5 to about 20 kV.
0 kV and a dose amount of about 5 × 10 ¹⁵ to about 1 × 10 ¹⁷ c
m ⁻² , in this embodiment, about 5 × 10 ¹⁶ cm ⁻² . In the present embodiment, this phosphorus is a gettering element.

Thereafter, the substrate is placed in an inert atmosphere for about 5 minutes.
The heat treatment was performed at a temperature of 20 to about 620 ° C for several hours. In the present embodiment, after heat-treating at a temperature of about 580 ° C. for about 1 hour in a nitrogen atmosphere, the temperature is raised to about 60 ° C.
The heat treatment was performed at 0 ° C. for about 6 hours. Thereafter, the substrate was cooled to room temperature.

In this heating step, as shown in FIG. 4D, the a-Si film 22 is crystallized to become a crystalline silicon film 24. In FIG. 4D, the crystalline silicon film 24 includes regions 24a and 24b.
These correspond to regions 22a and 22b, respectively. Here, the nickel that formed the crystallization nucleus was gettered by phosphorus and collected in the region 24a. The boundaries when viewed from above the regions 24a and 24b are indicated by dotted lines in FIG. This crystallization mechanism is described in Embodiment 1.
Since the mechanism is almost the same as that described above, the following description will focus on the differences. In the first embodiment, a photoresist is used as a mask film for selectively introducing phosphorus, but in this embodiment, a silicon oxide film is used. Further, in the first embodiment, the mask film is removed before the crystallization step. However, in the present embodiment, the amorphous silicon is crystallized by heat treatment with the mask film provided. Thus, in this embodiment, the silicon surface to be crystallized can be covered with a mask, thereby minimizing contamination introduced into the crystalline silicon 24 during heat treatment.

After the cooling step, the mask film 23, the nickel-containing film 25, and nickel silicide (not shown)
3 and 4A after removal of the
Referring to (e), the crystalline silicon film 24 is patterned in an island shape to form regions 24n and 24p to be active regions of N-type and P-type TFTs, respectively. Unnecessary portions were removed and device isolation was formed. Here, the unnecessary portion of the crystalline silicon film includes the region 24a containing nickel gettered by phosphorus as in the first embodiment, and is preferably a part of the region 24b located around the region 24a. It is a part including also. This removal step is performed by dry etching (reactive ion etching) according to the first embodiment.
The etching was performed under the same etching conditions.

At this stage, when the nickel concentration in the regions 24n and 24p is measured by secondary ion mass spectrometry (SIMS), the lower limit of measurement is 5 × 10 ¹⁵ atoms.
/ Cm ³ or less. Therefore, the regions 24n and 24p which become the active regions of the TFT did not contain nickel, and nickel (and phosphorus) was completely removed from the substrate. By removing nickel from the substrate,
It is possible to completely suppress the contamination of the TFT active region with nickel in a later step.

Next, referring to FIG. 4A (e),
Irradiation with a laser beam (indicated by an arrow in the drawing) promoted the crystallinity of the regions 24n and 24p to be the TFT active regions. As described above, since nickel has been removed from the substrate, no precipitation, rediffusion, or autodoping of nickel occurs during this step. Here, the used laser light and the irradiation conditions of the laser light are the same as those in the first embodiment, and thus the description is omitted.

Next, a silicon oxide film 26 as a gate insulating film is formed by plasma CVD so as to cover the crystalline silicon regions 24n and 24p to a thickness of about 20 to about 1.
The thickness was 50 nm, and in this embodiment, about 100 nm. Thereafter, in order to improve the characteristics of the gate insulating film 26 itself and the characteristics of the interface between the gate insulating film 26 and the crystalline silicon regions 24n and 24p, at a temperature of about 400 to about 600 ° C. in an inert gas atmosphere. The substrate was annealed for about 30 to about 120 minutes. In this embodiment, the temperature is set to about 450 ° C. for 60 minutes in an N ₂ atmosphere.

Next, as shown in FIG. 3, an aluminum film having a thickness of about 400 to about 800 nm, in this embodiment, about 600 nm is patterned by sputtering to form aluminum electrodes 27n and 27p as gate electrodes. And the gate bus line were integrally formed. Thereafter, referring to FIG. 4B (f), gate electrodes (aluminum electrodes) 27n and 27p and a gate bus line integrally formed therewith are anodized to form oxide layers 28n and 28p on the exposed surfaces thereof, respectively. Formed. The anodic oxidation conditions are the same as in the first embodiment, and will not be described.

Then, impurities (phosphorus and boron) were implanted from the upper surface of the substrate by ion doping using gate electrodes 27n and 27p and oxide layers 28n and 28p around them as masks. This step is
Unlike the first embodiment in which only an N-channel TFT is formed, a two-stage ion doping process for forming N-type and P-type TFTs is described below in more detail.

First, as shown in FIG. 4G, a photoresist 38 functioning as an ion implantation stopper film was formed so as to cover a region to be a P-channel TFT.
Next, the gate electrode 27n is formed by ion doping.
Then, impurities (phosphorus) were implanted from the upper surface of the substrate using the oxide layer 28n and the photoresist 38 around the mask as a mask. Thereby, as shown in FIG. 4B (g), regions 30n and 31n into which the impurities were implanted and regions 29n into which the impurities were not implanted were formed. The regions 30n and 31n function as source / drain regions of the N-channel TFT, and the region 29n functions as a channel region of the N-channel TFT. In this ion doping step, phosphine (PH ₃ ) was used as a doping gas. Here, the accelerating voltage is about 60
In this embodiment, the dose is about 1 × 10 ¹⁵ to about 8 × 10 ¹⁵ cm ⁻² , and in the present embodiment, about 2 × 10 ¹⁵ cm ⁻² . After that, the photoresist 38
Was peeled from the substrate.

Next, as shown in FIG.
Ion implantation strike so as to cover the region to be a tunnel type TFT.
A photoresist 39 functioning as a covering film was formed.
Next, the gate electrode 27p is formed by ion doping.
And its surrounding oxide layer 28p and photoresist
Using the dist 39 as a mask, impurities (ho
Element) was injected. Thereby, as shown in FIG.
And regions 30p and 31p into which impurities are implanted,
The region 29p into which the pure substance was not implanted was formed. Territory
Regions 30p and 31p are the sources of P-channel TFTs.
/ Drain region, and the region 29p is a P channel
Functions as a channel region of a TFT. This ion
In the doping process, dibo
Run (B _TwoH₆) Was used. Here, the accelerating voltage is about 40-
About 80 kV, about 65 kV in this embodiment, and a dose amount of about
1 × 10¹⁵~ 8 × 10¹⁵cm^-2In this embodiment, about 5
× 10¹⁵cm^-2And After that, the photoresist 39 is
Peeled from the substrate.

After the above-described ion doping step, the substrate is annealed by irradiating a laser beam to activate the impurities introduced into the regions 10 and 11 by ion implantation, and at the same time, to the region 30 where the crystallinity is deteriorated due to the impurity introduction.
The crystallinity of n, 31p, 30p, and 31p was improved. Here, the used laser light and the irradiation conditions of the laser light are the same as those in the first embodiment, and thus the description is omitted.

Next, referring to FIG. 4B (i), a silicon oxide film or a silicon nitride film having a thickness of about 600 nm was formed on the upper surface of the substrate by a plasma CVD method to form an interlayer insulating film 32. Interlayer insulating film 32 and gate insulating film 2
6 on the interlayer insulating film 32 so as to be electrically connected to the source / drain regions 30n, 31n, 30p, and 31p through contact holes passing through
4, and 35 were formed. This electrode / wiring 33, 3
Reference numerals 4 and 35 are formed of a two-layer film of a metal material, for example, titanium nitride and aluminum.

Finally, under a hydrogen atmosphere of 1 atm.
Annealing was performed at 50 ° C. for about 30 minutes to produce a semiconductor device 200 including the N-channel TFT 40n and the P-channel TFT 40p illustrated in FIGS. 3 and 4B (i). In order to protect these TFTs, a protective film made of a silicon nitride film or the like may be formed on the TFTs as needed.

Although the two embodiments according to the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications based on the technical concept of the present invention are possible.

In the first and second embodiments described above,
Although the spin coating method is used as a method for adding the catalyst element (nickel), a sputtering method may be used. Also, nickel was used as a catalyst element, but cobalt, palladium,
Platinum, copper, silver, gold, indium, tin, aluminum,
The same effect can be obtained by using antimony. Further, these elements may be used in combination as a catalyst element.

[0085]

According to the present invention, by suppressing the segregation of the catalytic element, a high-performance semiconductor device such as a driver monolithic active matrix liquid crystal display device having a stable characteristic with a small leakage current is realized.
A high-performance semiconductor device with a high degree of integration can be manufactured by a simple process. In addition, according to the method for manufacturing a semiconductor device of the present invention, the number of heat treatment steps can be reduced, so that the throughput and the yield can be greatly improved, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIGS. 1A to 1D are pixel TFTs according to a first embodiment;
FIG. 6 is a schematic partial plan view for explaining a method for manufacturing a liquid crystal display active matrix substrate including:

2 (a) to 2 (f) are cross-sectional views illustrating a manufacturing process of an active matrix substrate for liquid crystal display in a cross section of the TFT along line AA ′ in FIG. 1 (d).

FIG. 3 is a schematic plan view illustrating a semiconductor device including a CMOS circuit according to a second embodiment.

FIGS. 4A to 4E are cross-sectional views of the semiconductor device in steps taken along the line AA ′ of FIG. 3;

4B to 4I are cross-sectional views of the semiconductor device along a line AA 'in FIG.

[Explanation of symbols]

 Reference Signs List 1 glass substrate 2 amorphous silicon film (a-Si film) 2a region 2b region 3 mask film 4 crystalline silicon film 4a region 4b region 4c region 5 nickel-containing film 6 silicon oxide film (gate insulating film) 7 gate electrode (aluminum electrode) 8) oxide layer 9 channel region 10 source region 11 drain region 12 interlayer insulating film 13 source electrode / wiring 14 pixel electrode 100 active matrix substrate for liquid crystal display

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Naoki Makita 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Hiromi Sakamoto 22-22, Nagaike-cho, Abeno-ku, Osaka-shi, Osaka F-term within the company (reference) 5F052 AA02 AA11 BB07 CA02 DA02 DB03 EA16 FA06 FA19 HA01 HA07 JA01 JA04 5F110 AA06 AA16 BB01 BB02 CC02 DD02 EE03 EE34 EE44 FF02 FF30 FF36 GG02 GG13 GG25 H01 GG33 GG33 GG35 GG33 HM14 HM18 NN02 NN23 NN24 NN35 NN62 NN65 PP10 PP13 PP22 PP34 QQ28

Claims (13)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the steps of crystallizing an amorphous silicon film using a catalytic element to form a crystalline silicon film, wherein the amorphous silicon film is formed on a substrate having an insulating surface. Forming an amorphous silicon film, introducing a gettering element into a predetermined region of the amorphous silicon film, introducing a catalytic element into the amorphous silicon film, and heating the amorphous silicon film into which the catalytic element has been introduced. A crystallization step of forming a crystalline silicon film by crystallization, and heating the amorphous silicon film containing the catalyst element and the gettering element to the predetermined region of the amorphous silicon film. A gettering step of collecting the catalyst element, wherein the crystallization step and the gettering step are performed in a single heating step. Manufacturing method of a semiconductor device. 2. The step of introducing a catalyst element comprises the steps of: forming a catalyst element-containing film on the amorphous silicon film; and heating the catalyst element-containing film and the amorphous silicon film to form a crystal nucleus. A step of forming a mask film on the catalyst element-containing film, and patterning the mask film to form the amorphous silicon film. Removing the mask film formed on the predetermined region, and introducing the gettering element into the predetermined region of the amorphous silicon film using the patterned mask film. The heating step includes the crystal nucleus forming step, and the catalyst element-containing film and the patterned mask film are disposed on the amorphous silicon film. Performing the method in a state where a gettering element is introduced into the predetermined region of the amorphous silicon film. The method includes a step of removing the patterned mask film from the crystalline silicon film after the heating step. The method of manufacturing a semiconductor device according to claim 1, further comprising: removing at least the predetermined region of the crystalline silicon film. 3. The step of introducing a gettering element includes the steps of: forming a mask film on the amorphous silicon film; and patterning the mask film to form a mask film on the predetermined region of the amorphous silicon film. Removing the formed mask film; introducing the gettering element into the predetermined region of the amorphous silicon film by using the patterned mask film; and Removing the mask film, wherein the step of introducing the catalytic element comprises: forming a catalytic element-containing film on the amorphous silicon film into which the gettering element has been introduced; Heating the film and the amorphous silicon film to form a crystal nucleus, wherein the heating step comprises: A forming step, wherein the catalyst element-containing film is provided on the amorphous silicon film, the mask film is not provided, and the gettering element is provided in the predetermined region of the amorphous silicon. 2. The method according to claim 1, wherein the method is performed in an introduced state, and the method further includes a step of removing at least the predetermined region of the crystalline silicon film after the heating step. 3. 4. The method of manufacturing a semiconductor device according to claim 2, wherein said gettering element is phosphorus. 5. The method according to claim 2, wherein the step of removing at least the predetermined region includes the step of patterning the crystalline silicon film to form an active region of the semiconductor device.
4. The method for manufacturing a semiconductor device according to any one of items 3. 6. The step of removing at least a predetermined region includes etching the crystalline silicon film to form the crystalline silicon film including at least the predetermined region, the catalyst element, and a silicide of the catalyst element. 4. The method for manufacturing a semiconductor device according to claim 2, further comprising a step of removing the compound. 7. The method according to claim 5, wherein the step of removing at least the predetermined region is performed by a reactive ion etching method using a chlorine gas or a chlorine-based gas containing BCl ₃ and HCl. A method for manufacturing a semiconductor device. 8. The method according to claim 1, wherein the heating step is performed inside the amorphous silicon film and / or the crystalline silicon film.
4. The semiconductor device according to claim 2, wherein the process is performed within a temperature and time range in which the catalyst element diffuses, the gettering element does not diffuse, and natural nucleation does not occur. 5. Method. 9. The heating step is performed at 520 ° C. or higher and 620 ° C.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the method is performed within a temperature range of not more than C. 10. The amorphous silicon film has a thickness of 25.
The method for manufacturing a semiconductor device according to claim 2, wherein the semiconductor device has a thickness of not less than 80 nm and not more than 80 nm. 11. The method according to claim 5, wherein the concentration of the catalytic element contained in the active region is 1 × 10 ¹⁶ atoms / cm ³ or less. 12. The catalyst element is Ni, Co, Pd,
Pt, Cu, Ag, Au, In, Sn, Al, and S
b is at least one element selected from the group consisting of
A method for manufacturing a semiconductor device according to claim 2. 13. The method according to claim 12, wherein the catalyst element contains at least Ni.