JP2001085329A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To retrain manufacturing processes from increasing in number as much as possible and to prevent metal element from adversely affecting the characteristics of a thin film transistor by a method wherein a crystallization process is carried out using metal elements as a promoter, and a region adjoining to a crystallized region is made to getter metal elements. SOLUTION: Phosphorus is added to a region of an amorphous silicon film 102 which is not protected by a resist mask 103, by which phosphorus-loaded regions (gettering region) 104a and 104b are selectively formed. After phosphorus adding operation is finished, the resist mask 103 is removed. Thereafter, a solution which contains Ni that serves as a catalyst to promote the crystallization of the amorphous silicon film 102 is applied onto all the surface of the amorphous silicon film 102 by spin coating to form an Ni-containing layer 105. Then, a substrate 1 is thermally treated as prescribed. Lastly, Ni residing in an Ni-containing region 107 is nearly all fixed in the phosphorus-loaded regions 104a and 104b. By this setup. crystallization made by a catalytic action of Ni and gettering after crystallization is finished can be carried out through a single thermal treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
A thin film transistor (hereinafter referred to as TF) using a crystalline semiconductor film
T)) and a method for manufacturing the same. In particular, the present invention can be suitably used for an electro-optical device typified by a liquid crystal display device in which an image display region and a driving circuit thereof are provided on the same substrate, and an electronic device equipped with the electro-optical device. Note that a semiconductor device in this specification refers to all devices that function by utilizing semiconductor characteristics, and includes the above-described electro-optical device and electronic devices equipped with the electro-optical device in its category.

[0002]

2. Description of the Related Art Conventionally, TFTs using thin film semiconductors
It has been known. Thin-film semiconductors are roughly classified into two types: semiconductors made of amorphous semiconductors and semiconductors made of crystalline semiconductors.

An amorphous semiconductor has a low production temperature, can be relatively easily produced by a gas phase method, and has high mass productivity.
It is most commonly used and is mainly used to form an active matrix circuit of an active matrix type liquid crystal display device. However, the operation speed of a TFT using an amorphous silicon film is low, so that a P-channel type TFT is used.
However, there is a problem that cannot be put to practical use. Therefore, there is a strong demand for establishing a method for manufacturing a TFT made of a crystalline semiconductor, which has better physical properties such as conductivity than an amorphous semiconductor.

As a crystalline semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, and the like are known. As a method for obtaining these crystalline semiconductors, (1) a film having crystallinity is directly formed at the time of film formation. (2) An amorphous semiconductor film is formed and crystallinity is imparted by irradiating a laser beam. (3) An amorphous semiconductor film is formed and crystallinity is given by heat treatment. Such a method is known.

However, in the method (1), it is difficult to uniformly form a film having good semiconductor properties.
Since the film formation temperature is as high as 600 ° C. or more, there is a problem that an inexpensive glass substrate cannot be used.

The method (2) is known to provide a high-quality crystalline semiconductor even at a temperature of 400 ° C. or less.
Generally, a method using irradiation of excimer laser light is used. However, since the laser light irradiation area is small and the stability of the laser oscillation device is not sufficient, an inexpensive glass substrate with low heat resistance can be used, but throughput for processing amorphous silicon on a large-area substrate is required. And uniformity.

The method (3) has an advantage that it can cope with a large area. However, since the solid phase crystallization phenomenon is used, the variation in crystal grain size is large, and it takes several tens of hours at a high temperature of 600 to 900 ° C. or more. Heat treatment is required. Therefore, in addition to the problem of throughput, there is a problem that an inexpensive glass substrate cannot be used as in (1).

As one means for solving such a problem, there is a method of promoting crystallization using a predetermined metal element of the present applicant (JP-A-8-78329). This is a method in which a metal element typified by Ni is added to an amorphous semiconductor film, and then a crystalline semiconductor film is obtained by heat treatment. According to this method, a crystalline semiconductor film can be obtained at a temperature of 600 ° C. or less in a short time, so that an inexpensive glass substrate can be used. However, since the Ni element remains in the crystalline semiconductor film, the TFT manufactured by the Ni element has problems such as variations in characteristics and reduction in reliability.

[0009] Regarding the removal of the residual Ni element, a method by a gettering treatment by the present applicant (JP-A-10-21)
No. 4786) is disclosed, but a mask forming step for selectively adding a Ni element and a mask forming step for selectively adding a gettering element are required. And the gettering process need to be performed twice, which causes a problem of an increase in the number of processes, thereby deteriorating productivity and cost.

Further, the present applicant discloses a method by a gettering process (Japanese Patent Application Laid-Open No. H11-97352). However, a mask forming step for selectively adding a Ni element and a method for selecting a gettering element are disclosed. And a mask forming step for the selective addition. In addition, an inorganic film having high heat resistance is used as a mask.

[0011]

SUMMARY OF THE INVENTION According to the present invention, in a TFT manufactured using a crystalline semiconductor obtained by utilizing a metal element which promotes crystallization of silicon, an increase in the number of steps is suppressed as much as possible, and TFT characteristics are reduced. Another object of the present invention is to provide a technique for suppressing the adverse effect of the metal element.

[0012]

According to one aspect of the present invention, crystallization is performed by a metal element that promotes crystallization, and a getter of the metal element is formed in a region adjacent to the crystallized region. A method for manufacturing a semiconductor device, characterized in that a ring is formed.

In another aspect of the invention, crystallization is performed by a metal element that promotes crystallization, gettering of the metal element is performed in a region adjacent to the crystallized region, and crystallization and gettering are performed. This is a method for manufacturing a semiconductor device, which is performed in the same heat treatment step.

In still another aspect of the invention, crystallization is performed by a metal element that promotes crystallization, and the metal element is gettered in a region adjacent to the crystallized region, and the gettering element is non-gettered. The metal element selectively added to the crystalline semiconductor and promoting crystallization is added to the entire amorphous semiconductor including a region to which the gettering element is added (hereinafter, referred to as a gettering region). 3 illustrates a method for manufacturing a semiconductor device.

In the structures of the above three inventions, it is most preferable to use Ni as the metal element that promotes crystallization. Generally, Fe, Co, Ni, R
u, Rh, Pd, Os, Ir, Pt, Cu, Au, G
One or more kinds selected from e, Pb, and In can be used.

In the structures of the above three inventions, P (phosphorus) is most preferably used as the gettering element. As gettering elements, P, As, Sb,
N. In this sense, as the gettering element, an element selected from Group 15 elements in the long periodic table can be used. The invention disclosed in this specification can achieve the highest effect when nickel (Ni) is selected as the metal element and phosphorus (P) is selected as the gettering element.

The methods of adding a metal element and a gettering element for promoting crystallization include ion implantation, diffusion using a solution, diffusion using a solid, sputtering, and CV.
A method such as a method of diffusing a film formed by the method D, a plasma treatment method, and a gas adsorption method can be used. Further, these methods can be used in combination.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail in the following embodiments, taking an active matrix type liquid crystal display device as an example.

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. Here, the pixel TFT in the display area
And a method for manufacturing TFTs of a driver circuit provided around the display region on the same substrate will be described in detail according to the steps. However, for the sake of simplicity, the control circuit shows a CMOS circuit as a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit.

FIG. 1 shows a manufacturing process of this embodiment. First, the Corning 1737 glass substrate 101 (strain point 667)
℃) 20 to 150 nm (preferably 30 to 80 n
An amorphous silicon film 102 is formed to a thickness of m).

In this embodiment, an amorphous silicon film is formed as an amorphous semiconductor film to a thickness of 55 nm by a plasma CVD method, but other than an amorphous silicon semiconductor, a compound such as an amorphous silicon germanium film may be used. Semiconductor films can also be used.

In forming the amorphous semiconductor film, an insulating film may be inserted between the glass substrate and the amorphous semiconductor film. In particular, by continuously forming the insulating film and the amorphous semiconductor film without exposing the film to the atmosphere, it becomes possible to prevent the surface from being contaminated, and it is possible to prevent the variation in characteristics and the threshold voltage of the TFT to be manufactured. Voltage fluctuation can be reduced.

As a method of forming the amorphous semiconductor film, a known method such as a low pressure CVD method or a sputtering method can be used other than the plasma CVD method.

In this embodiment, Corning 1737 glass is used as the substrate 101.
It goes without saying that other substrate materials can be used according to the application. (Fig. 1 (A))

After the amorphous silicon film is formed, a resist mask 103 is formed from a photoresist as a mask for selectively adding the gettering element, and the gettering element is selectively added. A gettering region is formed. As the material of the mask, any material can be used as long as it can block the addition of the gettering element, such as a silicon oxide film, but in this embodiment, a photoresist is used to simplify the process.

Examples of the gettering element include phosphorus (P), arsenic (As), antimony (Sb), and nitrogen (N). In this sense, as the gettering element, an element selected from elements belonging to Group 15 of the long-period periodic table can be used. In this embodiment, phosphorus is used as the gettering element. Specifically, phosphine (PH ₃ ) was added by plasma-excited ion doping without mass separation. Of course, an ion implantation method for performing mass separation may be used.

A resist mask in the amorphous silicon film 102
1 × 10 in unprotected area ¹⁹~ 1 × 10^{twenty one}atom
s / cm^Three(P) is added at a concentration of
4a to 104b were obtained. Area protected by resist mask
Since phosphorus is not added to the region, the region is selectively doped with phosphorus.
(Gettering region) 104a-104b can be made
done. After completing the addition of the phosphorus element, the resist mask 103 is removed.
Removed. (Fig. 1 (B))

Thereafter, a solution containing Ni as a catalyst element for promoting crystallization of the amorphous silicon film 102 was applied by spin coating to form a Ni-containing layer 105. Ni is one of the metal element catalyst elements for promoting crystallization of the amorphous silicon film 102.
Other metal elements other than i include Fe, Co, Ru, Rh,
Pd, Os, Ir, Pt, Cu, Au, Ge, Pb, I
One or a plurality of types selected from n can be used.

In the present invention, the spin-coating method is used when forming the Ni-containing layer 105, but a means for forming a thin film containing a catalytic element by a gas phase method such as a sputtering method or a vapor deposition method may be used. (Fig. 1 (C))

Next, heat treatment (500-700 ° C., 2-2
4 hours, preferably 550 ° C to 600 ° C, 4 hours to 12
Time). Here, heat treatment was performed at 550 ° C. for 12 hours. In this heat treatment step, Ni is first crystallized in the phosphorus-added regions 104a to 104b at the same time as or immediately after the crystalline silicon 107a to 107c can be obtained by crystallization by the catalytic action of Ni. It was bound to phosphorus and immobilized.

Phosphorus hardly diffuses below 800 ° C.
In addition, since the bond between phosphorus and Ni is strong, almost all of the Ni that finally exists in the Ni-containing region layer 107 is fixed to the phosphorus element added regions 104a to 104b.

In the present embodiment, the heat treatment is performed in a heating furnace provided with a resistance heating type heater, but may be performed by, for example, irradiation with infrared light.

As described above, crystallization by the catalytic action of Ni and gettering of Ni after the crystallization can be performed by one heat treatment. (Fig. 1 (D))

In this heat treatment, crystal growth different from normal crystal growth is observed. (FIG. 15 (A), FIG. 15 (B))

Although Ni is retained on the entire surface of the amorphous silicon film, the presence of the phosphorus element added region
FIGS. 15A and 15A show needle-like crystals growing from the end of the phosphorus element-added region in a direction parallel to the substrate surface.
It can be observed in (B). The crystal of the region formed in this way is very large, and it is useful to arrange this region to be a source region or a drain region of a TFT because the resistance can be reduced and the TFT can be easily activated.

FIG. 15A is an optical microscope photograph after annealing at 575 ° C. for 12 hours and then performing FPM treatment for 60 minutes. Further, FIG.
After performing annealing at 0 ° C. for 12 hours, FPM treatment was performed for 6 hours.
It is an optical microscope photograph after performing for 0 minutes.

Although it depends on the content of hydrogen, the amorphous silicon film is preferably subjected to a heat treatment at 400 to 500 ° C. for about 1 hour to sufficiently desorb hydrogen before crystallization. In this case, the hydrogen content is preferably set to 5 atom% or less.

Then, the crystalline silicon 107a-107c is patterned into an island shape to form island-like semiconductor layers 108-111.
To form (Fig. 1 (C))

Thereafter, a mask layer 112 of a silicon oxide film having a thickness of 50 to 100 nm is formed by a plasma CVD method or a sputtering method. (Fig. 2 (A))

Then, a resist mask 113 is provided, and island-shaped semiconductor layers 109 to 111 for forming an n-channel TFT are formed.
1 × 10 ^{16 to} 5 for the purpose of controlling the threshold voltage
Boron (B) was added at a concentration of about × 10 ¹⁷ atoms / cm ³ as an impurity element imparting p-type. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film.

Although the addition of boron (B) here is not always necessary, the semiconductor layers 114 to 116 to which boron (B) is added in this step (called channel doping step) set the threshold voltage of the n-channel TFT to a predetermined value. It was preferable to form them so as to fall within the range. Note that in this specification, the semiconductor layer 114 containing a p-type impurity element in the above concentration range is used.
To 116 are called channel-doped semiconductor layers. (Figure 2
(B))

In order to form an LDD region of an n-channel TFT of a driving circuit, an impurity element imparting n-type is selectively added to the island-shaped semiconductor layers 114 and 116. Therefore, resist masks 117a to 117d were formed in advance. As an impurity element imparting n-type, phosphorus (P)
Or arsenic (As) may be used. Here, an ion doping method using phosphine (PH ₃ ) is applied to add phosphorus (P). Impurity regions 117, 118 formed
May be in the range of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 118 to 120 formed here is expressed as (n ⁻ ). Also, impurity region 1
Reference numeral 20 denotes a semiconductor layer for forming a storage capacitor of the pixel matrix circuit, and phosphorus (P) is added to this region at the same concentration. (Fig. 2 (C))

Next, a step of removing the mask layer 112 with hydrofluoric acid or the like and activating the impurity element added in FIGS. 2B and 2C is performed. The activation can be performed by a heat treatment at 500 to 600 ° C. for 1 to 4 hours in a nitrogen atmosphere or a laser activation method. Further, both may be performed in combination. In this embodiment, a KrF excimer laser beam (wavelength 248) is used by using a laser activation method.
nm) to form a linear beam and generate an oscillation frequency of 5 to 5 nm.
50 Hz, energy density 100 to 500 mJ / cm ²
The overlap ratio of the linear beam is 80 to 98%
To process the entire surface of the substrate on which the island-shaped semiconductor layer was formed. There are no particular restrictions on the laser light irradiation conditions, and the conditions may be determined appropriately by the practitioner. (Figure 2
(D))

Then, the gate insulating film 121 is formed by plasma C
The insulating film containing silicon is formed with a thickness of 10 to 150 nm by a VD method or a sputtering method. As the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used. The nitrided oxide film is an insulating film containing silicon, nitrogen and oxygen in predetermined amounts, and is an insulating film represented by SiOxNy. The nitrided oxide film is made of SiH ₄ , N ₂ O and NH
₃ can be used as a source gas, and the concentration of nitrogen contained is preferably 25 atomic% or more and less than 50 atomic%. In this embodiment, the silicon nitride oxide film is formed with a thickness of 120 nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, a first conductive layer is formed to form a gate electrode. The first conductive layer may be formed as a single layer, or may be formed as a two-layer or three-layer structure as necessary. In this embodiment, the conductive layer (A) 122 made of a conductive nitride metal film and the conductive layer (B) 123 made of a metal film are stacked. The conductive layer (B) 123 is made of tantalum (Ta), titanium (Ti), molybdenum (M
o), an element selected from tungsten (W), or an alloy containing the above element as a main component, or an alloy film (typically, a Mo—W alloy film or a Mo—Ta alloy film) that combines the above elements. The conductive layer (A) 122 may be formed using tantalum nitride (TaN), tungsten nitride (WN), a titanium nitride (TiN) film, and molybdenum nitride (MoN). As the conductive layer (A) 122, tungsten silicide, titanium silicide, or molybdenum silicide may be used as an alternative material. The conductive layer (B) may have a low impurity concentration in order to reduce the resistance, and it is particularly preferable that the oxygen concentration be 30 ppm or less. For example, tungsten (W) has an oxygen concentration of 30 pp.
m or less, a specific resistance value of 20 μΩcm or less could be realized.

The conductive layer (A) 122 has a thickness of 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 123 has a thickness of 200 to 400 nm (preferably 250 to 350 nm).
It is good. In this embodiment, the conductive layer (A) 122 is provided with a tantalum nitride film having a thickness of 30 nm, and the conductive layer (B) 12
For No. 3, a Ta film of 350 nm was used, and all were formed by a sputtering method. In the film formation by the sputtering method, if an appropriate amount of Xe or Kr is added to Ar of the gas for sputtering, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film doped with P (phosphorus) with a thickness of about 2 to 20 nm under the conductive layer (A) 122. Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, a small amount of the alkali metal element contained in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 120. Can be prevented. (FIG. 3 (A))

Next, the resist masks 124a to 124e
Is formed, and the conductive layer (A) 122 and the conductive layer (B) 123 are collectively etched to form the gate electrodes 125 to 128 and the capacitor wiring 129. The gate electrodes 125 to 128 and the capacitance wiring 129 are formed of the conductive layers (A).
28a and 125b to 128b made of a conductive layer (B) are integrally formed. At this time, the gate electrodes 126 and 127 formed in the drive circuit are
The gate insulating film 121 is formed so as to overlap with a part of the gate insulating film 19. (FIG. 3 (B))

Next, in order to form a source region and a drain region of the p-channel TFT of the driving circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligned manner using the gate electrode 125 as a mask. At this time, a region where the n-channel TFT is to be formed is covered with a resist mask 130. Then, an impurity region 131 was formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 131 formed here is expressed as (p ⁺⁺ ). (FIG. 3 (C))

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 132a to 132c were formed, and impurity regions 133 to 137 were formed by adding an impurity element imparting n-type. This was performed by an ion doping method using phosphine (PH ₃ ), and the phosphorus (P) concentration in this region was set to 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ . In this specification, the impurity region 13 formed here is used.
The concentration of the impurity element imparting n-type contained in 3 to 137 is represented as (n ⁺ ). (FIG. 3 (D))

The impurity regions 133 to 137 contain phosphorus (P) or boron (B) already added in the previous step, but P (phosphorus) is added at a sufficiently high concentration. Therefore, it is not necessary to consider the influence of phosphorus (P) or boron (B) added in the previous step. Also, impurity region 1
Since the concentration of phosphorus (P) added to 38 is ２〜 to ３ of the concentration of boron (B) added in FIG. 3C, p-type conductivity is ensured and has no effect on the characteristics of the TFT. Did not give.

Then, an n-type impurity imparting step for forming an LDD region of the n-channel TFT of the pixel matrix circuit was performed. Here, the gate electrode 128
Was used as a mask, and an impurity element imparting n-type in a self-aligned manner was added by ion doping. The concentration of the added phosphorus (P) is 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ , and FIG.
By adding at a lower concentration than the concentration of the impurity element added in FIG. 3C and FIGS. 3C and 3D, substantially only the impurity regions 138 and 139 are formed. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 138 and 139 is represented by (n ⁻ ). (FIG. 4
(A))

Thereafter, a heat treatment step is performed to activate the n-type or p-type imparting impurity element added at each concentration. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation step was performed by the furnace annealing method. The heat treatment is performed in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, at 400 to 800 ° C, typically 500 to 600 ° C.
In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours. Further, when a substrate having heat resistance such as a quartz substrate is used as the substrate 101, the substrate 101 is heated at 800 ° C. for 1 hour.
The heat treatment may be performed for a long time, and the activation of the impurity element and the junction between the impurity region to which the impurity element is added and the channel formation region can be favorably formed.

In this heat treatment, the gate electrodes 125 to 125
128 and metal film 125b-1 forming capacitor wiring 129
29b is a conductive layer (C) having a thickness of 5 to 80 nm from the surface.
125c to 129c are formed. For example, when the conductive layers (B) 125b to 129b are tungsten (W), tungsten nitride (WN) can be formed, and when tantalum (Ta), tantalum nitride (TaN) can be formed. In addition, the conductive layers (C) 125c to 129c
Are formed in a plasma atmosphere containing nitrogen using nitrogen or ammonia, etc.
9 can be formed in the same manner even if 9 is exposed. In addition, 3
300 to 450 ° C. in an atmosphere containing １００100% hydrogen
For 1 to 12 hours to hydrogenate the island-shaped semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
(FIG. 4 (B))

FIGS. 6A and 7A are top views of the TFT in the steps up to here, and the AA ′ section and the CC ′ section are taken along AA ′ and FIG. 4B in FIG. CC ′. The BB 'cross section and the DD' cross section correspond to the cross-sectional views of FIGS. 8A and 9A.
Although the gate insulating film is omitted in the top views of FIGS. 6 and 7, at least the island-shaped semiconductor layers 108 to
Gate electrodes 125 to 128 and capacitor wiring 129 on 111
Are formed as shown in the figure.

When the activation and hydrogenation steps are completed,
A second conductive film serving as a gate wiring is formed. This second conductive film is formed by adding a conductive layer (D) mainly composed of aluminum (Al) or copper (Cu), which is a low-resistance material, to titanium (T
i) or a conductive layer (E) made of tantalum (Ta), tungsten (W), or molybdenum (Mo). In this embodiment, an aluminum (Al) film containing 0.1 to 2% by weight of titanium (Ti) is formed as the conductive layer (D) 140, and a titanium (Ti) film is formed as the conductive layer (E) 141. The conductive layer (D) 140 may have a thickness of 200 to 400 nm (preferably 250 to 350 nm), and the conductive layer (E) 141 may have a thickness of 50 to 200 (preferably 100 to 15 nm).
0 nm). (FIG. 4 (C))

The conductive layer (E) 141 and the conductive layer (D) 1 are formed to form a gate wiring connected to the gate electrode.
40 are etched to form gate wirings 142, 14
3 and the capacitance wiring 144 were formed. The etching treatment is first performed from the surface of the conductive layer (E) to the conductive layer (D) by a dry etching method using a mixed gas of SiCl ₄ , Cl ₂ and BCl _3.
Then, the conductive layer (D) was removed by wet etching with a phosphoric acid-based etching solution, whereby the gate wiring could be formed while maintaining the selectivity with the base.

FIGS. 6B and 7B are top views in this state, and the AA 'section and the CC' section are shown in FIG.
(D) corresponds to AA ′ and CC ′. Also,
The BB 'section and the DD' section are shown in FIGS.
(B) corresponds to BB ′ and DD ′. FIG.
7B and FIG. 7B, the gate wiring 142,
Part of 143 overlaps part of the gate electrodes 125, 126, 128 and is in electrical contact therewith. This situation is B-
8 (B) and 9 (B) corresponding to the B ′ section and the DD ′ section, the conductive layer (C) forming the first conductive layer and the second conductive layer. The conductive layer (D) forming the layer is in electrical contact.

The first interlayer insulating film 145 has a thickness of 500 to 150
A contact hole is formed to a thickness of 0 nm with a silicon oxide film or a silicon oxynitride film, and then reaches a source region or a drain region formed in each of the island-shaped semiconductor layers. Wirings 150 to 153 are formed. Although not shown, in the present embodiment, the electrode is a three-layer laminated film in which a Ti film having a thickness of 100 nm, an aluminum film containing Ti having a thickness of 300 nm, and a Ti film having a thickness of 150 nm are continuously formed by a sputtering method.

Next, as a passivation film 154,
A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film
It is formed with a thickness of about 500 nm (typically 100 to 300 nm). When hydrogenation was performed in this state, favorable results were obtained with respect to the improvement of TFT characteristics. For example, 3 ~
The heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 100% hydrogen, or the same effect is obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film 154 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later. (FIG. 5
(A))

FIGS. 6C and 7C show top views in this state, and the AA 'section and CC' section are shown in FIG.
(A) corresponds to AA ′ and CC ′. Also,
The BB 'section and the DD' section are shown in FIGS.
(C) corresponds to BB ′ and DD ′. FIG.
In FIG. 7C and FIG. 7C, the first interlayer insulating film is omitted, but the source wiring 14 is formed in the not-shown source and drain regions of the island-shaped semiconductor layers 108, 109, and 111.
6, 147, 149 and drain wirings 150, 151, 1
53 are connected via contact holes formed in the first interlayer insulating film.

After that, a second interlayer insulating film 155 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used. Then, a contact hole reaching the drain wiring 153 is formed in the second interlayer insulating film 155, and pixel electrodes 156 and 157 are formed. As the pixel electrode, a transparent conductive film may be used for a transmission type liquid crystal display device, and a metal film may be used for a reflection type liquid crystal display device. In this embodiment, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by a sputtering method in order to obtain a transmission type liquid crystal display device. (FIG. 5 (B))

As described above, the TFT of the driving circuit is formed on the same substrate.
And a substrate having pixel TFTs in the display area. The driving circuit includes a p-channel TFT 201,
A first n-channel TFT 202, a second n-channel TFT 203, and a pixel TFT 204 and a storage capacitor 205 were formed in a display area. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the p-channel TFT 201 of the drive circuit, the channel forming region 206, the source regions 207a and 207b, the drain region 208a,
208b. First n-channel TFT 20
2 includes a channel forming region 20 in the island-shaped semiconductor layer 109.
9, an LDD region 210 overlapping with the gate electrode 126 (hereinafter, such an LDD region is referred to as Lov), a source region 211, and a drain region 212. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. In the second n-channel TFT 203, the channel forming region 213, the LDD regions 214 and 215, the source region 2
16 and a drain region 217. The LDD region includes an Lov region and an LDD region that does not overlap the gate electrode 127 (hereinafter, such an LDD region is referred to as Loff), and the length of the Loff region in the channel length direction is 0.3 to 2.0. 0 μm, preferably 0.5 to 1.5 μm. In the pixel TFT 204, channel forming regions 218 and 219 and Loff regions 220 to 2 are formed in the island-shaped semiconductor layer 111.
23, a source or drain region 224 to 226. The length of the Loff region in the channel length direction is 0.5 to
It is 3.0 μm, preferably 1.5 to 2.5 μm. Further, the storage capacitor 205 is formed from the capacitor wirings 129 and 144, an insulating film made of the same material as the gate insulating film, and the semiconductor layer 227 to which the n-type impurity element is added, which is connected to the drain region 226 of the pixel TFT 204. Are formed. In FIG. 5B, the pixel TFT 204 has a double gate structure, but may have a single gate structure or a multi-gate structure in which a plurality of gate electrodes are provided.

In the present embodiment, an example of a case of a top gate type as a TFT type has been described. However, a bottom gate type TFT whose gate electrode is below the active layer (substrate side)
The present invention can also be used. Further, by forming the gate electrode with a heat-resistant conductive material, the LD
The activation of the D region, the source region, and the drain region is facilitated, and the wiring resistance can be sufficiently reduced by forming the gate wiring with a low-resistance material. Therefore, the present invention can be applied to a display device having a display area (screen size) of 4 inches or more.

[Embodiment 2] In this embodiment, Embodiment 1
In this example, the heat treatment for crystallization and gettering is performed in two stages during the same heat treatment process. The drawings and reference numerals also serve as the first embodiment.

First, similarly to Embodiment 1, an amorphous silicon film 102 was formed on the substrate 101 to a thickness of 55 nm.

Next, a resist mask 103 was formed, and phosphorus (P) was selectively added as a gettering element. As in the first embodiment, the phosphine (PH ₃ ) is 1 × 10 ^19-
It was added at a concentration of 1 × 10 ²¹ atoms / cm ³ .

After removing the resist mask 103, a solution containing Ni as a catalyst element for promoting crystallization of the amorphous silicon film 102 was applied by spin coating to form a Ni-containing layer 105.

Next, heat treatment was performed at 550 ° C. for 4 hours in a heating furnace to crystallize the amorphous silicon film 102 by the catalytic action of Ni, thereby obtaining crystalline silicon 107a to 107c. Thereafter, a heat treatment at 600 ° C. for 4 hours was performed without taking out from the electric furnace, and a Ni gettering treatment was performed.

It is generally known that the heat treatment is performed at a temperature lower than the strain point of the substrate material, and that the substrate is more deformed as the processing temperature approaches the strain point. In this embodiment, a Corning 1737 glass substrate (strain point 667 ° C.) was used. However, at a processing temperature of this embodiment, the processing time could be reduced without causing any deformation of the substrate. .

As described above, although the heat treatment is performed substantially twice by changing the crystallization and gettering processing temperatures stepwise, the heat treatment is performed in the same heat treatment step. In this case, the process can be performed in a shorter time than in the first embodiment.

In changing the processing temperature stepwise, the processing temperature may be changed a plurality of times, or may be changed not stepwise but continuously.

In the subsequent steps, a TFT is manufactured according to the first embodiment or another known method.

[Embodiment 3] In this embodiment, a process for manufacturing an active matrix type liquid crystal display device from an active matrix substrate will be described. As shown in FIG.
An alignment film 601 is formed on the active matrix substrate in the state illustrated in FIG. 5B manufactured in Embodiment 1. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. A light blocking film 603,
A transparent conductive film 604 and an alignment film 605 were formed. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. Then, a sealing material or a spacer (both not shown) is formed by a well-known cell assembling process using a pixel matrix circuit, an active matrix substrate on which a CMOS circuit is formed, and a counter substrate.
Paste through such as. Thereafter, a liquid crystal material 606 was injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device shown in FIG. 10 was completed.

Next, the structure of the active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. 11 and the top view of FIG. 11 and 12 use the same reference numerals in order to correspond to the sectional structural views of FIGS. 1 to 5 and 10. The cross-sectional structure along EE 'shown in FIG. 12 corresponds to the cross-sectional view of the pixel matrix circuit shown in FIG.

In FIG. 11, an active matrix substrate is formed on a display area 306 formed on the glass substrate 101.
, Scanning signal driving circuit 304 and image signal driving circuit 30
5 is comprised. A pixel TFT 204 is provided in the display area, and a driving circuit provided in the periphery is configured based on a CMOS circuit. The scanning signal driving circuit 304 and the image signal driving circuit 305 are connected to the pixel TFT 204 by a gate wiring 128 and a source wiring 149, respectively. Further, the FPC 731 is connected to the external input terminal 734, and is connected to each drive circuit through the input wirings 302 and 303.

FIG. 12 is a top view showing substantially one pixel of the display area 306. The gate wiring 143 intersects with the underlying semiconductor layer 111 via a gate insulating film (not shown). Although not shown, an Loff region including a source region, a drain region, and an n ⁻ region is formed in the semiconductor layer. Reference numeral 161 denotes a contact portion between the source wiring 149 and the source region 224; 162, a contact portion between the drain wiring 153 and the drain region 226;
Denotes a contact portion between the drain wiring 153 and the pixel electrode 156. The storage capacitor 205 is formed in a region where the capacitor wirings 129 and 144 overlap with the semiconductor layer 227 extending from the drain region 226 of the pixel TFT 204 via a gate insulating film.

Although the active matrix liquid crystal display device of the present embodiment has been described with reference to the structure described in the first embodiment, the active matrix liquid crystal display device is manufactured by freely combining with the structure of the second embodiment. can do.

[Embodiment 4] An active matrix substrate, a liquid crystal display device, and an E manufactured according to the present invention are manufactured.
The L-type display device can be used for various electro-optical devices. The present invention can be applied to all electronic devices incorporating such an electro-optical device as a display device. Examples of the electronic device include a personal computer, a digital camera, a video camera, a portable information terminal (such as a mobile computer, a mobile phone, and an electronic book), and a navigation system.

FIG. 13A shows a personal computer, which comprises a main body 2001 provided with a microprocessor and a memory, an image input section 2002, a display device 2003, and a keyboard 2004. The present invention relates to a display device 20.
03 and other signal processing circuits can be formed.

FIG. 13B shows a video camera, which includes a main body 2101, a display device 2102, an audio input unit 2103, an operation switch 2104, a battery 2105, and an image receiving unit 21.
06. The present invention can be applied to the display device 2102 and other signal control circuits.

FIG. 13C shows an electronic game machine such as a video game or a video game. The main body 23 includes an electronic circuit 2308 such as a CPU, a recording medium 2304, and the like.
01, a controller 2305, a display device 2303, and a display device 2302 incorporated in the main body 2301. The display device 2303 and the display device 2302 incorporated in the main body 2301 may display the same information, or display information on the recording medium 2304 using the former as a main display device and the latter as a sub-display device. The operation state can be displayed or a touch panel function can be added to form an operation panel. Further, the main body 2301, the controller 2305, and the display device 2303 may be wired communication to transmit signals to each other, or may be a sensor unit 2306,
2307 may be provided for wireless communication or optical communication.
The present invention can be applied to the display devices 2302 and 2303. The display device 2303 can use a conventional CRT.

FIG. 13D shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display device 2402, and a speaker unit 2.
403, a recording medium 2404, and operation switches 2405. The recording medium is a DVD (Digital Versati
le Disc) and compact disc (CD)
Playback of music programs, video display, video games (or video games), information display via the Internet, and the like can be performed. The present invention can be suitably used for the display device 2402 and other signal control circuits.

FIG. 13E shows a digital camera, which comprises a main body 2501, a display device 2502, an eyepiece section 2503, operation switches 2504, and an image receiving section (not shown). The present invention can be applied to the display device 2502 and other signal control circuits.

FIG. 14A shows a front type projector, which comprises a light source optical system, a display device 2601, and a screen 2602. The present invention can be applied to a display device and other signal control circuits. FIG. 14B illustrates a rear projector, which includes a main body 2701, a light source optical system and a display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to a display device and other signal control circuits.

FIG. 14C shows the light source optical system and the display device 26 shown in FIGS. 14A and 14B.
01 and 2702 are shown as examples. A light source optical system and display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a beam splitter 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810.
It consists of. The projection optical system 2810 includes a plurality of optical lenses. FIG. 14C illustrates a liquid crystal display device 2808.
Although an example of a three-plate system using three is shown, the present invention is not limited to such a system, and a single-plate optical system may be used. An optical path indicated by an arrow in FIG. 14C may be provided with a suitable optical lens, a film having a polarizing function, a film for adjusting a phase, an IR film, or the like. FIG. 14D shows the light source optical system 2 shown in FIG.
801 is a diagram showing an example of the structure of FIG. In this embodiment,
The light source optical system 2801 includes a reflector 2811 and a light source 28.
12, a lens array 2813, 2814, a polarization conversion element 2815, and a condenser lens 2816. FIG.
The light source optical system shown in FIG. 4D is an example, and is not limited to the illustrated configuration.

Although not shown here, the present invention can also be applied to a navigation system, a reading circuit of an image sensor, and the like. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. In addition, the electronic apparatus according to the present embodiment includes first to third embodiments.
It can be realized by using a configuration composed of any combination of the above.

According to the invention disclosed in this specification, (1) a gettering region is selectively formed in an amorphous semiconductor film. (2) A metal element that promotes crystallization is added to the entire amorphous semiconductor film including the gettering region. (3) The crystallization of the amorphous semiconductor by the metal element and the gettering of the metal element are performed in the same heat treatment step. (3) The gettering region is removed, and a region crystallized by the metal element is used as an active layer. Is basically adopted.

Thus, in a TFT manufactured using a crystalline semiconductor film obtained by using a metal element that promotes crystallization of a semiconductor film, the characteristics of the TFT are prevented from being adversely affected by the metal element. can do.

Further, the invention disclosed in this specification has a feature that the above effects can be obtained in a simplified manufacturing process.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 6 is a top view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 7 is a top view illustrating a manufacturing process of a pixel TFT, a storage capacitor, and a TFT of a driver circuit.

FIG. 8 is a top view illustrating a manufacturing process of a TFT of a driver circuit.

FIG. 9 is a top view illustrating a manufacturing process of a pixel TFT.

FIG. 10 is a cross-sectional view illustrating a structure of a liquid crystal display device.

FIG. 11 is a perspective view illustrating a structure of a liquid crystal display device.

FIG. 12 is a top view illustrating pixels in a display area.

FIG. 13 illustrates an example of an electronic device.

FIG. 14 illustrates an example of an electronic device.

FIG. 15 is a photograph of crystal growth by an optical microscope.

[Explanation of symbols]

Reference Signs List 101 substrate 102 amorphous silicon film 103a to 103c resist mask 104a to 104b phosphorus element added region (gettering region) 105 Ni-containing layer 106 movement of Ni 107a to 107c crystalline silicon 108 to 111 island-like semiconductor layer 112 mask layer 113 Resist masks 114 to 116 Channel doped semiconductor layers 117a to 117d Resist masks 118 to 120 n-type impurity regions 121 Gate insulating film 122 Conductive layer (A) 123 Conductive layer (B) 124a to 124e Resist masks 125 to 128 Gate electrode 129 Capacitance Wiring 125c-129c Conductive layer (C) 130 Resist mask 131 P ++ Impurity region 132a-132c Resist mask 133-137 n + Impurity region 138-139 n- Impurity region 140 Conductive layer (D) 41 conductive layer (E) 142-143 gate wiring 144 capacitor wiring 145 first interlayer insulating film 146-149 source wiring 150-153 drain wiring 154 a passivation film 155 second interlayer insulating film 156-157 pixel electrode

Continued on the front page F-term (reference) PP01 PP10 PP34 PP35 QQ24 QQ25 QQ28

Claims (7)

[Claims] A step of forming a gettering region by selectively adding a group 15 element to the amorphous semiconductor film; Removing, a step of adding a metal element that promotes crystallization to the amorphous semiconductor film, and performing crystallization of the amorphous semiconductor film and gettering of the metal element by one heat treatment. A method for manufacturing a semiconductor device, comprising: A step of forming a gettering region by selectively adding a group 15 element to the amorphous semiconductor film; a step of forming a gettering region by selectively adding a group 15 element to the amorphous semiconductor film; Removing, adding a metal element that promotes crystallization to the amorphous semiconductor film, and performing crystallization of the amorphous semiconductor film and gettering of the metal element in the same heat treatment step. A method for manufacturing a semiconductor device, comprising: 3. A step of forming a mask on the amorphous semiconductor film; a step of forming a gettering region by selectively adding a group 15 element into the amorphous semiconductor film; Removing, adding a metal element that promotes crystallization to the entire surface of the amorphous semiconductor film, and performing crystallization of the amorphous semiconductor film and gettering of the metal element by the same heat treatment. A method for manufacturing a semiconductor device, comprising: 4. The method for manufacturing a semiconductor device according to claim 1, wherein the mask according to claim 1 is formed of a photoresist. 5. The method according to claim 1, wherein the metal element is Fe, Co, Ni, Ru, Rh, P
d, Os, Ir, Pt, Cu, Au, Ge, Pb, In
A method for manufacturing a semiconductor device, wherein one or more types selected from the group consisting of: 6. The method for manufacturing a semiconductor device according to claim 1, wherein Ni is used as the metal element. 7. The semiconductor device according to claim 1, wherein the semiconductor device is a video camera, a digital camera,
A method for manufacturing a semiconductor device, which is a projector, a goggle-type display, a car navigation, a personal computer, or a personal digital assistant.