JP4785258B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having a circuit including a thin film transistor (hereinafter referred to as TFT) using a method for effectively removing a metal element that promotes crystallization of an amorphous silicon film. For example, the present invention relates to an electro-optical device typified by an active matrix liquid crystal display device in which a pixel portion and a drive circuit are provided on the same substrate, and an electronic apparatus in which such an electro-optical device is mounted as a component.
[0002]
Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and includes not only a single element as a TFT but also an electro-optical device formed using the TFT, and such an electric device. Electronic devices and semiconductor circuits each including an optical device as a component are all semiconductor devices.
[0003]
[Prior art]
TFTs using semiconductor thin films are used in various integrated circuits. Semiconductor thin films include amorphous silicon films and crystalline silicon films. Amorphous silicon films are easy to form and have excellent productivity. It cannot be used for an active matrix liquid crystal display device in which peripheral driving circuits are integrated, or various integrated circuits cannot be configured. Therefore, a crystalline silicon film with better characteristics is used.
[0004]
As a method for manufacturing a crystalline silicon film, there are a thermal annealing method and a laser annealing method. However, the thermal annealing method requires a high-temperature process of 600 ° C. or higher, and therefore cannot be applied to a glass substrate that is inexpensive and can have a large area, and has a problem that the processing time is long. The laser annealing method can realize a process that does not cause thermal damage to the substrate, but has a problem that satisfactory crystallinity uniformity, reproducibility, and crystallinity cannot be obtained. As one means for solving such a problem, there is a method of promoting crystallization using a predetermined metal element.
[0005]
Among the above methods, there is a method disclosed in Japanese Patent Application Laid-Open No. 7-130552 by the present applicant as a technique for lowering the crystallization temperature to 600 ° C. or less applicable to a glass substrate while using thermal annealing. . This method is a method in which a metal element typified by Ni is introduced into an amorphous silicon film and thermally annealed, and a crystalline silicon film having good crystallinity is obtained.
[0006]
[Problems to be solved by the invention]
When a method that promotes crystallization using a predetermined metal element is used, crystallization proceeds with the diffusion and movement of this metal element, so that the metal element that promotes crystallization remains in the crystalline silicon film. To do. As a result, it precipitates near the surface of the crystalline silicon film, causing junction leakage, and forming a deep level to recombine and generate carriers, thereby impairing the stability and reliability of the TFT electrical characteristics. The problem arises. Therefore, various techniques based on gettering have been developed as techniques for removing or reducing this metal element.
[0007]
As the gettering method, for example, an amorphous silicon film is crystallized with a metal element to form a crystalline silicon film, and then a device region is covered with a mask layer such as an oxide film, and the gettering is performed in a region other than the device region. Masking the region to be a device region by masking the region that promotes gettering (hereinafter referred to as a gettering site) by doping a group 15 element such as P effective for the ring at a high concentration In addition, there is a method of forming a silicon film containing a high concentration of a group 15 element such as P as a gettering site. However, these methods require the formation of a film to be a mask layer and a patterning process, which increases the number of masks and increases the manufacturing cost and decreases the productivity.
[0008]
As another method, for example, there is a method in which the source and drain regions of the device are used as gettering sites. In this method, the number of masks can be reduced because patterning for gettering is unnecessary, but the gettering site is limited in volume, so that the gettering efficiency is slightly lowered, and the donor is also applied to the p-ch TFT. In order to dope with a group 15 element such as P, the ions serving as acceptors must be excessively doped, resulting in an increase in manufacturing cost and a decrease in productivity.
[0009]
The invention disclosed in this specification describes a TFT manufactured using a crystalline silicon film obtained by using a metal element that promotes crystallization of an amorphous silicon film. It is an object of the present invention to provide a technique capable of reducing the production cost and reducing the manufacturing cost and increasing the productivity.
[0010]
[Means for Solving the Problems]
One of the inventions disclosed in this specification is:
A crystalline silicon film having a source region, a drain region, and a channel formation region sandwiched between the source region and the drain region on an insulating surface;
A gate insulating film on the crystalline silicon film;
A gate electrode on the gate insulating film;
An interlayer insulating film on the gate electrode;
A silicon film containing phosphorus on the interlayer insulating film;
In a semiconductor device having a conductive layer on a silicon film containing an impurity element belonging to Group 15 of the periodic table,
A silicon film containing an impurity element belonging to Group 15 of the periodic table is in contact with a source region or a drain region of the crystalline silicon film through a contact hole formed in the interlayer insulating film;
The silicon film containing an impurity element belonging to Group 15 of the periodic table is a semiconductor device characterized in that a metal element required for forming the crystalline silicon film is segregated.
[0011]
Other aspects of the invention are:
A gate electrode on an insulating surface;
A gate insulating film on the gate electrode;
A crystalline silicon film having a source region and a drain region on the gate insulating film, and a channel formation region sandwiched between the source region and the drain region;
A protective insulating film on the crystalline silicon film;
An interlayer insulating film on the protective insulating film;
A silicon film containing an impurity element belonging to Group 15 of the periodic table on the interlayer insulating film;
In a semiconductor device having a conductive layer on a silicon film containing an impurity element belonging to Group 15 of the periodic table,
A silicon film containing an impurity element belonging to Group 15 of the periodic table is in contact with a source region or a drain region of the crystalline silicon film through a contact hole formed in the interlayer insulating film;
The silicon film containing an impurity element belonging to Group 15 of the periodic table is a semiconductor device characterized in that a metal element required for forming the crystalline silicon film is segregated.
[0012]
Other aspects of the invention are:
A first step of forming an amorphous silicon film on the insulating surface;
A second step of adding a metal element for promoting crystallization of the amorphous silicon film and growing the amorphous silicon film to form a crystalline silicon film;
A third step of forming a gate insulating film on the crystalline silicon film;
A fourth step of forming a gate electrode on the gate insulating film;
A fifth step of forming a source region and a drain region by adding an impurity element to a selected region of the crystalline silicon film;
A sixth step of forming an interlayer insulating film on the gate electrode;
A seventh step of forming a contact hole reaching the source region or the drain region in the interlayer insulating film;
An eighth step of forming a silicon film containing an impurity element belonging to Group 15 of the periodic table on the contact hole and the interlayer insulating film;
A ninth step of performing gettering of the metal element contained in the crystalline silicon film by thermal annealing;
A tenth step of forming a conductive film on a silicon film containing an impurity element belonging to Group 15 of the periodic table;
A method for manufacturing a semiconductor device having
[0013]
Other aspects of the invention are:
A first step of forming a gate electrode on the insulating surface;
A second step of forming a gate insulating film on the gate electrode;
A third step of forming an amorphous silicon film on the gate insulating film;
A fourth step of adding a metal element for promoting crystallization of the amorphous silicon film and growing the amorphous silicon film to form a crystalline silicon film;
A fifth step of forming a protective insulating film on the crystalline silicon film;
A sixth step of adding an impurity element to a selected region of the crystalline silicon film to form a source region and a drain region;
A seventh step of forming an interlayer insulating film on the protective insulating film;
An eighth step of forming contact holes reaching the source region or the drain region in the protective insulating film and the interlayer insulating film;
A ninth step of forming a silicon film containing an impurity element belonging to Group 15 of the periodic table on the contact hole reaching the source region or the drain region and the interlayer insulating film;
A tenth step of performing gettering of the metal element contained in the crystalline silicon film by thermal annealing;
An eleventh step of forming a conductive film on the silicon film containing an impurity element belonging to Group 15 of the periodic table;
A method for manufacturing a semiconductor device having
[0014]
In the structures of the four inventions described above, the silicon film containing an impurity element belonging to Group 15 of the periodic table is a metal element that promotes crystallization of the amorphous silicon film by thermal annealing through a contact hole reaching the source region or the drain region. Serves as a gettering site.
[0015]
In the configurations of the above four inventions, it has been found by the applicant's invention that it is preferable to use Ni as the metal element that promotes crystallization of the amorphous silicon film. In general, one kind selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, Ge, Pb, In as a metal element for promoting crystallization of an amorphous silicon film or Multiple types of elements can be used.
[0016]
In the structures of the four inventions described above, the impurity element belonging to Group 15 of the periodic table is an element for gettering a metal element that promotes crystallization of the amorphous silicon film. When nickel (Ni) is selected as the metal element for promoting crystallization of the amorphous silicon film and phosphorus (P) is selected as the gettering element, gettering can be effectively performed.
[0017]
When phosphorus is selected as the impurity element belonging to Group 15 of the periodic table, the phosphorus concentration in the silicon film containing phosphorus is 1 × 10 5. ¹⁹ atoms / cm ^Three That's it. In the p-ch TFT, the impurity region of the semiconductor layer and the silicon film form a PN junction. However, since the impurity element concentration contained in the impurity region and the silicon is high, the impurity region is inherent in the polycrystalline silicon film. Due to the large number of crystal defects, a tunnel junction is formed at the contact hole portion where the impurity region of the semiconductor layer and the silicon film containing phosphorus are in contact with each other, and a sufficiently low contact resistance can be obtained.
[0018]
The introduction of metal elements to promote crystallization includes ion implantation, diffusion using a solution, diffusion using a solid, diffusion from a film formed by sputtering or CVD, plasma treatment, A method such as a gas adsorption method can be used. A silicon film containing phosphorus, which is a gettering element, can be formed using a plasma CVD (P-CVD) apparatus, a low pressure CVD (LP-CVD) apparatus, a sputtering apparatus, or the like.
[0019]
In the four inventions described above, thermal annealing advances gettering of a metal element that promotes crystallization of an amorphous silicon film, and at the same time, an impurity element doped to form source and drain regions. The heat treatment process required for the progress of gettering and the activation of the impurity element can be performed at once.
[0020]
In the structures of the four inventions described above, the silicon film containing phosphorus forms a conductive film over the silicon film containing phosphorus, and is then patterned by self-alignment with the conductive film to function as a wiring.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a specific configuration example of the invention.
That is, the base insulating film 102 is formed over the substrate 101,
A crystalline silicon film 103 is formed over the base insulating film 102,
A gate insulating film 104 is formed over the channel formation region 103a, the crystalline silicon film 103 having the source region or the drain region 103b, and the base insulating film 102,
A gate electrode 105 is formed on the gate insulating film 104,
An interlayer insulating film 107 is formed over the gate electrode 105 and the gate insulating film 104,
Contact holes reaching the source region or the drain region 103b of the crystalline silicon film are formed in the interlayer insulating film 107 and the gate insulating film 104,
A silicon film 106 including an impurity element belonging to Group 15 of the periodic table is formed over the contact hole reaching the source region or the drain region and the interlayer insulating film 107, and is formed over the silicon film 106 including an impurity element belonging to Group 15 of the periodic table. A conductive film 108 is formed,
Finally, a source electrode or a drain electrode 109 having a silicon film 106 containing an impurity element belonging to Group 15 of the periodic table as a lower layer is formed.
Note that in this specification, the surface of the substrate and the surface of the insulating film formed on the substrate are referred to as an insulating surface.
[0022]
The crystalline silicon film is formed by forming an amorphous silicon film over the base insulating film 102, introducing a metal element that promotes crystallization into the amorphous silicon film, and performing thermal annealing. Therefore, the crystalline silicon film contains a metal element that promotes crystallization. Further, the impurity element belonging to Group 15 of the periodic table included in the silicon film 106 has an action of gettering a metal element that promotes crystallization by thermal annealing.
[0023]
Therefore, when thermal annealing is performed after forming the silicon film 106 containing an impurity element belonging to Group 15 of the periodic table, contact holes reaching the source region or the drain region 103b of the crystalline silicon film (hereinafter referred to as source contact and drain contact, respectively). The metal element that promotes crystallization is effectively removed from the crystalline silicon film by phosphorus having a gettering action in the silicon film 106. Further, by performing thermal annealing after the formation of the silicon film 106 containing an impurity element belonging to Group 15 of the periodic table, the entire silicon substrate 106 becomes a gettering site because the silicon substrate 106 exists on the entire substrate, and the source and drain regions are gettered. Gettering efficiency is higher compared to the site method. After that, the silicon film 106 containing an impurity element belonging to Group 15 of the periodic table functions as the source or drain electrode 109 together with the conductive film 108.
[0024]
A feature of this structure is that a silicon film containing an impurity element belonging to Group 15 of the periodic table is formed in contact with the source contact and the drain contact, and this is used as a gettering site. The formation process and the patterning process are unnecessary. Thereby, the manufacturing cost can be reduced and the productivity can be improved.
[0025]
This configuration is an example, and is not limited to this configuration. A silicon film containing an impurity element belonging to Group 15 of the periodic table is used as a gettering site through a source contact and a drain contact, and amorphous silicon is used. It is the intent of the present invention to getter metal elements that helped crystallize the film.
[0026]
【Example】
[Example 1]
In this embodiment, it is necessary to apply a crystallization method using a metal element disclosed in Japanese Patent Laid-Open No. 7-130652 as a method for producing a crystalline silicon film as an active layer of a TFT and to form a CMOS circuit. A method for manufacturing a n-channel TFT (n-ch TFT) and a p-channel TFT (p-ch TFT) on the same substrate will be described with reference to FIGS.
[0027]
As shown in FIG. 2A, base insulating films 202a and 202b are formed over a substrate 201 to form a base insulating layer. As the substrate 201, a glass substrate such as barium borosilicate glass or alumino borosilicate glass is used. Since such a glass substrate shrinks by several ppm to several tens of ppm depending on the temperature during heat treatment, it may be preheated at a temperature lower by 10 to 20 ° C. than the glass strain point. In addition, such a glass substrate contains a trace amount of an impurity element such as an alkali metal element such as sodium, and such an element may penetrate into the active layer and affect the electrical characteristics of the TFT. Base insulating films 202a and 202b are provided as blocking layers for such elements. As the base insulating film, a silicon nitride film or a silicon oxide film is used, but the silicon nitride film has an advantage of a high blocking effect of impurity elements, but has a disadvantage that there are many trap levels. Although there is an advantage that the gap is wide and the insulating property is high and the trap level is low, the blocking property of the impurity element is low. Therefore, by providing the silicon nitride film on the substrate side and the silicon oxide film on the active layer side, it is possible to form a base insulating layer taking advantage of both. Here, for example, a silicon oxynitride film with a high nitrogen component is disposed in the base insulating film 202a, and a silicon oxynitride film with a high oxygen component is disposed in the base insulating film 202b. The base insulating film 202a is made of SiH. _Four , NH _Three , N ₂ O is formed to a thickness of 10 to 100 nm (preferably 20 to 60 nm), and the base insulating film 202b is made of SiH. _Four , N ₂ O is formed to a thickness of 10 to 200 nm (preferably 20 to 100 nm).
[0028]
In this embodiment, since the glass substrate is used, the base insulating film is formed. However, a quartz substrate, a ceramic substrate, or a metal substrate may be used. Note that in the case where a substrate in which an impurity element is not diffused is used for the semiconductor film, it is not necessary to form a base insulating film.
[0029]
These films are formed using a conventional parallel plate type plasma CVD method. The silicon oxynitride film 202a is made of SiH. _Four 10SCCM, NH _Three 100SCCM, N ₂ O introduced into 20SCCM reaction chamber, substrate temperature 400 ° C, reaction pressure 0.3Torr, discharge power density 0.41W / cm ² The film was formed under the condition of a discharge frequency of 60 MHz. After the silicon oxynitride film 202a is formed, the chamber may be cleaned in order to stably supply the film such as a measure against dust. In the meantime, the substrate on which the silicon oxynitride film 202a is formed is taken out of the chamber, and therefore, pollutant elements such as phosphorus and carbon may adhere to the surface of the 202a due to the influence of the clean room environment. So N ₂ O plasma treatment may be performed to effectively remove phosphorus and carbon adhering to the surface of 202a. Thereby, the fluctuation | variation of the electrical property of TFT accompanying the movement to the active layer of a contaminating element can be reduced. On the other hand, the silicon oxynitride film 202b is made of SiH. _Four 4SCCM, N ₂ O was introduced into the 400SCCM reaction chamber, substrate temperature 400 ° C, reaction pressure 0.3 Torr, discharge power density 0.41 W / cm ² The film was formed under the condition of a discharge frequency of 60 MHz.
[0030]
The silicon oxynitride film 202a formed here has a density of 9.28 × 10 6. ^{twenty two} /cm ^Three And ammonium hydrogen fluoride (NH _Four HF ₂ ) 7.13% and ammonium fluoride (NH _Four A mixed solution containing 15.4% of F) (product name: LAL500, manufactured by Stella Chemifa) has a slow etching rate at 20 ° C. of 63 nm / min, and is a dense and hard film. By using such a film as the base insulating film, it is possible to prevent the alkali metal from diffusing into the active layer.
[0031]
Then, an amorphous silicon film 203a is formed to a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known method such as a plasma CVD method or a sputtering method to form an amorphous semiconductor layer. Here, for example, an amorphous silicon film is formed with a thickness of 55 nm. Further, the base film 202b and the amorphous silicon film 203a may be formed continuously. For example, after the silicon oxynitride film 202a and the silicon oxynitride film 202b are formed by plasma CVD as described above, the reaction gas is changed to SiH. _Four , N ₂ O to SiH _Four And H ₂ Or SiH _Four By switching only to this, continuous film formation can be performed without being exposed to the air atmosphere once. As a result, surface contamination of the silicon oxynitride film 202b can be prevented, and variations in characteristics of TFTs to be manufactured and variations in Vth can be reduced.
[0032]
In order to perform crystallization with a metal element, an aqueous solution containing 10 ppm of the metal element in terms of weight is applied by a spin coating method to form the layer 204 containing the metal element. As the metal element, Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, Ge, Pb, In, or the like is used. The metal element-containing layer 204 may be formed with a thickness of 1 to 5 nm by a sputtering method or a vacuum deposition method in addition to the spin coating method.
[0033]
In the crystallization step shown in FIG. 2B, first, heat treatment is performed at 400 to 500 ° C. for about 1 hour, so that the hydrogen content of the amorphous silicon film is 5 atomic% or less. Then, thermal annealing is performed in a nitrogen atmosphere at 550 to 600 ° C. for 1 to 8 hours using a furnace annealing furnace. Through the above steps, the crystalline silicon film 203b can be obtained. However, the crystalline silicon film 203b produced by thermal annealing in the steps so far consists of a plurality of crystal grains when observed microscopically with a transmission electron microscope or the like, and the size and arrangement of the crystal grains are uniform. It is not random. In addition, when a spectrum is observed from Raman spectroscopy or macroscopically observed with an optical microscope, it may be observed that an amorphous region remains locally.
[0034]
In order to further improve the crystallinity of such a crystalline silicon film 203b, it is effective to perform laser annealing at this stage. In the laser annealing method, the crystalline silicon film 203b is once melted and then recrystallized, so that the above object can be achieved. For example, a XeCl excimer laser (wavelength 308 nm) is used to form a linear beam with an optical system, and an oscillation frequency of 5 to 50 Hz and an energy density of 100 to 500 mJ / cm. ² Irradiation is performed with a linear beam overlap ratio of 80 to 98%. In this way, the crystallinity of the crystalline silicon film 203b can be further increased.
[0035]
Then, a photoresist pattern is formed on the crystalline silicon film 203b, and the crystalline silicon film is divided into islands by dry etching to form island-like semiconductor layers 205a and 206 to be active layers. CF for dry etching _Four And O ₂ The mixed gas was used. Thereafter, a mask layer 207 made of a silicon oxide film having a thickness of 50 to 130 nm is formed by plasma CVD, low pressure CVD, or sputtering. Here, SiH is used by the low pressure CVD method. _Four 40SCCM, NO ₂ Was introduced into a 400 SCCM reaction chamber and formed to a thickness of 130 nm under the conditions of a substrate temperature of 400 ° C. and a reaction pressure of 2 Torr.
[0036]
Then, a photoresist mask 208 is provided, and the island-like semiconductor layer 205a for forming the n-ch TFT is 1 × 10 6 for controlling Vth ¹⁶ ~ 5 × 10 ¹⁷ atoms / cm ^Three An impurity element imparting p-type is added at a moderate concentration. As an impurity element imparting p-type to a semiconductor, elements of Group 13 of the periodic table such as boron (B), aluminum (Al), and gallium (Ga) are known. Here, diborane (B ₂ H ₆ ) And boron (B) was added. Boron (B) addition is not always necessary and may be omitted. However, the semiconductor layer 205b to which boron (B) is added is formed in order to keep the threshold voltage of the n-ch TFT within a predetermined range. I was able to.
[0037]
In order to form the LDD region of the n-ch TFT, an impurity element imparting n-type conductivity is selectively added to the island-shaped semiconductor layer 205b. As an impurity element imparting n-type to a semiconductor, elements of Group 15 of the periodic table such as phosphorus (P), arsenic (As), and antimony (Sb) are known. A photoresist mask 209 is formed, and phosphorous (P) is added here to add phosphorus (P). _Three ) Was applied. The phosphorus (P) concentration in the impurity region 210 to be formed is 2 × 10 ¹⁶ ~ 5 × 10 ¹⁹ atoms / cm ^Three The range. In this specification, the concentration of an impurity element imparting n-type contained in the impurity region 210 is represented by (n−).
[0038]
Next, the mask layer 207 is removed with an etching solution such as hydrofluoric acid diluted with pure water. Then, a step of activating the impurity element added to the island-shaped semiconductor layer 205b in FIGS. 3B and 3C is performed. The activation can be performed by a method such as thermal annealing for 1 to 4 hours at 500 to 600 ° C. in a nitrogen atmosphere or laser annealing. Moreover, you may carry out using both methods together. In this example, a laser activation method is used, a KrF excimer laser beam (wavelength 248 nm) is used to form a linear beam, an oscillation frequency of 5 to 50 Hz, and an energy density of 100 to 500 mJ / cm. ² As a result, the entire surface of the substrate on which the island-shaped semiconductor layer was formed was processed by scanning the linear beam with an overlap ratio of 80 to 98%. Note that there are no particular limitations on the irradiation conditions of the laser beam, and the practitioner may make an appropriate decision.
[0039]
Next, the gate insulating film 211 is formed with an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method. First, a plasma cleaning process is performed prior to the formation of the gate insulating film. Plasma cleaning process is H ₂ 200 SCCM, reaction pressure 0.15 Torr, discharge power density 0.2 W / cm ² Then, plasma is generated under the condition of a discharge frequency of 60 MHz and processed for 2 minutes. Or H ₂ 100 SCCM and 100 SCCM of oxygen may be introduced, and plasma may be similarly generated at a reaction pressure of 0.3 Torr. The substrate temperature is 300 to 450 ° C., preferably 400 ° C. Thus, contaminants such as boron and phosphorus adsorbed on the surfaces of the island-like semiconductor layers 205b and 206 and organic substances can be removed. Also oxygen and N ₂ By introducing O at the same time, the outermost surface of the surface to be deposited and its vicinity are oxidized, and there is a preferable action such as reducing the interface state density with the gate insulating film. The gate insulating film 211 is formed in succession to the plasma cleaning process in the same manner as the silicon oxynitride film 202b described above. _Four 4SCCM, N ₂ O was introduced into the 400SCCM reaction chamber, substrate temperature 400 ° C, reaction pressure 0.3 Torr, discharge power density 0.41 W / cm ² The film was formed under the condition of a discharge frequency of 60 MHz.
[0040]
A conductive layer is formed over the gate insulating film 211 to form a gate electrode. Although this conductive layer may be formed as a single layer, it may have a laminated structure of two layers or three layers as required. In this example, a conductive layer (A) 212 made of a conductive nitride metal film and a conductive layer (B) 213 made of a metal film were laminated. The conductive layer (B) 213 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or an alloy film in which the elements are combined. (Typically Mo—W alloy film, Mo—Ta alloy film), and the conductive layer (A) 212 may be tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, or nitride. It is made of molybdenum (MoN). For the conductive layer (A) 212, tungsten silicide, titanium silicide, or molybdenum silicide may be used. In the conductive layer (B) 213, the impurity concentration contained in the conductive layer (B) 213 should be reduced in order to reduce the resistance. In particular, the oxygen concentration should be 30 ppm or less. For example, tungsten (W) was able to realize a specific resistance value of 20 μΩcm or less by setting the oxygen concentration to 30 ppm or less.
[0041]
The conductive layer (A) 212 may be 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 213 may be 200 to 400 nm (preferably 250 to 350 nm). In this example, a TaN film having a thickness of 30 nm was used for the conductive layer (A) 212 and a Ta film of 350 nm was used for the conductive layer (B) 213, both of which were formed by sputtering. The TaN film was formed using Ta as a target and a mixed gas of Ar and nitrogen as a sputtering gas. Ta used Ar as the sputtering gas. If an appropriate amount of Xe or Kr is added to these sputtering gases, the internal stress of the film can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm, which is suitable for use as a gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm, which is not suitable for a gate electrode. Since the TaN film has a crystal structure close to an α phase, an α phase Ta film can be easily obtained by forming a Ta film thereon. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 212. This improves adhesion and prevents oxidation of the conductive film formed thereon, and at the same time, an alkali metal element contained in a trace amount in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 211. Can be prevented. In any case, the conductive layer (B) preferably has a resistivity in the range of 10 to 500 μΩcm.
[0042]
Next, a photoresist mask 214 is formed, and the conductive layer (A) 212 and the conductive layer (B) 213 are etched together to form gate electrodes 215 and 216. For example, CF by dry etching _Four And O ₂ Mixed gas, or Cl ₂ At a reaction pressure of 1-20 Pa. The gate electrodes 215 and 216 are integrally formed of 215a and 216a made of a conductive layer (A) and 215b and 216b made of a conductive layer (B). At this time, the gate electrode 216 of the n-ch TFT is formed so as to overlap a part of the impurity region 210 with the gate insulating film 211 interposed therebetween. Alternatively, the gate electrode can be formed using only the conductive layer (B) (FIG. 3D).
[0043]
Next, impurity regions 218 serving as a source region and a drain region of the p-ch TFT are formed. Here, an impurity element imparting p-type conductivity is added using the gate electrode 215 as a mask, and an impurity region is formed in a self-aligning manner (FIG. 4A). At this time, the island-shaped semiconductor layer forming the n-ch TFT is covered with a photoresist mask 217. The impurity region 218 is diborane (B ₂ H ₆ ) Using an ion doping method. The boron (B) concentration in this region is 3 × 10 ²⁰ ~ 3 × 10 ^{twenty one} atoms / cm ^Three To be. In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 218 formed here is expressed as (p +).
[0044]
Next, an impurity region 219 for forming a source region or a drain region of the n-ch TFT was formed. Here, phosphine (PH _Three ), And the phosphorus (P) concentration in this region is 1 × 10 ²⁰ ~ 1 × 10 ^{twenty one} atoms / cm ^Three It was. In this specification, the concentration of the impurity element imparting n-type contained in the impurity region 219 formed here is expressed as (n +). Phosphorus (P) is also added to the impurity region 218 at the same time, but the concentration of phosphorus (P) added to the impurity region 218 is 1/2 that of the boron (B) concentration already added in the previous step. Since it was about 1, p-type conductivity was secured, and the TFT characteristics were not affected at all (FIG. 4B).
[0045]
After that, a silicon oxynitride film is formed to form an interlayer insulating layer 220 (FIG. 4C). That is, SiH _Four 27 SCCM, N ₂ O was introduced into the 900 SCCM reaction chamber, the substrate temperature was 400 ° C, the reaction pressure was 1.2 Torr, and the discharge power density was 0.14 W / cm. ² And a discharge frequency of 13.56 MHz and a thickness of 500-1500 nm (preferably 600-800 nm).
[0046]
Then, contact holes reaching the source region or drain region of the TFT are formed in the interlayer insulating layer 220, and a silicon film containing an impurity element belonging to Group 15 of the periodic table is formed. Here, phosphorus is selected as an impurity element belonging to Group 15 of the periodic table, and phosphorus is 1 × 10 ¹⁹ atoms / cm ^Three The gettering layer 221 is formed by depositing the silicon film including the above. As a formation method, any of a plasma CVD method, a low pressure CVD method, and a sputtering method may be used, and any of an amorphous silicon film, a microcrystalline silicon film, and a crystalline silicon film may be used. In the p-ch TFT, the impurity region of the semiconductor layer and the gettering layer 221 are in contact with each other at the contact portion with the semiconductor layer to form a pn junction. However, since the impurity concentration of the impurity region of the semiconductor layer in the contact portion is high, increasing the phosphorus concentration contained in the gettering layer 221 results in a tunnel junction and low contact resistance. Therefore, no trouble occurs in the contact portion (FIG. 4D).
[0047]
Thereafter, thermal activation is performed. The thermal activation condition is 400 to 800 ° C (preferably 500 to 600 ° C). By this thermal activation, the gettering layer 221 functions as a gettering site through the source contact and the drain contact, gettering the metal element that promotes crystallization remaining in the semiconductor layers 205 and 206, and the concentration of the metal element in the semiconductor layer Can be reduced to below the detection limit or to the extent that it does not affect the electrical characteristics of the TFT. Since the gettering layer 221 exists over the entire substrate surface, the entire substrate surface functions as a gettering site, and high gettering efficiency can be obtained. This thermal activation step also plays a role of activating the impurity element imparting n-type or p-type added at each concentration. Specifically, a furnace annealing furnace may be used for the thermal activation process.
[0048]
After the activation step, a heat treatment was performed at 300 to 500 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to hydrogenate the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0049]
After that, a second conductive layer 222 is formed as shown in FIG. The second conductive layer may be a laminated film for preventing hillocks and oxidation. Then, as shown in FIG. 5B, the second conductive layer 222 is patterned to function as part of the source wirings 223 and 226 and the drain wirings 224 and 225, and then is used as a mask for gettering by self-alignment. The ring layer 221 is etched so that the gettering layer 221 as well as the second conductive layer 222 functions as part of the source wirings 223 and 226 and the drain wirings 224 and 225.
[0050]
Next, a silicon nitride film or a silicon oxynitride film is formed as the passivation film 227 with a thickness of 50 to 500 nm (typically 100 to 300 nm). When the hydrogenation treatment is performed in this state, favorable results can be obtained with respect to the improvement of TFT characteristics. For example, thermal annealing may be performed at 300 to 500 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen.
[0051]
Thus, the n-ch TFT 236 and the p-ch TFT 235 were completed on the substrate 201. The p-ch TFT 235 includes a channel formation region 229, a source region 228, and a drain region 230 in the island-shaped semiconductor layer 206. The n-ch TFT 236 includes a channel formation region 233 and an LDD region 232 that overlaps with the gate electrode 216 (hereinafter, such an LDD region is referred to as Lov), a source region 234, and a drain region 231 in the island-shaped semiconductor layer 205. ing. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm (preferably 1.0 to 1.5 μm) with respect to the channel length of 3 to 8 μm. In this embodiment, each TFT has a single gate structure, but a double gate structure or a multi-gate structure provided with a plurality of gate electrodes may be used.
[0052]
Through the above steps, an n-ch TFT and a p-ch TFT necessary for forming a CMOS circuit can be manufactured on the same substrate.
[0053]
[Example 2]
Embodiments to which the gettering method of the present invention is applied when manufacturing a TFT having an inverted stagger structure will be described with reference to FIGS.
[0054]
First, a glass substrate such as a # 1737 substrate manufactured by Corning was prepared as the substrate 301. Then, a gate electrode 302 was formed on the substrate 301. Here, a tantalum (Ta) film was formed to a thickness of 200 nm by sputtering. The gate electrode 302 may have a two-layer structure of a tantalum nitride (TaN) film (film thickness 50 nm) and a Ta film (film thickness 250 nm). The Ta film is formed by sputtering using Ar gas and using Ta as the target. When sputtering is performed with a mixed gas in which Xe gas is added to Ar gas, the absolute value of the internal stress is 2 × 10. ⁸ It can be made Pa or less (FIG. 6A).
[0055]
Then, a gate insulating film 303 and an amorphous silicon film 304 were successively formed as an amorphous semiconductor layer without being sequentially opened to the atmosphere. As the gate insulating film 303, a nitrogen-rich silicon oxynitride film 303a is formed to a thickness of 25 nm by using a plasma CVD method, and an oxygen-rich silicon oxynitride film 303b is formed to a thickness of 125 nm on the silicon oxide film 303a. Form. The amorphous silicon film 304 was also formed by a plasma CVD method with a thickness of 20 to 100 nm, preferably 40 to 75 nm. Then, in the same manner as the crystallization described in the first embodiment, a metal element that promotes crystallization is used. First, a layer 305 containing a metal element is formed by a spin coating method, a sputtering method, a vacuum evaporation method, or the like (FIG. 6B).
[0056]
Thereafter, thermal annealing is performed at 450 to 550 ° C. for 1 hour using a furnace annealing furnace, thereby releasing hydrogen from the amorphous silicon film 304 and reducing the remaining hydrogen amount to 5 atomic% or less. Then, using a furnace annealing furnace, thermal annealing is performed in a nitrogen atmosphere at 550 to 600 ° C. for 1 to 8 hours, so that a crystalline silicon film 306 can be obtained (FIG. 6C). Here, as in Example 1, when laser annealing is performed in order to reduce locally remaining amorphous regions, it can effectively act and increase crystallinity.
[0057]
Next, a 200 nm thick silicon oxynitride film 307 was formed in close contact with the crystalline silicon film 306 thus formed to serve as a channel protective insulating film. After that, a resist mask 308 in contact with the silicon oxynitride 307 is formed by a patterning method using exposure from the back surface. Here, the gate electrode 302 serves as a mask, and the resist mask 308 can be formed in a self-aligning manner. As shown in the figure, the size of the resist mask was slightly smaller than the width of the gate electrode due to the wraparound of light (FIG. 6D).
[0058]
After the silicon oxynitride film 307 was etched using this resist mask 308 to form a channel protective insulating film 309, the resist mask 308 was removed. Through this step, the surface of the crystalline silicon film 306 other than the region in contact with the channel protective insulating film 309 was exposed. This channel protective insulating film 309 has the effect of preventing impurities from being added to the channel region in the subsequent impurity addition step and has the effect of reducing the interface state density of the crystalline silicon film (FIG. 7). (A)).
[0059]
Next, a resist mask 310 that covers a part of the n-ch TFT and the p-ch TFT region is formed by patterning using a photomask, and an n-type is applied to the region where the surface of the crystalline silicon film 306 is exposed. A step of adding an impurity element to be imparted was performed. And n ⁺ Region 311a was formed. Here, phosphine (PH _Three ), Dose amount 5 × 10 ¹⁴ atoms / cm ² Then, phosphorus (P) was added at an acceleration voltage of 10 kV. Further, the pattern of the resist mask 310 can be changed to n by an appropriate setting by the practitioner. ⁺ The width of the region is determined, n with the desired width ^- A mold region and a channel formation region can be formed (FIG. 7B).
[0060]
After removing the resist mask 310, a protective insulating film 312 was formed. This film was also formed to a thickness of 50 nm under the same conditions as the silicon oxynitride film 307 (FIG. 7C). Next, a step of adding an impurity element imparting n-type to the crystalline silicon film provided with the protective insulating film 312 on the surface is performed, and n ^- A mold region 313 was formed. However, in order to add impurities to the underlying crystalline silicon film through the protective insulating film 312, it is necessary to set appropriate conditions in consideration of the thickness of the protective insulating film 312. Here, dose amount 3 × 10 ¹³ atoms / cm ² The acceleration voltage was 60 kV. N formed in this way ^- The region 313 functions as an LDD region (FIG. 7D).
[0061]
Next, a resist mask 315 covering the n-ch TFT was formed, and a step of adding an impurity element imparting p-type to a region where the p-ch TFT was formed was performed. Here, diborane (B ₂ H ₆ ) And boron (B) was added. The dose amount is 4 × 10 ¹⁵ atoms / cm ² P as acceleration voltage 30 kV ⁺ A region was formed (FIG. 8A). After that, the channel protective insulating film 309 and the protective insulating film 312 are left as they are, and the crystalline silicon film is etched into a desired shape by a known patterning technique (FIG. 8B).
[0062]
Through the above steps, a source region 316, a drain region 317, an LDD region 318, 319, and a channel formation region 320 of the n-ch TFT are formed, and a source region 322, a drain region 323, and a channel formation region 321 of the p-ch TFT are formed. Formed. Next, a first interlayer insulating film 325 was formed to a thickness of 100 to 500 nm so as to cover the n-ch TFT and the p-ch TFT. (FIG. 8 (C)). Further, a second interlayer insulating film 326 was also formed to a thickness of 100 to 500 nm (FIG. 8D).
[0063]
Then, a predetermined resist mask was formed on the first interlayer insulating film 325 and the second interlayer insulating film 326, and contact holes reaching the source region and the drain region of each TFT were formed by an etching process. Then, as in Example 1, phosphorus is selected as the impurity element belonging to Group 15 of the periodic table, and phosphorus is 1 × 10 6. ¹⁹ atoms / cm ^Three A silicon film including the above is formed, and a gettering layer 327 is formed. As a formation method, any of a plasma CVD method, a low pressure CVD method, and a sputtering method may be used, and any of an amorphous silicon film, a microcrystalline silicon film, and a crystalline silicon film may be used. Thereafter, thermal activation is performed in the same manner as in Example 1 to getter the metal element remaining in the crystalline silicon film 306 with high efficiency. The thermal activation condition is 400 to 800 ° C (preferably 500 to 600 ° C). This thermal activation step plays a role of activating the impurity element imparting n-type or p-type added at each concentration, and the gettering layer 327 is formed as an amorphous silicon film or a microcrystalline silicon film. If formed, the gettering layer 327 is a crystalline silicon film. After the activation process, the process of hydrogenating the island-shaped semiconductor layer by further heat treatment at 300-500 ° C. for 1-12 hours in an atmosphere containing 3-100% hydrogen dangling the semiconductor layer It may be added to terminate the bond. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed (FIG. 9A).
[0064]
Thereafter, a second conductive layer is formed. The second conductive layer may be used as a laminated film for preventing hillocks and oxidation. Then, after patterning the second conductive layer to function as part of the source wirings 328 and 330 and the drain wiring 329, the gettering layer 327 is etched by self-alignment using the second conductive layer as a mask, together with the second conductive layer. The gettering layer 327 also functions as part of the source wirings 328 and 330 and the drain wiring 329 (FIG. 9B).
[0065]
Further, a step of forming a passivation film 331 was performed. The passivation film is SiH by plasma CVD. _Four , N ₂ O, NH _Three Silicon oxynitride film or SiH formed from _Four , N ₂ , NH _Three A silicon nitride film manufactured from First, prior to film formation, N ₂ O, N ₂ , NH _Three Etc. were introduced to carry out plasma hydrogenation treatment. Here, the hydrogen generated in the gas phase by being converted into plasma is also supplied into the second interlayer insulating film, and if the substrate is heated to 200 to 500 ° C., the hydrogen is converted into the first interlayer insulating film. Furthermore, it could be diffused to the lower layer side, and it could be a second hydrogenation step. The conditions for forming the passivation film are not particularly limited, but a dense film is desirable. Finally, thermal annealing at 300 to 550 ° C. was performed for 1 to 12 hours in an atmosphere containing hydrogen or nitrogen for the third hydrogenation step. At this time, hydrogen is transferred from the passivation film 331 to the second interlayer insulating film 326, from the second interlayer insulating film 326 to the first interlayer insulating film 325, and from the first interlayer insulating film 325 to the crystalline silicon film. Hydrogen can be diffused to effectively realize hydrogenation of the crystalline silicon film. Hydrogen is released from the film into the gas phase, but it could be prevented to some extent by forming the passivation film as a dense film, and it can be compensated by supplying hydrogen to the atmosphere. did it.
[0066]
Through the above steps, a p-ch TFT and an n-ch TFT can be formed on the same substrate with an inverted staggered structure.
[0067]
[Example 3]
A method for manufacturing the pixel TFT of the pixel portion and the TFT of the driver circuit provided around the pixel portion over the same substrate will be described with reference to FIGS. However, for simplification of description, in the drive circuit, a CMOS circuit which is a basic circuit such as a shift register circuit and a buffer circuit and an n-ch TFT forming a sampling circuit are illustrated.
[0068]
As shown in FIG. 10A, a base insulating film is formed over an insulating substrate 401. For example, a 1737 glass substrate manufactured by Corning is used for 401. On this glass substrate, SiH is used to prevent diffusion of impurities from the substrate. _Four , N ₂ O, NH _Three A silicon oxynitride film 402a made from 50 nm, SiH _Four , N ₂ A base insulating film 402 was formed by forming a silicon oxynitride film 402b made of O to a thickness of 100 nm.
[0069]
Next, an amorphous silicon film 403a is formed as an amorphous semiconductor layer with a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known method such as a plasma CVD method or a sputtering method. In this example, an amorphous silicon film was formed to a thickness of 55 nm by plasma CVD. Further, since the base film 402 and the amorphous silicon film 403a can be formed by the same film formation method, they may be formed continuously. After the base film 402 is formed, it is possible to prevent the surface from being contaminated by not exposing it to the air atmosphere, so that variations in characteristics of TFTs to be manufactured and variations in Vth can be reduced.
[0070]
Then, as in Example 1, in order to crystallize using a metal element, a layer containing a metal element is applied by spin coating with an aqueous solution containing 10 ppm of the metal element in terms of weight (not specifically shown). Was formed on the amorphous silicon film 403a. As the metal element, Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, Ge, Pb, In, or the like is used. In the crystallization step, first, thermal annealing is performed at 400 to 500 ° C. for about 1 hour to reduce the hydrogen content of the amorphous silicon film to 5 atomic% or less. Thereby, roughening of the film surface can be prevented. When forming an amorphous silicon film by plasma CVD, SiH is used as the reaction gas. _Four If the substrate temperature during film formation is 300 to 400 ° C. using Ar and Ar, the hydrogen concentration in the amorphous silicon film can be reduced to 5 atomic% or less. Is no longer necessary. Then, a crystalline silicon film can be obtained through the above steps using a furnace annealing furnace and performing thermal annealing at 550 to 600 ° C. for 1 to 8 hours in a nitrogen atmosphere. In this state, the concentration of the metal element remaining on the surface is 3 × 10 ^Ten ~ 2 × 10 ¹¹ atoms / cm ² Met. Thereafter, a laser annealing method may be used in combination to increase the crystallization rate. Thus, a crystalline semiconductor layer 403b made of a crystalline silicon film was formed. (FIG. 10 (B)).
[0071]
The crystalline silicon film thus formed is patterned into an island shape, and the active layer 404 of the p-ch TFT of the CMOS circuit, the active layer 405 of the n-ch TFT, and the activity of the n-ch TFT forming the sampling circuit are formed by dry etching. A layer 406 and an active layer 407 of the pixel portion TFT were formed. Thereafter, a mask layer 408 made of a silicon oxide film having a thickness of 50 to 100 nm is formed by plasma CVD, low pressure CVD, or sputtering. For example, SiH by low pressure CVD method _Four And O ₂ And a silicon oxide film is formed by heating to 400 ° C. at 266 Pa (FIG. 10C).
[0072]
Then, a channel doping process is performed. First, a photoresist mask 409 is provided, and 1 × 10 6 for the purpose of controlling Vth over the entire surface of the island-like semiconductor layers 405 to 407 forming the n-ch TFT. ¹⁶ ~ 5 × 10 ¹⁷ atoms / cm ^Three Boron (B) was added as an impurity element imparting p-type at a moderate concentration. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of an amorphous silicon film. Here, boron (B) addition is not necessarily required, but it is preferable to form the semiconductor layers 410 to 412 to which boron (B) is added in order to keep the Vth of the n-ch TFT within a predetermined range. . (FIG. 10 (D)).
[0073]
In order to form the LDD region of the n-channel TFT of the driver circuit, an impurity element imparting n-type conductivity is selectively added to the island-shaped semiconductor layers 410 and 411. Therefore, photoresist masks 413 to 416 were formed in advance. Here, phosphine (PH) is added to add phosphorus (P). _Three ) Was applied. Formed n ^- The phosphorus (P) concentration in the impurity regions 417 and 418 is 1 × 10 ¹⁷ ~ 5 × 10 ¹⁸ atoms / cm ^Three And The impurity region 419 is a semiconductor layer for forming a storage capacitor of the pixel portion, and phosphorus (P) is added to this region at the same concentration. (Fig. 11 (A))
[0074]
Next, the mask layer 408 is removed with hydrofluoric acid or the like, and a step of activating the impurity element added in the steps of FIGS. 10D and 11A is performed. The activation can be performed by thermal annealing at 500 to 600 ° C. for 1 to 4 hours in a nitrogen atmosphere or laser annealing. Moreover, you may carry out using both together. In this example, a laser activation method is used, a KrF excimer laser beam (wavelength 248 nm) is used to form a linear beam, an oscillation frequency of 5 to 50 Hz, and an energy density of 100 to 500 mJ / cm. ² As a result, the entire surface of the substrate on which the island-shaped semiconductor layer was formed was processed by scanning the linear beam with an overlap ratio of 80 to 98%. Note that there are no particular limitations on the irradiation conditions of the laser beam, and the practitioner may make an appropriate decision.
[0075]
Then, the gate insulating film 420 is formed with a thickness of 50 to 150 nm by plasma CVD. If plasma cleaning is performed using, for example, hydrogen before forming the gate insulating film, the interface between the gate insulating film 420 and the island-shaped semiconductor layers 404 and 410 to 412 is kept clean, which affects the electrical characteristics of the TFT. The interface state density exerted can be reduced. Oxygen and N ₂ Even if O is added, the interface state density can be further reduced by oxidizing the outermost surface of the island-shaped semiconductor layers 404 and 410 to 412 and the vicinity thereof. Then, a gate insulating film 420 is formed continuously with the plasma cleaning (FIG. 11B).
[0076]
Next, a first conductive layer is formed to form a gate electrode. In this embodiment, a conductive layer (A) 421 made of a conductive nitride metal film and a conductive layer (B) 422 made of a metal film are laminated. Here, the conductive layer (B) 422 is formed with tantalum (Ta) to a thickness of 250 nm by sputtering using Ta as a target, and the conductive layer (A) 421 is made of tantalum nitride (TaN) with a thickness of 50 nm. (FIG. 11C).
[0077]
Next, photoresist masks 423 to 427 are formed, and the conductive layer (A) 421 and the conductive layer (B) 422 are etched together to form gate electrodes 428 to 431 and a capacitor wiring 432. The gate electrodes 428 to 431 and the capacitor wiring 432 are integrally formed of 428a to 432a made of a conductive layer (A) and 428b to 432b made of a conductive layer (B). At this time, the gate electrodes 429 and 430 formed in the driver circuit are formed so as to overlap with part of the impurity regions 417 and 418 with the gate insulating film 420 interposed therebetween (FIG. 11D).
[0078]
Next, a step of adding an impurity element imparting p-type conductivity is performed in order to form a source region and a drain region of the p-channel TFT of the driver circuit. Here, the impurity region is formed in a self-aligning manner using the gate electrode 428 as a mask. A region where the n-channel TFT is formed is covered with a photoresist mask 433. And diborane (B ₂ H ₆ P) by ion doping method using ⁺ Impurity region 434 is 1 × 10 ^{twenty one} atoms / cm ^Three (FIG. 12A).
[0079]
Next, in an n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 435 to 437 were formed, and an impurity element imparting n-type conductivity was added to form impurity regions 438 to 441. This is the phosphine (PH _Three ) By ion doping using n) ⁺ Impurity regions 438 to 441 have a (P) concentration of 5 × 10 5 ²⁰ atoms / cm ^Three (FIG. 12B).
[0080]
Then, in order to form the LDD region of the n-channel TFT in the pixel portion, an impurity addition step for imparting n-type was performed. Here, an impurity element imparting n-type in a self-aligning manner is added by ion doping using the gate electrode 431 as a mask. The concentration of phosphorus (P) to be added is 5 x 10 ¹⁶ atoms / cm ^Three 11A, 12A, and 12B, the impurity element is added at a concentration lower than the concentration of the impurity element in FIG. ^- Only impurity regions 443 and 444 are formed. The impurity region 442 already contains boron (B) added in the previous step, but phosphorus (P) is added at a considerably lower concentration than that, so the effect of the added P Was not considered, and had no effect on the TFT characteristics (FIG. 12C).
[0081]
Next, a second conductive layer serving as a gate wiring is formed. The second conductive layer is formed of a conductive layer (D) mainly composed of aluminum (Al) or copper (Cu) which is a low resistance material. In any case, the resistivity of the second conductive layer is about 0.1 to 10 μΩcm. Further, a conductive layer (E) made of titanium (Ti), tantalum (Ta), tungsten (W), or molybdenum (Mo) is preferably stacked. In this embodiment, an aluminum (Al) film containing 0.1 to 2% by weight of titanium (Ti) is formed as the conductive layer (D) 445, and a titanium (Ti) film is formed as the conductive layer (E) 446. The conductive layer (D) 445 may have a thickness of 200 to 400 nm (preferably 250 to 350 nm), and the conductive layer (E) 446 may have a thickness of 50 to 200 nm (preferably 100 to 150 nm) (see FIG. 12 (D)).
[0082]
Then, in order to form a gate wiring connected to the gate electrode, the conductive layer (E) 446 and the conductive layer (D) 445 were etched to form gate wirings 447 and 448 and a capacitor wiring 449. The etching process starts with SiCl _Four And Cl ₂ And BCl _Three The conductive layer (E) is removed from the surface of the conductive layer (E) to the middle of the conductive layer (D) by a dry etching method using a mixed gas and then the conductive layer (D) is removed by wet etching with a phosphoric acid-based etching solution. Thus, the gate wiring can be formed while maintaining selective processability with the base (FIG. 13A).
[0083]
As the first interlayer insulating film 450, a silicon oxynitride film was formed to a thickness of 500 to 1500 nm. Thereafter, contact holes reaching the source region or the drain region formed in each island-like semiconductor layer are formed, and phosphorous is added at 1 × 10 6 as in the first and second embodiments. ¹⁹ atoms / cm ^Three The gettering layer 451 was formed by forming the silicon film including the above. As a formation method, any of a plasma CVD method, a low pressure CVD method, and a sputtering method may be used, and any of an amorphous silicon film, a microcrystalline silicon film, and a crystalline silicon film may be used. Thereafter, thermal activation is performed to getter the metal element remaining in the island-like semiconductor layers 404, 410 to 412 through the source contact and the drain contact. The thermal activation condition is 400 to 800 ° C (preferably 500 to 600 ° C). By this thermal activation step, an impurity element imparting n-type or p-type can be activated at the same time. Then, a hydrogenation step for terminating dangling bonds in the island-like semiconductor layers 404, 410 to 412 may be added (FIG. 13B).
[0084]
Thereafter, a third conductive layer that bears part of the source and drain wirings is formed. The third conductive layer may be a laminated film for preventing hillocks and oxidation. After patterning this conductive layer to function as part of the source wirings 452 to 455 and drain wirings 456 to 459, the gettering layer 451 is etched by self-alignment using this as a mask, and gettering is performed together with the third conductive layer. The layer 451 also functions as part of the source wirings 452 to 455 and the drain wirings 456 to 459.
[0085]
Next, a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed as the passivation film 460 with a thickness of 50 to 500 nm (typically 100 to 300 nm). In any case, the passivation film is formed so as to be a dense film to block moisture from the outside, and a function as a cap layer is added in the second hydrogenation step performed thereafter. For example, when the passivation film 460 is formed with a dense silicon nitride film to a thickness of 200 nm and hydrogenation is performed in this state, a favorable result can be obtained for improving the characteristics of the TFT. The heat treatment is preferably performed at 300 to 500 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen or in a nitrogen atmosphere. Of course, in addition to such a method, the same effect can be obtained if the hydrogenation treatment is performed before the above-described silicon nitride film is formed or a plasma hydrogenation method is used. Further, this plasma hydrogenation and the above-described hydrogenation may be used in combination. Note that an opening may be formed in the passivation film 460 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later. (Figure 13 (C))
[0086]
Thereafter, a second interlayer insulating film 461 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, it was formed by baking at 300 ° C. using a type of polyimide that is thermally polymerized after being applied to the substrate. Then, a contact hole reaching the drain wiring 459 is formed in the second interlayer insulating film 461, and pixel electrodes 462 and 463 are formed. The pixel electrode may be a transparent conductive film in the case of a transmissive liquid crystal display device, and may be a metal film in the case of a reflective liquid crystal display device. In this embodiment, in order to obtain a transmissive liquid crystal display device, an indium oxide and tin (ITO) film was formed to a thickness of 100 nm by sputtering. (Fig. 14)
[0087]
Through the steps described above, here, the pixel TFT of the pixel portion and the TFT of the driver circuit provided around the pixel portion can be manufactured over the same substrate.
[0088]
A p-channel TFT 501 of a CMOS circuit of a driver circuit includes a channel formation region 506, a source region 507, and a drain region 508 in an island-shaped semiconductor layer 404. Similarly, the n-channel TFT 502 of the CMOS circuit includes a channel formation region 509, an LDD region (Lov) 510 that overlaps with the gate electrode 429, a source region 511, and a drain region 512 in the island-like semiconductor layer 410. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. In the n-channel TFT 503 of the sampling circuit, a channel formation region 513, an Lov region and an Loff region (an LDD region that does not overlap with a gate electrode, hereinafter referred to as an Loff region) 514, 515, a source region or an island-like semiconductor layer 411 Drain regions 516 and 517 are formed, and the length of the Loff region in the channel length direction is 0.3 to 2.0 μm, preferably 0.5 to 1.5 μm. The pixel TFT 504 includes channel formation regions 518 and 519, Loff regions 520 to 523, and source or drain regions 524 to 526 in the island-shaped semiconductor layer 412. The length of the Loff region in the channel length direction is 0.5 to 3.0 μm, preferably 1.5 to 2.5 μm. Further, the storage capacitor 505 includes capacitor wirings 432 and 449, an insulating film made of the same material as the gate insulating film, and a semiconductor layer 527 connected to the drain region 526 of the pixel TFT 504 and doped with an impurity element imparting n-type conductivity. Is formed. In FIG. 14, the pixel TFT 504 has a double gate structure, but it may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.
[0089]
[Example 4]
Another method of adding a metal element for promoting crystallization of the amorphous silicon film used in Examples 1 to 3 will be described with reference to FIG.
[0090]
First, as shown in FIG. 15A, a base insulating film 602 and an amorphous silicon film 603 are formed over a substrate 601 as in the first to third embodiments. Next, a mask insulating film 604 made of a silicon oxide film is formed, and an opening 605 for selectively adding a metal element is formed.
[0091]
In this state, UV light is irradiated in an oxygen atmosphere to form a thin oxide film on the amorphous silicon film 603. Next, a nickel acetate solution containing 100 ppm of Ni is applied by a spin coating method, and a very thin Ni-containing layer 606 can be formed on the surface of the amorphous silicon film 603 exposed at the opening 605 (FIG. 15A). )).
[0092]
Then, thermal annealing is performed at 600 ° C. for 8 hours in a nitrogen atmosphere to crystallize the amorphous silicon film 603. Crystallization starts from the opening 605 of the mask insulating film 604 to which Ni is selectively added, and proceeds from this region to which Ni is added in a direction (lateral direction) parallel to the film surface. The region crystallized by this is called a lateral growth region. The amorphous silicon film 603 includes a Ni-added region 607, a laterally grown region (crystalline silicon film) 608, and a region (amorphous silicon film) 609 where lateral growth has not been achieved. In the case of a TFT active layer, the lateral growth region 608 is patterned by leaving it in an island shape.
[0093]
A crystalline silicon film was obtained as described above. Thereafter, it can be applied to the TFT in the same manner as in Examples 1 to 3.
[0094]
[Example 5]
The substrate manufactured in Embodiment 3 is referred to as an active matrix substrate. In this embodiment, an example of a process of manufacturing an active matrix liquid crystal display device from this active matrix substrate and its circuit arrangement will be described with reference to FIGS. explain. Since the manufacturing method of the active matrix substrate has already been described in Embodiment 3, it is omitted here.
[0095]
As shown in FIG. 16, an alignment film 701 is formed on the active matrix substrate in the state shown in FIG. Usually, a polyimide resin is often used for the alignment film of the liquid crystal display element. A light shielding film 703, a transparent conductive film 704, and an alignment film 705 were formed on the counter substrate 702 on the counter side. After the alignment film was formed, rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. Then, the pixel portion, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown), and the like by a known cell assembly process. Thereafter, a liquid crystal material 706 was injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. In this way, the active matrix liquid crystal display device shown in FIG. 16 is completed.
[0096]
FIG. 17 shows a simplified circuit arrangement of the active matrix substrate as shown in FIG. Reference numeral 801 denotes a pixel portion, in which gate wirings 806 and source wirings 807 intersect in a matrix. Reference numerals 802 and 803 in the periphery denote a scanning signal driving circuit and an image signal driving circuit, respectively.
[0097]
The circuit arrangement shown here is an example, and the circuit arrangement is not limited to this.
[0098]
[Example 6]
An active matrix substrate manufactured by implementing the present invention is used in various electro-optical devices such as an organic EL display device (a light-emitting device including a film containing an organic compound that can emit light by applying an electric field), a liquid crystal display device. Is also applicable. The present invention can be applied to all electronic devices in which such an electro-optical device is incorporated as a display medium. Examples of electronic devices include personal computers, digital cameras, video cameras, portable information terminals (mobile computers, mobile phones, electronic books, etc.), navigation systems, and the like. Examples of these are shown in FIGS.
[0099]
FIG. 18A illustrates a personal computer, which includes a main body 1001 including a microprocessor, a memory, and the like, an image input portion 1002, a display device 1003, and a keyboard 1004. The liquid crystal display device and the organic EL display device of the present invention can be applied to the display device 1003.
[0100]
FIG. 18B illustrates a video camera which includes a main body 1101, a display device 1102, an audio input portion 1103, operation switches 1104, a battery 1105, and an image receiving portion 1106. The liquid crystal display device and the organic EL display device of the present invention can be applied to the display device 1102.
[0101]
FIG. 18C illustrates a portable information terminal which includes a main body 1201, an image input unit 1202, an image receiving unit 1203, operation switches 1204, and a display device 1205. The liquid crystal display device and the organic EL display device of the present invention can be applied to the display device 1205.
[0102]
FIG. 18D shows a player that uses a recording medium (hereinafter referred to as a recording medium) in which a program is recorded, and includes a main body 1301, a display device 1302, a speaker unit 1303, a recording medium 1304, and operation switches 1305. Note that DVD (Digital Versatile Disc) or compact disc (CD) can be used as the recording medium, and music program playback, video display, video game (or video game), and information display via the Internet can be performed. . The liquid crystal display device and the organic EL display device of the present invention can be suitably used for the display device 1302.
[0103]
FIG. 19A illustrates a digital camera which includes a main body 1401, a display device 1402, an eyepiece unit 1403, an operation switch 1404, and an image receiving unit (not shown). The liquid crystal display device and the organic EL display device of the present invention can be applied to the display device 1402.
[0104]
FIG. 19B shows a mobile phone, which includes a main body 1501, an audio output portion 1502, an audio input portion 1503, a display portion 1504, operation switches 1505, an antenna 1506, and the like. The present invention can be applied to the audio output unit 1502, the audio input unit 1503, the display unit 1504, and other signal control circuits.
[0105]
FIG. 19C shows a display, which includes a main body 1601, a support base 1602, a display portion 1603, and the like. The present invention can be applied to the display portion 1603. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).
[0106]
FIG. 20A illustrates a front projector, which includes a light source optical system, a display device 2001, and a screen 2002. The present invention can be applied to display devices and other signal control circuits. FIG. 20B shows a rear projector, which includes a main body 2101, a light source optical system and display device 2102, a mirror 2103, and a screen 2104. The present invention can be applied to display devices and other signal control circuits.
[0107]
Note that FIG. 20C illustrates an example of the structure of the light source optical system and the display devices 2001 and 1022 in FIGS. 20A and 20B. The light source optical system and the display devices 2001 and 1022 include a light source optical system 2201, mirrors 2202 and 2204 to 2206, a dichroic mirror 2203, a beam splitter 2207, a liquid crystal display device 2208, a phase difference plate 2209, and a projection optical system 2210. The projection optical system 2210 includes a plurality of optical lenses. In FIG. 20C, a three-plate type example using three liquid crystal display devices 2208 is shown; however, the present invention is not limited to this type, and a single-plate type optical system may be used. In FIG. 20C, an optical path indicated by an arrow may be provided with an appropriate optical lens, a film having a polarization function, a film for adjusting a phase, an IR film, or the like. FIG. 20D illustrates an example of the structure of the light source optical system 2201 in FIG. In this embodiment, the light source optical system 2201 includes a reflector 2301, a light source 2302, lens arrays 2303 and 2304, a polarization conversion element 2305, and a condenser lens 2306. The light source optical system shown in FIG. 20D is an example and is not limited to the illustrated configuration.
[0108]
Although not shown here, the present invention can also be applied to a navigation system, a reading circuit of an image sensor, and the like. As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. In addition, the electronic apparatus of this example can be realized by using the crystallization technique of Embodiments 1 to 3 and using a configuration composed of any combination of Examples 1 to 6.
[0109]
【The invention's effect】
By forming a silicon film containing phosphorus in the source contact and drain contact portions and using it as a gettering site, the metal element that promotes the crystallization of the amorphous silicon film can be effectively removed or reduced, and the TFT In addition to improving the stability and reliability of the electrical characteristics, it is possible to eliminate the mask layer formation process and oxide film patterning process, which are required for conventional gettering, thereby improving productivity. Connected. Further, in gettering by doping, the crystal structure of the device region is damaged accompanying doping, and an additional doping step is required to reduce the source and drain resistance in the p-ch TFT. Good gettering can be performed without suffering such damage.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration example of the present invention.
FIG. 2 is a diagram showing a process of manufacturing n-ch and p-ch TFTs on the same substrate.
FIG. 3 is a diagram showing a process of manufacturing n-ch and p-ch TFTs on the same substrate.
FIG. 4 is a diagram showing a process of manufacturing n-ch and p-ch TFTs on the same substrate.
FIG. 5 is a diagram showing a process of manufacturing n-ch and p-ch TFTs on the same substrate.
FIG. 6 is a diagram showing a process of manufacturing inverted staggered n-ch and p-ch TFTs on the same substrate.
FIG. 7 is a diagram showing a process of manufacturing inverted staggered n-ch and p-ch TFTs on the same substrate.
FIG. 8 is a diagram showing a process of manufacturing inverted staggered n-ch and p-ch TFTs on the same substrate.
FIG. 9 is a diagram showing a process of manufacturing inverted staggered n-ch and p-ch TFTs on the same substrate.
FIG. 10 is a diagram showing a process of manufacturing a pixel TFT and a TFT of a driver circuit over the same substrate.
FIG. 11 is a diagram showing a process of manufacturing a pixel TFT and a TFT of a driver circuit over the same substrate.
FIG. 12 is a diagram showing a process of manufacturing a pixel TFT and a TFT of a driver circuit over the same substrate.
FIG. 13 is a diagram showing a process of manufacturing a pixel TFT and a TFT of a driver circuit over the same substrate.
FIG. 14 is a diagram showing a process of manufacturing a pixel TFT and a TFT of a driver circuit over the same substrate.
FIG. 15 shows a method for adding a metal element that promotes crystallization.
FIG 16 illustrates a structure of an active matrix liquid crystal display device.
FIG. 17 is a diagram showing a circuit layout of an active matrix liquid crystal display device.
FIG 18 illustrates an example of a semiconductor device.
FIG 19 illustrates an example of a semiconductor device.
FIG. 20 is a diagram showing an example of a projector

Claims (12)

A crystalline silicon film having a source region, a drain region, and a channel formation region between the source region and the drain region;
An interlayer insulating film on the crystalline silicon film;
A silicon film containing an impurity element belonging to Group 15 on the interlayer insulating film;
And a conductive layer on a silicon film containing an impurity element belonging to Group 15;
The crystalline silicon film is obtained by crystal growth of an amorphous silicon film to which a metal element that promotes crystallization is added,
The silicon film containing an impurity element belonging to Group 15 is in contact with the source region or the drain region in a contact hole provided in the interlayer insulating film, and the silicon film containing an impurity element belonging to Group 15 is A semiconductor device characterized in that a metal element that promotes crystallization is segregated. A crystalline silicon film having a source region, a drain region, and a channel formation region between the source region and the drain region;
A protective insulating film on the crystalline silicon film;
An interlayer insulating film on the protective insulating film;
A silicon film containing an impurity element belonging to Group 15 on the interlayer insulating film;
And a conductive layer on a silicon film containing an impurity element belonging to Group 15;
The crystalline silicon film is obtained by crystal growth of an amorphous silicon film to which a metal element that promotes crystallization is added,
The silicon film containing an impurity element belonging to Group 15 contains the impurity element belonging to Group 15 in contact with the source region or the drain region in a contact hole provided in the protective insulating film and the interlayer insulating film . A semiconductor device characterized in that the metal element that promotes the crystallization is segregated in the silicon film. In claim 1 or claim 2,
The metal element that promotes crystallization is one or more elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, Ge, Pb, and In. A semiconductor device characterized by the above. In any one of Claim 1 thru | or 3,
The semiconductor device according to claim 15, wherein the impurity element belonging to Group 15 is phosphorus. In any one of Claim 1 thru | or 3,
The semiconductor device is characterized in that the impurity element belonging to Group 15 is phosphorus, and the phosphorus concentration is 1 × 10 ¹⁹ atoms / cm ³ or more. Forming an amorphous silicon film,
A metal element for promoting crystallization is added to the amorphous silicon film, and the amorphous silicon film is crystal-grown to form a crystalline silicon film;
An impurity element is added to a selected region of the crystalline silicon film to form a source region and a drain region;
Forming an interlayer insulating film on the crystalline silicon film in which the source region and the drain region are formed;
Forming a contact hole reaching the source region or the drain region in the interlayer insulating film;
Forming a silicon film containing an impurity element belonging to Group 15 on the contact hole and the interlayer insulating film;
Gettering the metal element for promoting crystallization contained in the crystalline silicon film by thermal annealing to a silicon film containing an impurity element belonging to the group 15 ;
A method for manufacturing a semiconductor device, comprising forming a conductive layer over a silicon film containing an impurity element belonging to Group 15 above. Forming an amorphous silicon film,
A metal element for promoting crystallization is added to the amorphous silicon film, and the amorphous silicon film is crystal-grown to form a crystalline silicon film;
An impurity element is added to a selected region of the crystalline silicon film to form a source region and a drain region;
Forming a protective insulating film on the crystalline silicon film in which the source region and the drain region are formed;
Forming an interlayer insulating film on the protective insulating film;
Forming a contact hole reaching the source region or the drain region in the protective insulating film and the interlayer insulating film;
Forming a silicon film containing an impurity element belonging to Group 15 on the contact hole and the interlayer insulating film;
Gettering the metal element for promoting crystallization contained in the crystalline silicon film by thermal annealing to a silicon film containing an impurity element belonging to the group 15 ;
A method for manufacturing a semiconductor device, comprising forming a conductive layer over a silicon film containing an impurity element belonging to Group 15 above. Forming an amorphous silicon film,
A metal element for promoting crystallization is added to the amorphous silicon film, and the amorphous silicon film is crystal-grown to form a crystalline silicon film;
An impurity element is added to a selected region of the crystalline silicon film to form a source region and a drain region;
Forming a protective insulating film on the crystalline silicon film in which the source region and the drain region are formed;
Forming an interlayer insulating film on the protective insulating film;
Forming a contact hole reaching the source region or the drain region in the protective insulating film and the interlayer insulating film;
Forming a silicon film containing an impurity element belonging to Group 15 on the contact hole and the interlayer insulating film;
Gettering the metal element for promoting crystallization contained in the crystalline silicon film by thermal annealing to a silicon film containing an impurity element belonging to the group 15 ;
Forming a conductive layer on a silicon film containing an impurity element belonging to Group 15;
After patterning the conductive layer , the patterned conductive layer is used to pattern a silicon film containing an impurity element belonging to the group 15 by self-alignment, and the patterned conductive layer and the impurity element belonging to the group 15 A method for manufacturing a semiconductor device, comprising forming a wiring made of a silicon film containing silicon. In any one of Claims 6 thru | or 8,
The method of manufacturing a semiconductor device, wherein the thermal annealing causes gettering of a metal element that promotes crystallization, and activates an impurity element added to the source region and the drain region. In any one of Claims 6 thru | or 9,
The metal element that promotes crystallization is a semiconductor that is one or more elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, Ge, Pb, and In. Device fabrication method. In any one of Claims 6 thru | or 10,
The method for manufacturing a semiconductor device, wherein the impurity element belonging to Group 15 is phosphorus. In any one of Claims 6 thru | or 10,
The method for manufacturing a semiconductor device, wherein the impurity element belonging to Group 15 is phosphorus, and the phosphorus concentration is 1 × 10 ¹⁹ atoms / cm ³ or more.

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