JP2001326364A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the productivity by effectively removing metal elements which accelerate the crystallization of an amorphous silicon film in a thin film transistor. SOLUTION: The metal elements which accelerate the crystallization of amorphous silicon are effectively removed, or reduced, using a silicon film containing a XV group element such as phosphorus through a contact hole reaching the source and drain regions, to increase the productivity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit comprising a thin film transistor (hereinafter referred to as TFT) using a method for effectively removing a metal element which promotes crystallization of an amorphous silicon film. It relates to a manufacturing method. For example, the present invention relates to an electro-optical device typified by an active matrix type liquid crystal display device in which a pixel portion and a driver circuit are provided on the same substrate, and an electronic device including such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and includes not only a single element as a TFT but also an electro-optical device formed using a TFT. Electronic devices and semiconductor circuits on which such electro-optical devices are mounted as components are all semiconductor devices.

[0003]

2. Description of the Related Art A TFT using a semiconductor thin film is used for various integrated circuits. Semiconductor thin films include amorphous silicon films and crystalline silicon films.Amorphous silicon films are easy to form and have excellent productivity, but the operating speed is slow due to the low electrical characteristics of TFTs. It cannot be used for an active matrix type liquid crystal display device in which peripheral driving circuits are integrated, or various integrated circuits cannot be formed. Therefore, a crystalline silicon film having better characteristics is used.

[0004] As a method of manufacturing a crystalline silicon film,
There are a thermal annealing method and a laser annealing method. However, since the thermal annealing method requires a high-temperature process of 600 ° C. or higher, it cannot be applied to an inexpensive and large-sized glass substrate and has a problem that the processing time is long. In addition, although the laser annealing method can realize a process that does not cause thermal damage to the substrate, there is a problem that satisfactory ones such as uniformity of crystallinity, reproducibility, and crystallinity cannot be obtained. As one means for solving such a problem, there is a method of promoting crystallization using a predetermined metal element.

The above-mentioned method is disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652 by the present applicant as a technique for lowering the crystallization temperature to 600 ° C. or less which is applicable to a glass substrate while using thermal annealing.
There is a method disclosed in Japanese Patent Publication No. This method
A crystalline silicon film having good crystallinity has been obtained by a method of introducing a metal element represented by Ni into an amorphous silicon film and performing thermal annealing.

[0006]

When a method of promoting crystallization using a predetermined metal element is used, the crystallization proceeds with the diffusion and movement of the metal element. The element remains in the crystalline silicon film. As a result, it precipitates near the surface of the crystalline silicon film, causing junction leakage, and also forms a deep level and becomes the center of recombination and generation of carriers, which impairs the stability and reliability of the electrical characteristics of the TFT The problem arises. Therefore, various techniques using gettering have been developed as techniques for removing or reducing this metal element.

In the gettering method, for example, after the amorphous silicon film is crystallized with a metal element to form a crystalline silicon film, a portion to be a device region is covered with a mask layer such as an oxide film. In addition to this, a method of doping a group 15 element such as P, which is effective for gettering, at a high concentration so as to promote gettering (hereinafter referred to as a gettering site), or masking a location to be a device region similarly There is a method of forming a gettering site by forming a silicon film containing a high concentration of a group 15 element such as P thereon. However, these methods form a film to be a mask layer,
Since a patterning step is required, the number of masks increases, leading to an increase in manufacturing cost and a decrease in productivity.

As another method, for example, there is a method in which the source and drain regions of a device are used as gettering sites. In this method, the number of masks can be reduced because patterning for gettering is unnecessary, but the gettering efficiency is slightly reduced because the gettering site is limited in volume, and the donor is also used for p-ch TFTs. In order to dope a group 15 element such as P, which is to be used, ions serving as acceptors must be excessively doped, which causes an increase in manufacturing cost and a decrease in productivity.

The invention disclosed in the present specification is directed to a TFT manufactured using a crystalline silicon film obtained by utilizing a metal element which promotes crystallization of an amorphous silicon film. It is an object of the present invention to provide a technique capable of suppressing the adverse effect of the method and reducing the manufacturing cost and increasing the productivity.

[0010]

One of the inventions disclosed in this specification is a crystal having a source region, a drain region, and a channel formation region sandwiched between the source region and the drain region on an insulating surface. Crystalline silicon film, a gate insulating film on the crystalline silicon film, a gate electrode on the gate insulating film, an interlayer insulating film on the gate electrode,
In a semiconductor device having a silicon film containing phosphorus on the interlayer insulating film and a conductive layer on a silicon film containing an impurity element belonging to Group 15 of the periodic table, an impurity element belonging to Group 15 of the periodic table Is in contact with a source region or a drain region of the crystalline silicon film at a contact hole formed in the interlayer insulating film, and the silicon film containing an impurity element belonging to Group 15 of the periodic table is the crystalline silicon film. A semiconductor device in which a metal element required for forming a silicon film is segregated.

According to another aspect of the present invention, a gate electrode is provided on an insulating surface, a gate insulating film is provided on the gate electrode, and a source region and a drain region are provided on the gate insulating film. A crystalline silicon film having a channel formation region sandwiched between, a protective insulating film over the crystalline silicon film, an interlayer insulating film over the protective insulating film,
In a semiconductor device having a silicon film containing an impurity element belonging to Group 15 of the periodic table on the interlayer insulating film and a conductive layer on a silicon film containing an impurity element belonging to Group 15 of the periodic table, The silicon film containing an impurity element belonging to Group 15 of the Table is in contact with a source region or a drain region of the crystalline silicon film through a contact hole formed in the interlayer insulating film. The semiconductor device according to the present invention is characterized in that the contained silicon film has a metal element required for forming the crystalline silicon film segregated.

According to another aspect of the present invention, there is provided a first step of forming an amorphous silicon film on an insulating surface, and adding a metal element which promotes crystallization of the amorphous silicon film. The second step is to form a crystalline silicon film by growing a crystal on the film.
A third step of forming a gate insulating film on the crystalline silicon film, a fourth step of forming a gate electrode on the gate insulating film, and a selected region of the crystalline silicon film A fifth step of forming a source region and a drain region by adding an impurity element to the gate electrode, a sixth step of forming an interlayer insulating film on the gate electrode, and reaching the source region or the drain region in the interlayer insulating film. A seventh step of forming a contact hole; an eighth step of forming a silicon film containing an impurity element belonging to Group 15 of the periodic table on the contact hole and the interlayer insulating film; A ninth step of gettering the metal element contained in the silicon film and a step of forming a conductive film on the silicon film containing an impurity element belonging to Group 15 of the periodic table. 0 and steps, a method for manufacturing a semiconductor device having a.

According to another aspect of the invention, there is provided a first step of forming a gate electrode on the insulating surface, a second step of forming a gate insulating film on the gate electrode, and a step of forming a non-conductive layer on the gate insulating film. A third step of forming a crystalline silicon film, and a fourth step of adding a metal element for promoting crystallization of the amorphous silicon film and growing the amorphous silicon film to form a crystalline silicon film. A fifth step of forming a protective insulating film on the crystalline silicon film, and a sixth step of forming a source region and a drain region by adding an impurity element to a selected region of the crystalline silicon film. A step of forming an interlayer insulating film on the protective insulating film, an eighth step of forming a contact hole reaching the source region or the drain region in the protective insulating film and the interlayer insulating film, Source area A ninth step of forming a silicon film containing an impurity element belonging to Group 15 of the periodic table on the contact hole reaching the drain region and the interlayer insulating film, and including the silicon film in the crystalline silicon film by thermal annealing. A method for manufacturing a semiconductor device, comprising: a tenth step of performing gettering of the metal element; and an eleventh step of forming a conductive film on a silicon film containing an impurity element belonging to Group 15 of the periodic table. .

In the structure of the above four inventions, the silicon film containing an impurity element belonging to Group 15 of the periodic table promotes crystallization of the amorphous silicon film by thermal annealing through a contact hole reaching a source region or a drain region. Function as a gettering site for the metallic element to be formed.

It has been found from the invention by the present applicant that in the above four aspects of the present invention, it is preferable to use Ni as a metal element that promotes crystallization of the amorphous silicon film. In general, Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, as metal elements that promote crystallization of an amorphous silicon film,
One or more elements selected from Au, Ge, Pb, and In can be used.

In the above four inventions, the impurity element belonging to Group 15 of the periodic table is an element for gettering a metal element that promotes crystallization of the amorphous silicon film. When nickel (Ni) is selected as a metal element that promotes crystallization of an amorphous silicon film and phosphorus (P) is selected as a gettering element, gettering can be performed effectively.

When phosphorus is selected as an impurity element belonging to Group 15 of the periodic table, the phosphorus concentration in the phosphorus-containing silicon film is 1 × 10 ¹⁹ atoms / cm ³ or more. pc
In an hTFT, a PN junction is formed between an impurity region of a semiconductor layer and the silicon film. However, since the impurity region contained in the impurity region and the silicon has a high concentration, a large number of impurities existing in the polycrystalline silicon film are formed. Because of the crystal defect, a tunnel junction is formed at the contact hole where the impurity region of the semiconductor layer and the phosphorus-containing silicon film are in contact, and a sufficiently low contact resistance can be obtained.

The metal element for promoting crystallization is introduced by ion implantation, diffusion using a solution, diffusion using a solid, diffusion from a film formed by sputtering or CVD, plasma Methods such as a treatment method and a gas adsorption method can be used. As the silicon film containing phosphorus as a gettering element, a film formed by a plasma CVD (P-CVD) device, a low-pressure CVD (LP-CVD) device, a sputtering device, or the like can be used.

In the above four aspects of the present invention, the thermal annealing promotes the gettering of the metal element which promotes the crystallization of the amorphous silicon film, and at the same time, is doped to form the source and drain regions. The impurity element can be activated, and heat treatment steps required for the progress of gettering and activation of the impurity element can be performed at once.

In the above four aspects of the present invention, the phosphorus-containing silicon film is formed by forming a conductive film on the phosphorus-containing silicon film and then patterning the conductive film by self-alignment to function as a wiring.

[0021]

FIG. 1 shows a specific configuration example of the present invention. That is, a base insulating film 102 is formed over a substrate 101, a crystalline silicon film 103 is formed over the base insulating film 102, and a crystalline silicon film 10 having a channel formation region 103a and a source or drain region 103b.
3, a gate insulating film 104 is formed on the base insulating film 102, a gate electrode 105 is formed on the gate insulating film 104, and the gate electrode 105 and the gate insulating film 104 are formed.
An interlayer insulating film 107 is formed thereon, a contact hole reaching the source or drain region 103b of the crystalline silicon film is formed in the interlayer insulating film 107 and the gate insulating film 104, and a contact hole and an interlayer reaching the source or drain region are formed. 1 of the periodic table on the insulating film 107
A silicon film 106 containing an impurity element belonging to Group V is formed, a conductive film 108 is formed on the silicon film 106 containing an impurity element belonging to Group 15 of the periodic table, and finally an impurity element belonging to Group 15 of the periodic table. Containing silicon film 106
Is formed as a source or drain electrode 109 having a lower layer. In this specification, the surface of a substrate and the surface of an insulating film formed over the substrate are referred to as an insulating surface.

The crystalline silicon film is formed by forming an amorphous silicon film on the base insulating film 102, introducing a metal element which promotes crystallization into the amorphous silicon film, and performing thermal annealing. Therefore, the crystalline silicon film contains a metal element that promotes crystallization. Further, the impurity element belonging to Group 15 of the periodic table contained in the silicon film 106 has an action of gettering a metal element that has promoted crystallization by thermal annealing.

Therefore, when thermal annealing is performed after forming the silicon film 106 containing the impurity element belonging to Group 15 of the periodic table, the source region or the drain region 1 of the crystalline silicon film is formed.
Through a contact hole reaching 03b (hereinafter referred to as a source contact and a drain contact, respectively)
The metal element that promotes crystallization is effectively removed from the crystalline silicon film by phosphorus having a gettering action in the silicon film 106. Further, by performing thermal annealing after forming the silicon film 106 containing an impurity element belonging to Group 15 of the periodic table, the entire substrate becomes a gettering site because the silicon film 106 is present over the entire substrate,
Gettering efficiency is higher than in the method of using the drain region as a gettering site. After that, 15 of the periodic table
The silicon film 106 containing an impurity element belonging to the group functions as a source electrode or a drain electrode 109 together with the conductive film 108.

The feature of this structure is that a silicon film containing an impurity element belonging to Group 15 of the periodic table is formed in contact with the source contact and the drain contact, and this is used as a gettering site. This eliminates the need for the mask layer forming step and the patterning step. Thereby, a reduction in manufacturing cost and an improvement in productivity can be achieved.

This configuration is an example, and is not limited to this configuration. A silicon film containing an impurity element belonging to Group 15 of the periodic table is used as a gettering site through a source contact and a drain contact.
It is the intention of the present invention to getter the metal element that promoted the crystallization of the amorphous silicon film.

[0026]

[Embodiment 1] In this embodiment, a method of manufacturing a crystalline silicon film as an active layer of a TFT is disclosed in
By applying a crystallization method using a metal element disclosed in Japanese Patent No. 0652, an n-channel TFT (n-ch TFT) and a p-channel TFT (p-ch TFT) required for forming a CMOS circuit are obtained. For the method of manufacturing on the same substrate, FIG.
Explanation will be made with reference to FIG.

As shown in FIG. 2A, base insulating films 202a and 202b are formed on a substrate 201 to form a base insulating layer. As the substrate 201, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass is used.
Such a glass substrate has several ppm or more depending on the temperature during the heat treatment.
Shrinks by several tens of ppm, so it is 10 to 20 more than the glass strain point.
The heat treatment may be performed in advance at a temperature lower by ° C. In addition, such glass substrates contain trace amounts of impurity elements such as alkali metal elements such as sodium, which may penetrate into the active layer and affect the electrical characteristics of the TFT. The base insulating films 202a and 202b are provided as blocking layers for such elements. As a base insulating film, a silicon nitride film or a silicon oxide film is applied. The silicon nitride film has an advantage of a high blocking effect of an impurity element, but has a drawback of many trap levels. There is an advantage that the gap is wide, the insulating property is high, and the trap level is low, but the blocking property of the impurity element is low. Therefore, by providing the silicon nitride film on the substrate side and the silicon oxide film on the active layer side, it is possible to form a base insulating layer utilizing both advantages. Here, for example, a structure in which a silicon oxynitride film with a high nitrogen component is provided for the base insulating film 202a and a silicon oxynitride film with a high oxygen component is provided for the base insulating film 202b is used. The base insulating film 202a is made of SiH ₄ , NH
₃ , formed from N ₂ O to a thickness of 10 to 100 nm (preferably 20 to 60 nm), and the base insulating film 202 b is formed to a thickness of 10 to 200 nm from SiH ₄ and N ₂ O.
(Preferably 20 to 100 nm).

Although a base insulating film is formed in this embodiment because a glass substrate is used, a quartz substrate, a ceramic substrate, or a metal substrate may be used. Note that when a substrate in which an impurity element is not diffused is used for a semiconductor film, it is not necessary to form a base insulating film.

These films are made of a conventional parallel plate type plasma.
It is formed using a CVD method. Silicon oxynitride film 202a
Introduced the SiH ₄ 10 SCCM, the NH ₃ 100 SCCM, the N ₂ O to 20SCCM reaction chamber, a substrate temperature of 400 ° C., a reaction pressure 0.3 Torr, the discharge power density 0.41W / cm ^2, was formed on condition that the discharge frequency 60MHz .
After the silicon oxynitride film 202a is formed, the chamber may be cleaned to stably supply the film, for example, as a measure against dust. Meanwhile, the silicon oxynitride film 202
Since the substrate on which the film a is formed is taken out of the chamber, the substrate may be affected by a clean room environment, and contaminant elements such as phosphorus and carbon may adhere to the surface of the surface 202a. So, N ₂ O
Plasma treatment may be performed to effectively remove phosphorus and carbon attached to the surface of the 202a. Thereby, it is possible to reduce the change in the electrical characteristics of the TFT due to the transfer of the contaminant element to the active layer. On the other hand, the silicon oxynitride film 202b
SiH ₄ was introduced into the reaction chamber at ₄ SCCM and N ₂ O was introduced into the reaction chamber at 400 SCCM.
The film was formed under the conditions of 00 ° C., a reaction pressure of 0.3 Torr, a discharge power density of 0.41 W / cm ² , and a discharge frequency of 60 MHz.

The silicon oxynitride film 202 formed here
a has a density of 9.28 × 10 ²² / cm ³ , 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and ammonium fluoride (NH
₄ F) of 15.4% comprising mixed solution (Stella Chemifa Co., Ltd., trade name LAL500) slower etch rate at 20 ° C. is between 63 nm / min of a hard film is dense. By using such a film as the base insulating film, diffusion of the alkali metal into the active layer can be prevented.

Then, an amorphous silicon film 203a is formed to a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known method such as a plasma CVD method or a sputtering method to form an amorphous semiconductor layer. . Here, for example, an amorphous silicon film is 55 n
m. The base film 202b and the amorphous silicon film 203a may be formed continuously. Oxide, for example after the deposition silicon nitride film 202a and a silicon oxynitride film 202b by plasma CVD, once the atmosphere be switched reactive gas from SiH _4, N ₂ O only SiH ₄ and H ₂ or SiH ₄ as described above Continuous film formation without exposure to water. As a result, surface contamination of the silicon oxynitride film 202b can be prevented, and variation in characteristics of a TFT to be manufactured and variation in Vth can be reduced.

Then, in order to perform crystallization by a metal element,
An aqueous solution containing 10 ppm by weight of a metal element is applied by a spin coating method to form a layer 204 containing a metal element. Metal elements include Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, P
t, Cu, Au, Ge, Pb, In, or the like is used. The layer 204 containing the metal element may be formed in a thickness of 1 to 5 nm by a sputtering method or a vacuum evaporation method other than the spin coating method.

Then, in the crystallization step shown in FIG. 2B, first, a heat treatment is performed at 400 to 500 ° C. for about 1 hour to reduce the hydrogen content of the amorphous silicon film to 5 atomic% or less. Then, using a furnace annealing furnace, 550 in a nitrogen atmosphere.
Perform thermal annealing at ~ 600 ° C for 1-8 hours. Through the above steps, the crystalline silicon film 203b can be obtained. However, the crystalline silicon film 203b formed by the thermal annealing in the steps up to here is composed of a plurality of crystal grains when microscopically observed with a transmission electron microscope or the like, and the size and the arrangement of the crystal grains are uniform. Not random. Further, when the spectrum is obtained by Raman spectroscopy or macroscopically observed by optical microscope observation, it may be observed that an amorphous region locally remains.

In order to further enhance the crystallinity of the crystalline silicon film 203b, it is effective to perform the laser annealing at this stage. In the laser annealing method, the crystalline silicon film 203b is once melted and then recrystallized, so that the above object can be achieved. For example, using a XeCl excimer laser (wavelength 308 nm), a linear beam is formed by an optical system, and an oscillation frequency of 5 to 50 Hz, an energy density of 100 to 500 mJ / cm ^{2 and an} overlap ratio of the linear beam of 80 to 98 are used. Irradiate as%. Thus, the crystallinity of the crystalline silicon film 203b can be further improved.

Then, a photoresist pattern is formed on the crystalline silicon film 203b, and the crystalline silicon film is divided into islands by dry etching so that the island-like semiconductor layer 2 is formed.
The active layers 05a and 206 are formed. For dry etching, a mixed gas of CF ₄ and O ₂ was used. After that, plasma C
50 to 130 nm by VD method, low pressure CVD method, or sputtering method
A mask layer 207 of a silicon oxide film having a thickness of is formed. Here, 40 SCCM of SiH ₄ and NO _{2 were}
Into the 400SCCM reaction chamber, substrate temperature 400 ° C, reaction pressure 2T
It was formed to a thickness of 130 nm under the condition of orr.

Then, a photoresist mask 208 is provided, and the p-type is formed at a concentration of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ for the purpose of controlling Vth in the island-like semiconductor layer 205a forming the n-ch TFT. An impurity element to be added is added. As an impurity element that imparts p-type to a semiconductor, an element belonging to Group 13 of the periodic table such as boron (B), aluminum (Al), or gallium (Ga) is known. Here, boron (B) was added using diborane (B ₂ H ₆ ) by an ion doping method. Boron (B)
Although the addition is not always necessary and may be omitted,
The semiconductor layer 205b to which boron (B) was added could be formed to keep the threshold voltage of the n-ch TFT within a predetermined range.

In order to form an LDD region of an n-ch TFT, an impurity element imparting n-type is selectively added to the island-shaped semiconductor layer 205b. Elements belonging to Group 15 of the periodic table, such as phosphorus (P), arsenic (As), and antimony (Sb), are known as impurity elements that impart n-type to a semiconductor. A photoresist mask 209 was formed. Here, an ion doping method using phosphine (PH ₃ ) was applied to add phosphorus (P). The concentration of phosphorus (P) in the impurity region 210 to be formed is in the range of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting n-type contained in the impurity region 210 is represented by (n−).

Next, the mask layer 207 is removed with an etching solution such as hydrofluoric acid diluted with pure water. And FIG.
In FIG. 3B and FIG. 3C, a step of activating the impurity element added to the island-shaped semiconductor layer 205b is performed. Activation can be performed by a method such as thermal annealing in a nitrogen atmosphere at 500 to 600 ° C. for 1 to 4 hours or laser annealing. Further, both methods may be used in combination. In this embodiment, a KrF excimer laser beam (wavelength 2
48 nm) to form a linear beam and generate an oscillation frequency of 5 to
Scanning at 50 Hz, energy density of 100-500 mJ / cm ^{2 and} overlapping ratio of linear beam of 80-98%,
The entire surface of the substrate on which the island-shaped semiconductor layer was formed was processed. There are no particular restrictions on the laser light irradiation conditions, and the conditions may be determined appropriately by the practitioner.

Next, the gate insulating film 211 is formed by plasma CVD.
It is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a method. First, a plasma cleaning process is performed before forming a gate insulating film. In the plasma cleaning process, H ₂ is introduced at 200 SCCM, plasma is generated under the conditions of a reaction pressure of 0.15 Torr, a discharge power density of 0.2 W / cm ² , and a discharge frequency of 60 MHz, and the process is performed for 2 minutes. Alternatively, H ₂ is 100 SCC
M and oxygen may be introduced at 100 SCCM, and plasma may be similarly generated and processed at a reaction pressure of 0.3 Torr. Substrate temperature is 300 ~ 4
50 ° C, preferably 400 ° C. Thus, contaminants such as boron, phosphorus, and organic substances adsorbed on the surfaces of the island-shaped semiconductor layers 205b and 206 can be removed. In addition, simultaneous introduction of oxygen and N ₂ O oxidizes the outermost surface of the surface to be deposited and the vicinity thereof, and has a favorable effect of reducing the interface state density with the gate insulating film. The formation of the gate insulating film 211 is performed continuously with the plasma cleaning process, and the above-described silicon oxynitride film 2 is formed.
Similar to 02b, introducing SiH ₄ 4 sccm, the N ₂ O to 400SCCM reaction chamber, a substrate temperature of 400 ° C., a reaction pressure 0.3 Torr, the discharge power density 0.41W / cm ^2, was formed on condition that the discharge frequency 60 MHz.

On the gate insulating film 211, a conductive layer is formed to form a gate electrode. This conductive layer may be formed as a single layer, but may have a laminated structure such as two layers or three layers as necessary. In this embodiment, a conductive layer (A) 212 made of a conductive nitride metal film and a conductive layer (B) 213 made of a metal film are stacked. The conductive layer (B) 213 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the above elements as a main component, or an alloy film combining the above elements. (Typically, a Mo—W alloy film or a Mo—Ta alloy film), and the conductive layer (A) 212 is formed of tantalum nitride (TaN), tungsten nitride (WN), or titanium nitride (TN).
iN) film, molybdenum nitride (MoN) or the like. Further, as the conductive layer (A) 212, tungsten silicide, titanium silicide, or molybdenum silicide may be used. The conductive layer (B) 213 preferably has a low impurity concentration in order to achieve low resistance, and particularly preferably has an oxygen concentration of 30 ppm or less. For example, tungsten (W) has an oxygen concentration of 30 ppm
The following specific resistance values could be realized.

The conductive layer (A) 212 has a thickness of 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 213 has a thickness of 200 to 400 nm.
(Preferably 250 to 350 nm). In this embodiment, a TaN film having a thickness of 30 nm is used for the conductive layer (A) 212, and a Ta film having a thickness of 350 nm is used for the conductive layer (B) 213. The TaN film was formed using Ta as a target and a mixed gas of Ar and nitrogen as a sputtering gas. Ta
Used Ar as a sputtering gas. In addition, when an appropriate amount of Xe or Kr is added to these sputter gases, the internal stress of the film can be relaxed and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 μΩcm, which is suitable for use as a gate electrode. However, the resistivity of the β-phase Ta film is about 180 μΩcm, which is not suitable for use as a gate electrode. Since the TaN film has a crystal structure close to the α-phase, if a Ta film is formed thereon, an α-phase Ta film can be easily obtained. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 212. Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, a small amount of the alkali metal element contained in the conductive layer (A) or the conductive layer (B) diffuses into the gate insulating film 211. Can be prevented. In any case, the conductive layer (B) has a resistivity of 10 to 500
It is preferable to set it in the range of μΩcm.

Next, a photoresist mask 214 is formed, and the conductive layer (A) 212 and the conductive layer (B) 213 are collectively etched to form gate electrodes 215 and 216.
For example, the dry etching method can be used at a reaction pressure of 1 to 20 Pa using a mixed gas of CF ₄ and O ₂ or Cl ₂ . The gate electrodes 215 and 216 are formed of a conductive layer (A).
And 215a and 216a made of the conductive layer (B) are integrally formed. At this time, the gate electrode 216 of the n-ch TFT is
Is formed so as to overlap a part of the gate insulating film 211 with the gate insulating film 211 interposed therebetween. Alternatively, the gate electrode can be formed using only the conductive layer (B) (FIG. 3D).

Next, an impurity region 218 to be a source region and a drain region of the p-ch TFT is formed. Here, an impurity element imparting p-type conductivity is added using the gate electrode 215 as a mask to form an impurity region in a self-aligned manner (FIG. 4A). At this time, the island-shaped semiconductor layer forming the n-ch TFT is covered with a photoresist mask 217.
Then, the impurity region 218 is formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ .
In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 218 formed here is expressed as (p +).

Next, an impurity region 219 for forming a source region or a drain region of the n-ch TFT was formed. Here, the ion doping method using phosphine (PH ₃ ) is performed, and the phosphorus (P) concentration in this region is set to 1 × 10 ²⁰ to 1 × 10 ^21.
atoms / cm ³ . In this specification, the concentration of the impurity element imparting n-type contained in the impurity region 219 formed here is expressed as (n +). Phosphorus (P) is also added to the impurity region 218 at the same time, and the concentration of phosphorus (P) added to the impurity region 218 is 2 of that of boron (B) already added in the previous step. Since it was about 1/3, p-type conductivity was secured, and there was no effect on the TFT characteristics (FIG. 4B).

Thereafter, a silicon oxynitride film is formed to form an interlayer insulating layer 220 (FIG. 4C). In other words, Si
H ₄ was introduced into the reaction chamber at 27 SCCM, N ₂ O was introduced into the reaction chamber at 900 SCCM, the substrate temperature was 400 ° C, the reaction pressure was 1.2 Torr, and the discharge power density was 0.14 W / c.
m ² , at a discharge frequency of 13.56 MHz, 500 to 1500 nm (preferably
(600-800 nm).

Then, a contact hole reaching the source or drain region of the TFT is formed in the interlayer insulating layer 220, and a silicon film containing an impurity element belonging to Group 15 of the periodic table is formed. Here, phosphorus is selected as an impurity element belonging to Group 15 of the periodic table, and phosphorus is 1 × 10 ¹⁹ atom
A gettering layer 221 is formed by forming a silicon film containing s / cm ³ or more. As a forming method, any of a plasma CVD method, a low pressure CVD method, and a sputtering method may be used, and any of an amorphous silicon film, a microcrystalline silicon film, and a crystalline silicon film may be used. In a p-ch TFT, an impurity region of the semiconductor layer and a gettering layer 22 are formed at a contact portion with the semiconductor layer.
The pn junction is formed by the contact of 1. However, since the impurity concentration of the impurity region of the semiconductor layer in the contact portion is high, a tunnel junction is formed by increasing the phosphorus concentration contained in the gettering layer 221 to obtain a low contact resistance. Therefore, no trouble occurs in the contact portion (FIG. 4D).

Thereafter, thermal activation is performed. The heat activation is performed at 400 to 800 ° C (preferably 500 to 600 ° C). Due to this thermal activation, the gettering layer 221 functions as a gettering site through the source contact and the drain contact, and getters the metal element that has promoted crystallization remaining in the semiconductor layers 205 and 206 to obtain a metal element concentration in the semiconductor layer. Can be reduced below the detection limit or to such an extent that the electrical characteristics of the TFT are not affected. Since the gettering layer 221 exists on the entire substrate surface,
The entire substrate surface functions as a gettering site, and high gettering efficiency can be obtained. This thermal activation step also plays a role in activating the n-type or p-type impurity element added at each concentration. Specifically, a furnace annealing furnace may be used for the heat activation step.

After the activation step, a heat treatment was further performed at 300 to 500 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to hydrogenate the island-like semiconductor layer. . In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Thereafter, as shown in FIG. 5A, a second conductive layer 222 is formed. This second conductive layer may be a laminated film for preventing hillocks and oxidation. Then, as shown in FIG. 5B, after patterning the second conductive layer 222 so as to function as a part of the source wirings 223 and 226 and part of the drain wirings 224 and 225, the getter is self-aligned using this as a mask. The ring layer 221 is etched, and the gettering layer 221 is formed together with the second conductive layer 222 by the source wirings 223 and 226 and the drain wiring 2.
24, 225.

Next, as a passivation film 227,
50-500 nm silicon nitride or silicon oxynitride film
(Typically 100 to 300 nm). If hydrogenation is performed in this state, favorable results can be obtained for improving the characteristics of the TFT. For example, thermal annealing is preferably performed at 300 to 500 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen.

Thus, the n-ch TFT 236 is formed on the substrate 201.
And the p-ch TFT 235 were completed. p-ch T
The FT 235 includes a channel formation region 229, a source region 228, and a drain region 230 in the island-shaped semiconductor layer 206. The n-ch TFT 236 has an LDD that overlaps the channel formation region 233 and the gate electrode 216 on the island-shaped semiconductor layer 205.
Region 232 (hereinafter, such an LDD region is referred to as Lov),
It has a source region 234 and a drain region 231.
The length of the Lov region in the channel length direction is from channel length 3 to
0.5 to 3.0 μm (preferably 1.0 to 1.5 μm) for 8 μm
And In this embodiment, each TFT has a single gate structure, but may have a double gate structure or a multi-gate structure provided with a plurality of gate electrodes.

Through the above steps, an n-ch TFT and a p-ch TFT required to form a CMOS circuit can be manufactured on the same substrate.

[Embodiment 2] An embodiment in which the gettering method of the present invention is applied when fabricating a TFT having an inverted stagger structure will be described with reference to FIGS.

First, a glass substrate such as a Corning # 1737 substrate was prepared as the substrate 301. Then, a gate electrode 302 was formed over the substrate 301. Here, a tantalum (Ta) film was formed to a thickness of 200 nm by a sputtering method. Further, the gate electrode 302 may have a two-layer structure of a tantalum nitride (TaN) film (50 nm in thickness) and a Ta film (250 nm in thickness). The Ta film is sputtered using Ar gas.
Is formed as a target, but when sputtered with a mixed gas obtained by adding Xe gas to Ar gas, the absolute value of the internal stress becomes 2 × 10 ⁸
Pa or less (FIG. 6A).

Then, a gate insulating film 303 and an amorphous silicon film 304 as an amorphous semiconductor layer were successively formed without being sequentially opened to the atmosphere. The gate insulating film 303 is a plasma CV
The nitrogen-rich silicon oxynitride film 303a is
A silicon oxynitride film 303b, which is richer in oxygen than 303a, is formed with a thickness of 5 nm. Also, the amorphous silicon film 304 was formed with a thickness of 20 to 100 nm, preferably 40 to 75 nm by using the plasma CVD method. Then, in the same manner as the crystallization described in Embodiment 1, the crystallization is performed by using a metal element that promotes crystallization. First, a layer 305 containing a metal element is formed by a spin coating method, a sputtering method, a vacuum evaporation method, or the like.
(B)).

After that, using an furnace annealing furnace, 450
By performing thermal annealing at 550550 ° C. for one hour, hydrogen is released from the amorphous silicon film 304, and the amount of remaining hydrogen is reduced to 5 atomic% or less. Then, thermal annealing is performed in a nitrogen atmosphere at 550 to 600 ° C. for 1 to 8 hours using a furnace annealing furnace, so that a crystalline silicon film 306 can be obtained (FIG. 6C). Here, similarly to the first embodiment, if a laser annealing method is performed to reduce the locally remaining amorphous region, it effectively works and crystallinity can be improved.

Next, a 200-nm-thick silicon oxynitride film 307 was formed to be in close contact with the thus formed crystalline silicon film 306 and to serve as a channel protective insulating film. After that, a resist mask 308 in contact with the silicon oxynitride 307 is formed by a patterning method using exposure from the back. Here, the gate electrode 302 serves as a mask, so that the resist mask 308 can be formed in a self-aligned manner. This is because the size of the resist mask is
Due to the light wraparound, the width slightly became smaller than the width of the gate electrode (FIG. 6D).

After the silicon oxynitride film 307 was etched using this resist mask 308 to form a channel protective insulating film 309, the resist mask 308 was removed. Through this step, the surface of the crystalline silicon film 306 other than the region in contact with the channel protective insulating film 309 was exposed. The channel protective insulating film 309 has a function of preventing impurities from being added to the channel region in a later impurity adding step, and has an effect of reducing the interface state density of the crystalline silicon film (FIG. 7). (A)).

Next, patterning using a photomask
Layer that covers part of the n-ch TFT and the p-ch TFT area.
Forming a resist mask 310, and forming a crystalline silicon film 306;
Element that imparts n-type to the region where the surface of the surface is exposed
Was added. And n⁺Shape the area 311a
Done. Here, phosphine (P
H _Three), Dose amount 5 × 10¹⁴atoms / cm^Two, Acceleration voltage 10
 Phosphorus (P) was added as kV. In addition, the above registrar
The pattern of the disc 310 is appropriately set by the practitioner.
R⁺The width of the region is determined and n having the desired width^-Type area,
And channel formation region
(FIG. 7B).

After removing the resist mask 310, the protection
An insulating film 312 was formed. This film is also a silicon oxynitride film
Under the same conditions as 307, it was formed to a thickness of 50 nm (FIG. 7).
(C)). Next, a protective insulating film 312 is provided on the surface.
Doped n-type impurity element to crystalline silicon film
Perform the process of n^-A mold region 313 was formed. However,
Through the protective insulating film 312 to the underlying crystalline silicon film.
Consider the thickness of protective insulating film 312 to add pure substance
And set appropriate conditions. here,
Dose 3 × 10¹³ atoms / cm^TwoAnd the accelerating voltage was 60 kV.
The n thus formed ^-Area 313 functions as LDD area
(FIG. 7D).

Next, a resist mask 3 covering the n-ch TFT
Form 15 and add p-type to the area where p-ch TFT is formed
A step of adding an impurity element to be performed was performed. Here,
Diborane (B_TwoH₆) And boron (B)
Was added. Dose amount is 4 × 10 ^Fifteen atoms / cm^Two, Acceleration voltage
P as 30 kV⁺A region was formed (FIG. 8A). afterwards,
The channel protective insulating film 309 and the protective insulating film 312 are left as they are.
The crystalline silicon is left by a well-known patterning technique.
The film was etched into a desired shape (FIG. 8B).

Through the above steps, the source region 316, the drain region 317, and the LDD regions 318, 31 of the n-ch TFT
9. A channel formation region 320 was formed, and a source region 322, a drain region 323, and a channel formation region 321 of the p-ch TFT were formed. Then, n-ch TFT and p-ch T
A first interlayer insulating film 325 having a thickness of 100 to 500 nm was formed to cover the FT. (FIG. 8 (C)). Then, a second interlayer insulating film 326 was further formed to a thickness of 100 to 500 nm (FIG. 8D).

The first interlayer insulating film 325 and the second interlayer insulating film 326 are then formed by forming a predetermined resist mask.
The source region of each TFT by the etching process,
A contact hole reaching the drain region was formed. Then, as in the first embodiment, phosphorus is selected as an impurity element belonging to Group 15 of the periodic table, a silicon film containing 1 × 10 ¹⁹ atoms / cm ³ or more of phosphorus is formed, and a gettering layer 327 is formed. . As a formation method, any of a plasma CVD method, a low pressure CVD method, and a sputtering method may be used, and any of an amorphous silicon film, a microcrystalline silicon film, and a crystalline silicon film may be used. Thereafter, thermal activation is performed in the same manner as in the first embodiment, and the metal element remaining in the crystalline silicon film 306 is gettered with high efficiency. The heat activation is performed at 400 to 800 ° C (preferably 500 to 600 ° C). The thermal activation step plays a role of activating the n-type or p-type impurity element added at each concentration, and the gettering layer 327.
Is formed as an amorphous silicon film or a microcrystalline silicon film, the gettering layer 327 becomes a crystalline silicon film. After the activation step, a heat treatment is further performed at 300 to 500 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to hydrogenate the island-like semiconductor layer. It may be added to terminate the bond. Plasma hydrogenation (using hydrogen excited by plasma) may be performed as another means of hydrogenation (FIG. 9A).

After that, a second conductive layer is formed. This second conductive layer may be used as a laminated film for preventing hillocks and oxidation. Then, after patterning the second conductive layer to function as a part of the source wirings 328 and 330 and the drain wiring 329, the gettering layer 327 is etched by self-alignment using the second conductive layer as a mask, and the second conductive layer is etched together with the second conductive layer. The gettering layer 327 also functions as part of the source wirings 328 and 330 and the drain wiring 329 (FIG. 9B).

Further, a step of forming a passivation film 331 was performed. Passivation film is plasma CVD
It is formed by a silicon oxynitride film formed from SiH ₄ , N ₂ O, and NH ₃ by a method, or a silicon nitride film formed from SiH ₄ , N ₂ , and NH ₃ . First, prior to film formation, N ₂ O, N ₂ , NH ₃
And the like were introduced to perform a plasma hydrogenation treatment. Here, hydrogen generated in the gas phase by being converted into plasma is also supplied to the second interlayer insulating film, and if the substrate is heated to 200 to 500 ° C., the hydrogen is converted into the first interlayer insulating film. Further, it can be diffused to the lower layer side, and the second hydrogenation step can be performed. The conditions for forming the passivation film are not particularly limited, but a dense film is desirable. Finally, in the third hydrogenation step, thermal annealing at 300 to 550 ° C. was performed for 1 to 12 hours in an atmosphere containing hydrogen or nitrogen. At this time, hydrogen is supplied to the passivation film 331.
To the second interlayer insulating film 326 from the second interlayer insulating film 32
6 to the first interlayer insulating film 325 and from the first interlayer insulating film 325 to the crystalline silicon film, whereby hydrogenation of the crystalline silicon film can be effectively realized. Hydrogen is also released from the film into the gas phase, but if the passivation film was formed of a dense film, this could be prevented to some extent, and if hydrogen was supplied in the atmosphere, it could be compensated. did it.

Through the above steps, the p-ch TFT and the n-ch TFT can be formed on the same substrate in an inverted staggered structure.

[Embodiment 3] A method of manufacturing a pixel TFT in a pixel portion and a TFT of a driving circuit provided around the pixel portion on the same substrate will be described with reference to FIGS. However,
For the sake of simplicity, in the driving circuit, a CMOS circuit, which is a basic circuit such as a shift register circuit and a buffer circuit, and an n-ch TFT forming a sampling circuit are shown.

As shown in FIG. 10A, a base insulating film is formed on an insulating substrate 401. For example, a 1737 glass substrate manufactured by Corning Incorporated is used for 401. To prevent impurity diffusion from the substrate, Si
Silicon oxynitride film 402 manufactured from H ₄ , N ₂ O, and NH ₃
a was formed to a thickness of 50 nm and a silicon oxynitride film 402b formed of SiH ₄ and N ₂ O was formed to a thickness of 100 nm to form a base insulating film 402.

Next, 25 to 80 nm (preferably 30 to 60 nm)
Amorphous silicon film 403 as an amorphous semiconductor layer with a thickness of
a is formed by a known method such as a plasma CVD method or a sputtering method. In this example, an amorphous silicon film was formed to a thickness of 55 nm by a plasma CVD method. The base film 402
Since the amorphous silicon film 403a and the amorphous silicon film 403a can be formed by the same film forming method, both may be formed continuously. After the formation of the base film 402, the surface can be prevented from being contaminated by not once exposing it to the air atmosphere, so that the base film 402 is formed.
Variations in TFT characteristics and variations in Vth can be reduced.

Then, in the same manner as in Example 1, in order to crystallize using a metal element, an aqueous solution containing 10 ppm by weight of the metal element is applied by spin coating to form a layer containing the metal element (particularly as shown in FIG. (Not shown) for the amorphous silicon film 403a
Formed on top. Metal elements include Fe, Co, Ni, Ru, Rh, Pd,
Os, Ir, Pt, Cu, Au, Ge, Pb, In and the like are used. In the crystallization step, first, thermal annealing is performed at 400 to 500 ° C. for about 1 hour to reduce the hydrogen content of the amorphous silicon film to 5 atomic% or less. This can prevent the film surface from being roughened. When forming an amorphous silicon film by the plasma CVD method, the substrate temperature during film formation is set to 30 by using SiH ₄ and Ar as a reaction gas.
When the amorphous silicon film is formed at 0 to 400 ° C., the concentration of hydrogen contained in the amorphous silicon film can be reduced to 5 atomic% or less. In such a case, the dehydrogenation treatment becomes unnecessary. Then, using a furnace annealing furnace, in a nitrogen atmosphere at 550 to 600 ° C. for 1 to 8
A crystalline silicon film can be obtained up to the step of performing thermal annealing for a long time. In this state, the concentration of the metal element remaining on the surface was 3 × 10 ¹⁰ to 2 × 10 ¹¹ atoms / cm ² . Thereafter, a laser annealing method may be used in combination to increase the crystallization ratio. Thus, a crystalline semiconductor layer 403b made of a crystalline silicon film was formed. (FIG. 10
(B)).

The crystalline silicon film thus formed is patterned into an island shape, and the active layer 404 of the p-ch TFT and the active layer 405 of the n-ch TFT of the CMOS circuit are formed by dry etching.
An active layer 406 of an n-ch TFT forming a sampling circuit,
The active layer 407 of the pixel portion TFT was formed. Then, 50 to 100 by plasma CVD, low pressure CVD, or sputtering
A mask layer 408 of a silicon oxide film having a thickness of nm is formed. For example, a silicon oxide film is formed by heating at 400 ° C. at 266 Pa using a mixed gas of SiH ₄ and O ₂ by a low pressure CVD method (FIG. 10C).

Then, a channel doping step is performed. First,
A photoresist mask 409 is provided, and a p-type is formed at a concentration of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ for the purpose of controlling Vth over the entire surface of the island-shaped semiconductor layers 405 to 407 forming the n-ch TFT. Boron (B) was added as an impurity element to be provided. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film. Although the addition of boron (B) here is not always necessary, the semiconductor layer 41 to which boron (B) is added is used.
0 to 412 are preferably formed to keep the Vth of the n-ch TFT within a predetermined range. (FIG. 10 (D)).

In order to form an LDD region of an n-channel TFT of a driver circuit, an impurity element imparting n-type conductivity is selectively added to the island-shaped semiconductor layers 410 and 411. Therefore, photoresist masks 413 to 416 were formed in advance. Here, phosphine (P) is added to add phosphorus (P).
An ion doping method using H ₃ ) was applied. It formed n ^-
The phosphorus (P) concentration of the impurity regions 417 and 418 is 1 × 10 ¹⁷ to
5 × 10 ¹⁸ atoms / cm ³ . Further, the impurity region 419
Is a semiconductor layer for forming a storage capacitor in a pixel portion, and phosphorus (P) is added to this region at the same concentration.
(Fig. 11 (A))

Next, a step of removing the mask layer 408 with hydrofluoric acid or the like to activate the impurity element added in the steps of FIGS. 10D and 11A is performed. Activation can be performed by thermal annealing at 500 to 600 ° C. for 1 to 4 hours in a nitrogen atmosphere or by laser annealing. Further, both may be performed in combination. In this embodiment, a KrF excimer laser beam (wavelength 248 n
m) to form a linear beam and generate an oscillation frequency of 5 to 50 H
z, scanning was performed with an energy density of 100 to 500 mJ / cm ^{2 and an} overlap ratio of the linear beam of 80 to 98%, thereby treating the entire surface of the substrate on which the island-shaped semiconductor layer was formed. There are no particular restrictions on the laser light irradiation conditions, and the conditions may be determined appropriately by the practitioner.

Then, the gate insulating film 420 is plasma-CV
It is formed with a thickness of 50 to 150 nm by the D method. If plasma cleaning is performed using, for example, hydrogen before forming the gate insulating film, the gate insulating film 420 and the island-shaped semiconductor layers 404 and 41 are formed.
The interface with 0 to 412 is kept clean, and the interface state density affecting the electrical characteristics of the TFT can be reduced. Even if oxygen or N ₂ O is added, the island-shaped semiconductor layers 404 and 410
By oxidizing the outermost surface of 412 and its vicinity, the interface state density can be further reduced. And
A gate insulating film 420 is formed continuously with the plasma cleaning (FIG. 11B).

Next, a first conductive layer is formed to form a gate electrode. In this embodiment, a conductive layer (A) 421 made of a conductive nitride metal film and a conductive layer (B) 422 made of a metal film are laminated. Here, the conductive layer (B) 422 is tantalum (T
a) was formed to a thickness of 250 nm, and the conductive layer (A) 421 was formed to a thickness of 50 nm with tantalum nitride (TaN) (FIG. 11).
(C)).

Next, the photoresist masks 423-42
7 are formed, and the conductive layer (A) 421 and the conductive layer (B) 422 are collectively etched to form gate electrodes 428 to 431 and a capacitor wiring 432. The gate electrodes 428 to 431 and the capacitor wiring 432 are formed of conductive layers (A) 428 a to 428.
32a and 428b to 432b made of a conductive layer (B) are integrally formed. At this time, the gate electrodes 429 and 430 formed in the driving circuit are
18 is formed so as to overlap with part of the gate insulating film 18 with the gate insulating film 420 interposed therebetween (FIG. 11D).

Next, in order to form a source region and a drain region of the p-channel TFT of the driving circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligned manner using the gate electrode 428 as a mask. A region where the n-channel TFT is to be formed is covered with a photoresist mask 433. Then, the p ⁺ impurity region 4 is formed by ion doping using diborane (B ₂ H ₆ ).
34 were formed at a concentration of 1 × 10 ²¹ atoms / cm ³ (FIG. 12).
(A)).

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Forming resist masks 435 to 437,
The impurity region 438 is added by adding an impurity element imparting n-type.
~ 441 was formed. This is performed by an ion doping method using phosphine (PH ₃ ), and n ⁺ impurity regions 438 to 4
The (P) concentration of 41 was set to 5 × 10 ²⁰ atoms / cm ³ (FIG. 12).
(B)).

Then, in order to form the LDD region of the n-channel TFT in the pixel portion, a process of adding an impurity for imparting n-type was performed. Here, an impurity element imparting n-type in a self-aligned manner is added by an ion doping method using the gate electrode 431 as a mask. The concentration of phosphorus (P) to be added is 5 × 10 ¹⁶ atoms
/ Cm ³ and FIGS. 11 (A), 12 (A) and 12
By adding at a concentration lower than the concentration of the impurity element added in (B), the n ⁻ impurity regions 443 and 444 are substantially obtained.
Only are formed. Further, although the impurity region 442 already contains boron (B) added in the previous step, phosphorus (P) is added at a considerably lower concentration than that, so that the influence of the added P Need not be considered, and did not affect the characteristics of the TFT at all (FIG. 12C).

Next, a second conductive layer serving as a gate wiring is formed. This second conductive layer is formed of a conductive layer (D) mainly containing aluminum (Al) or copper (Cu) as a low-resistance material. In any case, the resistivity of the second conductive layer is 0.1
About 10 μΩcm. Further, a conductive layer (E) made of titanium (Ti), tantalum (Ta), tungsten (W), or molybdenum (Mo) is preferably formed by lamination. In this embodiment, aluminum (A) containing 0.1 to 2% by weight of titanium (Ti) is used.
l) The film was formed as a conductive layer (D) 445, and the titanium (Ti) film was formed as a conductive layer (E) 446. Conductive layer (D) 445 is 20
The conductive layer (E) 446 may have a thickness of 50 to 200 nm (preferably 100 to 150 nm).
m) (FIG. 12D).

Then, a conductive layer (E) 446 and a conductive layer (D) 44 are formed to form a gate wiring connected to the gate electrode.
5 is etched to form gate wirings 447 and 448.
And a capacitor wiring 449 were formed. Etching first
The conductive layer (E) is removed from the surface of the conductive layer (E) to the middle of the conductive layer (D) by dry etching using a mixed gas of SiCl ₄ , Cl ₂ and BCl _3, and then conductive by wet etching with a phosphoric acid-based etching solution. By removing the layer (D), the gate wiring could be formed while maintaining the selectivity with the base (FIG. 13A).

As the first interlayer insulating film 450, a silicon oxynitride film was formed with a thickness of 500 to 1500 nm. Thereafter, a contact hole reaching a source region or a drain region formed in each of the island-shaped semiconductor layers is formed.
Similarly to 2, a gettering layer 451 was formed by forming a silicon film containing 1 × 10 ¹⁹ atoms / cm ³ or more of phosphorus. As a formation method, any of a plasma CVD method, a low pressure CVD method, and a sputtering method may be used, and any of an amorphous silicon film, a microcrystalline silicon film, and a crystalline silicon film may be used. After that, thermal activation is performed to getter the metal elements remaining in the island-shaped semiconductor layers 404, 410 to 412 through the source contact and the drain contact. The heat activation is performed at 400 to 800 ° C (preferably 500 to 600 ° C). By this thermal activation step, the impurity element imparting n-type or p-type can be simultaneously activated. Then, a hydrogenation step for terminating dangling bonds in the island-shaped semiconductor layers 404, 410 to 412 may be added (FIG. 13).
(B)).

Thereafter, a third conductive layer serving as a part of the source and drain wirings is formed. This third conductive layer may be a laminated film for preventing hillocks and oxidation. This conductive layer is formed by using source wirings 452 to 455 and drain wirings 456 to 4.
After patterning in order to function as a part of 59, the gettering layer 451 is etched in a self-aligned manner using this as a mask. Function as part of

Next, as a passivation film 460,
A silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed with a thickness of 50 to 500 nm (typically, 100 to 300 nm). In any case, the passivation film is formed to be a dense film to block moisture from the outside, and to add a function as a cap layer in a second hydrogenation step to be performed later. For example, if the passivation film 460 is formed of a dense silicon nitride film to a thickness of 200 nm and hydrogenation is performed in this state, favorable results can be obtained for improving the characteristics of the TFT. This is 3-100%
300 to 5 in an atmosphere containing hydrogen or in a nitrogen atmosphere
It is preferable to perform heat treatment at 00 ° C. for 1 to 12 hours. Of course, in addition to the above-described method, the same effect can be obtained by performing the hydrogenation before forming the above-described silicon nitride film or by using a plasma hydrogenation method. Further, the plasma hydrogenation and the above-described hydrogenation may be used in combination. Here, the passivation film 46 is formed at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later.
An opening may be formed at zero. (Fig. 13 (C))

Thereafter, a second interlayer insulating film 461 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, it is formed by baking at 300 ° C. using a polyimide of a type which is thermally polymerized after being applied to the substrate. Then, a contact hole reaching the drain wiring 459 is formed in the second interlayer insulating film 461, and the pixel electrodes 462, 4
63 is formed. As the pixel electrode, a transparent conductive film may be used for a transmission type liquid crystal display device, and a metal film may be used for a reflection type liquid crystal display device. In this embodiment, in order to form a transmission type liquid crystal display device, an indium oxide and tin (ITO) film is formed to a thickness of 100 nm by a sputtering method. (FIG. 14)

Through the steps described above, here, the pixel TFT of the pixel portion and the TFT of the driving circuit provided around the pixel portion are provided.
Can be manufactured on the same substrate.

P-channel TFT 50 of CMOS circuit of drive circuit
1 includes a channel forming region 50 in the island-shaped semiconductor layer 404.
6, a source region 507 and a drain region 508. Similarly, in an n-channel TFT 502 of a CMOS circuit, a channel forming region 509, an LDD region (Lov) 510 overlapping with a gate electrode 429, a source region 51
1. It has a drain region 512. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 3.0 μm.
It was 1.5 μm. Sampling circuit n-channel TFT50
3 includes a channel forming region 51 in the island-shaped semiconductor layer 411.
3. Lov regions and Loff regions (LDD regions that do not overlap with the gate electrode, hereinafter referred to as Loff regions) 514 and 515, and source or drain regions 516 and 517 are formed, and the length of the Loff region in the channel length direction is formed. 0.3 ~ 2.0μ
m, preferably 0.5 to 1.5 μm. In the pixel TFT 504, channel formation regions 518, 5
19, Loff regions 520 to 523, and source or drain regions 524 to 526. The length of the Loff region in the channel length direction is 0.5 to 3.0 μm, preferably 1.5 to 2.5 μm. Further, a storage capacitor 505 is formed from the capacitor wirings 432 and 449, an insulating film made of the same material as the gate insulating film, and a semiconductor layer 527 to which an n-type impurity element is added and which is connected to the drain region 526 of the pixel TFT 504. Are formed. In FIG. 14, the pixel TFT 504 has a double gate structure, but may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

[Embodiment 4] Another method of adding a metal element for promoting crystallization of the amorphous silicon film used in Embodiments 1 to 3 will be described with reference to FIG.

First, as shown in FIG. 15A, a base insulating film 602 and an amorphous silicon film 603 are formed on a substrate 601 as in the first to third embodiments. Next, a mask insulating film 604 made of a silicon oxide film is formed, and an opening 605 for selectively adding a metal element is formed.

In this state, a thin oxide film is formed on the amorphous silicon film 603 by irradiating UV light in an oxygen atmosphere. Next, a nickel acetic acid solution containing 100 ppm of Ni is applied by spin coating to form a very thin Ni-containing layer 606 on the surface of the amorphous silicon film 603 exposed at the opening 605 (FIG. 15A )).

Then, thermal annealing is performed at 600 ° C. for 8 hours in a nitrogen atmosphere to crystallize the amorphous silicon film 603. The crystallization is performed by using a mask insulating film 60 to which Ni is selectively added.
Starting from the opening 605 of No. 4 and proceeding in a direction (lateral direction) parallel to the film surface from this region to which Ni has been added. The region crystallized by this is called a lateral growth region. The amorphous silicon film 603 includes a Ni-added region 607, a laterally grown region (crystalline silicon film) 608, and a region that has not been laterally grown (amorphous silicon film) 609. In the case of forming an active layer of a TFT, the present invention is applied by leaving a portion of the lateral growth region 608 in an island shape.

As described above, a crystalline silicon film was obtained. After that, it can be applied to the TFT in the same manner as in the first to third embodiments.

Embodiment 5 The substrate manufactured in Embodiment 3 is called an active matrix substrate. In this embodiment, an example of a process for manufacturing an active matrix liquid crystal display device from this active matrix substrate and an example of a circuit arrangement thereof. Will be described with reference to FIGS. The method for manufacturing the active matrix substrate has already been described in Embodiment 3, and thus is omitted here.

As shown in FIG. 16, an orientation film 701 is formed on the active matrix substrate in the state shown in FIG. Usually, a polyimide resin is often used for an alignment film of a liquid crystal display element. A light-shielding film 703, a transparent conductive film 704, and an alignment film 705 were formed on the opposite substrate 702 on the opposite side. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. Then, the pixel portion, the active matrix substrate on which the CMOS circuit is formed, and the opposing substrate are attached to each other via a sealing material or a spacer (both not shown) by a known cell assembling process. Then, a liquid crystal material 7 is placed between the two substrates.
06 was injected and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device shown in FIG. 16 is completed.

FIG. 17 shows a simplified circuit arrangement of the active matrix substrate as shown in FIG. Reference numeral 801 denotes a pixel portion, in which a gate wiring 806 and a source wiring 807 intersect in a matrix. Reference numerals 802 and 803 indicate a scanning signal driving circuit and an image signal driving circuit, respectively.

The circuit arrangement shown here is an example, and the present invention is not limited to this, and may be appropriately set by the practitioner.

Example 6 An active matrix substrate manufactured by carrying out the present invention includes various electro-optical devices, for example, an organic EL display device (including a film containing an organic compound capable of emitting light by applying an electric field). Light-emitting devices) and liquid crystal display devices. The present invention can be applied to all electronic devices incorporating such an electro-optical device as a display medium. Examples of the electronic device include a personal computer, a digital camera, a video camera, a portable information terminal (a mobile computer, a mobile phone, an electronic book, and the like), a navigation system, and the like. Examples of these are shown in FIGS.

FIG. 18A shows a personal computer, which includes a main body 1001 including a microprocessor and a memory, an image input unit 1002, a display device 1003, and the like.
A keyboard 1004 is provided. The liquid crystal display device and the organic EL display device of the present invention can be applied to the display device 1003.

FIG. 18B shows a video camera, which includes a main body 1101, a display device 1102, an audio input unit 1103, an operation switch 1104, a battery 1105, and an image receiving unit 11.
06. The liquid crystal display device and the organic EL display device of the present invention can be applied to the display device 1102.

FIG. 18C shows a portable information terminal, which comprises a main body 1201, an image input section 1202, an image receiving section 1203, operation switches 1204, and a display device 1205. The liquid crystal display device or the organic EL display device of the present invention is a display device 1205.
Can be applied to

FIG. 18D shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 1301, a display device 1302, and a speaker unit 1.
303, a recording medium 1304, and operation switches 1305. The recording medium is DVD (Digital Versatile).
Discs and compact discs (CDs) can be used to play music programs, display images, display video games (or video games), and display information via the Internet. The liquid crystal display device and the organic EL display device of the present invention can be suitably used for the display device 1302.

FIG. 19A shows a digital camera, which comprises a main body 1401, a display device 1402, an eyepiece unit 1403, operation switches 1404, and an image receiving unit (not shown). The liquid crystal display device or the organic EL display device of the present invention is a display device 1
402 can be applied.

FIG. 19B shows a mobile phone, and the main body 15
01, audio output unit 1502, audio input unit 1503, display unit 1504, operation switch 1505, antenna 1506
And so on. The present invention can be applied to the audio output unit 1502, the audio input unit 1503, the display unit 1504, and other signal control circuits.

FIG. 19C shows a display, which includes a main body 1601, a support 1602, a display portion 1603, and the like.
The present invention can be applied to the display portion 1603. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly, 30 inches or more).

FIG. 20A shows a front type projector, which comprises a light source optical system, a display device 2001, and a screen 2002. The present invention can be applied to a display device and other signal control circuits. FIG. 20B illustrates a rear projector, which includes a main body 2101, a light source optical system and a display device 2102, a mirror 2103, and a screen 2104. The present invention can be applied to a display device and other signal control circuits.

FIG. 20C shows the light source optical system and the display device 200 shown in FIGS. 20A and 20B.
1 and 2102 show an example of the structure. The light source optical system and display devices 2001 and 2102 include a light source optical system 2201, mirrors 2202 and 2204 to 2206, a dichroic mirror 2203, a beam splitter 2207, a liquid crystal display device 2208, a phase difference plate 2209, and a projection optical system 2210. The projection optical system 2210 includes a plurality of optical lenses. In FIG. 20C, an example of a three-panel system using three liquid crystal display devices 2208 is shown; however, the present invention is not limited to such a system, and a single-panel optical system may be used. Also,
In FIG. 20C, an optical path indicated by an arrow may be provided with a suitable optical lens, a film having a polarizing function, a film for adjusting a phase, an IR film, or the like. FIG.
FIG. 0 (D) is a diagram showing an example of the structure of the light source optical system 2201 in FIG. 20 (C). In this embodiment, the light source optical system 2201 includes a reflector 2301, a light source 2302, lens arrays 2303 and 2304, a polarization conversion element 2305,
It is composed of a condenser lens 2306. The light source optical system shown in FIG. 20D is an example and is not limited to the illustrated configuration.

Although not shown here, the present invention is also applicable to a navigation system, a reading circuit of an image sensor, and the like. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using the crystallization technology of Embodiments 1 to 3 and using the configuration of any combination of Embodiments 1 to 6.

[0109]

According to the present invention, a silicon film containing phosphorus is formed at the source contact and drain contact portions, and this is used as a gettering site, thereby effectively removing the metal element which promoted the crystallization of the amorphous silicon film. In addition to reducing or improving the stability and reliability of the electrical characteristics of the TFT, the step of forming a mask layer such as an oxide film and the step of patterning the oxide film, which were conventionally required for gettering, can be omitted. It leads to improvement of productivity. Also,
In gettering by doping, the crystal structure of the device region is damaged and the p-
Although a further doping step is required to lower the source and drain resistance in the ch TFT, the gettering can be performed well without such damage by the method according to the present invention.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of the present invention.

FIG. 2 is a diagram showing a process for manufacturing n-ch and p-ch TFTs on the same substrate.

FIG. 3 is a diagram showing a process for manufacturing n-ch and p-ch TFTs on the same substrate.

FIG. 4 is a diagram showing a process for manufacturing n-ch and p-ch TFTs on the same substrate.

FIG. 5 is a diagram showing a process for manufacturing n-ch and p-ch TFTs on the same substrate.

FIG. 6 is a diagram illustrating a process of manufacturing an inverted staggered n-ch and p-ch TFT on the same substrate.

FIG. 7 is a view showing a step of manufacturing an inverted staggered n-ch and p-ch TFT on the same substrate.

FIG. 8 is a view showing a process of manufacturing an inverted staggered n-ch and p-ch TFT on the same substrate.

FIG. 9 is a diagram showing a step of manufacturing an inverted staggered n-ch and p-ch TFT on the same substrate.

FIG. 10 is a view showing a step of manufacturing a pixel TFT and a TFT of a driver circuit over the same substrate.

FIG. 11 is a view showing a step of manufacturing a pixel TFT and a TFT of a driver circuit over the same substrate.

FIG. 12 is a view showing a step of manufacturing a pixel TFT and a TFT of a driver circuit over the same substrate.

FIG. 13 is a view showing a step of manufacturing a pixel TFT and a TFT of a driver circuit over the same substrate.

FIG. 14 is a view showing a step of manufacturing a pixel TFT and a TFT of a driver circuit over the same substrate.

FIG. 15 illustrates a method for adding a metal element which promotes crystallization.

FIG. 16 illustrates a structure of an active matrix liquid crystal display device.

FIG. 17 is a diagram showing a circuit arrangement of an active matrix liquid crystal display device.

FIG. 18 illustrates an example of a semiconductor device.

FIG. 19 illustrates an example of a semiconductor device.

FIG. 20 illustrates an example of a projector.

Claims (13)

[Claims] A source region and a drain region on an insulating surface;
And a crystalline silicon film having a channel formation region between the source region and the drain region; a gate insulating film over the crystalline silicon film; a gate electrode over the gate insulating film; In a semiconductor device having an interlayer insulating film, a silicon film containing an impurity element belonging to Group 15 of the periodic table on the interlayer insulating film, and a conductive layer on a silicon film containing an impurity element belonging to Group 15 of the periodic table The silicon film containing an impurity element belonging to Group 15 of the periodic table is in contact with the source region or the drain region through a contact hole formed in the interlayer insulating film, and contains an impurity element belonging to Group 15 of the periodic table. A semiconductor device, wherein a metal element required for forming the crystalline silicon film is segregated in the silicon film. A gate electrode on the insulating surface, a gate insulating film on the gate electrode, a source region, a drain region, and a channel forming region between the source region and the drain region on the gate insulating film. A crystalline silicon film, a protective insulating film on the crystalline silicon film, an interlayer insulating film on the protective insulating film, and a silicon film containing an impurity element belonging to Group 15 of the periodic table on the interlayer insulating film. In a semiconductor device having a conductive layer on a silicon film containing an impurity element belonging to Group 15 of the periodic table, the silicon film containing an impurity element belonging to Group 15 of the periodic table may be a contact layer formed on the interlayer insulating film. The silicon film which is in contact with the source region or the drain region by a hole and contains an impurity element belonging to Group 15 of the periodic table is the crystalline silicon film. The semiconductor device metal element required for formation is characterized by being segregated. 3. The metal element according to claim 1, wherein the metal element that promotes crystallization of the amorphous silicon film is Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, or Pt. , Cu, Au, Ge,
A semiconductor device comprising one or more elements selected from Pb and In. 4. The semiconductor according to claim 1, wherein the impurity element contained in the silicon film containing an impurity element belonging to Group 15 of the periodic table is phosphorus. apparatus. 5. The method according to claim 1, wherein the concentration of phosphorus contained in the silicon film containing an impurity element belonging to Group 15 of the periodic table is:
Wherein a is ^{1 × 10 1 9 atoms / cm} 3 or more. 6. A first step of forming an amorphous silicon film on an insulating surface, and adding a metal element that promotes crystallization of the amorphous silicon film to cause the amorphous silicon film to grow. A second step of forming a crystalline silicon film, a third step of forming a gate insulating film on the crystalline silicon film, a fourth step of forming a gate electrode on the gate insulating film, A fifth step of forming a source region and a drain region by adding an impurity element to a selected region of the crystalline silicon film, a sixth step of forming an interlayer insulating film on the gate electrode, A seventh step of forming a contact hole reaching the source region or the drain region in the film; and forming a silicon film containing an impurity element belonging to Group 15 of the periodic table on the contact hole and the interlayer insulating film. An eighth step of performing gettering of the metal element contained in the crystalline silicon film by thermal annealing, and conducting a conductive treatment on the silicon film containing an impurity element belonging to Group 15 of the periodic table. And a tenth step of forming a film. 7. A first step of forming a gate electrode on an insulating surface, a second step of forming a gate insulating film on the gate electrode, and forming an amorphous silicon film on the gate insulating film A third step of adding a metal element that promotes crystallization of the amorphous silicon film, and growing the amorphous silicon film to form a crystalline silicon film;
A fifth step of forming a protective insulating film on the crystalline silicon film, a sixth step of adding an impurity element to a selected region of the crystalline silicon film to form a source region and a drain region, A seventh step of forming an interlayer insulating film on the protective insulating film, an eighth step of forming a contact hole reaching the source region or the drain region in the protective insulating film and the interlayer insulating film, A ninth step of forming a silicon film containing an impurity element belonging to Group 15 of the periodic table on the hole and the interlayer insulating film, and performing gettering of the metal element contained in the crystalline silicon film by thermal annealing. A method for manufacturing a semiconductor device, comprising: a tenth step to be performed; and an eleventh step of forming a conductive film on a silicon film containing an impurity element belonging to Group 15 of the periodic table. . 8. The semiconductor according to claim 6, wherein the thermal annealing advances gettering of a metal element that promotes crystallization of the amorphous silicon film. Method for manufacturing the device. 9. The method according to claim 6, wherein:
The manufacturing of a semiconductor device, wherein the thermal annealing promotes gettering of a metal element which promotes crystallization of the amorphous silicon film and activates an impurity element added to the crystalline silicon film. Method. 10. The metal element according to claim 6, wherein the metal element that promotes crystallization of the amorphous silicon film is Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt. , Cu, Au, G
A method for manufacturing a semiconductor device which is one or more elements selected from e, Pb, and In. 11. The semiconductor according to claim 6, wherein the impurity element contained in the silicon film containing an impurity element belonging to Group 15 of the periodic table is phosphorus. Method for manufacturing the device. 12. The silicon film containing an impurity element belonging to Group 15 of the periodic table according to claim 6, wherein the concentration of phosphorus contained in the silicon film is 1 × 1.
A method for manufacturing a semiconductor device, which is at least 0 ¹⁹ atoms / cm ³ . 13. The silicon film containing an impurity element belonging to Group 15 of the periodic table according to any one of claims 6, 7, 11, and 12, wherein the silicon film is self-aligned with the conductive film. A method for manufacturing a semiconductor device, wherein wiring is formed.