JPH07122756A - Manufacture of thin film semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the jumping of the OFF-leak current or an element TFT by a method wherein the impurities such as phosphorus, arsenic and the like are ion-implanted through the first intern-layer insulating film, and a picture element TFT only is selectively formed into an LDD structure. CONSTITUTION:A picture element resist mask 1-15 is formed on a driver P- channel TFT and a driver N-channel TFT. Subsequently, donor type impurity ions P and the like are implanted. The accelerating energy of ions are set in such a manner that the first interlayer insulating film is thickly formed in the range of 3200Angstrom to 8200Angstrom on the region at a distance about 1mum from the gate electrode, but the ion accelerating energy becomes almost constant at 3200Angstrom on the region aparting 1mum or more from the end part of the gate electrode. The implanted ions are normally distributed to the depth, and the impurity density on the part 1mum from the end part of the gate electrode becomes small by two figures or more, then the impurity density of the region in the distance of 1mum or more. Accordingly, a low density LDD region 1-18 is formed automatically, and the jumping of OFF-leak current of the picture element TFT can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION Pixel switching N-channel thin film transistor, and N-channel thin film transistor and P for driving the pixel switching thin film transistor.
A driving circuit composed of channel thin film transistors relates to a method of manufacturing a thin film semiconductor device integrated on the same substrate. More specifically, the off leakage current of the pixel switching N channel thin film transistor is reduced, and the pixel holding characteristic is improved. The present invention relates to a method of manufacturing a thin film semiconductor device suitable for realizing an active matrix type liquid crystal display device in which a driving circuit having an improved display unevenness, flicker and resolution and at the same time a driving circuit having a large driving frequency are laminated on the same substrate. It is a thing.

[0002]

2. Description of the Related Art A thin film transistor is used in an active matrix type liquid crystal display device (hereinafter referred to as a liquid crystal display), a pixel switching element, a driver circuit, a contact image sensor, or an SRAM.
(Static Random Access Memo
It is applied to LSIs such as Ries).

A sufficiently large on-current is required for a thin film transistor which constitutes a drive circuit of a liquid crystal display. On the other hand, with respect to the pixel switching thin film transistor, a sufficiently low off-leakage current is required in order to improve the retention characteristic of the pixel and realize an active matrix type liquid crystal display device having excellent display unevenness, flicker and resolution. Further, an increase in off-leakage current (hereinafter referred to as “off-leakage current jump”) when a reverse bias voltage is applied to the gate electrode must be suppressed as much as possible (flat panel display 91, pp80−).
87, Nikkei BP).

Next, a thin film transistor (hereinafter abbreviated as poly-Si TFT) using a polycrystalline silicon thin film will be described in terms of obtaining a sufficient on-current. In the poly-Si thin film, crystal grain boundaries in which defect levels are distributed at a high density are present in the boundary region between crystal grains. Due to the synergistic effect of the existence of this defect level and the reverse bias electric field applied to the drain end, poly-Si
The off-leakage current of the TFT is very large (Jpn. J. Appl. Phys., Vol. 31).
(1992) pp. 206-209). In order to alleviate the electric field at the drain end, an LDD (Lightly Dope)
It is known that it is effective to form a d Drain) structure, but using a technique such as anisotropic etching,
Since a difficult step of forming a side wall at the end of the gate electrode is required, it has not been adopted so far in the TFT step.

In the conventional liquid crystal display, since the pixel switching thin film transistor does not have the LDD structure, the off leak current of the pixel switching thin film is very large. The characteristics are shown in FIG. The horizontal axis shows the gate voltage,
The vertical axis represents the drain current. The gate voltage 0V to -20V is the off region. The off-leakage current rapidly increases as the reverse bias voltage increases.

As described above, in the conventional liquid crystal display, since the off-leakage current of the pixel switching thin film transistor is extremely large, the pixel retention characteristic is insufficient. Therefore, flicker is large,
It was a liquid crystal display with large display unevenness. This point becomes a serious problem when manufacturing a panel with a larger size or a panel for high-definition. Also, when a new driving method such as so-called common swing is adopted, a larger reverse bias voltage is applied, so the requirement for off-leakage current becomes even more severe (seminar text, development technology and characteristics analysis of TFT color liquid crystal, Applied design, November 21st, 22nd, 1991, Japan Industrial Technology Sensor, pp9-24).

[0007]

SUMMARY OF THE INVENTION The object of the present invention is to solve the above-mentioned problems of the prior art and to achieve a very simple method by using the same number of photo processes as the conventional one or a smaller number of photo processes than the conventional one. , By selectively forming only the pixel switching thin film transistor into the LDD structure,
The purpose is to prevent the off-leakage current of T from rising, and to secure a sufficient on-current of the driver TFT. Further, it is a great problem to provide a method for easily manufacturing a liquid crystal display having excellent display characteristics by improving the pixel retention characteristics.

[0008]

According to the present invention, pixels arranged in a matrix, a pixel switching N-channel thin film transistor provided for each pixel for selecting the pixel, an N-channel thin film transistor and a P-channel thin film transistor are provided. A pixel driving circuit configured is a method of manufacturing a thin film semiconductor device in which the same thin film semiconductor device is accumulated on an insulating transparent substrate, in which a first thin film semiconductor layer, a gate insulating film and a gate electrode are formed on the substrate. After the first
By the photo step of (1), a P-channel resist mask is formed, impurities such as boron are ion-implanted, and a P-channel thin film transistor (hereinafter referred to as a driver P-channel TFT) that constitutes the pixel drive circuit is formed in a self-aligned manner. Step, and after peeling off the P-channel resist mask, a second photo-process is performed to form an N-channel resist mask and ion-implant impurities such as phosphorus or arsenic to configure the pixel drive circuit in a self-aligned manner. N-channel thin film transistor (hereinafter referred to as driver N-channel TF
T), a step of laminating a first interlayer insulating film having a film thickness of 1000 Å to 3000 Å after peeling off the N-channel resist mask, and a third photo step, whereby the driver P-channel is formed. A pixel resist mask for covering the TFT and the driver N-channel TFT is formed, impurities such as phosphorus or arsenic are ion-implanted, and the source and drain portions of the pixel switching N-channel thin film transistor (hereinafter referred to as pixel TFT) and L
It is characterized by at least including a step of simultaneously forming a DD (Lightly Doped Drain) region and a step of laminating a second interlayer insulating film after peeling the pixel resist mask.

Further, according to the present invention, pixels arranged in a matrix, pixel switching N-channel thin film transistors provided for each pixel to select the pixels, and pixels composed of N-channel thin film transistors and P-channel thin film transistors. A driving circuit is a method of manufacturing a thin film semiconductor device integrated on the same insulating transparent substrate, the method comprising: forming a first thin film semiconductor layer, a gate insulating film and a gate electrode on the substrate; Forming a P-channel resist mask by the photo step of (1), ion-implanting impurities such as boron with an ion implantation amount Np, and forming a driver P-channel TFT in a self-aligned manner; and removing the P-channel resist mask. After that, an N channel resist mask is formed by a second photo process,
A step of ion-implanting impurities such as phosphorus or arsenic to form a driver N-channel TFT in a self-aligned manner, and peeling off the N-channel resist mask, and then laminating a first interlayer insulating film having a film thickness of 1000Å to 3000Å And an impurity such as phosphorus or arsenic with an ion implantation amount Nn is ion-implanted over the entire surface of the substrate to form the source and drain portions of the pixel TFT and LDD (Lightly Doped D
at least the step of simultaneously forming a (rain) region and the step of laminating a second interlayer insulating film after ion implantation to the entire surface of the substrate.

Here, the ion implantation amount Np of the above-mentioned boron
Is preferably larger than the ion implantation amount Nn of phosphorus or arsenic.

[0011]

According to the structure of the present invention, the off-leakage current of the pixel switching TFT and the rising of the off-leakage current are reduced. As a result, a liquid crystal display with less flicker and display unevenness and excellent pixel holding characteristics is realized. The photo process does not increase.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) First, regarding the first invention,
The description starts with FIG. Insulating amorphous material (substrate) 1-
A non-single-crystal semiconductor thin film 1-2 is formed on the film 1. As the insulating amorphous material, a quartz substrate, a glass substrate, a nitride film, a SiO ₂ film, or the like is used. When a quartz substrate is used, the process temperature is allowed up to about 1200 ° C., but when a glass substrate is used, it is limited to a low temperature process of 600 ° C. or lower. Hereinafter, a case where a quartz substrate is used and a solid phase growth Si thin film is used as the non-single crystal semiconductor thin film will be described as an example. Of course, not only solid-phase-grown Si thin film, but also low-pressure CVD method and plasma CV
Polycrystalline Si thin film formed by D method or sputtering method or SOI (Silicon on Insulator)
r) or SOS (Silicon on Sapp)
The present invention can be realized by using hire).

Using a plasma CVD apparatus, as shown in FIG. 2, a mixed gas of SiH ₄ and H ₂ is decomposed by a high frequency glow discharge of 13.56 MHz on a quartz substrate 1-1 to form an amorphous Si film. Deposit 1-2. The SiH ₄ concentration of the mixed gas is 10 to 20%, and the internal pressure during deposition is 0.
It is about 5 to 1.5 torr. Substrate temperature is 250 ° C
Hereafter, about 180 ° C. is suitable. When the amount of bound hydrogen was determined by infrared absorption measurement, it was about 8 atomic%. The chamber before the deposition of the amorphous Si film 1-2 was subjected to Freon cleaning. The subsequently deposited amorphous Si film contains 2 × 10 ¹⁸ cm ⁻³ of fluorine. Therefore, in the present invention, after the Freon cleaning, dummy deposition is performed and then actual deposition is performed. Alternatively, the Freon cleaning is abolished and the chamber is cleaned by another method such as bead treatment.

Then, the amorphous Si film is formed at 400 ° C. to 5 ° C.
Heat treatment is performed at 00 ° C. to release hydrogen. This process is intended to prevent the explosive desorption of hydrogen.

Next, the amorphous thin film 1-2 is solid-phase grown. As a solid phase growth method, furnace annealing with a quartz tube is convenient. As the annealing atmosphere, nitrogen gas, hydrogen gas, argon gas, helium gas, or the like is used. 1 x 1
The annealing may be performed in a high vacuum atmosphere of 0 ⁻⁶ to 1 × 10 ⁻¹⁰ torr. Solid phase growth annealing temperature is 500 ° C
-700 degreeC. In such low temperature annealing, only the crystal grains having a crystal orientation with a small activation energy for crystal growth selectively grow, and slowly grow large. In the experiment of the inventor, by performing solid phase growth at an annealing temperature of 600 ° C. and an annealing time of 16 hours, 2 μ
A large-grain silicon thin film of m or more is obtained. In FIG. 3, 1-3 shows a solid phase growth silicon thin film.

The method for producing a silicon thin film by the solid phase growth method has been described above.
The silicon thin film may be formed by a method such as a sputtering method or a vapor deposition method.

Next, as shown in FIG. 4, the solid-phase-grown silicon thin film is formed by photolithography.
Pattern in an island shape. The reason for drawing the three islands is to explain the three TFTs of the driver P-channel TFT, the driver N-channel TFT, and the pixel TFT.

Next, as shown in FIG. 5, a gate oxide film 1-4 is formed. As the method for forming the gate oxide film, LPCVD method, photo-excited CVD method, plasma CVD method, ECR plasma CVD method, high vacuum vapor deposition method, plasma oxidation method, high pressure oxidation method, etc. There is a low temperature method.
The gate oxide film formed by the low temperature method is heat-treated to be a denser and excellent film having less interface states. When a quartz substrate is used as the amorphous insulating substrate 1-1, a thermal oxidation method can be used. Dr in the thermal oxidation method
There are y oxidation method and wet oxidation method. In the wet oxidation method,
An oxide film is formed at about 800 ° C. or higher. When a quartz substrate is used, it is suitable to carry out dry oxidation at a temperature as high as possible, for example 1000 ° C. or higher. A suitable thickness of the gate oxide film is about 500Å to 1500Å. After forming the gate oxide film, boron may be channel-implanted and channel-doped if necessary. This is intended to prevent the threshold voltage of the N-channel thin film transistor from shifting to the negative side. When the deposited thickness of the amorphous silicon film is about 500 to 1500Å, the dose amount of boron is 1 × 10 ^{22 to} 5 × 10.
¹² cm ^-2 is suitable. When the thickness of the amorphous silicon film is 500 Å or less, the boron dose amount is reduced to 1 × 10 ¹² cm ^-2 or less. Further, when the film thickness is 1500 Å or more, the boron dose amount is increased, and as a guide, it is 5 × 10 ¹² cm ^-2 or more.

Instead of channel ion implantation, boron may be added at the time of depositing the silicon film 1-2. this is,
It is obtained by flowing diborane gas (B ₂ H ₆ ) together with silane gas into the chamber to cause a reaction during the deposition of the silicon film.

Next, as shown in FIG. 6, the method of forming the gate electrodes 1-5 will be described. Here, a case of using a low resistance polycrystalline silicon film will be described as an example.
First, a film forming method using the diffusion method will be described. LP
A polycrystalline silicon film is deposited by a method such as a CVD method, and then by a POCl ₃ diffusion method at 900 to 1000 ° C.
P is added to the polycrystalline silicon film. At this time, since a thin oxide film is formed on the polycrystalline silicon film,
The oxide film is removed with an aqueous solution containing hydrofluoric acid. There is also a method of adding P by an ion implantation method. In addition, by depositing a doped polycrystalline silicon film, the gate electrode 1-
There is also a method of forming 5. This is SiH ₄ gas and PH
_This is a method of forming a film by decomposing a mixed gas of _three gases. An impurity-doped polycrystalline silicon film is formed by thermal decomposition at 500 to 700 ° C. in the LPCVD method and glow discharge decomposition in the PECVD method. With the PECVD method, a doped amorphous silicon film can be formed at about 300 ° C. By the solid phase growth method as described above,
It is also an effective method to grow this doped amorphous silicon film into a high quality polycrystalline silicon film.

The polycrystalline silicon film added with P of 1 × 10 ¹⁹ cm ⁻³ or more is 500 to 2000 by the above method.
Å Deposit about. In this case, the sheet resistance of the gate electrode is about 20 to 30 Ω / □.

In order to further reduce the sheet resistance of the gate electrode, there is a method of using a two-layer gate electrode in which an impurity-doped polycrystalline silicon film and a silicide film are laminated. As the silicide film, cobalt silicide (CoSi ₂ ), nickel silicide (NiSi), titanium silicide (TiSi ₂ ), molybdenum silicide (MoSi ₂ ), or tungsten silicide (WS) is used.
i ₂ ) etc. When a MoSi ₂ film is used as the silicide film, the sheet resistance is 7 when deposited at 1500 Å.
It is about 8Ω / □. The resistance of the gate line is reduced to about one third.

Next, the formation of the driver P-channel TFT will be described first. As shown in FIG. 7, a P-channel resist mask 1-6 is formed on the driver N-channel TFT and the pixel TFT by the first photo process. Then, ion implantation is performed to form the source region and the drain region. Ion implantation of an acceptor type impurity into the first semiconductor layer by an ion implantation method,
A source region and a drain region are formed in self-alignment with the gate electrode 1-5. In FIG. 7, 1-7
Is a source region heavily ion-implanted, and 1-8
Indicates the drain region.

Boron (B) or the like is used as the acceptor type impurity. As an impurity addition method, there are methods such as a laser doping method and a plasma doping method other than the ion implantation method. The arrows indicated by 1-9 represent the ion beam of impurities. When a quartz substrate is used as the insulating amorphous material 1-1, a thermal diffusion method can be used. Impurity dose is 1 × 10
^-14 to 1 × 10 ¹⁷ cm ^-2 . Converted into impurity concentration, the source region 1-7 and the drain region 1-8
Then, it is about 1 × 10 ¹⁹ to 1 × 10 ²² cm ⁻³ . Further, the ion acceleration energy is set so that the maximum value of the concentration distribution of the implanted impurities exists near the interface between the polycrystalline silicon thin film 1-3 and the gate insulating film 1-4. For example, if the gate oxide film thickness is 1200Å,
An ion acceleration energy of 30 to 40 keV is suitable.

After peeling off the P-channel resist mask 1-6, as shown in FIG. 8, an N-channel resist mask 1-10 is formed on the driver P-channel TFT and the pixel TFT by a second photo step. To do. Then, donor type impurity ions are implanted by an ion implantation method. As the donor type impurity, phosphorus (P), arsenic (As), or the like is used. 1-11 is a driver N
The source region and the drain region 1-12 of the channel TFT are shown. 1-13 has shown the ion beam.

As a method for adding impurities, there are methods such as a laser doping method and a plasma doping method in addition to the ion implantation method. When a quartz substrate is used as the insulating amorphous material 1-1, a thermal diffusion method can be used.

Subsequently, as shown in FIG. 9, a first interlayer insulating film 1-14 is laminated. As the first interlayer insulating film, S
An iO ₂ film is suitable. The film thickness is about 1000 to 3000Å.

At the end of the gate electrode 1-5, the film thickness of the first interlayer insulating film becomes thicker by the thickness of the gate electrode. For example,
If the thickness of the gate electrode is 5000Å, the thickness of the gate insulating film 1-4 is 1200Å, and the thickness of the first interlayer insulating film is 2000Å, the variation of the thickness of the first interlayer insulating film is 8200Å at the end of the gate electrode. On the other hand, when the distance from the end of the gate electrode is about 1 μm, the thickness becomes thin and becomes 3200Å. As will be explained later, this is utilized to make the pixel TFT LDD.
It is a structure.

Next, a method of forming an N-channel thin film transistor which constitutes a pixel switching thin film transistor will be described. As shown in FIG. 10, the pixel resist mask 1-15 is formed on the driver P-channel TFT and the driver N-channel TFT by the third photo process. Then, donor-type impurity ions are implanted by an ion implantation method. The donor-type impurities include
Phosphorus (P) or arsenic (As) is used. 1-19
Indicates an ion beam.

As a method for adding impurities, there are methods such as a laser doping method and a plasma doping method in addition to the ion implantation method. When a quartz substrate is used as the insulating amorphous material 1-1, a thermal diffusion method can be used.

When the ion implantation method is used, the ion acceleration energy is an important parameter. As described above, in the region of about 1 μm from the edge of the gate electrode, the film thickness of the first interlayer insulating film is large, from 8200Å to 3200Å.
However, at a distance of about 1 μm or more from the end of the gate electrode, it is almost constant at 3200 Å. The acceleration energy of the ions is adjusted so that the maximum concentration distribution of the implanted impurities exists on the surface of the polycrystalline silicon thin film 1-3 in the region where the thickness of the first interlayer insulating film is almost constant at 3200Å. Set. Therefore, when phosphorus is ion-implanted, the LSS theory (reference literature IEICE '73
/ 3 Vol. 56-C No. 3 179), it is suitable to set the ion acceleration energy of 280 keV to 330 keV. In a region of about 1 μm from the end of the gate electrode, the film thickness of the first interlayer insulating film is thick and varies in the range of 8200Å to 3200Å. Further, the implanted ions have a normal distribution with respect to the depth. Therefore, the impurity concentration in the range of 1 μm from the end of the gate electrode is about two orders of magnitude smaller than the impurity concentration in the region 1 μm or more away. Therefore, as shown in FIG. 10, a low-concentration LDD region 1-18 and a high-concentration source region 1-16 and drain region 1-17 are automatically formed.

Subsequently, the pixel resist mask 1-15
Then, as shown in FIG. 11, a second interlayer insulating film 1-20 is formed. The method for forming the oxide film is LP
There are methods such as a CVD method, an APCVD method, a plasma CVD method, an ECR plasma CVD method, and a photoexcitation CVD method. Further, as a source gas, an organosilicon compound TEOS (Te
tra Etyhl Ortho-Silicate)
There is also a method of using ozone. When TEOS is used, excellent step coverage is realized. In addition, PSG (Phos
phosphate glass) and BSG (Bo
By reflowing the silicate glass), a more excellent step coverage can be realized.
Regarding the film thickness, it is common that the film thickness is several thousand liters to several μm.
LPCVD or plasma CVD is a simple method for forming the nitride film. For the reaction, a mixed gas of ammonia gas (NH ₃ ), silane gas and nitrogen gas,
Alternatively, a mixed gas of silane gas and nitrogen gas or the like is used.

Then, activation annealing is performed for the purpose of densifying the interlayer insulating film, activating the source region and drain region, and recovering the crystallinity. The activation annealing conditions are 800 to 1000 ° C. in a N ₂ gas atmosphere.
The temperature is lowered to about 10 minutes, and the annealing time is set to about 20 minutes to 1 hour. At 900 to 1000 ° C., the impurities are considerably activated by annealing for about 20 minutes. Annealing is performed for 20 minutes to 1 hour at 800 to 900 ° C. On the other hand, first, the crystallinity is sufficiently restored by annealing at 500 to 800 ° C. for about 1 to 20 hours, and then 900 to 1000 ° C.
The two-step activation annealing method of activating at high temperature is also effective. In addition, RTA (Rapid Thermal Annea) using an infrared lamp or a halogen lamp.
ling) method is also effective. Furthermore, it is also effective to use a laser activation method using a laser beam or the like.

Next, when hydrogen ions are introduced by a method such as a hydrogen plasma method, a hydrogen ion implantation method, or a hydrogen diffusion method from a plasma nitride film, dangling bonds existing at crystal grain boundaries or a gate oxide film. Defects existing at the interface or the like and defects existing at the junction between the source / drain portion and the channel portion are inactivated. Such a hydrogenation process may be performed before stacking the second interlayer insulating film 1-16. Alternatively, as described later, the hydrogenation step may be performed after forming the source electrode and the drain electrode.

Next, as shown in FIG. 12, contact holes are formed in the first interlayer insulating film 1-14, the second interlayer insulating film 1-20, and the gate oxide film 1-4 by photoetching. Then, as shown in FIG.
21 and the drain electrode 1-22 are formed. The source electrode and the drain electrode are formed of a metal material such as aluminum or chromium. In this way, a thin film transistor is formed. 1-23 is a pixel TFT, 1-2
4 is a driver N-channel TFT, 1-25 is a driver P
A channel TFT is shown.

(Embodiment 2) By defining the impurity concentration of the source and drain regions of the driver P-channel TFT and the driver N-channel TFT, the photo process can be further reduced by one process, which is the second invention. This will be described below.

Until the step of forming the first interlayer insulating film, the first
Since it is the same as the process of the invention of 1, the description thereof is omitted here.
Therefore, description will be made with reference to the subsequent figures from FIG.

After forming the first interlayer insulating film 1-14 as shown in FIG. 13, phosphorus or arsenic ion implantation is performed on the entire surface of the substrate without forming a photoresist, as shown in FIG. Then, a pixel TFT is formed. This time,
It is important that the dose amount Nn of phosphorus or arsenic be smaller than the dose amount Np of boron. in this way,
By setting each dose amount, the driver P
The source and drain portions of the channel TFT maintain the properties of P-type semiconductor. Therefore, it is not necessary to perform the third photo process described in the first embodiment.

Since the pixel TFTs 1-23 are ion-implanted through the first interlayer insulating film, the LDD is automatically
Become a structure.

In the subsequent steps, the thin film transistor is manufactured by the same steps as the steps described with reference to FIG.

[0042]

As described above in the embodiments, according to the present invention, it becomes possible to form only the conductive type thin film transistor which constitutes the pixel switching thin film transistor with the LDD structure by a very simple method. According to the present invention, the off-leakage current of the pixel switching thin film transistor can be reduced. The characteristics are shown in FIG. This corresponds to FIG. 1 described above. Gate voltage-20V
However, the off-leakage current is extremely small, and the rebound is significantly suppressed. As a result, flicker and display unevenness of the liquid crystal display are remarkably improved, and a very large effect on the improvement of panel characteristics is expected. Moreover, the present invention is realized by the same number of photo processes as the conventional process. Therefore, the manufacturing cost is the same as before.

Since only the pixel switching thin film transistor has the LDD structure selectively, it has no adverse effect on the drive circuit. Further, since the contact resistance of the source and drain electrodes does not increase at all, the signal writing characteristic to the pixel is improved. On the other hand, the driver TFT is L
Since it does not have the DD structure, a sufficiently high on-current can be obtained, and thus high-speed operation is possible. Therefore, the characteristics required for high definition and high definition TV (HDTV) are also satisfied.

The off-leakage current of the pixel switching thin film transistor is reduced, and further, the off-leakage current jump is significantly reduced. As a result, the pixel holding characteristic is improved, and it becomes possible to realize a good liquid crystal display with extremely few flicker and display unevenness. On the other hand, there is a driving method called common swing in order to improve display characteristics. According to this driving method, a larger reverse bias voltage is applied to the pixel switching thin film transistor. According to the present invention, the rise of the off-leakage current is remarkably reduced, so that it can sufficiently withstand a driving method such as common swing. Therefore, further improvement in display characteristics is expected. Moreover, since the on-current of the pixel TFT is sufficiently high,
Excellent writing characteristics are realized.

Since the driver TFT does not have the LDD structure, it has a high on-current and a high driving frequency.

Up to now, since the ion implantation has been performed only through the gate oxide film, the lateral diffusion of the implanted ions creates an overlap region between the source / drain end and the gate. The current could not be reduced. However, in the present invention, after the relatively thin first interlayer insulating film is formed,
Since the ion implantation is performed, the LDD structure is automatically obtained. Thus, the LDD structure can be formed by a very simple method. Conventionally, the LDD structure has been formed by forming a sidewall at the end of the gate electrode by anisotropic etching. However, according to the present invention, it is possible to omit the difficult and poorly controlled process as in the conventional technique.

Further, by making the ion dose amount of the source and drain portions of the N channel smaller than that of the P channel, the photo process can be further reduced by one.

When the two-layer scanning line using the silicide film is applied to the present invention, the sheet resistance of the scanning line is reduced from 25 Ω / □ in the case of the conventional polycrystalline silicon to about 1/3 to 8 Ω / □. be able to. Also in this case, the LDD structure can be easily formed. As a result, it is possible to easily manufacture an active matrix substrate having an extremely small off-leakage current and a low scanning line resistance value.

Since the gate signals are sent to the scanning lines from both the left and right sides, even if a disconnection occurs in the scanning lines, the signal delay is small because the scanning line resistance is sufficiently small, and there is no effect on the screen display of the liquid crystal display. There is no. Therefore, even if a short circuit occurs between the source line and the scanning line, the short circuit defect can be remedied by cutting the scanning lines on both sides of the short circuit point. Thus, there is a great effect on the improvement of yield.

Since the scanning line resistance decreases, the time constant τ of the scanning line decreases. Therefore, the rising characteristics of the pixel transistor are uniform at the center and the edges of the screen. as a result,
Flicker or display unevenness can be reduced. In addition, since the line capacitance of the scanning line does not have to be reduced, the pixel retention characteristic does not deteriorate. As described above, according to the present invention, it is possible to realize a liquid crystal display with extremely little flicker or display unevenness without deteriorating the pixel holding characteristic.

With respect to the high-definition TFT, a light valve or the like is required to form a projection type display, so that a large TFT panel of about 4 inches must be manufactured. When a panel having such long scanning lines is manufactured, the effect of the present invention is further enhanced.

Since the resistance of the scanning line is reduced, it is possible to eliminate the additional pixel holding capacitance line. Therefore, the aperture ratio is improved, and as a result, a very bright liquid crystal display can be realized.

Since it has an offset gate structure,
The pixel retention characteristics are improved. Furthermore, a great effect is expected in reducing the current consumption.

By using the solid phase growth method, a silicon thin film having excellent crystallinity can be formed on an amorphous insulating substrate, which greatly contributes to the development of SOI technology. Lowering the resistance of the gate line has a great effect in maximizing the characteristics of the thin film transistor improved by a method such as solid phase growth and realizing a very excellent liquid crystal display.

When the present invention is applied to a contact-type image sensor in which a photoelectric conversion element and its scanning circuit are integrated in the same chip, when reading speed is increased, resolution is increased, and gradation is obtained, It produces a very large effect. When higher resolution is achieved, the application to a contact image sensor for color reading becomes easier. Of course, the effect is great also for the reduction of power supply voltage, the reduction of current consumption, and the improvement of reliability. Further, since it can be manufactured by a low temperature process, the contact type image sensor chip can be made long, and a single chip can realize a reading device for a large facsimile such as A4 size or A3 size. Therefore, it is possible to avoid a technique of unreliableness, such as double splicing of sensor chips, and to improve the mounting yield.

Not only quartz substrates and glass substrates but also sapphire substrates or MgO.Al ₂ O ₃ , BP, CaF ₂
A crystalline insulating substrate such as the above can also be used.

Although the effect of the present invention has been described above by taking a thin film transistor as an example, the present invention can be applied to an element using a thin film such as a bipolar transistor or a heterojunction bipolar transistor. Further, the present invention can be applied to an element using SOI technology such as a three-dimensional device.

Further, the present invention has been described by taking the solid phase growth method as an example. However, the present invention is not limited to the solid phase growth method, and the LPCVD method and other methods such as the EB vapor deposition method, the sputtering method and the MBE method. It can also be applied to the case where a thin film semiconductor device is manufactured using the formed poly-Si thin film. It can also be applied to a general MOS type semiconductor device.

[Brief description of drawings]

FIG. 1 is a diagram showing characteristics of an N-channel thin film transistor used in a conventional pixel switching thin film transistor.

FIG. 2 is a process sectional view showing the method of manufacturing the thin-film semiconductor device of the first invention of the present invention.

FIG. 3 is a process sectional view showing the method of manufacturing the thin-film semiconductor device of the first invention of the present invention.

FIG. 4 is a process sectional view showing the method of manufacturing the thin-film semiconductor device of the first invention of the present invention.

FIG. 5 is a process sectional view showing the method of manufacturing the thin-film semiconductor device of the first invention of the present invention.

FIG. 6 is a process sectional view showing the method of manufacturing the thin-film semiconductor device of the first invention in the present invention.

FIG. 7 is a process sectional view showing the method of manufacturing the thin-film semiconductor device of the first invention of the present invention.

FIG. 8 is a process sectional view showing the method of manufacturing the thin-film semiconductor device of the first invention of the present invention.

FIG. 9 is a process sectional view showing the method of manufacturing the thin-film semiconductor device of the first invention of the present invention.

FIG. 10 is a process sectional view showing the method of manufacturing the thin-film semiconductor device of the first invention of the present invention.

FIG. 11 is a process sectional view showing the method of manufacturing the thin-film semiconductor device of the first invention in the present invention.

FIG. 12 is another process sectional view showing the method of manufacturing the thin-film semiconductor device of the first invention of the present invention.

FIG. 13 is a process sectional view of a substantial part showing the method for manufacturing the thin film semiconductor device of the second invention in the present invention.

FIG. 14 is a process cross-sectional view of the essential parts showing the method for manufacturing a thin-film semiconductor device of the second invention in the present invention.

FIG. 15 is a diagram showing characteristics of an N-channel thin film transistor used in the pixel switching thin film transistor according to the present invention.

[Explanation of symbols]

 1-3 Polycrystalline silicon thin film 1-5 Gate electrode 1-14 First interlayer insulating film 1-16 Source region 1-17 Drain region 1-18 LDD region 1-20 Second interlayer insulating film 1-23 Pixel TFT 1-24 Driver N-channel TFT 1-25 Driver P-channel TFT

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/336

Claims (3)

[Claims] 1. A pixel arranged in a matrix, a pixel switching N-channel thin film transistor provided for each pixel to select the pixel, and a pixel driving circuit including an N-channel thin film transistor and a P-channel thin film transistor. A method of manufacturing a thin film semiconductor device accumulated on the same insulating transparent substrate, comprising: forming a first thin film semiconductor layer, a gate insulating film and a gate electrode on the substrate, and then performing a first photo process. Forming a P-channel resist mask, ion-implanting impurities such as boron, and forming a P-channel thin film transistor that constitutes the pixel driving circuit in a self-aligning manner; and after removing the P-channel resist mask, An N channel resist mask is formed by the photo step of No. 2, and phosphorus or arsenic or the like is removed. Things to ion implantation, and forming an N-channel thin film transistors forming a self-aligned manner with said pixel drive circuit, after peeling off the N-channel resist mask 1000
A pixel resist mask for covering the P-channel thin film transistor and the N-channel thin film transistor forming the pixel driving circuit is formed by a step of laminating a first interlayer insulating film having a film thickness of Å to 3000 Å and a third photo step. hand,
Impurities such as phosphorus or arsenic are ion-implanted, and the source and drain parts of the pixel switching N-channel thin film transistor and LDD (Lightly Doped Dr) are formed.
ain) region at the same time, and a step of laminating a second interlayer insulating film after peeling off the pixel resist mask, a method of manufacturing a thin film semiconductor device. 2. A pixel arranged in a matrix, a pixel switching N-channel thin film transistor provided for each pixel to select the pixel, and a pixel driving circuit including an N-channel thin film transistor and a P-channel thin film transistor. A method for manufacturing a thin film semiconductor device integrated on the same insulating transparent substrate, comprising: forming a first thin film semiconductor layer, a gate insulating film and a gate electrode on the substrate, and then performing a first photo process. Forming a P-channel resist mask, ion-implanting impurities such as boron with an ion-implantation amount Np to form a driver P-channel TFT in a self-aligning manner, and after removing the P-channel resist mask, By the photo step of (1), an N channel resist mask is formed, and impurities such as phosphorus or arsenic are ionized. Type, and forming an N-channel thin film transistors forming a self-aligned manner with said pixel drive circuit, after peeling off the N-channel resist mask 1000
A step of laminating a first interlayer insulating film having a thickness of Å to 3000 Å, and an impurity such as phosphorus or arsenic having an ion implantation amount Nn is ion-implanted on the entire surface of the substrate to form the source and drain portions of the pixel switching N-channel thin film transistor LDD (Li
A method for manufacturing a thin film semiconductor device, comprising: a step of simultaneously forming a thickly doped drain region; and a step of laminating a second interlayer insulating film after ion implantation into the entire surface of the substrate. 3. The method for manufacturing a thin film semiconductor device according to claim 2, wherein the ion implantation amount Np of boron is larger than the ion implantation amount Nn of phosphorus or arsenic.